Image forming apparatus, method and control device for image forming apparatus

Abstract

To detect and reset a circuit that is a cause of occurrence of an abnormality in a second controller to prevent repeated occurrence of the abnormality in the second controller and prevent loss of data held in a second control unit.SOLUTION: An image forming apparatus has a first control unit that includes a first controller, controls an image forming unit in a first operation mode, and for which a power supply is cut off in a second operation mode. The image forming apparatus has a second control unit that includes a second controller operating in the first and second operation modes. When detecting an abnormality in the second controller in the second operation mode, the second control unit causes the first control unit to return from the second operation mode to the first operation mode, on the basis of, an information acquisition request from the first control unit, outputs circuit information indicating a state of a plurality of circuits in the second control unit to the first control unit, and resets a circuit indicated by a reset request received from the first control unit.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to an image forming apparatus, a control method for an image forming apparatus, and a control device for an image forming apparatus. [Background technology]

[0002] There is known an image forming apparatus having a main control device that controls devices such as an image processing engine in a normal mode, and a sub-controller that controls part of the devices in place of the main control device in an energy-saving mode that consumes less power than the normal mode. In an image forming apparatus in which an I / O controller that communicates with the outside and a sub-CPU are mounted in the sub-controller, if the sub-CPU goes out of control, a method is known for preventing abnormal operation of the control device by resetting everything except for a circuit that constantly communicates with the outside (for example, see Patent Document 1).

[0003] In addition, when a sub-CPU goes out of control and cannot return to normal operation, a method is known in which the power to the entire image forming apparatus is turned off to prevent unnecessary power consumption by the sub-control unit that repeatedly resets itself (see, for example, Patent Document 2). Summary of the Invention [Problem to be solved by the invention]

[0004] If the reset range when the sub-CPU goes out of control is predetermined, the sub-CPU may go out of control again due to an abnormality in an element that is not reset. In this case, data stored in the sub-control unit before the out-of-control state may be lost.

[0005] The disclosed technology aims to prevent repeated abnormalities in the second controller by detecting and resetting the circuit that is the cause of the abnormality in the second controller, and to prevent the loss of data held in the second control unit. [Means for solving the problem]

[0006] In order to solve the above technical problem, an image forming apparatus according to one aspect of the present invention includes an image forming unit that forms an image, a first control unit that includes a first controller and controls the image forming unit in a first operation mode and is powered off together with the image forming unit in a second operation mode that consumes less power than the first operation mode, and a second control unit that includes a second controller that operates in the first operation mode and the second operation mode, wherein the second control unit includes an abnormality detection unit that outputs an abnormality detection signal when an abnormality in the second controller is detected in the second operation mode, and a return processing unit that returns the first control unit from the second operation mode to the first operation mode based on the abnormality detected by the abnormality detection unit. a circuit information holding unit that holds circuit information indicating states of a plurality of circuits in the second control unit; Based on information request , the circuit information stored in the circuit information storage unit A circuit information notification unit that outputs circuit information to the first control unit, and a reset unit that resets a circuit indicated by a reset request received from the first control unit. the first control unit has a stop request issuing unit that issues a stop request to the second control unit to stop operation of the second controller when it is not possible to determine the circuit in which an abnormality has occurred in the second control unit based on the circuit information notified from the second control unit, The second control unit has a stop signal generating circuit that generates a stop signal for stopping the operation of the second controller based on the stop request. It is characterized by: Effect of the Invention

[0007] By detecting and resetting the circuit that is the cause of the abnormality in the second controller, it is possible to prevent the abnormality in the second controller from occurring repeatedly and to prevent the loss of data held in the second control unit. [Brief description of the drawings]

[0008] [Figure 1] 1 is a block diagram showing an example of an image forming apparatus according to a first embodiment of the present invention. [Diagram 2] 2 is a sequence diagram showing an example of an operation of the image forming apparatus in FIG. 1. [Diagram 3] 1. FIG. 4 is a sequence diagram showing another example of the operation of the image forming apparatus in FIG. [Figure 4] 1. FIG. 4 is a sequence diagram showing yet another example of the operation of the image forming apparatus in FIG. [Diagram 5] FIG. 11 is a block diagram showing an example of an image forming apparatus according to a second embodiment of the present invention. [Figure 6] 6 is a sequence diagram showing an example of the operation of the image forming apparatus in FIG. 5. [Figure 7] FIG. 11 is a block diagram showing an example of an image forming apparatus according to a third embodiment of the present invention. [Figure 8] FIG. 11 is a block diagram showing an example of a control device according to a fourth embodiment of the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0009] Hereinafter, the embodiments will be described with reference to the drawings. In the following, the same reference numerals as the signal names are used for signal lines through which information such as signals is transmitted. In addition, in each drawing, the same components are given the same reference numerals, and duplicated explanations may be omitted.

[0010] (First embodiment) Fig. 1 is a block diagram showing an example of an image forming apparatus according to a first embodiment of the present invention. The image forming apparatus 100 shown in Fig. 1 has an engine 10, a main control unit 20, a sub-control unit 30, a ROM (Read Only Memory) 60, and an operation unit 70. The main control unit 20 is an example of a first control unit, and the sub-control unit 30 is an example of a second control unit.

[0011] For example, engine 10 has a scanner 11 that reads images recorded on paper media or the like to form image data, and a plotter 12 that forms an image on paper media or the like using the image data or the like. Note that engine 10 may include a printer that prints image data or the like on paper media using toner or ink instead of plotter 12. Engine 10 is an example of an image forming unit that forms an image.

[0012] Among the elements shown in FIG. 1, elements enclosed in bold frames operate in a normal mode, which is one of the operation modes, and stop operating in an energy saving mode, which is another of the operation modes. Elements not enclosed in bold frames in FIG. 1 operate in the normal mode and the energy saving mode. Hereinafter, the energy saving mode is also referred to as the energy saving mode. The normal mode is an example of a first operation mode, and the energy saving mode is an example of a second operation mode.

[0013] The main control unit 20 includes a main CPU (Central Processing Unit) 21, a PMC (Power Management Controller) 22, and a PCIe (Peripheral Component Interconnect express) interface (I / F) 23.

[0014] The sub-control unit 30 has a sub-CPU 31, a PCIe interface 32, a watchdog timer (WDT) 33, a PMC 34, a system register 35, a reset generator 36, and an arbiter 37. The sub-control unit 30 also has a QSPI (Quad Serial Peripheral Interface) 38, a work RAM 39, a USB (Universal Serial Bus) interface 40, a network interface 41, and an operation unit interface 42. Hereinafter, the watchdog timer 33 will also be referred to as the WDT 33.

[0015] The PCIe interface 32 includes a communication interface 51, a determination circuit 52, a HALT generation circuit 53, a circuit information holding unit 54, and a reset generation circuit 55. The determination circuit 52, the HALT generation circuit 53, the circuit information holding unit 54, and the reset generation circuit 55 are formed using, for example, programmable logic in the PCIe interface 32.

[0016] This makes it possible to provide the determination circuit 52, the HALT generation circuit 53, the circuit information holding unit 54, and the reset generation circuit 55 in the sub-control unit 30 without adding new circuits in the sub-control unit 30. Note that the determination circuit 52, the HALT generation circuit 53, the circuit information holding unit 54, and the reset generation circuit 55 may be provided outside the PCIe interface 32.

[0017] The main CPU 21 is an example of a first controller, and the sub CPU 31 is an example of a second controller. Note that the main CPU 21 and the sub CPU 31 may be processors or controllers other than a CPU.

[0018] In the normal mode, the main CPU 21 controls the overall operation of the image forming apparatus 100, and also controls the engine 10 to perform a scanner operation, a plotting operation, etc. The main CPU 21 repeatedly starts and stops depending on the operation mode.

[0019] The PMC 22 controls the supply of power to each element in the main control unit 20 based on an instruction from the PMC 34 of the sub-control unit 30. For example, the PMC 22 powers on and starts up the main CPU 21 and the PCIe interface 23 based on a power return instruction to return from the energy saving mode to the normal mode. Also, the PMC 22 ends the operation of the main CPU 21 and the PCIe interface 23 and cuts off the power supply based on a power cut-off instruction to transition from the normal mode to the energy saving mode.

[0020] The PCIe interface 23 communicates with the PCIe interface 32 of the sub-controller 30 by using packets (PCIe packets). This allows circuit information, a reset request, a hold request, and the like, which will be described later, to be transmitted and received between the main control unit 20 and the sub-controller 30 by using an existing interface. Furthermore, by using an existing main control unit 20 that has already been developed, and simply improving the program executed by the main CPU 21, it is possible to realize the operations shown in Figs. 2 to 4, which will be described later. Note that the main control unit 20 and the sub-controller 30 may be connected by a communication interface other than the PCIe interface.

[0021] In the energy saving mode, the sub CPU 31 controls the entire image forming apparatus 100 in place of the main CPU 21. The sub CPU 31 always operates regardless of the operation mode. The main CPU 21 controls the operation of the engine 10 and performs processes with a high load such as image processing, so the circuit scale is large and power consumption is high. In contrast, the sub CPU 31 does not perform image processing etc. associated with the operation of the engine 10, so the circuit scale can be made smaller and power consumption can be reduced compared to the main CPU 21. Therefore, the power consumption of the image forming apparatus 100 in the energy saving mode in which the engine 10 does not operate can be further reduced compared to the normal mode.

[0022] The communication interface 51 transmits and receives packets to and from a communication interface (not shown) of the PCIe interface 23. The determination circuit 52 determines whether or not a packet received from the main CPU 21 via the communication interface 51 is a specific packet that has been set in advance.

[0023] When the specific packet indicates a HALT request for stopping the operation of the sub CPU 31, the determination circuit 52 outputs a HALT instruction to the HALT generation circuit 53. The HALT request is an example of a stop request, and the main CPU 21 that issues the HALT request is an example of a stop request issuing unit.

[0024] When a specific packet indicates a reset request for resetting a predetermined element in the sub-controller 30, the determination circuit 52 outputs a reset instruction to the reset generation circuit 55. The main CPU 21 that issues the reset request is an example of a reset request issuing unit.

[0025] Furthermore, the determination circuit 52 acquires circuit information indicating the state of each circuit in the sub-controller 30 from the circuit information storage unit 54 based on an information acquisition request from the main CPU 21, and transmits the acquired circuit information to the main CPU 21 via the communication interface 51. The main CPU 21 that issues the information acquisition request is an example of an acquisition request issuing unit. The communication interface 51 and the determination circuit 52 are an example of a circuit information notification unit that outputs circuit information indicating the states of multiple circuits in the sub-controller 30 to the main control unit 20 based on an information acquisition request from the main control unit 20.

[0026] Here, if the return to the normal mode by the PMC 22 is based on an abnormality in the operation of the sub-controller 30, the main CPU 21 issues an information acquisition request to the sub-controller 30 to determine the extent to which the abnormality has occurred within the sub-controller 30. Then, the main CPU 21 issues a HALT request, a reset request, or the like to the sub-controller 30 based on the circuit information acquired from the sub-controller 30. Note that the main CPU 21 may issue an information acquisition request to the sub-controller 30 based on the instruction to return to the normal mode by the PMC 22, regardless of whether the return is based on an abnormality in the operation of the sub-controller 30 or not.

[0027] The HALT generation circuit 53 asserts a stop signal HALT to the sub CPU 31 in response to a HALT instruction from the determination circuit 52. In addition, the HALT generation circuit 53 negates the stop signal HALT to the sub CPU 31 in response to a HALT release instruction from the determination circuit 52. The HALT generation circuit 53 is an example of a stop signal generation circuit.

[0028] The output of the HALT generation circuit 53 is connected directly to the sub CPU 31 by a dedicated stop signal line HALT without passing through the arbiter 37. As a result, even if the main control unit 20 receives a power restoration instruction from the PMC 34 based on an abnormality in the arbiter 37, for example, the HALT generation circuit 53 can halt the sub CPU 31 without passing through the arbiter 37 in which the abnormality occurred. This makes it possible to prevent malfunctions of the sub CPU 31, such as erroneous rewriting of the work RAM 39.

[0029] The reset generation circuit 55 issues reset information RST to the reset generator 36 to reset a circuit corresponding to the reset range included in the reset instruction, based on the reset instruction from the determination circuit 52. The reset generation circuit 55 is an example of a reset information generation circuit that outputs the reset information RST to the reset generator 36.

[0030] The output of the reset generation circuit 55 is directly connected to the reset generator 36 by a dedicated reset signal line without passing through the arbiter 37. This allows the reset generator 36 to reset the arbiter 37, for example, even if the main control unit 20 receives a power restoration instruction from the PMC 34 based on an abnormality in the arbiter 37.

[0031] In the normal mode, the circuit information holding unit 54 constantly receives circuit information from each circuit in the sub-control unit 30 via, for example, the arbiter 37, and holds the received circuit information. Note that the circuit information holding unit 54 may receive circuit information directly from each circuit (including the arbiter 37) without going through the arbiter 37. The circuit information holding unit 54 is a register, a latch, a buffer, or a memory. The circuit information holding unit 54 may also be provided in the determination circuit 52.

[0032] The WDT 33 resets a built-in timer (counter) in response to a reset signal received at a predetermined frequency from the sub CPU 31 via a signal line (not shown). If the WDT 33 is unable to receive a reset signal due to runaway of a program executed by the sub CPU 31 during energy saving mode, causing a timeout, the WDT 33 outputs a return signal to the PMC 34 to return the main control unit 20 to the normal mode from the energy saving mode.

[0033] Furthermore, if a timeout occurs during the energy saving mode, the WDT 33 outputs a return signal to the PCIe interface 32 to return the PCIe interface 32 to the normal mode from the energy saving mode. The WDT 33 is an example of an abnormality detection unit that outputs a return signal, which is an abnormality detection signal, when an abnormality of the sub CPU 31 is detected during the energy saving mode. The PCIe interface 32 is started in response to the return signal and becomes operable.

[0034] In response to a return signal from the sub CPU 31 or a return signal from the WDT 33, the PMC 34 outputs a power return instruction for returning the PMC 22 and the engine 10 from the energy saving mode to the normal mode. As described above, the PMC 22 returns the main control unit 20 from the energy saving mode to the normal mode based on the power return instruction.

[0035] The PMC 34 may output a return signal based on detection of an abnormality by the WDT 33 or the like, and a return signal for returning the sub-controller 30 from the energy saving mode to the normal mode while the sub-controller 30 is operating normally, to the PMC 22 and the engine 10. The PMC 34 outputs the return signal while the sub-controller 30 is operating normally, based on, for example, an operation of the operating unit 70 by the user.

[0036] In response to the power restoration instruction, the engine 10 supplies power to internal elements such as the scanner 11 and the plotter 12, and restores to the normal mode. The PMC 34 is an example of a restoration processing unit that restores the main control unit 20 from the energy saving mode to the normal mode in response to an abnormality detected by the WDT 33.

[0037] The system register 35 has, for example, a number of bits corresponding to circuits that can be reset within the sub-controller 30. The system register 35 asserts a signal corresponding to the bit set by the sub-CPU 31 and outputs it to the reset generator 36. The reset generator 36 resets the circuit corresponding to the asserted signal. This allows the sub-CPU 31 to reset any circuit that can be reset. The system register 35 may hold a value in which information indicating the circuit to be reset is coded. In this case, the reset generator 36 determines the circuit to be reset by decoding the coded value.

[0038] As described above, the reset generator 36 outputs a reset signal for resetting a corresponding circuit in response to the assertion of the reset information RST from the reset generation circuit 55 or the signal output from the system register 35. The reset generation circuit 55 and the reset generator 36 are an example of a reset unit that resets a circuit indicated by a reset request received from the main control unit 20.

[0039] The arbiter 37 has an internal bus that interconnects the circuits in the sub-controller and has a function of arbitrating the right to use the internal bus by each circuit. The arbiter 37 is an example of an interconnect that includes an internal bus that interconnects multiple circuits.

[0040] The QSPI 38 accesses a ROM 60 such as a serial flash memory based on an access request received via the arbiter 37. The ROM 60 may store a program executed by the sub CPU 31. The work RAM 39 holds work data used by the sub CPU 31, circuit information indicating the state of each circuit in the sub control unit 30, and the like.

[0041] The USB interface 40 communicates with a USB device (not shown) connected to a USB terminal. The network interface 41 is connected to a network. The operation unit interface 42 accepts operations by a user of the operation unit 70 of the image forming apparatus 100, and displays information related to the operation of the image forming apparatus 100 on a screen mounted on the operation unit 70.

[0042] Fig. 2 is a sequence diagram showing an example of the operation of the image forming apparatus 100 in Fig. 1. That is, Fig. 2 shows an example of a control method of the image forming apparatus 100. In the initial state of Fig. 2, the main control unit 20 and the PCIe interface 32 are stopped in the energy saving mode (energy saving). Although not shown, the engine 10 is also stopped. In Fig. 2, a vertically long rectangle indicates that each circuit is operating. A black circle in a rectangle indicates that information such as a signal is being relayed.

[0043] The sub CPU 31 periodically resets the WDT 33, and the WDT 33 avoids a timeout by being reset. If the sub CPU 31 goes out of control for some reason, the sub CPU 31 cannot reset the WDT 33. As a result, a timeout occurs (fires) in the WDT 33. The WDT 33 outputs a recovery signal to the PCIe interface 32, which releases the power saving mode of the PCIe interface 32 and causes it to return to the normal mode. The WDT 33 also outputs a recovery signal to the main control unit 20 via the PMC 34, which releases the power saving mode of the main control unit 20 and causes it to return to the normal mode.

[0044] The main CPU 21, which has returned from the power saving mode to the normal mode, acquires circuit information from the circuit information storage unit 54 of the PCIe interface 32, and detects the state of each circuit in the sub-control unit 30. In the example shown in Fig. 2, the main CPU 21 analyzes the acquired circuit information, but is unable to determine the circuit (cause) in which an abnormality has occurred in the sub-control unit 30.

[0045] In this case, the main CPU 21 issues a HALT request to the PCIe interface 32. The HALT generation circuit 53 of the PCIe interface 32 outputs a stop signal HALT of an assert level to the sub CPU 31 to stop the operation of the sub CPU 31. This makes it possible to prevent malfunctions such as erroneous rewriting of the work RAM 39 due to runaway of the sub CPU 31.

[0046] Thereafter, the main CPU 21 issues a memory access request to the work RAM 39 via the PCIe interface 32 and the arbiter 37. Then, the main CPU 21 backs up information for analyzing the cause of the abnormality in the sub-control unit 30, such as communication data and log data held in the work RAM 39.

[0047] It becomes possible to determine the cause of an abnormality that cannot be determined by obtaining circuit information by obtaining communication data and log data, etc., through main CPU 21. The cause of an abnormality may be determined by a control program executed by main CPU 21, or may be determined by a developer or the like who debugs image forming apparatus 100 by analyzing the communication data and log data.

[0048] The main CPU 21 may back up the work data and the like stored in the work RAM 39. This makes it possible to restore the work data even if the sub-CPU 31 goes out of control again after rebooting and the data in the work RAM 39 is rewritten.

[0049] The main CPU 21 determines the circuits to be reset using at least one of the acquired circuit information and data acquired from the work RAM 39. Then, the main CPU 21 outputs a reset request (reset instruction, reset information RST) including information indicating the circuits to be reset to the reset generator 36 via the PCIe interface 32. In the example shown in Fig. 2, the main CPU 21 determines to reset only the sub-CPU 31 based on the acquired circuit information.

[0050] The reset generator 36 outputs a reset signal to reset the sub CPU 31 and work RAM 39 instructed by the reset instruction. The reset sub CPU 31 is restarted and resumes program execution. After outputting a reset request to the sub control unit 30, the main CPU 21 releases the HALT request. The work RAM 39 is initialized by the reset.

[0051] 2, the main CPU 21 determines which circuits in the sub-controller 30 to reset based on the circuit information received from the sub-controller 30, thereby making it possible to reset the minimum number of circuits necessary to recover from an abnormality. In other words, by not fixing the range to be reset but determining which circuits to reset depending on the abnormal state of the sub-controller 30, it is possible to reduce the possibility that an abnormality will occur again after resetting, thereby improving the reliability of the image forming apparatus 100. In addition, since the circuits to be reset can be appropriately determined and reset, it is possible to prevent malfunctions such as data in the work RAM 39 being erroneously rewritten.

[0052] Fig. 3 is a sequence diagram showing another example of the operation of the image forming apparatus 100 in Fig. 1. That is, Fig. 3 shows an example of a control method for the image forming apparatus 100. Detailed description of the same operations as those in Fig. 2 will be omitted. In Fig. 3, the internal bus of the arbiter 37 stalls, causing the sub-CPU 31 to run out of control and the WDT 33 to ignite. The operations up until the main CPU 21 stops (HALT) the operation of the sub-CPU 31 are the same as those in Fig. 2, except that the internal bus of the arbiter 37 stalls.

[0053] The main CPU 21 detects a stall in the internal bus based on an analysis of the acquired circuit information. Then, the main CPU 21 outputs a reset request including an instruction to reset the internal bus to the reset generator 36 via the PCIe interface 32. The reset generator 36 outputs a reset signal to reset the internal bus based on the reset instruction.

[0054] After the internal bus returns to a normal state, the main CPU 21 backs up the data held in the work RAM 39 via the arbiter 37 (internal bus) in the same manner as in Fig. 2. Then, the main CPU 21 outputs a reset request including an instruction to reset the sub CPU 31 and the work RAM 39 to the reset generator 36 via the PCIe interface 32. Based on the reset instruction, the reset generator 36 resets the work RAM 39 and outputs a reset signal to the sub CPU 31, thereby restarting the sub CPU 31.

[0055] 3, by not fixing the range to be reset and determining the circuits to be reset depending on the abnormal state of the sub-controller 30, it is possible to reduce the possibility that an abnormality will occur again after resetting, thereby improving the reliability of the image forming apparatus 100. Furthermore, if an abnormality occurs in the arbiter 37, data can be backed up normally by copying the data held in the work RAM 39 after resetting the arbiter 37. Furthermore, if the data to be backed up includes history information on the operation of the sub-controller 30, it becomes possible to use the backed up data to investigate the cause of the malfunction of the sub-controller 30.

[0056] 4 is a sequence diagram showing yet another example of the operation of the image forming apparatus 100 in FIG. 1. That is, FIG. 4 shows an example of a control method of the image forming apparatus 100. Detailed description of the same operations as those in FIG. 2 and FIG. 3 will be omitted. In FIG. 4, during the energy saving mode, the sub CPU 31 detects an abnormality in the USB interface 40, and instructs the PMC 34 and the PCIe interface 32 to cancel the energy saving mode via the arbiter 37. After returning to the normal mode, the operation until the main CPU 21 backs up the data held in the work RAM 39 is the same as that in FIG. 2, except that the energy saving mode is canceled by the sub CPU 31, not by the WDT 33.

[0057] Even if the sub-CPU 31 is not running away, the main CPU 21 issues a HALT request after acquiring the circuit information and stops the operation of the sub-CPU 31. This makes it possible to prevent the sub-CPU 31 from running away due to an abnormality in the USB interface 40, for example, and to prevent the abnormal state in the sub-controller 30 from expanding. As a result, it is possible to increase the possibility that the sub-controller 30 can be restored to normal, and the reliability of the image forming apparatus 100 can be improved.

[0058] Based on the analysis of the acquired circuit information, the main CPU 21 detects an abnormality in the USB interface 40. Then, after backing up the data from the work RAM 39, the main CPU 21 outputs a reset request including an instruction to reset the USB interface 40 and the work RAM 39 to the reset generator 36 via the PCIe interface 32.

[0059] Based on the reset instruction, the reset generator 36 outputs a reset signal to reset the USB interface 40 and the work RAM 39. After that, the main CPU 21 issues a HALT release request to the PCIe interface 32. The HALT generation circuit 53 of the PCIe interface 32 negates the stop signal HALT based on the HALT release request, thereby issuing a HALT release instruction to the sub CPU 31 and causing the sub CPU 31 to resume operation.

[0060] As described above, in the first embodiment, when the sub-controller 30 detects runaway of the sub-CPU 31 during the energy saving mode, it resets the circuits that need to be reset in the sub-controller 30 based on an instruction from the main CPU 21. For example, the main CPU 21 determines the circuits to be reset in the sub-controller 30 based on circuit information received from the sub-controller 30, and outputs information indicating the determined circuits to the sub-controller 30.

[0061] Since the circuits to be reset can be appropriately determined and reset, it is possible to prevent repeated runaway of the sub-CPU 31. This makes it possible to prevent malfunctions such as data in the work RAM 39 being erroneously rewritten due to repeated runaway. In other words, by not fixing the range to be reset but determining the circuits to be reset according to the abnormal state of the sub-controller 30, it is possible to reduce the possibility of an abnormality reoccurring after resetting, and to improve the reliability of the image forming apparatus 100.

[0062] The sub-controller 30 temporarily halts the operation of the sub-CPU 31 based on a HALT request from the main controller 20. Thereafter, by resetting a specific circuit in the sub-controller 30 based on a reset request from the main controller 20, the reset operation of the circuit can be completed normally without being affected by the operation of the sub-CPU 31.

[0063] When a reset request from the main control unit 20 includes an instruction to reset the arbiter 37, the sub-control unit 30 resets the arbiter 37. As a result, the main CPU 21 can normally back up data by copying the data held in the work RAM 39 after the arbiter 37 is reset. In addition, when the data to be backed up includes historical information on the operation of the sub-control unit 30, it becomes possible to investigate the cause of a malfunction of the sub-control unit 30 using the backed up data.

[0064] Second embodiment Fig. 5 is a block diagram showing an example of an image forming apparatus according to a second embodiment of the present invention. The same elements as those in Fig. 1 are given the same reference numerals, and detailed description will be omitted. The image forming apparatus 100A shown in Fig. 5 has a main control unit 20A and a sub-control unit 30A instead of the main control unit 20 and the sub-control unit 30 in Fig. 1. The other configurations of the image forming apparatus 100A are the same as those in Fig. 1.

[0065] The main control unit 20A is obtained by adding a UART (Universal Asynchronous Receiver / Transmitter) 24 to the main control unit 20 in Fig. 1. The UART 24 is an example of a communication interface, and is an example of a serial interface that transmits and receives serial signals. That is, the main CPU 21 has a function of communicating with the sub-control unit 30A using the PCIe interface 23 and the UART 24.

[0066] The sub-control unit 30A has a UART 44 added to the sub-control unit 30 in Fig. 1, and has a PCIe interface 32A instead of the PCIe interface 32 in Fig. 1. That is, the sub-CPU 31 has a function of communicating with the sub-control unit 30A using the PCIe interface 32A and the UART 44.

[0067] The PCIe interface 32A is configured by deleting the determination circuit 52, the HALT generation circuit 53, the circuit information holding unit 54, and the reset generation circuit 55 from the PCIe interface 32 in Fig. 1. That is, the PCIe interface 32A has only the communication interface 51 of the PCIe interface 32 in Fig. 1. The other configuration of the sub-control unit 30A is the same as that of the sub-control unit 30 in Fig. 1, except that the WDT 33 outputs a return signal to the UART 44 and the PCIe interface 32A.

[0068] The UART 44 has a communication interface 45, a determination circuit 52, a HALT generation circuit 53, a circuit information holding unit 54, and a reset generation circuit 55. The connections between the HALT generation circuit 53, the circuit information holding unit 54, and the reset generation circuit 55 and the other circuits are the same as those in Fig. 1. Note that the determination circuit 52, the HALT generation circuit 53, the circuit information holding unit 54, and the reset generation circuit 55 may be provided outside the UART 44.

[0069] Although the PCIe interfaces 23 and 32A can realize high-speed data transmission, they have a complex mechanism and are prone to bit errors. Furthermore, when the PCIe interfaces 23 and 32A cannot correct a bit error, a link error may occur. On the other hand, serial interfaces such as UARTs 24 and 44 have a slower data transmission speed than the PCIe interface, but have a relatively simple mechanism and are therefore less prone to errors.

[0070] Therefore, by mounting the determination circuit 52, the HALT generation circuit 53, the circuit information holding unit 54, and the reset generation circuit 55 on the UART 44, it is possible to reliably transmit and receive circuit information, a reset request, a HALT request, and the like between the main control unit 20A and the sub-control unit 30A. Furthermore, if the cause of the runaway of the sub-CPU 31 is a link error or the like of the PCIe interface 32A, the PCIe interface 32A can be reset using the UART 44.

[0071] Fig. 6 is a sequence diagram showing an example of the operation of the image forming apparatus 100A in Fig. 5. That is, Fig. 6 shows an example of a control method of the image forming apparatus 100A. Detailed description of the same operations as those in Fig. 2 to Fig. 4 will be omitted. In Fig. 6, during the energy saving mode, the sub-CPU 31 instructs the PMC 34, the UART 44, and the PCIe interface 32A to return from the energy saving mode to the normal mode based on, for example, the user's operation of the operation unit 70.

[0072] 6, however, the opening of the PCIe interfaces 23 and 32A fails, and the failure to open causes the sub-CPU 31 to go out of control. The operations from when the sub-CPU 31 goes out of control to when the data held in the work RAM 39 is backed up are the same as those in FIG. 2, except that various instructions from the main CPU 21 are executed via the UARTs 24 and 44.

[0073] After backing up the data, the main CPU 21 outputs a reset request including an instruction to reset the PCIe interface 32A, the sub CPU 31, and the work RAM 39 to the reset generator 36 via the UART 44. In addition, the main CPU 21 resets the PCIe interface 23 in the main control unit 20.

[0074] As described above, in the second embodiment, the same effects as those of the first embodiment can be obtained by transmitting and receiving circuit information, a reset request, a HALT request, and the like between the main control unit 20A and the sub control unit 30A using the serial interfaces UARTs 24 and 44. Furthermore, in the second embodiment, if the cause of the runaway of the sub CPU 31 is the PCIe interface 32A, the PCIe interface 32A can be reset using the UART 44.

[0075] (Third embodiment) Fig. 7 is a block diagram showing an example of an image forming apparatus according to a third embodiment of the present invention. The same elements as those in Figs. 1 and 5 are given the same reference numerals, and detailed description thereof will be omitted. The image forming apparatus 100B shown in Fig. 7 has a sub-controller 30B instead of the sub-controller 30A in Fig. 5. The other configurations of the image forming apparatus 100B are the same as those in Fig. 1.

[0076] The sub-control unit 30B has the PCIe interface 32 of Fig. 1 instead of the PCIe interface 32A of Fig. 5. Other configurations of the sub-control unit 30B are similar to those of the sub-control unit 30A of Fig. 5, except that the reset generator 36 receives reset information RST output from the reset generation circuit 55 of the PCIe interface 32.

[0077] As described above, the third embodiment can also provide the same effects as the first and second embodiments. Furthermore, in the third embodiment, the PCIe interface 32 and the UART 44 are each equipped with a determination circuit 52, a HALT generation circuit 53, a circuit information holding unit 54, and a reset generation circuit 55. This makes it possible to restore the sub-control unit 30B to a normal state even if the sub-CPU 31 goes out of control due to either the PCIe interface 32 or the UART 44.

[0078] (Fourth embodiment) Fig. 8 is a block diagram showing an example of a control device according to a fourth embodiment of the present invention. The same elements as those in Fig. 1 are given the same reference numerals, and detailed description will be omitted. The control device 200 shown in Fig. 8 has a device 15 that realizes a predetermined function instead of the engine 10 in Fig. 1. The other configurations of the control device 200 are the same as those of the image forming device 100 in Fig. 1.

[0079] For example, the device 15 is a display or a mechanical part of a robot, and returns from a standby state and operates based on the operation of the operation unit 70. Examples of the operation of the control device 200 are similar to those in Figs. 2, 3, and 4. Note that the control device 200 may be configured by replacing the engine 10 in Fig. 5 or 7 with the device 15. As described above, the fourth embodiment can also provide the same effects as the above-mentioned embodiments.

[0080] Although the present invention has been described above based on the embodiments, the present invention is not limited to the requirements shown in the above embodiments. These requirements can be changed without departing from the spirit of the present invention, and can be appropriately determined according to the application form. [Explanation of symbols]

[0081] 10 Engine 11 Scanner 12 Plotter 15 Equipment 20, 20A Main control unit 21 Main CPU 23 PCIe Interface 24 UART 30, 30A, 30B Sub-control unit 31 Sub CPU 32, 32A PCIe interface 33 WDT 34 PMC 35 System Registers 36 Reset Generator 37 Arbitrator 38 QSPI 39 Work RAM 40 USB interface 41 Network Interface 42 Operation Interface 44 UART 45 Communication Interface 51 Communication Interface 52 Judgment circuit 53 HALT generation circuit 54 Circuit information holding section 55 Reset Generation Circuit 60 ROM 70 Operation section 100, 100A, 100B Image forming apparatus 200 Control device HALT stop signal RST Reset information [Prior art documents] [Patent documents]

[0082] [Patent Document 1] JP 2007-286859 A [Patent Document 2] JP 2011-51217 A

Claims

1. an image forming unit that forms an image; a first control unit including a first controller, which controls the image forming unit in a first operation mode, and is powered off together with the image forming unit in a second operation mode that consumes less power than the first operation mode; a second control unit including a second controller that operates in the first operation mode and in the second operation mode; The second control unit is an abnormality detection unit that outputs an abnormality detection signal when an abnormality in the second controller is detected in the second operation mode; a return processing unit that returns the first control unit to the first operation mode from the second operation mode based on the abnormality detection signal; a circuit information storage unit that stores circuit information indicating states of a plurality of circuits in the second control unit; a circuit information notification unit that outputs the circuit information held in the circuit information holding unit to the first control unit based on an information acquisition request issued from the first control unit when the operation mode is returned from the second operation mode to the first operation mode; a reset unit that resets a circuit indicated by a reset request received from the first control unit; having the first control unit has a stop request issuing unit that issues a stop request to the second control unit to stop operation of the second controller when it is not possible to determine the circuit in which an abnormality has occurred in the second control unit based on the circuit information notified from the second control unit, The second control unit has a stop signal generating circuit that generates a stop signal for stopping the operation of the second controller based on the stop request. An image forming apparatus comprising:

2. The first control unit is an acquisition request issuing unit that issues the information acquisition request when the operation mode is returned from the second operation mode to the first operation mode by the return processing unit; a reset request issuing unit that issues to the second control unit the reset request indicating a reset range determined based on the circuit information notified from the second control unit, The reset unit is a reset information generating circuit that outputs reset information indicating a circuit to be reset based on the reset request; a reset generation circuit that generates a reset signal for resetting a circuit indicated by the reset information received from the reset information generation circuit.

2. The image forming apparatus according to claim 1,

3. the second control unit has an interconnect including an internal bus that connects the plurality of circuits to each other; the reset request issuing unit of the first control unit issues the reset request to the second control unit to reset the interconnect when the circuit information notified from the second control unit indicates an abnormality in the interconnect.

3. The image forming apparatus according to claim 2,

4. The second control unit has a communication interface for communicating with the first control unit, The communication interface includes at least one of the reset information generating circuit and the stop signal generating circuit.

4. The image forming apparatus according to claim 2, wherein:

5. the communication interface includes a PCIe interface, The first control unit transmits the reset request, the information acquisition request, and the stop request as PCIe packets to the communication interface.

5. The image forming apparatus according to claim 4,

6. the communication interface includes a serial interface; the first control unit transmits the reset request, the information acquisition request, and the stop request as serial signals to the communication interface; 5. The image forming apparatus according to claim 4,

7. The second control unit has a memory for storing history information indicating a history of an operation of the second control unit, The first control unit issues a memory access request to the memory after being notified of the circuit information from the second control unit, and reads out the history information stored in the memory.

7. The image forming apparatus according to claim 1, wherein:

8. An operation unit connected to the second control unit and operated by a user, the second controller instructs the return processing unit to return from the second operation mode to the first operation mode based on an operation of the operation unit during the second operation mode; The return processing unit returns the first control unit from the second operation mode to the first operation mode based on a return instruction from the second controller.

8. The image forming apparatus according to claim 1, wherein:

9. A control method for an image forming apparatus having an image forming unit that forms an image, a first control unit that controls the image forming unit in a first operation mode and is powered off together with the image forming unit in a second operation mode that consumes less power than the first operation mode, and a second control unit including a second controller that operates in the first operation mode and the second operation mode, The second control unit When an abnormality of the second controller is detected during the second operation mode, an abnormality detection signal is output; returning the first control unit from the second operation mode to the first operation mode based on the abnormality detection signal; holding circuit information indicating states of a plurality of circuits in the second control unit; outputting the held circuit information to the first control unit based on an information acquisition request issued from the first control unit when the operation mode is returned from the second operation mode to the first operation mode; resetting a circuit indicated by a reset request received from the first control unit; when the first control unit cannot determine the circuit in which an abnormality has occurred in the second control unit based on the circuit information notified from the second control unit, the first control unit issues a stop request to the second control unit to stop operation of the second controller; The second control unit generates a stop signal for stopping the operation of the second controller based on the stop request. A control method for an image forming apparatus comprising the steps of:

10. A device having a predetermined function; a first control unit including a first controller, which controls the device in a first operation mode and is powered off together with the device in a second operation mode that consumes less power than the first operation mode; a second control unit including a second controller that operates in the first operation mode and in the second operation mode; The second control unit is an abnormality detection unit that outputs an abnormality detection signal when an abnormality in the second controller is detected in the second operation mode; a return processing unit that returns the first control unit to the first operation mode from the second operation mode based on the abnormality detection signal; a circuit information storage unit that stores circuit information indicating states of a plurality of circuits in the second control unit; a circuit information notification unit that outputs the circuit information held in the circuit information holding unit to the first control unit based on an information acquisition request issued from the first control unit when the operation mode is returned from the second operation mode to the first operation mode; a reset unit that resets a circuit indicated by a reset request received from the first control unit; having the first control unit has a stop request issuing unit that issues a stop request to the second control unit to stop operation of the second controller when it is not possible to determine the circuit in which an abnormality has occurred in the second control unit based on the circuit information notified from the second control unit, The second control unit has a stop signal generating circuit that generates a stop signal for stopping the operation of the second controller based on the stop request. A control device comprising:

Images