Chip reset control method and device, equipment and medium

Abstract

The invention discloses a chip reset control method and device, equipment and a medium, and relates to the technical field of integrated circuit design. The method comprises the following steps: determining a target chip comprising a plurality of functional modules, and constructing a reset matrix for the target chip according to reset requirements of the functional modules; loading and analyzing the reset matrix to determine a reset trigger condition of each functional module, and based on the reset trigger condition, generating a multi-stage reset control signal conforming to a reset control strategy through a preset general reset control circuit; distributing the multi-stage reset control signal to each functional module according to a preset reset time sequence so as to control each functional module to perform reset operation; and adjusting the dynamic control dimension parameters in the reset matrix in real time by presetting a dynamic configuration interface so as to perform reset adjustment and optimization on the target chip after tape-out. Through the technical scheme of the invention, the problems of low efficiency, time sequence conflict and insufficient flexibility in the traditional reset design can be solved.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit design technology, and in particular to a chip reset control method, apparatus, device, and medium. Background Technology

[0002] In modern integrated circuit design, especially in the field of System-on-Chips (SoCs), reset signal management is a core element ensuring normal chip startup and reliable operation. With increasing chip integration and diversified application scenarios, reset design faces significant challenges: SoCs typically contain multiple functional modules (such as CPU, GPU, and peripheral controllers), each of which may need to support multiple reset types (such as power-on reset, software reset, and watchdog reset), and the reset timing of different modules must be strictly coordinated to avoid conflicts. The complex power-on startup process requires standardization of the reset release sequence and timing; simultaneously, SoCs need to remain stable under extreme environments (such as temperature and voltage fluctuations), requiring reset parameters (such as delay period and polarity) to have dynamic adjustment capabilities.

[0003] Current mainstream reset management technologies have significant limitations: On the one hand, manually coded reset logic design is inefficient, has a long development cycle, is prone to timing conflicts, signal omissions and other human errors, is difficult to maintain and lacks flexibility, and is hard to adapt to changing requirements; on the other hand, solutions based on modular reset control IP have fixed functions, making it difficult to flexibly expand or adapt to complex reset requirements; multi-clock domain reset synchronization capabilities are insufficient, making it difficult to cope with dynamic clock changes; integration complexity is high, interface matching workload is large and error-prone. Therefore, current technologies cannot efficiently and reliably meet the complex reset management requirements of highly integrated, multi-scenario SoCs, and a new solution is urgently needed. Summary of the Invention

[0004] In view of this, the purpose of this invention is to provide a chip reset control method, apparatus, device, and medium that can solve the problems of low efficiency, timing conflicts, and insufficient flexibility in traditional reset designs, significantly shortening the development cycle and improving system reliability. The specific solution is as follows:

[0005] In a first aspect, this application discloses a chip reset control method, including:

[0006] Identify the target chip containing multiple functional modules, and construct a reset matrix for the target chip based on the reset requirements of each functional module; the reset matrix is ​​used to define the reset control strategy of each functional module in the form of structured parameters.

[0007] Load and parse the reset matrix to determine the reset trigger conditions of each functional module, and based on the reset trigger conditions, generate multi-level reset control signals that conform to the reset control strategy through a preset general reset control circuit;

[0008] According to the preset reset timing, multi-level reset control signals are distributed to each functional module to control each functional module to perform a reset operation;

[0009] By using a preset dynamic configuration interface, the dynamic control dimension parameters in the reset matrix can be adjusted in real time to reset, adjust, and optimize the target chip after tape-out.

[0010] Optionally, a reset matrix can be constructed for the target chip based on the reset requirements of each functional module, including:

[0011] Based on the reset requirements of each functional module, a reset matrix is ​​constructed for the target chip, including functional dimension parameters, timing dimension parameters, and dynamic control dimension parameters; among which,

[0012] The functional dimension parameters include reset type and reset trigger condition. The reset type is a configuration parameter used to define the reset range, and the reset trigger condition is a configuration parameter used to define the reason for initiating the reset operation.

[0013] The timing dimension parameters include release order and synchronization mode. Release order is a configuration parameter used to define the preset reset timing, and synchronization mode is a configuration parameter used to define the synchronization strategy for cross-clock domain reset signals.

[0014] The dynamic control dimension parameters are configuration parameters used to control the behavior of the reset signal during operation. They include one or more of the following: reset polarity, independent reset, delay period, and reset configurable permission. Reset polarity is a configuration parameter used to define the effective level of the reset signal. Independent reset is a configuration parameter used to define that a functional module can be reset independently. Delay period is a configuration parameter that specifies the number of clock cycles required for the reset signal to be activated or released according to the synchronization mode. Reset configurable permission is a permission configuration parameter used to characterize whether the response of the reset source can be configured.

[0015] Optionally, the reset matrix is ​​loaded and parsed to determine the reset trigger conditions for each functional module, including:

[0016] Establish a mapping relationship between different reset sources and each functional module;

[0017] Load and parse the reset matrix, and determine the identifier content to be filled in the mapping relationship based on the reset type in the reset matrix; the identifier content is an identifier in the form of a logical formula used to determine whether the functional module is triggered by the reset source.

[0018] Based on the mapping relationship and the identification content, the reset trigger conditions for each functional module are determined.

[0019] Optionally, after constructing a reset matrix for the target chip based on the reset requirements of each functional module, the following may also be included:

[0020] The reset matrix is ​​self-checked based on preset dependency constraint rules; the self-check process includes data type verification, logical conflict verification, and runtime rule checking.

[0021] Optionally, based on the reset trigger condition, a multi-level reset control signal conforming to the reset control strategy is generated through a preset general reset control circuit, including:

[0022] Receive the reset source signal from the target chip and generate reset requests for each functional module according to the reset trigger conditions;

[0023] Based on the synchronization mode configured in the reset matrix, the reset request is processed for cross-clock domain synchronization in order to output a synchronized reset signal.

[0024] Based on the synchronized reset signal and the release order configured in the reset matrix, a reset output signal conforming to the preset reset timing is generated;

[0025] Based on the reset polarity configured in the reset matrix, the polarity of the reset output signal is adjusted to generate a multi-level reset control signal that conforms to the hardware design of the functional module.

[0026] Optionally, before loading and resolving the reset matrix, the following steps are also included:

[0027] When the target chip is detected to be powered on stably and the clock is stable, the power-on reset signal is released.

[0028] Based on the configuration requirements of the target chip, determine whether to perform a latch operation on the boot pin, whether to perform a reset and release of the phase-locked loop, and whether to perform a read operation on the non-volatile memory upon power-up.

[0029] Optionally, the dynamic control dimension parameters in the reset matrix can be adjusted in real time through a preset dynamic configuration interface to perform reset adjustment and optimization on the target chip after tape-out, including:

[0030] Configuration values ​​are written to the function registers corresponding to the preset dynamic configuration interface, and the dynamic control dimension parameters in the reset matrix are adjusted in real time to reset, adjust and optimize the target chip after tape-out; each configuration parameter in the function register and the dynamic control dimension parameters correspond one-to-one.

[0031] Secondly, this application discloses a chip reset control device, comprising:

[0032] The matrix construction module is used to identify a target chip containing multiple functional modules and construct a reset matrix for the target chip based on the reset requirements of each functional module. The reset matrix is ​​used to define the reset control strategy of each functional module in the form of structured parameters.

[0033] The signal output module is used to load and parse the reset matrix to determine the reset trigger conditions of each functional module, and based on the reset trigger conditions, generate multi-level reset control signals that conform to the reset control strategy through a preset general reset control circuit.

[0034] The reset control module is used to distribute multi-level reset control signals to each functional module according to a preset reset timing sequence, so as to control each functional module to perform a reset operation.

[0035] The dynamic optimization module is used to adjust the dynamic control dimension parameters in the reset matrix in real time through a preset dynamic configuration interface, so as to perform reset adjustment and optimization on the target chip after tape-out.

[0036] Thirdly, this application discloses an electronic device, which includes a processor and a memory; wherein the memory is used to store a computer program, which is loaded and executed by the processor to implement the aforementioned chip reset control method.

[0037] Fourthly, this application discloses a computer-readable storage medium for storing a computer program; wherein the computer program, when executed by a processor, implements the aforementioned chip reset control method.

[0038] The beneficial technical effects of this application are as follows: By abstracting scattered and complex reset requirements into unified structured parameters and storing and managing them in matrix form, the complex reset logic that traditionally relied on manual coding is transformed into a configurable standardized process. Based on the reset control strategy defined in the matrix, the logic generation of the hardware control circuit is directly driven, reducing the workload of manual layer-by-layer design and avoiding logical omissions caused by human operation, thus significantly optimizing development efficiency. Furthermore, the structured parameters in the reset matrix realize a modular architecture, supporting rapid expansion and scenario switching. When adding a new functional module, the reset logic integration can be completed by expanding the matrix configuration entries; the same hardware architecture can adapt to reset strategies for different scenarios by adjusting the matrix parameters, significantly improving design reusability and scenario adaptability. In addition, a dynamically configurable interface is provided, supporting direct modification of dynamically controllable parameters in the reset matrix after tape-out. This provides a powerful and convenient backdoor for chip debugging, performance optimization, and fault diagnosis, shortening the problem localization cycle and enabling fine-tuning of reset characteristics for specific application scenarios.

[0039] In addition, the chip reset control device, equipment and storage medium provided in this application correspond to the above-mentioned chip reset control method and have the same effect. Attached Figure Description

[0040] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on the provided drawings without creative effort.

[0041] Figure 1 This is a flowchart of a chip reset control method disclosed in this application;

[0042] Figure 2 This is a schematic diagram of the implementation process of a reset matrix disclosed in this application;

[0043] Figure 3 This is a schematic diagram of a SoC chip reset control process disclosed in this application;

[0044] Figure 4 This is a schematic diagram of a general reset control circuit disclosed in this application;

[0045] Figure 5 This is a schematic diagram of a standardized power-on start-up control circuit disclosed in this application;

[0046] Figure 6 This is a schematic diagram of the structure of a chip reset control device disclosed in this application;

[0047] Figure 7 This is a structural diagram of an electronic device disclosed in this application. Detailed Implementation

[0048] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0049] Currently, reset management is crucial for the reliable startup and operation of SoCs. SoC chips typically require timing coordination across multiple modules and reset types. Manual design is prone to human error, such as timing mismatches and signal conflicts. The lack of unified timing management for multi-clock domain reset signals can easily lead to metastability or logic errors. Furthermore, as chip power-on processes become increasingly complex, the traditional handwritten reset release sequence and timing lack standardization, making manual implementation error-prone. Additionally, chip stability under extreme temperatures, voltage fluctuations, or load changes requires dynamically adjustable reset parameters (such as delay period and polarity), which traditional fixed logic cannot meet. These issues necessitate manually writing Register Transfer Level (RTL) code using traditional methods, resulting in long development cycles, high error rates, and a lack of flexibility in post-tapeupling debugging, making it difficult to quickly respond to changes in reset requirements.

[0050] Technical solutions for SoC reset management mainly fall into the following two categories, but they still have significant limitations:

[0051] 1. Based on manual coding, the reset logic design requires engineers to write RTL code line by line according to functional requirements and manually define the trigger conditions, timing relationships and synchronization logic of the reset signal. Its limitations are: (1) Low efficiency: The reset logic of complex SoCs needs to be completed in several weeks or even months, resulting in a long development cycle; (2) High error rate: Manual coding is prone to problems such as timing conflicts, signal omissions or inconsistent naming; (3) Difficult maintenance: The reset logic is scattered in the code, and global modifications are required when requirements change, which can easily lead to version confusion; (4) Lack of flexibility: Fixed logic is difficult to adapt to multiple scenario requirements.

[0052] 2. A solution based on modular reset control IP uses a predefined reset controller IP core (such as the ARMCore Sight reset module) and sets some reset parameters (such as delay time) through a configuration interface. Its limitations are: (1) Fixed function: The IP core supports a limited number of reset types and timing rules, which cannot be flexibly extended or adapted to complex requirements; (2) Insufficient cross-domain synchronization: Multi-clock domain reset synchronization relies on a fixed strategy, which is difficult to cope with dynamic clock frequency changes; (3) High integration complexity: It is necessary to manually connect the IP core and each functional module, which requires a large amount of interface matching work and is prone to errors.

[0053] To address this, this application provides a chip reset control scheme that reduces manual coding, eliminates the risk of timing conflicts in multi-clock domain reset signals, and ensures the reliability and consistency of the power-on reset process.

[0054] This invention discloses a chip reset control method, see [link to relevant documentation]. Figure 1 As shown, the method includes:

[0055] Step S11: Determine the target chip containing multiple functional modules, and construct a reset matrix for the target chip according to the reset requirements of each functional module; the reset matrix is ​​used to define the reset control strategy of each functional module in the form of structured parameters.

[0056] Reset management is crucial for the reliable startup and operation of chips containing multiple functional modules. The reset management process needs to meet timing coordination requirements under multiple modules and reset types, standardization requirements for complex power-up procedures, and dynamic parameter adjustment requirements under extreme environments. In this application embodiment, the target chip is illustrated using a System-on-a-Chip (SOC) chip. An SOC chip is an integrated circuit that integrates multiple functional modules, such as CPU, GPU, memory, communication modules, and power management, onto a single chip. Those skilled in the art will understand that the use of an SOC chip as the target chip is merely illustrative and does not limit the chip type described above. The following embodiments all use an SOC chip as an example for illustration, and will not be elaborated upon further.

[0057] In this embodiment, a reset matrix is ​​constructed by abstracting the reset requirements of each functional module in the chip into configurable parameters, thus abstracting the scattered and complex reset requirements into a structured and configurable parameter table. Reset requirements originate from the hardware characteristics and system-level design specifications of each functional module in the chip; they are descriptive goals to be achieved. For example, the CPU must be initialized after all peripherals are initialized before it can start, corresponding to a timing requirement; the DDR controller requires a low-level active reset signal, corresponding to a polarity requirement. Abstracting reset requirements into a unified structured parameter matrix allows for parameterized configuration instead of manual coding, significantly shortening the development cycle and reducing human error.

[0058] It should be noted that the reset matrix is ​​used to define the reset control strategy for each functional module in the form of structured parameters. This strategy is an executable, instruction-based scheme for implementing reset requirements. For example, to meet the timing requirements of the CPU, the strategy is: "Assign release order = 3 to the CPU, and release order = 2 to the peripherals"; to meet the polarity requirements of the DDR controller, the strategy is: "Configure the reset polarity field of the DDR controller to active low".

[0059] Step S12: Load and parse the reset matrix to determine the reset trigger conditions of each functional module, and based on the reset trigger conditions, generate multi-level reset control signals that conform to the reset control strategy through a preset general reset control circuit.

[0060] In this embodiment, the reset matrix is ​​loaded and parsed by a general-purpose hardware circuit. The configuration parameters of the reset matrix are implemented through standardized hardware logic circuits to automatically generate all multi-level reset control signals, replacing manual coding. It should be noted that the multi-level reset signals refer to a series of interrelated reset signals that have a temporal sequence and a global and local scope.

[0061] The preset general-purpose reset control circuit is a dedicated circuit module pre-hardened through hardware logic, used to parse the configuration parameters in the reset matrix and execute multi-level reset control signal processing. In this step, the reset trigger conditions of each functional module are determined by parsing the reset matrix, and these are used as inputs to the logic gates in the preset general-purpose reset control circuit. The reset request logic (AND gate / OR gate combination) in the control circuit determines which reset sources will trigger the reset of the corresponding functional module. The hardware circuit automatically generates response logic for different reset source requests, resulting in multi-level reset control signals. Its specific execution logic will be described in detail in the following embodiments of the invention, and will not be repeated here.

[0062] Step S13: Distribute multi-level reset control signals to each functional module according to the preset reset timing sequence to control each functional module to perform a reset operation.

[0063] In this embodiment, the preset reset timing can be obtained by parsing the reset matrix, thus clarifying the release order of multi-level reset control signals during the chip initialization phase. The preset reset timing can be determined by parsing the release order field of the timing dimension parameter in the parsing matrix.

[0064] According to the preset reset timing sequence, multi-level reset control signals are distributed to each functional module to control the reset operation of each functional module, ensuring precise control and high consistency of the reset and release timing between different functional modules. This fundamentally avoids system logic errors or metastability problems caused by timing conflicts or asynchronous resets, and enhances the reliability of chip startup and operation.

[0065] Step S14: Adjust the dynamic control dimension parameters in the reset matrix in real time through the preset dynamic configuration interface to reset, adjust and optimize the target chip after tape-out.

[0066] In this embodiment, to simplify the debugging and maintenance process, a preset dynamic configuration interface is provided. This interface supports real-time adjustment of dynamic control dimension parameters in the reset matrix via registers after tape-out, and supports chip debugging of reset delay and polarity, thereby achieving dynamic mapping between requirements and hardware. Timing can be optimized without hardware refactoring, reducing the complexity of fault location and repair.

[0067] In this embodiment, the dynamic control dimension parameters characterize the adjustability of the reset behavior. A bus-configurable function register, corresponding to the dynamic control dimension parameters, stores adjustable parameters such as independent reset requests, reset configurable permissions, and delay cycles for each functional module, mapping to the "independent reset," "configurable reset," and "delay cycle" components in the dynamic control dimension of the reset matrix. The system supports real-time adjustment of reset parameters via registers through a dynamic configuration interface, and post-tape-out reset adjustment and optimization are also supported via registers.

[0068] Specifically, configuration values ​​are written into the function registers corresponding to the preset dynamic configuration interface, and the dynamic control dimension parameters in the reset matrix are adjusted in real time to reset, adjust and optimize the target chip after tape-out; each configuration parameter in the function register and the dynamic control dimension parameters correspond one-to-one.

[0069] For example, dynamic control dimension parameters may include the following reset parameters:

[0070] 1. It will provide an independent reset request signal and a corresponding MASK masking signal according to the needs of each IP module. When the reset request is fulfilled, it will perform a reset operation to meet the individual reset requirements of the module.

[0071] 2. Since the reset matrix grants configurable reset permissions for each reset request, it can meet the needs of all reset sources through the combination of logic to complete the corresponding reset operation;

[0072] 3. Select a fixed delay or dynamic synchronization strategy based on the "synchronization mode" (hard synchronization / soft synchronization) in the reset matrix. The dynamic parameter function register provides the delay period value. In the post-tape-out stage, it supports real-time adjustment of the delay parameter through the register. By rewriting the delay register value, the wake-up time can be optimized, solving the problem of initialization failure caused by insufficient reset time in some modules.

[0073] By linking register data with reset matrix parameters, the registers dynamically adjust control dimension parameters (such as delay period) in real time to ensure signal stability under different operating conditions and improve system robustness. It can provide backdoor methods for easy observation of hardware behavior, rapid chip problem localization, and shorten the problem localization cycle. Post-tape fabrication reset dynamic optimization significantly improves chip reliability; it also allows for fine-tuning of reset characteristics for specific application scenarios, suitable for various differentiated situations. This systematically improves the efficiency of SOC reset design.

[0074] The beneficial technical effects of this application are as follows: By abstracting scattered and complex reset requirements into unified structured parameters and storing and managing them in matrix form, the complex reset logic that traditionally relied on manual coding is transformed into a configurable standardized process. Based on the reset control strategy defined in the matrix, the logic generation of the hardware control circuit is directly driven, reducing the workload of manual layer-by-layer design and avoiding logical omissions caused by human operation, thus significantly optimizing development efficiency. Furthermore, the structured parameters in the reset matrix realize a modular architecture, supporting rapid expansion and scenario switching. When adding a new functional module, the reset logic integration can be completed by expanding the matrix configuration entries; the same hardware architecture can adapt to reset strategies for different scenarios by adjusting the matrix parameters, significantly improving design reusability and scenario adaptability. In addition, a dynamically configurable interface is provided, supporting direct modification of dynamically controllable parameters in the reset matrix after tape-out. This provides a powerful and convenient backdoor for chip debugging, performance optimization, and fault diagnosis, shortening the problem localization cycle and enabling fine-tuning of reset characteristics for specific application scenarios.

[0075] like Figure 2 The diagram shows a flowchart of a reset matrix implementation provided in the above embodiments. It can be divided into three stages: initialization, reset execution, and post-reset. In the initialization stage, the reset matrix configuration is loaded, abstracting the reset requirements into configurable parameters. In the reset execution stage, the reset operation is performed through hardware circuitry according to the release order in the matrix. In the post-reset stage, the parameters in the reset matrix are dynamically optimized based on the matrix parameters to adapt to environmental changes. It is evident that the standardized process of "requirement modeling - timing control - dynamic optimization" reduces manual coding, eliminates the risk of timing conflicts in multi-clock domain reset signals, and ensures the reliability and consistency of the power-on reset process. This process method allows the system to quickly complete chip reset management, thereby greatly improving the efficiency and accuracy of reset design. Furthermore, as... Figure 3 The diagram illustrates a specific SOC chip reset control flow. A reset matrix is ​​constructed by abstracting the chip's reset requirements into configurable parameters. This reset matrix serves as the core driver, based on a standardized power-on startup process, and is controlled by a general-purpose reset hardware circuit. Hardware logic is used to combine and synchronize reset requests. The dynamic configuration interface supports real-time adjustment of reset parameters via registers and allows for chip debugging of reset delay and polarity, thereby achieving dynamic mapping between requirements and hardware.

[0076] Based on the above embodiments, in one feasible implementation, the power-on startup is the chip initialization and configuration loading stage. Only when the power supply stability and clock signal validity are met, and the basic conditions are met to start the chip, can the reset parameters and timing be adjusted in real time by dynamically responding to changes in the conditions of the functional modules (such as environmental fluctuations, hardware failures, load requirements, etc.). At this time, the release order, function, timing, and dynamic control parameters in the reset matrix configuration can be executed by the hardware.

[0077] Considering the complex condition changes of functional modules during the power-on process of an SOC chip, this embodiment provides a standardized process of state and transition conditions. Based on the actual situation of each functional module, the power-on configuration information requirements are analyzed to form a configurable power-on startup control circuit process. Since the direct mapping relationship between the reset matrix parameters and hardware logic has been established in the aforementioned embodiments, based on the power-on conditions set according to requirements in this embodiment, the process results are organized and encapsulated and returned to a visual graphical interface. This allows users to intuitively view the required power-on reset information, check the state and transition conditions, and facilitate subsequent dynamic adjustments. Specifically, the prerequisite and preparation stage for performing the reset operation may also include the following steps:

[0078] When the target chip is detected to be powered on stably and the clock is stable, the power-on reset signal is released.

[0079] Based on the configuration requirements of the target chip, determine whether to perform a latch operation on the boot pin, whether to perform a reset and release of the phase-locked loop, and whether to perform a read operation on the non-volatile memory upon power-up.

[0080] Combination Figure 4The process involves several steps. First, after the chip powers on and the system reference clock stabilizes, the power-on reset is released. If the power-on bootloader is involved in the startup process, a latch operation is performed on the bootstrap pins during power-on. This ensures that the chip can correctly read and lock the configuration values ​​of these pins during startup, thereby determining the chip's operating mode or initialization parameters. Next, it checks if a Phase-Locked Loop (PLL) startup is required. A PLL is a feedback control circuit, an oscillating circuit that outputs a signal at a specific frequency. A PLL can be used to synchronize external input signals with internal oscillation signals. If the PLL is involved in the startup process, the PLL reset must be released first, and the PLL will then start working to provide the chip's actual operating clock. Then, it checks if there is a need to read non-volatile memory (efuse). efuse can be used to store data for memory repair or to store chip information, such as the chip's usable power supply voltage, chip version number, production date, and key configuration information. After the chip is manufactured, it is tested, and the chip's information is written to efuse. If efuse is involved in the startup process, upon power-up, the chip needs to read the corresponding information from the memory repair efuse and the functional efuse respectively, and complete the efuse reading according to the power-up requirements.

[0081] After the prerequisite and preparation phases are completed, the next step is to parse and execute the configuration in the loaded reset matrix, thereby generating and distributing multi-level reset control signals that conform to the control strategy, ultimately controlling each functional module to perform reset and release operations. For example... Figure 4 As shown, after completing the efuse read, according to the release order in the reset matrix, the peripherals and subsystems are released first. The reset interval between the peripherals and the CPU is adjusted according to the dynamic control dimension parameters to ensure compliance with chip safety requirements. Then, the processor module's reset signal is released, allowing the CPU to send commands for secure access to the released peripherals and subsystems. During CPU operation, the system continuously monitors for reset requests. If a reset request occurs, all working modules are reset under that request. Once the reset request is withdrawn, the system returns to the reset release state of the peripherals and subsystems. If there is no reset request, the system remains in a working state, and the CPU can continuously send commands for access.

[0082] As can be seen, this embodiment provides the release order of reset signals for each functional module on the chip, analyzes the "release order" in the timing dimension parameters of the reset matrix, and generates multi-level reset control signals to meet the requirements of timing control standardization. Specifically, this includes: whether the chip needs power-on boot, whether a PLL module is involved, whether there is an efuse requirement, the CPU reset release interval, and whether the system has related reset requests. In this way, through the standard power-on process of the SOC chip, it is ensured that the reset signals of each module are released safely and reliably according to the release order defined by the matrix when the chip powers on. This allows engineers of different experience levels to quickly and accurately complete high-quality reset designs based on this matrix, reducing over-reliance on the experience of senior engineers and simplifying subsequent testing, maintenance, and transfer costs.

[0083] Based on the above embodiments, this embodiment will describe the specific implementation details of constructing the reset matrix in the above embodiments. Specifically, according to the functional module requirements of the SOC chip (such as CPU, peripherals, and debugging modules), the reset requirements are abstracted into configurable parameters from three dimensions: function, timing, and dynamic control. The reset matrix contains the following key fields, and the specific configuration principles are as follows:

[0084] 1. Functional Dimension: This includes reset type and reset trigger condition. The reset type is a configuration parameter defining the reset scope, including global reset and local reset. The reset trigger condition is a configuration parameter defining the reason for initiating the reset operation. This parameter specifies the events or conditions (such as power-on, watchdog timeout, software write, debug request, etc.) under which a reset needs to be initiated to the target module. This solves the problem of "under what circumstances is a reset necessary?"

[0085] Global reset: This is usually assigned to core modules (such as CPU and power management unit), and the trigger condition is power-on reset to ensure the initialization of basic system functions.

[0086] Partial reset: Used for peripherals or subsystems (such as GPUs, network controllers). Triggering conditions may include software reset, debug reset, etc., to achieve on-demand reset.

[0087] 2. Timing dimension: including release order and synchronization mode; where:

[0088] Release order: This is a configuration parameter used to define the preset reset timing, assigning different priority values ​​to each functional module regarding the order in which reset signals are released. In one feasible implementation, smaller values ​​indicate higher priority, and their reset signals are released first. For example, critical modules (such as power management and clock generators) should be set to high priority (release order = 1); peripherals (such as USB and SPI) should be set to medium priority (release order = 2); and the processor (CPU) should be set to low priority (release order = 3) to prevent the CPU from accessing peripherals that are not yet ready, ensuring the CPU's safe access to peripherals at all levels.

[0089] Synchronization Mode: This is a configuration parameter used to define the synchronization strategy for cross-clock domain reset signals. It specifies how asynchronous reset requests are safely and stably synchronized to the target module's local clock domain. The strategy selection (e.g., hard synchronization / soft synchronization) directly determines the behavior of subsequent delay cycles and is a critical part of timing control. Synchronization modes include hard synchronization and soft synchronization; hard synchronization is suitable for modules with fixed clock frequencies, such as DDR controllers that always operate at 100MHz; soft synchronization is suitable for modules with dynamically adjusted clock frequencies, such as CPU cores that switch clock frequencies based on load.

[0090] 3. Dynamic control dimension: Used to control the behavior of the reset signal during operation, including one or more of the following: reset polarity, independent reset, delay period, and reset configurable permissions.

[0091] Reset Polarity: This is a configuration parameter used to define the valid level of the reset signal. This parameter specifies at what level the reset signal output to the target module is valid (e.g., active low or active high). It must match the hardware design of the functional module (e.g., if a module requires a low-level reset, it is configured to be active low) to ensure correct matching between the reset control logic and the module's physical interface.

[0092] Independent Reset: Independent reset is a configuration parameter used to define the independent reset of a functional module. It provides an independent reset request for the module and a corresponding independent reset MASK signal. When debugging a target functional module, it allows the module to be reset independently without affecting the operating status of other modules in the system, providing flexibility for debugging and fault isolation.

[0093] Delay period: This is a configuration parameter specifying the number of clock cycles required for the reset signal to activate or release according to the synchronization mode configuration. This parameter reflects the adjustability of the reset behavior. It can be a fixed value, used in hard synchronization mode, such as a delay period of 15 cycles; or it can be a dynamically adjustable range or value, used in soft synchronization mode, such as a delay period that can be set to a dynamic range of 5 to 20 cycles, adjusted in real time by runtime environmental parameters (temperature, voltage).

[0094] Reset Configurable: This is a permission configuration parameter used to characterize whether the response to a reset source can be configured. This parameter defines whether, during chip operation, its response capability to a specific reset source (such as watchdog reset or software reset) can be modified through registers. It provides configurable permissions for reset requests and, through the cooperation of combinational logic, is compatible with the needs of all reset sources to complete the corresponding reset operation. It realizes dynamic management of reset trigger conditions.

[0095] Based on the above requirements, Table 1 provides an example format for the reset matrix configuration:

[0096] Table 1. Reset Matrix Configuration Example

[0097]

[0098] As can be seen, the structured configuration of the reset matrix abstracts traditionally scattered reset requirements into a unified structured parameter matrix through three dimensions: function, timing, and dynamic control. This matrix includes fields such as module ID, reset type, trigger condition, release order, synchronization mode, reset polarity, and delay period, achieving a direct mapping from requirements to hardware. Replacing manual coding with matrix configuration improves reset management efficiency, solves problems of low design efficiency and poor consistency, and significantly reduces iteration costs when adding new functional modules—only matrix entries need to be expanded without modifying the core logic.

[0099] Furthermore, after constructing the reset matrix, the process of loading and parsing the reset matrix to determine the reset trigger conditions for each functional module may include the following steps:

[0100] Establish a mapping relationship between different reset sources and each functional module;

[0101] Load and parse the reset matrix, and determine the identifier content to be filled in the mapping relationship based on the reset type in the reset matrix; the identifier content is an identifier in the form of a logical formula used to determine whether the functional module is triggered by the reset source.

[0102] Based on the mapping relationship and the identification content, the reset trigger conditions for each functional module are determined.

[0103] In this embodiment, the reset triggering conditions are configured in the form of a logical table to define the mapping relationship between different reset sources and the functional modules that need to be reset. The columns of the logical table represent different reset source events, the rows represent different functional modules, and the values ​​in the table are used to identify whether a specific reset source event triggers the reset of a specific functional module.

[0104] When parsing the reset matrix, it is first necessary to analyze the functional dimensions of the reset. The functions of the reset signal include initializing system registers, restoring system state, and restarting the system in case of system abnormality. The output level value of the reset signal must be a definite signal. Based on the reset type, the reset range corresponding to the module ID can be preliminarily determined. Only when the reset type is a local reset, the module reset and reset request in the trigger conditions are abstracted into configurable parameters according to the reset requirements.

[0105] In this embodiment, CNF (Conjunctive Normal Form) is used as a logical formula representation, defined as the parsing rule for reset trigger conditions. Assuming R represents a need to be reset and U represents no reset, R / U is the abstracted configurable parameter. Local reset requests include, for example, power-on reset, watchdog (WDT) reset, software (SW) reset, CPU self-reset, debug reset, etc., which can be extended to any reset type in the SOC system. Different reset requests correspond to different reset ranges. In fact, a module ID can be associated with multiple rows of trigger conditions, allowing multiple reset source requests. Therefore, the trigger conditions are split into independent parsing tables, listing different reset sources and their attributes. Table 2 shows an example of a reset trigger condition parsing.

[0106] Table 2 Example of Reset Trigger Condition Analysis

[0107]

[0108] Analysis of the two reset module requirements above:

[0109] 1. Since the reset type of IP0 is global, IP0 is only affected by power-on reset;

[0110] 2. By default, all IP modules on the chip must be affected by power-on reset, so IP1 is no exception;

[0111] 3. Since the reset type of IP1 is local, it is affected by watchdog (WDT) reset and software (SW) reset, but not by CPU self-reset or debug reset.

[0112] Furthermore, due to inconsistent understandings of reset requirements among engineers, and given that the internal reset of the SOC chip in this application strictly relies on the reset matrix, to prevent human-caused misconfiguration of the reset matrix from causing the generated reset design to malfunction in actual hardware, a feasible implementation provides a self-checking function for the reset matrix. This function checks the correctness of data types, logical conflicts, and rule checks, ensuring that the generated reset matrix meets design requirements. Specifically, after constructing the reset matrix, the implementation also includes: performing a self-check on the reset matrix based on preset dependency constraint rules. This mainly includes the following parts:

[0113] Based on experience in reset design, this embodiment provides dependency constraints between fields in the reset matrix configuration. By defining the logical constraint relationships between fields, the legality and consistency of the configuration are ensured.

[0114] 1. Global Reset: Power-on reset is the trigger condition for global reset. By default, when triggered by power-on reset, all module IDs must be forcibly reset; the release order must be the minimum value (≤2) in the entire table and unique.

[0115] 2. Partial Reset: Multiple trigger conditions can be associated with the same module ID, supporting watchdog (WDT), software (SW), CPU self-reset, and debug reset. Partial resets need to be allocated in a release order (≥2) according to functional dependencies. Different module IDs can share the same release order. Special reset scope: CPU self-reset can only reset the CPU processor itself, and the debug subsystem is only affected by independent resets.

[0116] 3. Independent Reset: Must be configured separately through the "Independent Reset" field in the matrix configuration (e.g., triggered by the debug interface);

[0117] 4. Synchronization Mode: Global reset only supports hard synchronization; local reset can select hard / soft synchronization. If the synchronization mode is "soft synchronization", the delay period must be within the dynamic range.

[0118] 5. Configurable permissions: The global reset module must be set to "fixed" and can only be viewed (such as the power-on reset of the global reset); the local reset module can be dynamically adjusted, and engineers can modify the shielding status;

[0119] 6. Delay period: Hard synchronization requires a fixed value; soft synchronization can be a fixed value or a dynamic range.

[0120] Based on the dependency constraints between the fields in the reset matrix configuration, Table 3 provides a standard reset matrix configuration that can be directly applied to the SOC system, and Table 4 provides a standard reset trigger condition that can be directly applied to the SOC system, to help general engineers quickly complete the basic reset configuration.

[0121] Table 3 Standard configurations of reset matrices that can be directly applied to SOC systems

[0122]

[0123] Table 4. Standard reset trigger conditions that can be directly applied to the SOC system

[0124]

[0125] Furthermore, the self-checking process includes data type validation, logical conflict validation, and runtime rule checks, for example:

[0126] 1. Data Type Validation: The release order must be a positive integer, and the delay period must be a number or a dynamic identifier (such as "dynamic"). Example: If you enter the text "A" in the "Delay Period" column, the tooltip will say "Illegal input, must be a number or dynamic."

[0127] 2. Logical conflict verification: If the trigger condition for global reset is set to "module request", the tool prompts "Global reset trigger condition is illegal"; if the release order of local reset is set to 1, the tool prompts "Local reset priority must not be higher than global".

[0128] 3. Runtime rule checks: Global reset uniqueness: If multiple global reset modules have the same release order, the message "Global reset release order must be unique" will be displayed. Soft synchronization dynamic compatibility: If the synchronization mode is soft synchronization but the delay period is a fixed value, the "dynamic" identifier must be added or the system must be switched to hard synchronization.

[0129] In one feasible implementation, user-defined reset trigger conditions and reset matrix fields are supported, extending the reset control strategy. For experienced engineers, user-defined rule extensions can be added. For example, for new PCIe hot and link-down reset requirements on the chip, as shown in Tables 5 and 6, extended configurations can be derived based on the matrix rules.

[0130] Table 5 User-defined PCIE_Ctrl reset matrix configuration

[0131]

[0132] Table 6 User-defined PCIE_Ctrl reset trigger conditions

[0133]

[0134] The above configuration method based on the reset matrix effectively lowers the technical threshold, ensuring that senior engineers and ordinary engineers output designs of equal quality. It can also include the following operational procedures:

[0135] 1. Operating procedures for general engineers:

[0136] Standard Reset Configuration: Refer to Tables 3 and 4 above for the standard reset matrix configuration and standard reset trigger condition configuration that can be directly applied to complete the standard reset configuration;

[0137] Dependency constraint guidance: Matrix automatically suggests dependencies between fields;

[0138] Self-check correction: Correct errors based on matrix self-check prompts and submit configuration.

[0139] 2. Operating procedures for senior engineers:

[0140] Configure the reset matrix: Based on module requirements and dependency constraints, match basic fields such as module ID, reset type, and trigger conditions to complete the reset matrix configuration and reset trigger condition configuration.

[0141] Custom rule extensions: Select extension requirements from the predefined rule library (such as "Add reset trigger condition").

[0142] As can be seen, this embodiment supports rule self-checking and user-defined extensions. By resetting the matrix dependency constraint rules to achieve self-checking of configuration rules, the technical threshold is effectively lowered, ensuring that senior engineers and ordinary engineers output designs of equal quality. Support for custom rule extensions facilitates early reviews of system architecture and design.

[0143] Based on the above embodiments, and according to the aforementioned reset triggering conditions, the reset requirements of each module are analyzed. The general reset control circuit (RESET_COMMON) is driven by structured parameters to achieve corresponding control over various reset sources, responding to various reset requests from the source. For example... Figure 5 The diagram shows the hardware logic of the preset general-purpose reset control circuit RESET_COMMON, which includes reset request logic, asynchronous reset synchronizer, reset output logic, and dynamic polarity control. Specifically, the process of generating multi-level reset control signals conforming to the reset control strategy through the preset general-purpose reset control circuit based on reset trigger conditions can include the following steps:

[0144] Step 1: Receive the reset source signal from the target chip and generate reset requests for each functional module according to the reset trigger conditions.

[0145] In this embodiment, the reset request logic mainly receives a combination of reset source (power-on, watchdog, software, etc.) trigger conditions, specifically the reset trigger condition configuration in the reset matrix. It determines whether a reset operation corresponding to the reset request is required based on these conditions. If the reset request is valid, the module performs a reset; if the reset request is invalid, the module's reset output is maintained. The reset request logic is composed of an AND / OR gate combination circuit, receiving external reset sources and matrix configuration parameters. In the reset trigger condition configuration, other reset sources besides power-on reset are enabled or disabled through configuration registers.

[0146] Step 2: Based on the synchronization mode configured in the reset matrix, perform cross-clock domain synchronization processing on the reset request to output a synchronized reset signal.

[0147] In this embodiment, an asynchronous reset synchronizer is used to handle the synchronization of reset signals across clock domains. A fixed delay or dynamic synchronization strategy is selected based on the "synchronization mode" (hard synchronization / soft synchronization) in the reset matrix. The delay period value can be provided through a function register (dynamic parameter register). Hard synchronization: Signal synchronization is achieved using a fixed-length shift register chain (e.g., a delay of 10 cycles). Soft synchronization dynamically calculates the delay period based on the current clock frequency, implemented through a configurable counter, which is provided by the dynamic configuration interface.

[0148] Step 3: Generate a reset output signal that conforms to the preset reset timing based on the synchronized reset signal and the release order configured in the reset matrix.

[0149] In this embodiment, the reset output logic completes the reset operation after the reset request logic output takes effect; on the other hand, it completes the reset release according to the release sequence of the power-on startup standardized process output, and provides a reset output pre-signal to the dynamic polarity control.

[0150] Step 4: Adjust the polarity of the reset output signal according to the reset polarity configured in the reset matrix to generate a multi-level reset control signal that conforms to the hardware design of the functional module.

[0151] In this embodiment, dynamic polarity control is used to adjust the reset output preamplifier signal according to the "Reset Polarity" field (high / low active) in the reset matrix. It internally includes a polarity inversion circuit to generate the final reset signal and distribute it to each functional module. The output range (global / local) is determined based on the "Module ID" and "Reset Type" in the reset matrix.

[0152] As can be seen, this embodiment uses structured parameters to drive hardware logic, realizing reset request processing, synchronization, output, and polarity control, significantly improving the efficiency, reliability, and flexibility of chip reset control design. It is suitable for various complex SOC application scenarios and has broad application prospects. By improving design efficiency, reducing human error, enhancing flexibility, improving maintainability, optimizing timing control, and supporting combinations of multiple reset types, it provides an efficient, flexible, and reliable system reset management design solution for SOC design.

[0153] Based on the aforementioned embodiments, in one feasible implementation, this solution can be optimized from three dimensions: dynamic intelligent adaptation, cross-scenario compatibility, and design automation. For example, regarding dynamic intelligent adaptation, machine learning algorithms can be introduced to construct a dynamic optimization model for target reset parameters (such as delay period and synchronization strategy) in the reset matrix by real-time collection of environmental parameters such as temperature, voltage, and load during chip operation. For instance, when the chip is detected to be in a high-temperature environment for an extended period, the reset delay period of key modules is automatically increased to avoid initialization failure, achieving self-learning and self-adjustment of the reset strategy and overcoming the limitations of traditional fixed parameter configuration. For example, regarding cross-scenario compatibility, a multi-mode reset matrix switching mechanism can be designed, with pre-set differentiated reset rule templates for different application scenarios. By reading the scenario identifier stored in efuse when the chip is powered on, the corresponding template is automatically loaded, allowing for rapid adaptation to multi-domain requirements without hardware refactoring and improving the universality of the solution. For example, regarding design automation, a seamless interface between the reset matrix and EDA tools can be developed to directly convert matrix configuration parameters into synthesizable RTL code, while integrating an automated verification module to perform full-process detection of timing conflicts and synchronization risks in the generated reset logic.

[0154] Accordingly, this application also discloses a chip reset control device, see [link to relevant documentation]. Figure 6 As shown, the device includes:

[0155] The matrix construction module 11 is used to determine the target chip containing multiple functional modules and construct a reset matrix for the target chip according to the reset requirements of each functional module; the reset matrix is ​​used to define the reset control strategy of each functional module in the form of structured parameters.

[0156] The signal output module 12 is used to load and parse the reset matrix to determine the reset trigger conditions of each functional module, and based on the reset trigger conditions, generate multi-level reset control signals that conform to the reset control strategy through a preset general reset control circuit.

[0157] The reset control module 13 is used to distribute multi-level reset control signals to each functional module according to a preset reset timing sequence, so as to control each functional module to perform a reset operation.

[0158] The dynamic optimization module 14 is used to adjust the dynamic control dimension parameters in the reset matrix in real time through a preset dynamic configuration interface, so as to perform reset adjustment and optimization on the target chip after tape-out.

[0159] For more detailed information on the working process of each of the above modules, please refer to the relevant content disclosed in the foregoing embodiments, which will not be repeated here.

[0160] Therefore, the above-described solution in this embodiment abstracts scattered and complex reset requirements into unified structured parameters, which are stored and managed in matrix form. This transforms the complex reset logic, which traditionally relied on manual coding, into a configurable and standardized process. Based on the reset control strategy defined in the matrix, the logic generation of the hardware control circuit is directly driven, reducing the workload of manual layer-by-layer design and avoiding logical oversights caused by human operation, thus significantly optimizing development efficiency. Furthermore, the structured parameters in the reset matrix enable a modular architecture, supporting rapid expansion and scenario switching. When adding a new functional module, reset logic integration can be completed by expanding the matrix configuration entries; the same hardware architecture can adapt to reset strategies for different scenarios by adjusting matrix parameters, significantly improving design reusability and scenario adaptability. In addition, a dynamically configurable interface is provided, supporting direct modification of dynamically controllable parameters in the reset matrix after tape-out. This provides a powerful and convenient backdoor for chip debugging, performance optimization, and fault diagnosis, shortening the problem localization cycle and enabling fine-tuning of reset characteristics for specific application scenarios.

[0161] In one specific implementation, the matrix construction module 11 is specifically used for:

[0162] Based on the reset requirements of each functional module, a reset matrix is ​​constructed for the target chip, including functional dimension parameters, timing dimension parameters, and dynamic control dimension parameters.

[0163] In one specific implementation, the signal output module 12 includes a loading and parsing module, used for:

[0164] Establish a mapping relationship between different reset sources and each functional module;

[0165] Load and parse the reset matrix, and determine the identifier content to be filled in the mapping relationship based on the reset type in the reset matrix; the identifier content is an identifier in the form of a logical formula used to determine whether the functional module is triggered by the reset source.

[0166] Based on the mapping relationship and the identification content, the reset trigger conditions for each functional module are determined.

[0167] Signal output unit, used for:

[0168] Receive the reset source signal from the target chip and generate reset requests for each functional module according to the reset trigger conditions;

[0169] Based on the synchronization mode configured in the reset matrix, the reset request is processed for cross-clock domain synchronization in order to output a synchronized reset signal.

[0170] Based on the synchronized reset signal and the release order configured in the reset matrix, a reset output signal conforming to the preset reset timing is generated;

[0171] Based on the reset polarity configured in the reset matrix, the polarity of the reset output signal is adjusted to generate a multi-level reset control signal that conforms to the hardware design of the functional module.

[0172] In one specific embodiment, the chip reset control device further includes:

[0173] The self-test module is used to perform a self-test on the reset matrix based on preset dependency constraint rules; the self-test process includes data type verification, logical conflict verification, and runtime rule checking.

[0174] The initialization module is used to release the power-on reset signal when the target chip is detected to be powered on stably and the clock is stable. According to the configuration requirements of the target chip, it determines whether to perform latching operation of the boot pin, whether to perform reset release of the phase-locked loop, and whether to perform read operation of non-volatile memory at power-on.

[0175] In one specific implementation, the dynamic optimization module 14 is specifically used for:

[0176] Configuration values ​​are written to the function registers corresponding to the preset dynamic configuration interface, and the dynamic control dimension parameters in the reset matrix are adjusted in real time to reset, adjust and optimize the target chip after tape-out; each configuration parameter in the function register and the dynamic control dimension parameters correspond one-to-one.

[0177] Furthermore, embodiments of this application also disclose an electronic device, Figure 7 This is a structural diagram of an electronic device 20 according to an exemplary embodiment. The content of the diagram should not be construed as limiting the scope of this application.

[0178] Figure 7 This is a schematic diagram of the structure of an electronic device 20 provided in an embodiment of this application. The electronic device 20 may specifically include: at least one processor 21, at least one memory 22, a power supply 23, a communication interface 24, an input / output interface 25, and a communication bus 26. The memory 22 stores a computer program, which is loaded and executed by the processor 21 to implement the relevant steps in the chip reset control method disclosed in any of the foregoing embodiments.

[0179] In this embodiment, the power supply 23 is used to provide operating voltage for each hardware device on the electronic device 20; the communication interface 24 can create a data transmission channel between the electronic device 20 and external devices, and the communication protocol it follows can be any communication protocol applicable to the technical solution of this application, and is not specifically limited here; the input / output interface 25 is used to acquire external input data or output data to the outside world, and its specific interface type can be selected according to specific application needs, and is not specifically limited here.

[0180] In addition, the memory 22, as a carrier for resource storage, can be a read-only memory, random access memory, disk, or optical disk, etc. The resources stored on it can include an operating system 221, computer programs 222, and data 223, etc. The data 223 can include various types of data. The storage method can be temporary storage or permanent storage.

[0181] The operating system 221 is used to manage and control the various hardware devices on the electronic device 20 and the computer program 222, which may be Windows Server, Netware, Unix, Linux, etc. In addition to including a computer program capable of performing the chip reset control method executed by the electronic device 20 as disclosed in any of the foregoing embodiments, the computer program 222 may further include a computer program capable of performing other specific tasks.

[0182] Furthermore, this application also discloses a computer-readable storage medium, which includes random access memory (RAM), main memory, read-only memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, registers, hard disks, magnetic disks, optical disks, or any other form of storage medium known in the art. When a computer program is executed by a processor, it implements the aforementioned chip reset control method. The specific steps of this method can be found in the corresponding content disclosed in the foregoing embodiments, and will not be repeated here.

[0183] Furthermore, embodiments of this application also provide a computer program product, including a computer program / instruction, which, when executed by a processor, implements any of the above-described chip reset control methods.

[0184] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on its differences from other embodiments. Similar or identical parts between embodiments can be referred to interchangeably. For the apparatus disclosed in the embodiments, since it corresponds to the method disclosed in the embodiments, the description is relatively simple; relevant parts can be referred to in the method section.

[0185] The steps of the chip reset control method or algorithm described in conjunction with the embodiments disclosed herein can be implemented directly by hardware, a software module executed by a processor, or a combination of both. The software module can be located in random access memory (RAM), main memory, read-only memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, registers, hard disk, removable disk, CD-ROM, or any other form of storage medium known in the art.

[0186] Finally, it should be noted that in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes the element.

[0187] The chip reset control method, apparatus, device, and medium provided by the present invention have been described in detail above. Specific examples have been used to illustrate the principle and implementation of the present invention. The description of the above embodiments is only for the purpose of helping to understand the method and core idea of ​​the present invention. At the same time, for those skilled in the art, there will be changes in the specific implementation and application scope based on the idea of ​​the present invention. Therefore, the content of this specification should not be construed as a limitation of the present invention.

Claims

1. A chip reset control method, characterized in that, include: A target chip containing multiple functional modules is identified, and a reset matrix is ​​constructed for the target chip according to the reset requirements of each functional module; the reset matrix is ​​used to define the reset control strategy of each functional module in the form of structured parameters. The reset matrix is ​​loaded and parsed to determine the reset trigger conditions of each functional module, and based on the reset trigger conditions, a multi-level reset control signal conforming to the reset control strategy is generated through a preset general reset control circuit. The multi-level reset control signal is distributed to each of the functional modules according to the preset reset timing sequence, so as to control each of the functional modules to perform a reset operation; By using a preset dynamic configuration interface, the dynamic control dimension parameters in the reset matrix can be adjusted in real time to reset, adjust, and optimize the target chip after tape-out.

2. The chip reset control method according to claim 1, characterized in that, The step of constructing a reset matrix for the target chip based on the reset requirements of each functional module includes: Based on the reset requirements of each functional module, a reset matrix is ​​constructed for the target chip, including functional dimension parameters, timing dimension parameters, and dynamic control dimension parameters; wherein, The functional dimension parameters include reset type and reset trigger condition. The reset type is a configuration parameter used to define the reset range, and the reset trigger condition is a configuration parameter used to define the reason for initiating the reset operation. The timing dimension parameters include release order and synchronization mode. The release order is a configuration parameter used to define the preset reset timing, and the synchronization mode is a configuration parameter used to define the cross-clock domain reset signal synchronization strategy. The dynamic control dimension parameters are configuration parameters used to control the runtime behavior of the reset signal, including one or more of reset polarity, independent reset, delay period, and reset configurable permission. The reset polarity is a configuration parameter used to define the effective level of the reset signal. The independent reset is a configuration parameter used to define that the functional module can be reset independently. The delay period is a configuration parameter that specifies the number of clock cycles required for the reset signal to be activated or released according to the synchronization mode. The reset configurable permission is a permission configuration parameter used to characterize whether the response of the reset source can be configured.

3. The chip reset control method according to claim 2, characterized in that, Load and parse the reset matrix to determine the reset trigger conditions for each functional module, including: Establish a mapping relationship between different reset sources and each of the aforementioned functional modules; Load and parse the reset matrix, and determine the identifier content to be filled in the mapping relationship according to the reset type in the reset matrix; the identifier content is an identifier in the form of a logical formula used to determine whether the functional module is triggered by the reset source; Based on the mapping relationship and the identification content, the reset trigger conditions for each of the functional modules are determined.

4. The chip reset control method according to claim 1, characterized in that, After constructing a reset matrix for the target chip according to the reset requirements of each functional module, the method further includes: The reset matrix is ​​self-checked based on preset dependency constraint rules; the self-check process includes data type verification, logical conflict verification and runtime rule checking.

5. The chip reset control method according to claim 2, characterized in that, Based on the reset triggering conditions, a multi-level reset control signal conforming to the reset control strategy is generated through a preset universal reset control circuit, including: Receive the reset source signal from the target chip, and generate reset requests for each of the functional modules according to the reset trigger conditions; According to the synchronization mode configured in the reset matrix, the reset request is processed for cross-clock domain synchronization to output a synchronized reset signal; Based on the synchronized reset signal and the release order configured in the reset matrix, a reset output signal conforming to the preset reset timing is generated; The polarity of the reset output signal is adjusted according to the reset polarity configured in the reset matrix to generate a multi-level reset control signal that conforms to the hardware design of the functional module.

6. The chip reset control method according to claim 1, characterized in that, Before loading and parsing the reset matrix, the process also includes: When the target chip is detected to be powered on stably and the clock is stable, the power-on reset signal is released. Based on the configuration requirements of the target chip, determine whether to perform a latching operation on the boot pin, whether to perform a reset and release of the phase-locked loop, and whether to perform a read operation on the non-volatile memory upon power-up.

7. The chip reset control method according to any one of claims 1 to 6, characterized in that, The step of adjusting the dynamic control dimension parameters in the reset matrix in real time through a preset dynamic configuration interface to perform reset adjustment and optimization on the target chip after tape-out includes: Configuration values ​​are written into the function register corresponding to the preset dynamic configuration interface, and the dynamic control dimension parameters in the reset matrix are adjusted in real time to reset, adjust and optimize the target chip after tape-out; each configuration parameter in the function register corresponds one-to-one with the dynamic control dimension parameters.

8. A chip reset control device, characterized in that, include: A matrix construction module is used to determine a target chip containing multiple functional modules and construct a reset matrix for the target chip according to the reset requirements of each functional module; the reset matrix is ​​used to define the reset control strategy of each functional module in the form of structured parameters. The signal output module is used to load and parse the reset matrix to determine the reset trigger conditions of each functional module, and based on the reset trigger conditions, generate a multi-level reset control signal that conforms to the reset control strategy through a preset general reset control circuit. A reset control module is used to distribute the multi-level reset control signals to each of the functional modules according to a preset reset timing sequence, so as to control each of the functional modules to perform a reset operation; The dynamic optimization module is used to adjust the dynamic control dimension parameters in the reset matrix in real time through a preset dynamic configuration interface, so as to perform reset adjustment and optimization on the target chip after tape-out.

9. An electronic device, characterized in that, The electronic device includes a processor and a memory; wherein the memory is used to store a computer program, which is loaded and executed by the processor to implement the chip reset control method as described in any one of claims 1 to 7.

10. A computer-readable storage medium, characterized in that, Used to store computer programs; wherein the computer programs, when executed by a processor, implement the chip reset control method as described in any one of claims 1 to 7.

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