Stacked wafer and manufacturing method thereof

Abstract

To provide a laminated wafer in which an intermediate layer between a single crystal silicon substrate and a single crystal silicon layer has high etching selectivity with respect to the single crystal silicon layer, and that has high conductivity.SOLUTION: A laminated wafer 100 according to the present invention includes a single crystal silicon substrate 10, a polycrystalline diamond layer 16 formed on the single crystal silicon substrate 10, and a single crystal silicon layer 26 formed on the polycrystalline diamond layer 16, and the monocrystalline silicon substrate 10 has a resistivity of 10 Ω cm or less, and the polycrystalline diamond layer 16 contains boron and has a resistivity of 0.001 Ω cm or more and 1000 Ω cm or less.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to a laminated wafer in which a polycrystalline diamond layer and a single crystal silicon layer are laminated in this order on a single crystal silicon substrate, and to a method for manufacturing the same. [Background technology]

[0002] Regarding MEMS (Micro Electro Mechanical Systems) devices, high added value is being considered from various perspectives, from device process flow to circuit design. For example, it is being considered to aim for high sensitivity and low cost by forming a composite device by forming a MEMS device and a CMOS circuit on a single chip on a silicon wafer.

[0003] When an acceleration sensor (MEMS sensor), which is a type of MEMS device, is fabricated on a single chip on a silicon wafer together with a CMOS circuit, it is necessary to form a cavity under the MEMS sensor. In this case, it is considered to use an SOI wafer having an SOI (Silicon on Insulator) structure as the silicon wafer. The SOI wafer has a structure in which an insulating layer (BOX layer) made of a silicon oxide film and a single crystal silicon layer (active layer) are formed in sequence on a single crystal silicon substrate (support substrate). In this case, as shown in the upper diagram of Figure 4, the BOX layer becomes the cavity region under the MEMS sensor. However, since the silicon oxide film of the BOX layer has high insulating properties, the active layer is insulated from the support substrate, and during plasma processing in the device process (e.g., reactive ion etching, resist ashing, plasma CVD), charges are accumulated in the active layer (gate film and pn junction of CMOS transistors (CMOS-FETs)), which increases the leakage current (gate film leakage, pn junction leakage), which may lead to device failure.

[0004] Patent Document 1 describes an SOI wafer in which the intermediate layer between the single crystal silicon substrate and the single crystal silicon layer is an insulating polycrystalline diamond layer instead of a BOX layer made of silicon oxide film. That is, Patent Document 1 describes an SOI wafer having a single crystal silicon substrate (support substrate), a polycrystalline diamond layer formed on the single crystal silicon substrate, and a single crystal silicon layer (active layer) formed on the polycrystalline diamond layer. Patent Document 1 also describes a method for manufacturing the SOI wafer by the steps of attaching diamond particles onto the single crystal silicon substrate (support substrate), growing a polycrystalline diamond layer on the single crystal silicon substrate by chemical vapor deposition using the diamond particles as nuclei, flattening the surface of the polycrystalline diamond layer, bonding the active layer substrate made of single crystal silicon and the polycrystalline diamond layer by vacuum room temperature bonding, and reducing the thickness of the active layer substrate to form a single crystal silicon layer (active layer). [Prior art documents] [Patent documents]

[0005] [Patent Document 1] JP 2019-62020 A Summary of the Invention [Problem to be solved by the invention]

[0006] Like the BOX layer, the polycrystalline diamond layer also has high selectivity in etching with the single crystal silicon layer. For this reason, it is possible to use the SOI wafer of Patent Document 1 as a silicon wafer for fabricating a MEMS sensor together with a CMOS circuit on a single chip. However, even in the SOI wafer of Patent Document 1, the polycrystalline diamond layer has high insulating properties like the BOX layer. For this reason, the active layer and the support substrate are insulated by the polycrystalline diamond layer, and in the plasma processing in the device process, charges may accumulate in the active layer, increasing the leakage current and causing device failure. In order to avoid this problem, a laminated wafer in which the intermediate layer between the single crystal silicon substrate and the single crystal silicon layer has high electrical conductivity is required.

[0007] In view of the above problems, the present invention aims to provide a laminated wafer in which an intermediate layer between a single crystal silicon substrate and a single crystal silicon layer has high electrical conductivity while having high selectivity in etching with the single crystal silicon layer, and an advantageous method for manufacturing the same. [Means for solving the problem]

[0008] In order to solve the above problems, the present inventors have studied an intermediate layer that is highly conductive and has high selectivity in etching with a single crystal silicon layer, and have come up with the idea of ​​a laminated wafer in which the BOX layer made of silicon oxide film in a conventional SOI wafer is replaced with a conductive polycrystalline diamond layer. This laminated wafer was realized by adding boron to the raw material gas when forming the polycrystalline diamond layer in Patent Document 1, thereby reducing the resistance of the polycrystalline diamond layer.

[0009] As shown in the lower diagram of Figure 4, if a laminated wafer with an intermediate layer made of a conductive polycrystalline diamond layer is used as the silicon wafer on which the MEMS sensor and CMOS circuit are fabricated on a single chip, conductivity will be high from the surface of the active layer to the back surface of the supporting substrate, and charge will be less likely to accumulate in the active layer during plasma processing in the device process, preventing an increase in leakage current.

[0010] The essential features of the present invention, which has been completed based on the above-mentioned concept, are as follows. [1] A single crystal silicon substrate; a polycrystalline diamond layer formed on the single crystal silicon substrate; a monocrystalline silicon layer formed on the polycrystalline diamond layer; having the single crystal silicon substrate has a resistivity of 10 Ω cm or less; A laminated wafer, wherein the polycrystalline diamond layer contains boron and has a resistivity of 0.001 Ω·cm or more and 1000 Ω·cm or less.

[0011] [2] The polycrystalline diamond layer has a thickness of 1×10 18 atoms / cm 3 More than 1×10 23 atoms / cm 3 The laminated wafer according to [1] above, having the following boron concentration:

[0012] [3] The laminated wafer according to [1] or [2] above, wherein an amorphous silicon layer and an amorphous diamond layer are present between the single crystal silicon layer and the polycrystalline diamond layer.

[0013] [4] The laminated wafer according to [1] or [2] above, wherein an amorphous diamond layer is present within the polycrystalline diamond layer.

[0014] [5] depositing diamond particles on a single crystal silicon substrate; a step of supplying a gas containing hydrogen, carbon and boron onto the single crystal silicon substrate, and growing a boron-doped polycrystalline diamond layer on the single crystal silicon substrate by chemical vapor deposition using the diamond particles as nuclei; planarizing a surface of the polycrystalline diamond layer; a step of irradiating a surface of a substrate for an active layer made of single crystal silicon and a flattened surface of the polycrystalline diamond layer with an ion beam or a neutral atomic beam in a vacuum at room temperature to activate both surfaces; subsequently bonding the active layer substrate and the polycrystalline diamond layer together by contacting the activated surfaces of both substrates in a vacuum at room temperature; a step of reducing the thickness of the active layer substrate to form a single crystal silicon layer; and obtaining a laminated wafer in which the polycrystalline diamond layer and the single crystal silicon layer are sequentially laminated on the single crystal silicon substrate.

[0015] [6] depositing first diamond particles onto a single crystal silicon substrate; supplying a gas containing hydrogen, carbon and boron onto the single crystal silicon substrate, and growing a first polycrystalline diamond layer doped with boron on the single crystal silicon substrate by chemical vapor deposition using the first diamond particles as nuclei; planarizing a surface of the first polycrystalline diamond layer; Adhering second diamond particles onto an active layer substrate made of single crystal silicon; supplying a gas containing hydrogen, carbon and boron onto the active layer substrate, and growing a boron-doped second polycrystalline diamond layer on the active layer substrate by chemical vapor deposition using the second diamond particles as nuclei; planarizing a surface of the second polycrystalline diamond layer; irradiating the surfaces of the first and second polycrystalline diamond layers with an ion beam or a neutral atomic beam in a vacuum at room temperature to activate both surfaces; subsequently, bonding the first polycrystalline diamond layer and the second polycrystalline diamond layer together by contacting both activated surfaces under vacuum at room temperature to obtain a polycrystalline diamond layer in which the first and second polycrystalline diamond layers are integrated; a step of reducing the thickness of the active layer substrate to form a single crystal silicon layer; and obtaining a laminated wafer in which the polycrystalline diamond layer and the single crystal silicon layer are sequentially laminated on the single crystal silicon substrate.

[0016] [7] A method for producing a laminated wafer according to [5] or [6] above, wherein the polycrystalline diamond layer has a resistivity of 0.001 Ω·cm or more and 1000 Ω·cm or less.

[0017] [8] The method for producing a laminated wafer according to any one of the above [5] to [7], wherein the single crystal silicon substrate has a resistivity of 10 Ω·cm or less.

[0018] [9] The method for manufacturing a laminated wafer according to any one of [5] to [8] above, wherein the gas contains a boron-based gas and a hydrocarbon-based gas, and the boron concentration of the boron-based gas is 1 ppm or more and 100,000 ppm or less of the carbon concentration of the hydrocarbon-based gas. Effect of the Invention

[0019] In the laminated wafer of the present invention, the intermediate layer between the single crystal silicon substrate and the single crystal silicon layer has high conductivity while having high selectivity in etching with the single crystal silicon layer. According to the manufacturing method of the laminated wafer of the present invention, it is possible to manufacture a laminated wafer in which the intermediate layer between the single crystal silicon substrate and the single crystal silicon layer has high conductivity while having high selectivity in etching with the single crystal silicon layer. [Brief description of the drawings]

[0020] [Figure 1] 1(A) to 1(K) are schematic cross-sectional views illustrating a method for producing a laminated wafer 100 according to an embodiment of the present invention. [Diagram 2] FIG. 1 is a schematic cross-sectional view of a vacuum room temperature bonding apparatus 50 used in one embodiment of the present invention. [Diagram 3] FIG. 2 is a cross-sectional view of a device for measuring current in an embodiment. [Figure 4] These are cross-sectional views of a composite device in which a MEMS sensor and a CMOS circuit are formed on a single chip on a silicon wafer. The upper figure shows the case where the cavity formation region is formed from a silicon oxide film (BOX layer), and the lower figure shows the case where the cavity formation region is formed from a conductive layer. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0021] (Laminated Wafer Manufacturing Method) A method for manufacturing a laminated wafer 100 according to an embodiment of the present invention will be described with reference to Figs. 1(A)-(K). First, as shown in Figs. 1(A) and (B), a solution containing diamond particles is applied onto a single crystal silicon substrate 10. This forms a diamond particle-containing liquid film 12 on the single crystal silicon substrate 10. Thereafter, as shown in Figs. 1(B) and (C), the single crystal silicon substrate 10 is subjected to a heat treatment to evaporate the solvent in the diamond particle-containing liquid film 12 and to strengthen the bonding force between the surface of the single crystal silicon substrate 10 and the diamond particles 14, thereby attaching the diamond particles 14 onto the single crystal silicon substrate 10. Thereafter, as shown in Figs. 1(C) and (D), a polycrystalline diamond layer 16 is grown on the single crystal silicon substrate 10 by chemical vapor deposition (CVD) using the diamond particles 14 as nuclei. Thereafter, as shown in Figs. 1(D) and (E), a surface 16A of the polycrystalline diamond layer is flattened.

[0022] As shown in FIG. 1(H), a substrate 20 for active layer made of single crystal silicon is prepared. Then, as shown in FIG. 1(F), (G), (H), (I), a surface 16A of the polycrystalline diamond layer and a surface 20A of the substrate 20 for active layer are irradiated with an ion beam or a neutral atom beam under vacuum at room temperature to activate both surfaces 16A, 20A. At this time, as shown in FIG. 1(G), an amorphous diamond layer 18 is formed on the surface of the polycrystalline diamond layer 16, and as shown in FIG. 1(I), an amorphous silicon layer 22 is formed on the surface of the substrate 20 for active layer. After that, as shown in FIG. 1(G), (I), (J), both activated surfaces are brought into contact under vacuum at room temperature to bond the substrate 20 for active layer and the polycrystalline diamond layer 16 together using the activated surfaces as bonding surfaces (jointing surfaces), thereby obtaining a bonded substrate 30. Thereafter, as shown in FIGS. 1(J) and 1(K), the thickness of the active layer substrate 20 is reduced to form a single crystal silicon layer 26.

[0023] In this embodiment, through the above steps, a laminated wafer 100 can be manufactured in which a polycrystalline diamond layer 16 and a single crystal silicon layer 26 are sequentially laminated on a single crystal silicon substrate 10. Here, the single crystal silicon layer 26 becomes a device layer for forming a semiconductor device. In the laminated wafer 100, an amorphous silicon layer 22 and an amorphous diamond layer 18, each having a thickness of 1 nm or more and 5 nm or less, exist between the single crystal silicon layer 26 and the polycrystalline diamond layer 16.

[0024] [Single crystal silicon substrate] The single crystal silicon substrate 10 can be made by slicing a single crystal silicon ingot grown by the Czochralski method (CZ method), the MCZ method (Magnetic field applied Czochralski method) in which a magnetic field is applied to the CZ method, or the floating zone melting method (FZ method) using a wire saw or the like.

[0025] The resistivity of the single crystal silicon substrate 10 is preferably 10 Ω·cm or less. If the resistivity exceeds 10 Ω·cm, the insulating properties of the single crystal silicon substrate 10 itself become high, and regardless of the resistivity of the polycrystalline diamond layer 16, electric charges may accumulate in the single crystal silicon layer 26 (active layer) during plasma processing in the device process, increasing the leakage current and causing device failure.

[0026] There is no limitation on the type of dopant added to the single crystal silicon substrate 10. Specifically, boron is used as a p-type dopant, and phosphorus, arsenic, and antimony are used as n-type dopants. The resistivity of the single crystal silicon substrate 10 may be low, and there is no particular limitation on the lower limit, but currently, the manufacturing limit resistivity for each substrate is 0.0001 Ω·cm when boron is contained, 0.0005 Ω·cm when phosphorus is contained, 0.001 Ω·cm when arsenic is contained, and 0.005 Ω·cm when antimony is contained.

[0027] The thickness of the single crystal silicon substrate 10 may be set according to the thickness of the polycrystalline diamond layer 16, and since the thicker the polycrystalline diamond layer 16, the greater the warpage, it is preferable to thicken the single crystal silicon substrate 10 to prevent warpage. Specifically, the thickness of the single crystal silicon substrate 10 is preferably set to 500 μm or more and 5 mm or less.

[0028] [Active layer substrate] Similarly to the single crystal silicon substrate 10, the active layer substrate 20 may be obtained by slicing a single crystal silicon ingot grown by the CZ method, the MCZ method, or the FZ method with a wire saw or the like.

[0029] The resistivity of the active layer substrate 20 is not particularly limited, but can generally be 1 Ω·cm or more and 100 Ω·cm or less. The dopant species added to the active layer substrate 20 is not limited. Specifically, boron is used as a p-type dopant, and phosphorus, arsenic, and antimony are used as n-type dopants.

[0030] The thickness of the active layer substrate 20 is preferably 200 μm or more and 1 mm or less. If it is less than 200 μm, the active layer substrate 20 may warp during vacuum room temperature bonding, which may cause wafer bonding failure. Also, if it exceeds 1 mm, it is not preferable from the viewpoint of the process time and material cost in the step of reducing the thickness of the active layer substrate 20 described later.

[0031] [Diamond particle attachment process] The step of adhering diamond particles 14 onto the single crystal silicon substrate 10 is preferably carried out by applying a solution containing diamond particles onto the single crystal silicon substrate 10 and then subjecting the single crystal silicon substrate 10 to a heat treatment.

[0032] [[Application of a solution containing diamond particles]] As shown in Figures 1(A) and (B), a solution containing diamond particles is applied onto a single crystal silicon substrate 10 to form a diamond particle-containing liquid film 12 on the single crystal silicon substrate 10. Examples of application methods include spin coating, spraying, and immersion, with spin coating being particularly preferred. By using the spin coating method, the diamond particle-containing solution can be applied uniformly only to one of the two surfaces of the single crystal silicon substrate 10 to which diamond particles 14 are to be attached.

[0033] The average particle size of the diamond particles contained in the diamond particle-containing solution is preferably 1 nm or more and 50 nm or less, and more preferably 10 nm or less. If it is 1 nm or more, the phenomenon that the diamond particles 14 are sputtered off the surface of the single crystal silicon substrate 10 by the sputtering action can be suppressed in the initial stage of growing the polycrystalline diamond layer 16, and if it is 50 nm or less, the polycrystalline diamond layer 16 can be densely grown without abnormal growth, and the flatness that allows wafer bonding can be realized in the flattening process described later. Diamond particles of such a size can be suitably produced from graphite by a known detonation method, implosion method, or pulverization method. Note that the "average particle size of the diamond particles contained in the diamond particle-containing solution" is calculated according to JIS 8819-2, and means the average particle size calculated assuming that the particle size distribution measured by a known laser diffraction type particle size distribution measuring device follows a normal distribution.

[0034] Here, the single crystal silicon substrate 10 before the diamond particle-containing solution is applied is generally acid-cleaned using hydrofluoric acid or the like to remove metal impurities attached to its surface. Since the surface of the acid-cleaned single crystal silicon substrate 10 is an active water-repellent surface, particles are likely to adhere to the surface. For this reason, it is preferable to clean the acid-cleaned single crystal silicon substrate 10 with pure water or the like to make the surface of the single crystal silicon substrate 10 a hydrophilic surface on which a natural oxide film is formed. Alternatively, it is preferable to leave the acid-cleaned single crystal silicon substrate 10 in a clean room for a long time to form a natural oxide film on the surface of the single crystal silicon substrate 10. This makes it possible to suppress the adhesion of particles to the surface of the single crystal silicon substrate 10. At this time, a fixed charge having a positive charge is generated in the natural oxide film. Therefore, if a diamond particle-containing solution containing negatively charged diamond particles is applied on the positively charged natural oxide film, the single crystal silicon substrate 10 and the diamond particles 14 are firmly bonded by Coulomb attraction. As a result, the adhesion of the polycrystalline diamond layer 16 to the single crystal silicon substrate 10 is improved. The diamond particles thus negatively charged can be obtained by terminating the diamond particles with carboxyl group or ketone group through oxidation treatment.For example, the oxidation treatment can include the method of oxidizing the diamond particles with heat, or the method of immersing the diamond particles in ozone solution, nitric acid solution, hydrogen peroxide solution, or perchloric acid solution.

[0035] Examples of the solvent for the diamond particle-containing solution include water and organic solvents such as methanol, ethanol, 2-propanol, and toluene. These solvents may be used alone or in combination of two or more.

[0036] The content of diamond particles in the diamond particle-containing solution is preferably 0.03% by mass or more and 10% by mass or less with respect to the entire diamond particle-containing solution. If the content is 0.03% by mass or more, the diamond particles 14 can be uniformly attached to the single crystal silicon substrate 10, and if the content is 10% by mass or less, abnormal growth of the attached diamond particles 14 during the growth process of the diamond layer 16 can be suppressed.

[0037] From the viewpoint of improving the adhesion between the diamond particles 14 and the single crystal silicon substrate 10, it is preferable to make the diamond particle-containing solution gel-like, and a thickener may be contained in the diamond particle-containing solution. Examples of the thickener include agar, carrageenan, xanthan gum, gellan gum, guar gum, polyvinyl alcohol, polyacrylate-based thickeners, water-soluble celluloses, polyethylene oxide, etc., and one or more of these can be used. When a thickener is contained, it is preferable that the pH of the diamond particle-containing solution is in the range of 6 to 8.

[0038] The diamond particle-containing solution may be prepared by mixing the diamond particles in the above-mentioned solvent and stirring the mixture to disperse the diamond particles in the solvent. The stirring speed is preferably 500 rpm or more and 3000 rpm or less, and the stirring time is preferably 10 minutes or more and 1 hour or less.

[0039] [[Heat treatment]] Next, as shown in Fig. 1(B) and (C), the single crystal silicon substrate 10 is subjected to a heat treatment. This causes the solvent in the diamond particle-containing liquid film 12 to evaporate, and the bonding force between the surface of the single crystal silicon substrate 10 and the diamond particles 14 is strengthened, so that the diamond particles 14 are attached to the single crystal silicon substrate 10. The temperature of the single crystal silicon substrate 10 during the heat treatment is preferably less than 100°C, and more preferably 30°C to 80°C. If the temperature is less than 100°C, the generation of bubbles caused by the boiling of the diamond particle-containing solution can be suppressed, so that no part of the single crystal silicon substrate 10 where the diamond particles 14 are partially absent is generated, and there is no risk of the polycrystalline diamond layer 16 peeling off from this part. If the temperature is 30°C or higher, the single crystal silicon substrate 10 and the diamond particles 14 are sufficiently bonded, so that the diamond particles 14 can be suppressed from being blown off by the sputtering action during the process of growing the polycrystalline diamond layer 16 by the CVD method, and the polycrystalline diamond layer 16 can be grown uniformly. The heat treatment time is preferably from 1 minute to 30 minutes. As the heat treatment apparatus, a known heat treatment apparatus may be used, and the heat treatment may be performed by, for example, placing the single crystal silicon substrate 10 on a heated hot plate.

[0040] The method of attaching diamond particles to the single crystal silicon substrate is not limited to the coating method of applying a solution containing diamond particles, but may be a known scratching method. In the case of the scratching method, diamond particles are embedded in the surface of the single crystal silicon substrate to attach the diamond particles to the single crystal silicon substrate. The methods of embedding diamond particles include (1) distributing dry diamond powder on the surface of the single crystal silicon substrate and applying a pressing force to the substrate surface, (2) spraying high-velocity gas containing diamond particles onto the surface of the single crystal silicon substrate, (3) placing the single crystal silicon substrate in a fluidized bed of diamond particles, and (4) ultrasonically cleaning the single crystal silicon substrate in a solution in which diamond particles are dispersed. In the scratching method, the embedding depth of the diamond particles varies, which tends to cause the thickness of the polycrystalline diamond layer to become nonuniform, and if the scratches generated on the surface of the single crystal silicon substrate during the embedding of diamond particles are large, the smoothness of the surface of the polycrystalline diamond layer tends to deteriorate, so it is preferable to use the coating method.

[0041] [Growth of polycrystalline diamond layer] 1(C) and (D), a polycrystalline diamond layer 16 is grown on the single crystal silicon substrate 10 by a CVD method using the diamond particles 14 as nuclei. As the CVD method, a plasma CVD method, a hot filament CVD method, or the like can be suitably used.

[0042] In this embodiment, it is important to supply a source gas containing hydrogen, carbon and boron onto the single crystal silicon substrate 10 to make the polycrystalline diamond layer 16 contain boron, thereby making the polycrystalline diamond layer 16 conductive, i.e., low-resistance. If the resistivity of the polycrystalline diamond layer 16 exceeds 1000 Ω·cm, the polycrystalline diamond layer 16 in the laminated wafer 100 has high insulation, and in the plasma processing in the device process, electric charges are accumulated in the single crystal silicon layer 26 (active layer), and the leakage current increases, which may lead to device failure. Therefore, the resistivity of the polycrystalline diamond layer 16 is set to 1000 Ω·cm or less, preferably 10 Ω·cm or less, and more preferably 0.1 Ω·cm or less. On the other hand, if the resistivity of the polycrystalline diamond layer 16 is less than 0.001 Ω·cm, when the laminated wafer 100 is subjected to high-temperature heat treatment in the device manufacturing process, the boron in the polycrystalline diamond layer 16 may diffuse into the single crystal silicon layer 26, causing the resistivity of the single crystal silicon layer 26 to fluctuate. Therefore, the resistivity of the polycrystalline diamond layer 16 is set to 0.001 Ω·cm or more.

[0043] The source gas supplied to the single crystal silicon substrate 10 may include a boron-based gas and a hydrocarbon-based gas. Examples of the hydrocarbon-based gas include methane, ethane, propane, butane, etc., and one or more of these may be used. Examples of the boron-based gas include trimethoxyborane, triethylborane, trimethylboron, diborane, etc., and one or more of these may be used. The boron concentration of the boron-based gas is preferably 1 ppm or more and 100,000 ppm or less of the carbon concentration of the hydrocarbon-based gas. If the boron concentration is 1 ppm or more, boron is uniformly incorporated into the polycrystalline diamond layer when the polycrystalline diamond layer is formed, and there are no scattered portions of low boron concentration in the polycrystalline diamond layer. Also, if the boron concentration is 100,000 ppm or less, boron is uniformly incorporated into the polycrystalline diamond layer when the polycrystalline diamond layer is formed, and there are no scattered portions of high boron concentration in the polycrystalline diamond layer.

[0044] When using the plasma CVD method, for example, hydrogen is used as a carrier gas, and source gases such as methane and trimethoxyborane are introduced into the chamber, and the temperature of the single crystal silicon substrate 10 is set to 700°C or higher and 1300°C or lower to grow the polycrystalline diamond layer 16 containing boron. From the viewpoint of improving the uniformity of the thickness of the polycrystalline diamond layer 16, it is preferable to use the microwave plasma CVD method. The microwave plasma CVD method is a method in which source gases such as methane and trimethoxyborane are decomposed by microwaves in a plasma chamber to generate plasma, and the plasma source gas is introduced onto the heated single crystal silicon substrate 10 to grow the polycrystalline diamond layer 16. Here, the pressure in the plasma chamber, the microwave output, and the temperature of the single crystal silicon substrate 10 are preferably set as follows. The pressure in the plasma chamber is 1.3×10 3 Pa or more 1.3×10 5 Pa or less, and 1.1×10 4 Pa or more 4.0×10 4 The pressure in the microwave oven is preferably 0.1 Pa or less, and more preferably 1 kW or more and 10 kW or less. The temperature of the single crystal silicon substrate 10 is preferably 700° C. or more and 1300° C. or less, and more preferably 900° C. or more and 1200° C. or less.

[0045] When using the hot filament CVD method, a filament made of tungsten, tantalum, rhenium, molybdenum, iridium, or the like is used, the filament temperature is set to about 1900°C or more and 2300°C or less, carbon radicals are generated from a hydrocarbon source gas such as methane, and boron radicals are generated from a boron source gas such as trimethoxyborane. The carbon radicals and boron radicals are guided onto a heated single crystal silicon substrate 10 to grow a polycrystalline diamond layer 16 containing boron. The hot filament CVD method can easily accommodate larger diameter wafers. Here, the pressure in the chamber, the distance between the filament and the single crystal silicon substrate 10, and the temperature of the single crystal silicon substrate 10 are preferably set as follows. The pressure in the chamber is 1.3×10 3 Pa or more 1.3×10 5 The pressure is preferably 50 Pa or less. The distance between the filament and the single crystal silicon substrate 10 is preferably 5 mm or more and 20 mm or less. The temperature of the single crystal silicon substrate 10 is preferably 700° C. or more and 1300° C. or less.

[0046] Since the polycrystalline diamond layer 16 functions as an intermediate layer of the laminated wafer 100, its thickness is preferably 1 μm or more and 10 μm or less. In this specification, the "thickness of the polycrystalline diamond layer" refers to the average thickness measured by observing the cross section of three 10 μm × 10 μm regions with an optical microscope, the three regions being centered on the center point of the surface 16A of the polycrystalline diamond layer (i.e., the center point of the wafer) and two intersection points between the circumference of a 95% radius of the surface 16A of the polycrystalline diamond layer from the center point of the wafer and the diameter of the surface 16A of the polycrystalline diamond layer.

[0047] [Planarization of polycrystalline diamond layer] Next, as shown in Figures 1(D) and (E), the surface 16A of the polycrystalline diamond layer is planarized. The planarization method is not particularly limited, but for example, a known chemical mechanical polishing (CMP) method can be suitably used. Note that even after planarization, the thickness of the polycrystalline diamond layer 16 is preferably 1 μm or more and 10 μm or less.

[0048] [Bonding using vacuum room temperature bonding method] In this embodiment, as shown in Figs. 1(F), (G), (H), and (I), the polycrystalline diamond layer 16 and the active layer substrate 20 are bonded together by vacuum room temperature bonding to obtain a bonded substrate 30. The vacuum room temperature bonding method is a method of bonding the single crystal silicon substrate 10 and the active layer substrate 20 at room temperature without heating. In this embodiment, the surface 16A of the polycrystalline diamond layer and the surface 20A of the active layer substrate are activated by irradiating an ion beam or a neutral atom beam at vacuum room temperature, and both surfaces 16A and 20A are activated surfaces. As a result, dangling bonds appear on the activated surfaces. Therefore, when the above-mentioned two activated surfaces are subsequently brought into contact at vacuum room temperature, a bonding force is instantly applied, and the polycrystalline diamond layer 16 and the active layer substrate 20 are firmly bonded together with the above-mentioned activated surfaces as the bonding surfaces.

[0049] The activation process can be performed by accelerating ionized elements in a plasma atmosphere toward the surface of each substrate, or by accelerating ionized elements from an ion beam device toward the surface of each substrate. One embodiment of an apparatus for implementing this method will be described with reference to Fig. 2. A vacuum room temperature bonding apparatus 50 has a plasma chamber 51, a gas inlet 52, a vacuum pump 53, a pulse voltage application device 54, and wafer fixing tables 55A and 55B.

[0050] First, the single crystal silicon substrate 10 and the active layer substrate 20 are placed and fixed on the wafer fixing stages 55A and 55B in the plasma chamber 51, respectively. Next, the pressure in the plasma chamber 51 is reduced by the vacuum pump 53, and then the raw material gas is introduced into the plasma chamber 51 from the gas inlet 52. Next, a negative voltage is applied in pulses to the wafer fixing stages 55A and 55B (as well as the single crystal silicon substrate 10 and the active layer substrate 20) by the pulse voltage application device 54. This allows plasma of the raw material gas to be generated, and ions of the raw material gas contained in the generated plasma to be accelerated and irradiated toward the surfaces of the polycrystalline diamond layer 16 formed on the single crystal silicon substrate 10 and the active layer substrate 20.

[0051] The element to be irradiated is preferably at least one selected from the group consisting of Ar, Ne, Xe, H, He and Si.

[0052] The chamber pressure in the plasma chamber 51 is 1×10 -5 It is preferable to set the pressure to 1×10 Pa or less. -5 If the pressure is less than Pa, the sputtered elements are unlikely to re-adhere to the surface of each substrate, and there is no risk of a decrease in the rate of formation of dangling bonds.

[0053] The pulse voltage applied to the single crystal silicon substrate 10 and the active layer substrate 20 is preferably set so that the acceleration energy of the irradiated element relative to the surface of each substrate is 100 eV or more and 10 keV or less. If it is 100 eV or more, there is no risk of the irradiated element being deposited on the surface of each substrate, and if it is 10 keV or less, there is no risk of the irradiated element being implanted into the inside of each substrate, so that dangling bonds can be stably formed.

[0054] The frequency of the pulse voltage determines the number of times that the single crystal silicon substrate 10 and the active layer substrate 20 are irradiated with ions or neutral atoms. The frequency of the pulse voltage is preferably 10 Hz or more and 10 kHz or less. If the frequency is 10 Hz or more, the variation in the irradiation of ions or neutral atoms can be absorbed, so that the amount of irradiation of ions or neutral atoms is stable, and if the frequency is 10 kHz or less, the plasma formation by glow discharge is stable.

[0055] The pulse width of the pulse voltage determines the time during which the single crystal silicon substrate 10 and the active layer substrate 20 are irradiated with ions or neutral atoms. The pulse width is preferably 1 μsec or more and 10 ms or less. If the pulse width is 1 μsec or more, the ions or neutral atoms can be irradiated stably onto each substrate, and if the pulse width is 10 ms or less, plasma formation by glow discharge is stable.

[0056] Since the single crystal silicon substrate 10 and the active layer substrate 20 are not heated, their temperatures are room temperature (usually 30° C. to 90° C.).

[0057] By using the vacuum room temperature bonding method in this way, the following effects can be obtained. In the vacuum room temperature bonding method, the single crystal silicon substrate 10 and the active layer substrate 20 are not heated. Therefore, it is possible to suppress the outward diffusion of impurities in the single crystal silicon substrate 10 to the active layer substrate 20. In addition, since both substrates can be bonded instantaneously and firmly, it is possible to prevent the occurrence of slip and dislocation. Also, the thermal stress caused by the high temperature heat treatment is not introduced into the polycrystalline diamond layer 16. Furthermore, by the activation treatment in the vacuum room temperature bonding method, an amorphous diamond layer 18 having a thickness of 1 nm to 5 nm is formed on the surface layer of the polycrystalline diamond layer 16 (FIG. 1(G)), and an amorphous silicon layer 22 having a thickness of 1 nm to 5 nm is formed on the surface layer of the active layer substrate 20 (FIG. 1(I)). Both amorphous layers function as gettering layers, and it is possible to suppress the outward diffusion of oxygen and impurities in the single crystal silicon substrate 10 to the active layer substrate 20. Furthermore, both amorphous layers have good thermal conductivity, which contributes to improving the heat dissipation of the laminated wafer 100, which is the final product.

[0058] [Reducing the thickness of the active layer substrate] 1(J) and (K), the active layer substrate 20 is reduced in thickness to form a single crystal silicon layer 26. Specifically, the active layer substrate 20 is reduced in thickness by grinding and polishing from the surface opposite to the bonding surface. The thickness of the single crystal silicon layer 26 can be appropriately determined depending on the type and structure of the semiconductor device to be formed thereon, and is preferably 1 μm to 500 μm, more preferably 5 μm to 20 μm. In addition, for this grinding and polishing, a known or arbitrary grinding method and polishing method can be suitably used, and specifically, a surface grinding method and a mirror polishing method can be used.

[0059] According to the method for manufacturing a laminated wafer according to the present embodiment described above, it is possible to manufacture a laminated wafer in which an intermediate layer between the single crystal silicon substrate and the single crystal silicon layer has high selectivity in etching with the single crystal silicon layer and high electrical conductivity.

[0060] In the above embodiment, the polycrystalline diamond layer 16 is grown only on the single crystal silicon substrate 10 as a support substrate, and then the single crystal silicon substrate 10 and the active layer substrate 20 are bonded together by a vacuum room temperature bonding method. However, the present invention is not limited to this, and it is also possible to grow a polycrystalline diamond layer on each of the single crystal silicon substrate 10 as a support substrate and the active layer substrate 20, and then bond the single crystal silicon substrate 10 and the active layer substrate 20 together by a vacuum room temperature bonding method.

[0061] That is, a method for manufacturing a laminated wafer according to another embodiment of the present invention includes the following steps.

[0062] First, the process involves the steps of adhering first diamond particles onto a single crystal silicon substrate, supplying a gas containing hydrogen, carbon and boron onto the single crystal silicon substrate to grow a first polycrystalline diamond layer doped with boron on the single crystal silicon substrate by chemical vapor deposition using the first diamond particles as nuclei, and planarizing the surface of the first polycrystalline diamond layer.

[0063] The method also includes the steps of adhering second diamond particles onto an active layer substrate made of single crystal silicon, supplying a gas containing hydrogen, carbon and boron onto the active layer substrate to grow a boron-added second polycrystalline diamond layer on the active layer substrate by chemical vapor deposition using the second diamond particles as nuclei, and planarizing the surface of the second polycrystalline diamond layer.

[0064] Then, the following steps are performed: irradiating the surfaces of the first and second polycrystalline diamond layers with an ion beam or a neutral atom beam at room temperature in vacuum to activate both surfaces; subsequently, bonding the first and second polycrystalline diamond layers together by contacting both activated surfaces at room temperature in vacuum to obtain a polycrystalline diamond layer in which the first and second polycrystalline diamond layers are integrated; and reducing the thickness of the active layer substrate to form a single crystal silicon layer.

[0065] Through the above steps, a laminated wafer is obtained in which the polycrystalline diamond layer and the single crystal silicon layer are laminated in this order on the single crystal silicon substrate. For this embodiment, the details are the same as those of the embodiment shown in Figures 1(A) to (K).

[0066] (Stacked wafers) 1(K), a laminated wafer 100 manufactured by this embodiment has a single crystal silicon substrate 10, a polycrystalline diamond layer 16 formed on the single crystal silicon substrate 10, and a single crystal silicon layer 26 formed on the polycrystalline diamond layer 16, the single crystal silicon substrate 10 having a resistivity of 10 Ω·cm or less, and the polycrystalline diamond layer 16 containing boron and having a resistivity of 0.001 Ω·cm or more and 1000 Ω·cm or less. In the laminated wafer 100, between the single crystal silicon layer 26 and the polycrystalline diamond layer 16, there are an amorphous silicon layer 22 and an amorphous diamond layer 18 each having a thickness of 1 nm or more and 5 nm or less.

[0067] In the case of an embodiment in which a polycrystalline diamond layer is grown on each of the single crystal silicon substrate 10 as a support substrate and the active layer substrate 20, and then the single crystal silicon substrate 10 and the active layer substrate 20 are bonded together by a vacuum room temperature bonding method, an amorphous diamond layer is present within the polycrystalline diamond layer. This is because the surface layer parts of the first polycrystalline diamond layer and the second polycrystalline diamond layer become amorphous diamond layers.

[0068] If the resistivity of the polycrystalline diamond layer 16 exceeds 1000 Ω·cm, the insulating property of the polycrystalline diamond layer 16 in the laminated wafer 100 is high, and in the plasma processing in the device process, electric charges are accumulated in the single crystal silicon layer 26 (active layer), and the leakage current increases, which may cause device failure. Therefore, the resistivity of the polycrystalline diamond layer 16 is set to 1000 Ω·cm or less, preferably 10 Ω·cm or less, and more preferably 0.1 Ω·cm or less. On the other hand, if the resistivity of the polycrystalline diamond layer 16 is less than 0.001 Ω·cm, when the laminated wafer 100 is subjected to high-temperature heat treatment in the device manufacturing process, boron in the polycrystalline diamond layer 16 may diffuse into the single crystal silicon layer 26, causing the resistivity of the single crystal silicon layer 26 to fluctuate. Therefore, the resistivity of the polycrystalline diamond layer 16 is set to 0.001 Ω·cm or more.

[0069] To achieve the above range of resistivity, the boron concentration of the polycrystalline diamond layer 16 is set to 1×10 18 atoms / cm 3 More than 1×10 23 atoms / cm 3 It is preferable that the value is less than 1×10 20 atoms / cm 3 More than 1×10 22 atoms / cm 3 It is more preferable that:

[0070] The "boron concentration of polycrystalline diamond layer 16" is determined by measuring the boron concentration distribution in the thickness direction of polycrystalline diamond layer 16 using secondary ion mass spectrometry (SIMS), and averaging the boron concentration distribution in the thickness direction.

[0071] The manufacturing method, resistivity, and thickness of the single crystal silicon substrate 10 are as described above.

[0072] The resistivity of the single crystal silicon layer 26 is the same as the resistivity of the above-mentioned active layer substrate 20. The thickness of the single crystal silicon layer 26 is also as described above.

[0073] In this specification, the resistivities of the single crystal silicon substrate 10, the polycrystalline diamond layer 16, and the single crystal silicon layer 26 are values ​​measured by a four-terminal method.

[0074] In the laminated wafer 100 of this embodiment, the polycrystalline diamond layer 16, which is an intermediate layer between the single crystal silicon substrate 10 and the single crystal silicon layer 26, has high conductivity while having high etching selectivity with the single crystal silicon layer 26. EXAMPLES

[0075] (Fabrication of stacked wafers) In Nos. 1 to 7 and 9 to 13 in Table 1, freestanding polycrystalline diamond substrates according to the invention or comparative examples were manufactured through the steps shown in Figs. 1(A) to (K).

[0076] As a support substrate, a p-type (100) single crystal silicon substrate was prepared, which was cut from a single crystal silicon ingot grown by the CZ method, had a diameter of 2 inches, a thickness of 3 mm, contained boron as a dopant, and had the resistivity shown in the "Resistivity of single crystal Si substrate" column in Table 1.

[0077] In addition, as a substrate for the active layer, an n-type (100) single crystal silicon substrate was prepared, which was cut and processed from a single crystal silicon ingot grown by the CZ method, had a diameter of 2 inches, a thickness of 500 μm, contained phosphorus as a dopant, and had the resistivity shown in the column "Resistivity of single crystal Si layer" in Table 1.

[0078] Next, diamond particles with an average particle size of 5 nm were prepared by the detonation method. These diamond particles were terminated with carboxyl groups (COOH) by immersing them in a hydrogen peroxide solution, and were negatively charged. Next, the diamond particles were dissolved in a solvent (H 2 O) and stirred to prepare a diamond particle-containing solution with a diamond particle content of 0.1 mass %. The stirring speed was 1100 rpm, the stirring time was 50 minutes, and the temperature of the diamond particle-containing solution during stirring was 25°C. Next, a single crystal silicon substrate (support substrate) was washed with pure water to form a natural oxide film on the surface, and then the diamond particle-containing solution was applied onto the single crystal silicon substrate (support substrate) by spin coating to form a diamond particle-containing liquid film.

[0079] Next, the single crystal silicon substrate (support substrate) was placed on a hot plate set at 80°C for 3 minutes to perform a heat treatment to strengthen the bond between the single crystal silicon substrate and the diamond particles, thereby adhering the diamond particles onto the single crystal silicon substrate (support substrate).

[0080] Next, using hydrogen as the carrier gas and methane and trimethoxyborane as the source gases, the aforementioned microwave plasma CVD method was used to grow a polycrystalline diamond layer 5.5 μm thick using the diamond particles attached to the single crystal silicon substrate (support substrate) as nuclei. The boron concentration of trimethoxyborane relative to the carbon concentration of methane is shown in Table 1. The pressure in the plasma chamber was set to 1.7 × 10 4 The temperature of the single crystal silicon substrate (support substrate) was 1050°C, and the growth time was 1 hour.

[0081] Next, the surface of the polycrystalline diamond layer was flattened by CMP, so that the thickness of the flattened polycrystalline diamond layer was 5 μm.

[0082] At this stage, the resistivity and boron concentration of the polycrystalline diamond layer were measured by the method described above, and are shown in Table 1. In this embodiment, the resistivity and boron concentration of the polycrystalline diamond layer were measured before bonding with the active layer substrate, but in the case of vacuum room temperature bonding, boron diffusion does not occur due to bonding, so even if the resistivity and boron concentration of the polycrystalline diamond layer are measured at the laminated wafer stage, the values ​​will be equivalent. Even in the laminated wafer, it is possible to measure the resistivity and boron concentration of the polycrystalline diamond layer by peeling off the single crystal silicon layer (active layer).

[0083] Next, 25°C, 1 x 10 -5Ar was flowed into a vacuum chamber at 10 Pa to generate plasma, and Ar ions were irradiated to the surface of the polycrystalline diamond layer and the surface of the active layer substrate with an acceleration energy of 5 keV, a frequency of 140 Hz, and a pulse width of 55 μsec to activate both surfaces. Subsequently, the activated surfaces were brought into contact with each other under vacuum at room temperature, and the polycrystalline diamond layer and the active layer substrate were bonded together using the activated surfaces as bonding surfaces. By this activation process, an amorphous diamond layer was formed on the surface of the polycrystalline diamond layer, and an amorphous silicon layer was formed on the surface of the active layer substrate. The total thickness of both amorphous layers is shown in Table 1. The thicknesses of the amorphous layers were the same. The thicknesses of the amorphous layers were determined by observing the bonded interface with a cross-sectional TEM.

[0084] The active layer substrate was then ground and polished to obtain a single crystal silicon layer having a thickness of 2 μm. In this manner, a laminated wafer was obtained in which a polycrystalline diamond layer and a single crystal silicon layer were sequentially laminated on a single crystal silicon substrate.

[0085] In addition, in No. 8 of Table 1, an SOI wafer was produced in which a silicon oxide film was formed instead of a polycrystalline diamond layer. The silicon oxide film and the active layer substrate were bonded by vacuum room temperature bonding, as described above.

[0086] (Measurement of resistivity) In each of the invention examples and comparative examples, the resistivity of the single crystal silicon substrate, the polycrystalline diamond layer, and the single crystal silicon layer was measured by a four-terminal four-point probe method. The resistivity of the single crystal silicon substrate was obtained by measuring the back surface of the laminated wafer, and the resistivity of the single crystal silicon layer was obtained by measuring the front surface of the laminated wafer. The resistivity of the polycrystalline diamond layer was obtained by removing the single crystal silicon layer by immersing it in an alkaline aqueous solution and etching it, and then removing the amorphous diamond layer by CMP, and measuring the surface of the polycrystalline diamond layer.

[0087] (Current measurement) In each of the invention examples and comparative examples, the current flowing from the surface of the single crystal silicon layer (active layer) to the back surface of the single crystal silicon substrate (support substrate) was measured. A TEG for measurement, as shown in FIG. 3, was fabricated. A voltage was applied between the metal and the back surface of the support substrate (0 V to the back surface of the support substrate, -3 V to 3 V to the p+ region) to evaluate the conductivity on the front and back surfaces of the sample. First, a boron-doped p region was formed by photolithography and heat-treated at 1000°C for 2 hours in a nitrogen atmosphere. After that, etching was performed by photolithography, and then SiO was formed by CVD. 2 Then, an interlayer insulator was deposited to form an STI region, and then etching was performed by photolithography. After that, boron was injected and heat treatment was performed at 900°C for 0.5 hours in a nitrogen atmosphere to form a p+ contact region, and metal was embedded in the through-hole via.

[0088] [Table 1]

[0089] As shown in Table 1, in the example of the invention, the value of the current flowing from the surface of the active layer to the rear surface of the support substrate is large. Therefore, it is expected that charge is less likely to accumulate in the active layer during plasma processing in the device process, and an increase in leakage current can be avoided. On the other hand, in the comparative example, the value of the current flowing from the surface of the active layer to the rear surface of the support substrate is small. Therefore, charge may accumulate in the active layer during plasma processing in the device process, increasing the leakage current and causing device failure. [Industrial Applicability]

[0090] On the laminated wafer of the present invention, a composite device can be produced by forming a MEMS device and a CMOS circuit on one chip. [Explanation of symbols]

[0091] 100 stacked wafers 10 Single crystal silicon substrate 12 Diamond particle-containing liquid film 14 Diamond particles 16 Polycrystalline diamond layer 16A Surface of polycrystalline diamond layer 18 Amorphous diamond layer 20 Substrate for active layer (single crystal silicon substrate) 20A Surface of the active layer substrate 22 Amorphous silicon layer 26 Single crystal silicon layer 30 Bonded substrate 50 Vacuum room temperature bonding equipment 51 Plasma Chamber 52 Gas inlet 53 Vacuum Pump 54 Pulse voltage application device 55A Wafer Fixing Stand 55B Wafer Fixing Stand

Claims

1. A single crystal silicon substrate; a polycrystalline diamond layer formed on the single crystal silicon substrate; a monocrystalline silicon layer formed on the polycrystalline diamond layer; having the single crystal silicon substrate has a resistivity of 10 Ω cm or less; A laminated wafer, wherein the polycrystalline diamond layer contains boron and has a resistivity of 0.001 Ω·cm or more and 1000 Ω·cm or less.

2. The polycrystalline diamond layer is 1×10 １８ atoms / cm ３ Above 1 x 10 ２３ atoms / cm ３ 2. The laminated wafer of claim 1 having a boron concentration of:

3. 3. A laminated wafer according to claim 1 or 2, wherein an amorphous silicon layer and an amorphous diamond layer are present between the single crystal silicon layer and the polycrystalline diamond layer.

4. 3. A laminated wafer according to claim 1 or 2, wherein an amorphous diamond layer is present within the polycrystalline diamond layer.

5. A process for depositing diamond particles on a single crystal silicon substrate having a resistivity of 10 Ω cm or less; a step of supplying a gas containing hydrogen, carbon and boron onto the single crystal silicon substrate, and growing a boron-doped polycrystalline diamond layer having a resistivity of 0.001 Ω cm or more and 1000 Ω cm or less on the single crystal silicon substrate by chemical vapor deposition using the diamond particles as nuclei; planarizing a surface of the polycrystalline diamond layer; a step of irradiating a surface of a substrate for an active layer made of single crystal silicon and a flattened surface of the polycrystalline diamond layer with an ion beam or a neutral atomic beam in a vacuum at room temperature to activate both surfaces; subsequently bonding the active layer substrate and the polycrystalline diamond layer together by contacting the activated surfaces of both substrates in a vacuum at room temperature; a step of reducing the thickness of the active layer substrate to form a single crystal silicon layer; and obtaining a laminated wafer in which the polycrystalline diamond layer and the single crystal silicon layer are sequentially laminated on the single crystal silicon substrate.

6. A method of manufacturing a semiconductor device comprising the steps of: depositing first diamond particles on a single crystal silicon substrate having a resistivity of 10 Ω cm or less; supplying a gas containing hydrogen, carbon and boron onto the single crystal silicon substrate, and growing a first polycrystalline diamond layer doped with boron on the single crystal silicon substrate by chemical vapor deposition using the first diamond grains as nuclei; planarizing a surface of the first polycrystalline diamond layer; Adhering second diamond particles onto an active layer substrate made of single crystal silicon; supplying a gas containing hydrogen, carbon and boron onto the active layer substrate, and growing a second polycrystalline diamond layer doped with boron on the active layer substrate by chemical vapor deposition using the second diamond particles as nuclei; planarizing a surface of the second polycrystalline diamond layer; a step of irradiating surfaces of the first and second polycrystalline diamond layers with an ion beam or a neutral atomic beam in a vacuum at room temperature to activate both surfaces; subsequently, bonding the first polycrystalline diamond layer and the second polycrystalline diamond layer together by contacting both activated surfaces under vacuum at room temperature to obtain a polycrystalline diamond layer having a resistivity of 0.001 Ω cm or more and 1000 Ω cm or less, in which the first and second polycrystalline diamond layers are integrated; a step of reducing the thickness of the active layer substrate to form a single crystal silicon layer; and obtaining a laminated wafer in which the polycrystalline diamond layer and the single crystal silicon layer are sequentially laminated on the single crystal silicon substrate.

7. 7. The method for manufacturing laminated wafers according to claim 5, wherein the gas contains a boron-based gas and a hydrocarbon-based gas, and the boron concentration of the boron-based gas is 1 ppm or more and 100,000 ppm or less of a carbon concentration of the hydrocarbon-based gas.

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