MEMORY DEVICE WITH REPAIR OF FAILED MAIN BANK USING REDUNDANT BANK - Patent application

Abstract

To provide a memory device for repairing a failed main bank using a redundant bank.SOLUTION: A memory device 1700 includes an array of memory cells including P (P is a positive integer) groups of banks. Each group of banks includes N main banks 702 (for example, N=8) and a redundant bank 704 for simultaneous data input / output, and the P redundant banks are included and shared in the P groups of banks. An I / O circuit 407 is coupled to the P groups of banks in the memory device 1700 via, for example, a page buffer / sense amplifier 404 and a column decoder / bit line driver 406 or a page buffer / sense amplifier section 1406 and a column decoder / bit line driver section 1506.SELECTED DRAWING: Figure 17

Description

[Technical field]

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS This application claims the benefit of priority to International Application No. PCT / CN2021 / 082696, filed March 24, 2021, and entitled "MEMORY DEVICE WITH FAILED MAIN BANK REPAIR USING REDUNDANT BANK," and International Application No. PCT / CN2021 / 082687, filed March 24, 2021, and entitled "MEMORY DEVICE WITH FAILED MAIN BANK REPAIR USING REDUNDANT BANK," both of which are incorporated by reference in their entireties herein.

[0002] The present disclosure relates to memory devices and methods of operating the same. [Background technology]

[0003] Flash memory is a low-cost, high-density, non-volatile solid-state storage medium that can be electrically erased and reprogrammed. Flash memory includes NOR flash memory or NAND flash memory. As the number of memory cells in flash memory continues to increase, faulty (defective) memory cells may occur during the manufacturing of memory devices.

[0004] For example, most NAND flash memory devices leave the manufacturing facility with some faulty memory cells. These cells are typically identified according to a specified faulty cell marking strategy. By allowing for some faulty cells, manufacturers can achieve a higher yield than if they had to ensure that all cells were good. This significantly reduces the cost of NAND flash memory and only slightly reduces the storage capacity of the part. Summary of the Invention [Means for solving the problem]

[0005] In one aspect, a memory device includes an array of memory cells, an input / output (I / O) circuit, and an I / O control logic coupled to the I / O circuit. The array of memory cells includes P groups of banks. Each group of banks includes N main banks and a redundant bank such that P redundant banks are included in and shared by the P groups of banks. P and N are each positive integers. The I / O circuit is coupled to the P groups of banks and configured to direct the P×N data to or from the P×N working banks, respectively. The I / O control logic is configured to determine the P×N working banks from the P groups of banks based on bank failure information indicating K failed main banks from the P groups of banks. The P×N working banks include K redundant banks of the P redundant banks. K is a positive integer less than or equal to P. The I / O control logic is also configured to control the I / O circuit to direct the P×N data to or from the P×N working banks, respectively.

[0006] In another aspect, a system includes a memory device configured to store data and a memory controller coupled to the memory device and configured to control the memory device. The memory device includes an array of memory cells, an I / O circuit, and an I / O control logic coupled to the I / O circuit. The array of memory cells includes P groups of banks. Each group of banks includes N main banks and a redundant bank such that P redundant banks are included in and shared by the P groups of banks. P and N are each positive integers. The I / O circuit is coupled to the P groups of banks and configured to direct the P×N data to or from the P×N working banks, respectively. The I / O control logic is configured to determine the P×N working banks from the P groups of banks based on bank failure information indicating K failed main banks from the P groups of banks. The P×N working banks include K redundant banks of the P redundant banks. K is a positive integer less than or equal to P. The I / O control logic is also configured to control the I / O circuit to direct the P×N data to or from the P×N working banks, respectively.

[0007] In yet another aspect, a method of operating a memory device is provided. The memory device includes an array of memory cells. The array of memory cells includes P groups of banks. Each group of banks includes N main banks and redundant banks, such that P redundant banks are included in the P groups of banks, where P and N are each positive integers. P×N working banks are determined from the P groups of banks based on bank failure information indicating K failed main banks from the P groups of banks. The P×N working banks include K redundant banks of the P redundant banks, where K is a positive integer less than or equal to P. The P×N data are respectively directed to or from the P×N working banks.

[0008] The accompanying drawings, which are incorporated in and form a part of this specification, illustrate aspects of the present disclosure and, together with the description, serve to further explain the principles of the present disclosure and to enable those skilled in the art to make and use the disclosure. [Brief description of the drawings]

[0009] [Figure 1] FIG. 1 illustrates a block diagram of an example system having a memory device in accordance with some aspects of the disclosure. [Figure 2A] 1 illustrates a diagram of an exemplary memory card having a memory device in accordance with some aspects of the present disclosure. [Figure 2B] 1 illustrates a diagram of an exemplary solid-state drive (SSD) having a memory device in accordance with some aspects of the present disclosure. [Diagram 3] 1 illustrates a schematic diagram of an exemplary memory device including peripheral circuitry in accordance with some aspects of the present disclosure. [Figure 4] 1 illustrates a block diagram of an exemplary memory device including a memory cell array and peripheral circuits in accordance with some aspects of the disclosure. [Diagram 5] 1 shows a block diagram of a memory device that implements a failed main bank repair scheme using redundant banks. [Figure 6A] 6 illustrates a failed main bank repair scheme using redundant banks implemented by the memory device of FIG. 5. [Figure 6B] 6 illustrates a failed main bank repair scheme using redundant banks implemented by the memory device of FIG. 5. [Figure 7] 1 illustrates a block diagram of an exemplary memory device implementing a failed main bank repair scheme using a redundant bank for data input in accordance with some aspects of the present disclosure. [Figure 8] 1 illustrates a block diagram of an exemplary memory device implementing a failed main bank repair scheme using a redundant bank for data output in accordance with some aspects of the present disclosure. [Figure 9] 1 illustrates a block diagram of example I / O control logic in a memory device in accordance with certain aspects of the present disclosure. [Figure 10A] 10 illustrates an exemplary failed main bank repair scheme using redundant banks implemented by the memory devices of FIGS. 7-9, according to some aspects of the disclosure. [Figure 10B] 10 illustrates an exemplary failed main bank repair scheme using redundant banks implemented by the memory devices of FIGS. 7-9, according to some aspects of the disclosure. [Figure 10C] 10 illustrates an exemplary failed main bank repair scheme using redundant banks implemented by the memory devices of FIGS. 7-9, according to some aspects of the disclosure. [Figure 11] 1 illustrates a flowchart of an exemplary method for operating a memory device having a failed main bank and a redundant bank in accordance with some aspects of the present disclosure. [Figure 12] 4 illustrates a flowchart of another exemplary method for operating a memory device having a failed main bank and a redundant bank in accordance with some aspects of the present disclosure. [Figure 13] 1 illustrates a schematic diagram of an exemplary memory device including multiple planes in accordance with some aspects of the present disclosure. [Figure 14A] 1 illustrates a schematic diagram of an exemplary plane within a memory device in accordance with some aspects of the present disclosure. [Figure 14B] 14B illustrates a schematic diagram of an example data bus in the plane of FIG. 14A according to some aspects of the disclosure. [Figure 15A] 1 illustrates a block diagram of an exemplary memory device including a first level memory unit having multiple second level memory units and I / O circuitry in accordance with some aspects of the disclosure. [Figure 15B] 1 illustrates a block diagram of an exemplary memory device including a die having multiple planes and I / O circuitry in accordance with some aspects of the disclosure. [Figure 15C] 1 illustrates a block diagram of another example memory device including a die having multiple planes and I / O circuitry in accordance with some aspects of the disclosure. [Figure 15D]15D shows a schematic diagram of an example data bus in the memory device of FIG. 15C according to some aspects of the disclosure. [Figure 16A] 1 illustrates a schematic diagram of an exemplary memory device, each including multiple planes and multiple I / O circuits, in accordance with some aspects of the disclosure. [Figure 16B] 1 illustrates a schematic diagram of an exemplary memory device, each including multiple planes and multiple I / O circuits, in accordance with some aspects of the disclosure. [Figure 16C] 1 illustrates a schematic diagram of an exemplary memory device, each including multiple planes and multiple I / O circuits, in accordance with some aspects of the disclosure. [Figure 16D] 1 illustrates a schematic diagram of an exemplary memory device, each including multiple planes and multiple I / O circuits, in accordance with some aspects of the disclosure. [Figure 17] 1 illustrates a schematic diagram of an example memory device that implements a failed main bank repair scheme at the data input using a write multiplexer (MUX) array having multiple write sub-arrays in accordance with some aspects of the present disclosure. [Figure 18A] 1 illustrates a schematic diagram of an example memory device that implements a failed main bank repair scheme at the data input using a write MUX array with two write sub-arrays, in accordance with some aspects of the disclosure. [Figure 18B] 18B illustrates an exemplary failed main bank repair scheme at the data input implemented by the memory device of FIG. 18A in accordance with some aspects of the present disclosure. [Figure 18C] 18B illustrates an exemplary failed main bank repair scheme at the data input implemented by the memory device of FIG. 18A in accordance with some aspects of the present disclosure. [Figure 18D] 1 illustrates a schematic diagram of another example memory device that implements a failed main bank repair scheme at the data input using a write MUX array with two write sub-arrays, in accordance with some aspects of the disclosure. [Figure 19A]1 illustrates a schematic diagram of an example memory device that implements a failed main bank repair scheme at the data input using a write MUX array with three write sub-arrays, in accordance with some aspects of the disclosure. [Figure 19B] 19B illustrates an exemplary failed main bank repair scheme at the data input implemented by the memory device of FIG. 19A in accordance with some aspects of the present disclosure. [Figure 19C] 19B illustrates an exemplary failed main bank repair scheme at the data input implemented by the memory device of FIG. 19A in accordance with some aspects of the present disclosure. [Figure 20] 1 illustrates a schematic diagram of an example memory device that implements a failed main bank repair scheme at the data output using a read MUX array with multiple read sub-arrays in accordance with some aspects of the disclosure. [Figure 21A] 1 illustrates a schematic diagram of an example memory device that implements a failed main bank repair scheme at the data output using a read MUX array with two read sub-arrays, in accordance with some aspects of the disclosure. [Figure 21B] FIG. 21A illustrates an exemplary failed main bank repair scheme at data output implemented by a memory device in accordance with some aspects of the present disclosure. [Figure 21C] 1 illustrates a schematic diagram of another example memory device that implements a failed main bank repair scheme at the data output using a read MUX array with two read sub-arrays in accordance with some aspects of the disclosure. [Figure 22A] 1 illustrates a schematic diagram of an example memory device that implements a failed main bank repair scheme at the data output using a read MUX array with three read sub-arrays, in accordance with some aspects of the disclosure. [Figure 22B] 21B illustrates an exemplary failed main bank repair scheme at the data output implemented by the memory device of FIG. 21A in accordance with some aspects of the present disclosure. [Figure 22C]21B illustrates an exemplary failed main bank repair scheme at the data output implemented by the memory device of FIG. 21A in accordance with some aspects of the present disclosure. [Diagram 23] 4 illustrates a flowchart of an example method for operating a memory device implementing a failed main bank repair scheme in accordance with some aspects of the present disclosure. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0010] The present disclosure will be described with reference to the accompanying drawings.

[0011] While specific configurations and arrangements are discussed, it should be understood that this is done for illustrative purposes only. Thus, other configurations and arrangements can be used without departing from the scope of the present disclosure. The present disclosure can also be used in a variety of other applications. The functional and structural features described in this disclosure can be combined, coordinated, and modified with each other in ways not specifically shown in the drawings, such that these combinations, coordination, and modifications are within the scope of the present disclosure.

[0012] Generally, terminology can be understood, at least in part, from usage in context. For example, the term "one or more" as used herein can be used to describe any feature, structure, or feature in the singular, or can be used to describe a combination of features, structures, or features in the plural, depending at least in part on the context. Similarly, terms such as "a," "an," or "the" can be understood to convey singular usage or plural usage, depending at least in part on the context. Furthermore, the term "based on" is not necessarily intended to convey an exclusive set of factors, but instead can be understood to allow for the presence of additional factors not necessarily explicitly described, depending at least in part on the context.

[0013] As the number of memory cells continues to increase, the possibility of memory cells failing during the manufacturing of memory devices also increases in order to meet the ever-increasing demand for larger storage capacity. One way to deal with failed memory cells is to add redundant memory cell areas (e.g., redundant banks, also known as redundant columns or groups) in addition to main memory cell areas (e.g., main banks, also known as main columns or groups). For each memory device, if the number of defective memory cell areas identified during post-manufacturing testing falls below a limit (e.g., does not exceed the number of redundant memory cell areas), then a repair scheme can be adopted so that the redundant memory cell areas can replace the failed memory cell areas for reading and writing data during operation of the memory device.

[0014] Some known memory devices, such as NAND flash memory devices, can perform simultaneous data input / output (I / O) operations to read and write eight pieces of data (e.g., eight bytes) to or from eight physically separated main memory cell regions (e.g., main banks). An equal number of eight redundant memory cell regions (e.g., redundant banks) are coupled to the main memory cell regions, respectively. When a main memory cell region is identified as a faulty main memory cell region, the corresponding redundant memory cell region replaces the faulty memory cell region in data input and output according to a known repair scheme. However, such repair schemes and redundant bank designs have various problems. For example, a large number of redundant banks may waste chip area, since often not all of them can be used. A relatively large number of redundant banks may also affect the flexibility of the repair scheme. Also, the additional routing length to couple each main bank and each redundant bank may increase skew on the data lines.

[0015] To address one or more of the aforementioned problems, the present disclosure introduces a solution that allows a smaller number of redundant banks than main banks to be used with a flexible repair scheme to handle a failed main bank in a memory device, such as a NAND flash memory device. Consistent with certain aspects of the present disclosure, multiplexers can be used to couple adjacent banks together so that input or output data can be shifted between adjacent banks (either main banks or redundant banks). As a result, redundant banks are no longer dedicated to a particular main bank, but can instead replace a failed main bank without coupling to each main bank. Thus, the total chip area of ​​the redundant banks can be significantly reduced, as well as the possibility of wasting redundant bank area. Furthermore, the data shifting-based repair scheme can also reduce the skew between each data line, as each bank is connected only to its adjacent bank, resulting in shorter data line wiring lengths. The redundant bank design and data shifting-based repair scheme disclosed herein can increase repair flexibility even with a smaller number of redundant banks compared to known approaches.

[0016] Consistent with certain aspects of the present disclosure, the data shifting based repair scheme disclosed herein can be implemented at the die level (or plane level) of a memory device. The I / O circuitry and I / O control logic used to implement the data shifting based repair scheme can be shared by multiple planes in a die (or shared by multiple plane sections in a plane). For example, instead of implementing an instance of the I / O circuitry and an instance of the I / O control logic in each plane section of every plane, the I / O circuitry and I / O control logic can be implemented on the die and shared by different planes in the die. Alternatively, an instance of the I / O circuitry and an instance of the I / O control logic can be implemented on each plane and shared by different plane sections in the respective plane. As a result, the I / O circuitry and I / O control logic are shared in different planes (or different plane sections of each plane) of the die, reducing circuit area overhead and making it easier to implement optimization of timing control of the data shifting based repair scheme.

[0017] Consistent with certain aspects of the present disclosure, each group of banks for simultaneous data input / output in a memory device may include multiple main banks and redundant banks. The I / O circuitry disclosed herein may include a write MUX array and a read MUX array, each of which includes multiple subarrays (e.g., multiple levels of data shifting subcircuits). In this case, the redundant bank in each group of banks may not only be shared by multiple main banks in the same group, but also by one or more other groups of banks to replace a failed main bank in one or more other groups. Thus, the total chip area of ​​the redundant bank, as well as the possibility of wasting redundant bank area, may be further reduced.

[0018] FIG. 1 illustrates a block diagram of an exemplary system 100 having a memory device according to some aspects of the present disclosure. The system 100 may be a mobile phone, a desktop computer, a laptop computer, a tablet, an in-vehicle computer, a gaming console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an augmented reality (AR) device, or other suitable electronic device having storage. As shown in FIG. 1, the system 100 may include a host 108 and a memory system 102 having one or more memory devices 104 and a memory controller 106. The host 108 may be a processor of an electronic device, such as a central processing unit (CPU), or a system on a chip (SoC), such as an application processor (AP). The host 108 may be configured to transmit or receive data to or from the memory device 104.

[0019] The memory device 104 may be any memory device disclosed in this disclosure. As disclosed in detail below, the memory device 104, such as a NAND flash memory device, may include fewer redundant banks than main banks and may implement a flexible data shifting-based repair scheme with data input and output operations to handle faulty main banks identified during post-manufacturing testing of the memory device 104.

[0020] According to some implementations, the memory controller 106 is coupled to the memory device 104 and the host 108 and configured to control the memory device 104. The memory controller 106 can manage data stored in the memory device 104 and communicate with the host 108. In some implementations, the memory controller 106 is designed to operate in low duty cycle environments such as Secure Digital (SD) cards, Compact Flash (CF) cards, Universal Serial Bus (USB) flash drives, or other media used in electronic devices such as personal computers, digital cameras, and mobile phones. In some implementations, the memory controller 106 is designed to operate in high duty cycle environments SSDs or embedded multimedia cards (eMMCs) used as data storage in mobile devices such as smartphones, tablets, and laptop computers, and enterprise storage arrays. The memory controller 106 can be configured to control operations of the memory device 104, such as read, erase, and program operations. The memory controller 106 may also be configured to manage various functions related to data stored or to be stored in the memory device 104, including, but not limited to, bad block management, garbage collection, logical to physical address translation, wear leveling, etc. In some implementations, the memory controller 106 is further configured to process error correction codes (ECC) on data read from or written to the memory device 104. Any other suitable functions may also be performed by the memory controller 106, such as, for example, formatting the memory device 104. The memory controller 106 may communicate with an external device (e.g., the host 108) according to a particular communication protocol.For example, the memory controller 106 may communicate with external devices via at least one of a variety of interface protocols, such as a USB protocol, an MMC protocol, a Peripheral Component Interconnect (PCI) protocol, a PCI-express (PCI-E) protocol, an Advanced Technology Attachment (ATA) protocol, a Serial ATA protocol, a Parallel ATA protocol, a Small Computer Small Area Interface (SCSI) protocol, an Enhanced Small Disk Interface (ESDI) protocol, an Integrated Drive Electronics (IDE) protocol, a Firewire protocol, and the like.

[0021] The memory controller 106 and the one or more memory devices 104 can be integrated into various types of storage devices, and can be included in the same package, such as a Universal Flash Storage (UFS) package or an eMMC package. That is, the memory system 102 can be implemented and packaged into various types of end electronic products. In one example shown in FIG. 2A, the memory controller 106 and the single memory device 104 can be integrated into a memory card 202. The memory card 202 can include a PC card (PCMCIA, Personal Computer Memory Card International Association), a CF card, a Smart Media (SM) card, a memory stick, a multimedia card (MMC, RS-MMC, MMCmicro), an SD card (SD, miniSD, microSD, SDHC), UFS, and the like. The memory card 202 can further include a memory card connector 204 that couples the memory card 202 to a host (e.g., the host 108 of FIG. 1). In another example shown in FIG. 2B, the memory controller 106 and the multiple memory devices 104 can be integrated into an SSD 206. The SSD 206 may further include an SSD connector 208 that couples the SSD 206 to a host (e.g., the host 108 in FIG. 1). In some implementations, the storage capacity and / or operating speed of the SSD 206 is greater than that of the memory card 202.

[0022] FIG. 3 illustrates a schematic circuit diagram of an exemplary memory device 300 including peripheral circuits according to some aspects of the disclosure. The memory device 300 may be an example of the memory device 104 of FIG. 1. The memory device 300 may include a memory cell array 301 and peripheral circuits 302 coupled to the memory cell array 301. The memory cell array 301 may be a NAND flash memory cell array provided in the form of an array of NAND memory strings 308, each of which has memory cells 306 extending vertically above a substrate (not shown). In some implementations, each NAND memory string 308 includes multiple memory cells 306 coupled in series and stacked vertically. Each memory cell 306 may hold a continuous analog value, such as a voltage or charge, that depends on the number of electrons trapped within the area of ​​the memory cell 306. Each memory cell 306 may be either a floating gate type memory cell including a floating gate transistor, or a charge trap type memory cell including a charge trap transistor.

[0023] In some implementations, each memory cell 306 is a single level cell (SLC) that has two possible memory states and can therefore store one bit of data. For example, a first memory state "0" can correspond to a first range of voltages, and a second memory state "1" can correspond to a second range of voltages. In some implementations, each memory cell 306 is a multi-level cell (MLC) that can store more than one bit of data in more than four memory states. For example, an MLC can store two bits per cell, three bits per cell (also called a triple level cell (TLC)), or four bits per cell (also called a quad level cell (QLC)). Each MLC can be programmed to assume a range of possible nominal storage values. In one example, if each MLC stores two bits of data, the MLC can be programmed to take one of three possible programming levels from an erased state by writing one of three possible nominal storage values ​​to the cell. A fourth nominal storage value can be used for the erased state.

[0024] 3, each NAND memory string 308 may include a source select gate (SSG) 310 at its source end and a drain select gate (DSG) 312 at its drain end. The SSG 310 and DSG 312 may be configured to activate a selected NAND memory string 308 (column of the array) during read and program operations. In some implementations, the SSGs 310 of the NAND memory strings 308 in the same block 304 are coupled to the same source line (SL) 314, e.g., a common SL, e.g., to ground. According to some implementations, the DSGs 312 of each NAND memory string 308 are coupled to a respective bit line 316 through which data can be read and written via an output bus (not shown). In some implementations, each NAND memory string 308 is configured to be selected or deselected by applying a select voltage (e.g., equal to or greater than the threshold voltage of a transistor having DSG 312) or a deselect voltage (e.g., 0V) to the respective DSG 312 via one or more DSG lines 313 and / or by applying a select voltage (e.g., greater than the threshold voltage of a transistor having SSG 310) or a deselect voltage (e.g., 0V) to the respective SSG 310 via one or more SSG lines 315.

[0025] As shown in FIG. 3, the NAND memory strings 308 can be organized into multiple blocks 304, and each block can have a common source line 314. In some implementations, each block 304 is the basic data unit of an erase operation. That is, all memory cells 306 on the same block 304 are erased at the same time. Memory cells 306 of adjacent NAND memory strings 308 can be coupled via word lines 318 that select which row of memory cells 306 is affected by read and program operations. In some implementations, each word line 318 is coupled to a page 320 of memory cells 306, which is the basic data unit of a program operation. The size of one page 320 in bits can be related to the number of NAND memory strings 308 coupled by the word lines 318 in one block 304. Each word line 318 can include multiple control gates (gate electrodes) to each memory cell 306 in the respective page 320, and gate lines coupling the control gates.

[0026] The peripheral circuits 302 can be coupled to the memory cell array 301 via bit lines 316, word lines 318, source lines 314, SSG lines 315, and DSG lines 313. The peripheral circuits 302 can include any suitable analog, digital, and mixed-signal circuitry to facilitate operation of the memory cell array 301 by applying and sensing voltage and / or current signals to and from each target memory cell 306 via the bit lines 316, word lines 318, source lines 314, SSG lines 315, and DSG lines 313. The peripheral circuits 302 can include various types of peripheral circuits formed using metal-oxide-semiconductor (MOS) technology. For example, FIG. 4 illustrates several exemplary peripheral circuits 302 including a page buffer / sense amplifier 404, a column decoder / bit line driver 406, an I / O circuit 407, a row decoder / word line driver 408, a voltage generator 410, control logic 413, a register 414, an interface 416, and a data bus 418. The control logic 413 may include I / O control logic 412 configured to control the operation of the I / O circuitry 407. It will be understood that in some examples, additional peripheral circuitry not shown in FIG.

[0027] The page buffer / sense amplifier 404 can be configured to read and program (write) data from and to the memory cell array 301 according to control signals from the control logic 413. In one example, the page buffer / sense amplifier 404 can store a page of program data (write data) to be programmed into one page 320 of the memory cell array 301. In another example, the page buffer / sense amplifier 404 can perform a program verify operation to ensure that data has been properly programmed into the memory cells 306 coupled to a selected word line 318. In yet another example, the page buffer / sense amplifier 404 can also sense low power signals from the bit lines 316 representing data bits stored in the memory cells 306 and amplify small voltage swings to recognizable logic levels in a read operation.

[0028] The column decoder / bit line driver 406 can be configured to select one or more NAND memory strings 308 by applying a bit line voltage generated from a voltage generator 410 as controlled by the control logic 413. The I / O circuitry 407 can be coupled to the page buffer / sense amplifier 404 and / or the column decoder / bit line driver 406 and can be configured to direct (route) data inputs from a data bus 418 to a desired memory cell region (e.g., a bank) of the memory cell array 301, as well as direct data outputs from the desired memory cell region to the data bus 418. As described in more detail below, the I / O circuitry 407 can include a write multiplexer (MUX) array and a read MUX array to implement the flexible data shifting based repair scheme disclosed herein, as controlled by the control logic 413 (including the I / O control logic 412).

[0029] The row decoder / word line driver 408 can be configured to be controlled by the control logic 413, a selected block 304 of the memory cell array 301, and a word line 318 of the selected block 304. The row decoder / word line driver 408 can be further configured to drive the selected word line 318 using a word line voltage generated from a voltage generator 410. The voltage generator 410 can be controlled by the control logic 413 and configured to generate word line voltages (e.g., read voltages, program voltages, pass voltages, local voltages, and verify voltages) that are provided to the memory cell array 301.

[0030] As part of the peripheral circuit 302, the control logic 413 may be coupled to the other peripheral circuits mentioned above and configured to control the operation of the other peripheral circuits. The registers 414 may be coupled to the control logic 413 and may include a status register, a command register, and an address register for storing status information, command operation codes (OP codes), and command addresses for controlling the operation of each peripheral circuit. The interface 416 may be coupled to the control logic 413 and may function as a control buffer to buffer and relay control commands received from a host (not shown) to the control logic 413 and relay status information received from the control logic 413 to the host. The interface 416 may also be coupled to the I / O circuit 407 via a data bus 418 and may function as a data I / O interface and a data buffer, buffering and relaying write data received from the host (not shown) to the I / O circuit 407 and relaying read data from the I / O circuit 407 to the host. For example, the interface 416 may include a data I / O 417 coupled to the data bus 418.

[0031] FIG. 5 shows a block diagram of a memory device 500 that implements a failed main bank repair scheme using redundant banks. The memory cell array 301 in the memory device 500 includes eight main banks 502 ( <0> …and <7> ) and eight redundant banks 504 ( <0> …and <7> ), and each main bank 502 includes j sets of data lines (L <0> ...or L <7> ) to their respective redundant banks 504. That is, each main bank 502 has a dedicated redundant bank 504 as a backup in case the main bank 502 is identified as a faulty main bank during post-manufacturing testing. The memory device 500 can simultaneously input or output eight pieces of data (e.g., eight bytes) to each of the eight main banks 502. The memory device 500 includes an i set of eight main banks 502 and a j set of eight redundant banks 504.

[0032] The column decoder / bit line driver 406 of the memory device 500 includes i main decoders 510 each coupled to an i set of eight main banks 502, and j redundant decoders 511 each coupled to a j set of eight redundant banks 504. The column decoder / bit line driver 406 of the memory device 500 also includes a main pre-decoder 506 coupled to the i main decoders 510, and a redundant (RED) pre-decoder 508 coupled to the j redundant decoders 511. The I / O control logic 412 of the memory device 500 implements the failed main bank repair scheme by controlling the main pre-decoder 506 and the redundant pre-decoder 508 via control signals, such as a redundancy enable signal (RED_EN). Based on the control signals from the I / O control logic 412, the main pre-decoder 506 provides a select / deselect signal (YSEL <0> …, YSEL ) to disable any one of the eight main banks 502 that is a faulty main bank in each main bank set. Meanwhile, based on a control signal from the I / O control logic 412, the redundancy predecoder 508 causes each of the j redundancy decoders 511 to enable any one of the eight redundant banks 504, which is controlled by a select / deselect signal (YREDSEL <0> …and YREDSEL <j>) are coupled to the corresponding failing main bank through respective bit lines in each redundant bank set. The page buffer / sense amplifiers 404 of the memory device 500 are shared by the main bank 502 and the redundant bank 504 for read and write operations.

[0033] 6A and 6B illustrate a failed main bank repair scheme using redundant banks implemented by the memory device 500 of FIG. 5. FIGS. 6A and 6B show one set of eight main banks 502 and one set of eight redundant banks 504. The eight main banks 502 include bank 0 low (B0_L), bank 0 high (B0_H), bank 1 low (B1_L), bank 1 high (B1_H), bank 2 low (B2_L), bank 2 high (B2_H), bank 3 low (B3_L), and bank 3 high (B3_H). The eight main banks 502 are isolated from each other. That is, data intended for one main bank 502 cannot be redirected to another main bank 502 because they are not coupled by data lines. Instead, each main bank 502 has only one data line between them (e.g., L in FIG. 5). <0> … or L <7> ) to a respective redundant bank 504 (the adjacent one on the right as shown in FIGS. 6A and 6B).

[0034] 6A illustrates the case where all eight main banks 502 are working banks, i.e., there are no faulty main banks identified by post-manufacturing testing. In this case, the first eight data (0, ..., and 7) are directed to or from each of the eight main banks 502, while all eight redundant banks 704 are unused, i.e., no data (labeled "x"). Similarly, the second eight data (8 ..., and 15) are directed to or from each of the eight main banks 502, while all eight redundant banks 504 remain unused, i.e., no data (labeled "x").

[0035] FIG. 6B illustrates the case where one of the eight main banks 502 is a faulty main bank identified by post-manufacturing testing. In one example where B2_H is the faulty main bank, seven of the first eight data (0, 1, 2, 3, 4, 6, and 7) are directed to or from the seven working main banks 502 (except B2_H), respectively, while data (5) is redirected to or from B2_H. That is, the faulty main bank B2_H is replaced by a dedicated backup (redundant bank 504 coupled to B2_H for data input and output). In another example where B0_L is the faulty main bank, seven of the second eight data (9..., and 15) are directed to or from the seven working main banks 502 (except B0_L), respectively, while data (8) is redirected to or from the redundant bank 504 coupled to B0_L. That is, the failed main bank B0_L is replaced with a dedicated backup (redundant bank 504 coupled to B0_L for data input and output).

[0036] As described above, the redundant bank design and related repair scheme shown in Figures 5, 6A, and 6B suffer from various problems. First, seven of the eight redundant banks 504 are wasted, and only one of the redundant banks 504 is used to repair one failed main bank. Second, the repair scheme lacks flexibility because the failed main bank can only be replaced by a pre-assigned dedicated redundant bank 504. Third, each main bank 502 needs to be coupled to a respective redundant bank 504 via data lines, which increases the data line routing length and data line skew.

[0037] To overcome one or more of these problems, the present disclosure provides an improved redundant bank design having a smaller number of redundant banks and an associated flexible data shifting-based repair scheme. Consistent with the scope of the present disclosure, a memory device may include an array of memory cells (e.g., memory cell array 301 of FIGS. 3 and 4), an I / O circuit (e.g., I / O circuit 407 of FIG. 4), and a control logic (e.g., I / O control logic 412 of FIG. 4). The array of memory cells may include N main banks and M redundant banks, where N and M are each positive integers and N is greater than M. That is, the array of memory cells may have a smaller number of redundant banks than the main banks. It is understood that, similar to memory device 500 of FIG. 5, the array of memory cells may include multiple sets of N main banks as well as multiple sets of M redundant banks. Nevertheless, N is the number of data that can be simultaneously input (written / programmed) and output (read) to the array of memory cells. It is also understood that the term "bank" as used herein (in the context of either a "main bank," a "redundant bank," or a "working bank") may refer to a region of memory cells to which or from which one of N simultaneous data is directed. A bank may be, for example, a portion of a page, block, or plane within an array of memory cells.

[0038] The I / O circuitry may be coupled to the N main banks and the M redundant banks and configured to direct the N pieces of data to or from the N working banks, respectively. In some implementations, the I / O circuitry is coupled to each pair of adjacent banks of the N main banks and the M redundant banks, such that the I / O circuitry is configured to direct one piece of data to or from either bank of the pair of adjacent banks (e.g., see Figures 7 and 8 below).

[0039] In some implementations, M is equal to 1. That is, a single redundant bank can be used to repair a set of N (2, 3, 4, 5, etc.) main banks. This can significantly reduce the chip area of ​​the redundant banks and the waste of unused redundant banks. For example, FIGS. 7 and 8 show block diagrams of an example memory device 700 implementing a failed main bank repair scheme using redundant banks for data input and data output, respectively, according to some aspects of the present disclosure. The memory device 700 may be an example of the memory device 300 of FIGS. 3 and 4. For ease of explanation, details of components within the memory device 300 may be omitted in the description of the memory device 700 and may apply to the memory device 700 as well. As shown in FIGS. 7 and 8, the memory device 700 may include a memory cell array 301 having eight main banks 702 (B0_L, B0_H, B1_L, B1_H, B2_L, B2_H, B3_L, and B3_H) and one redundant bank 704 (RED). That is, in memory device 700, N is equal to 8 and M is equal to 1. In other words, memory cell array 301 includes nine banks, including eight main banks 702 and one redundant bank 704, according to some implementations.

[0040] The I / O circuitry 407 may be coupled, for example, to eight main banks 702 and one redundant bank 704 via a page buffer / sense amplifier 404 and a column decoder / bit line driver 406. In some implementations shown in FIG. 7, at data input (e.g., a write operation), the page buffer / sense amplifier 404 and the column decoder / bit line driver 406 include nine drivers 706 respectively coupled to the eight main banks 702 and one redundant bank 704. In some implementations shown in FIG. 8, at data output (e.g., a read operation), the page buffer / sense amplifier 404 and the column decoder / bit line driver 406 include nine sense amplifiers 802 respectively coupled to the eight main banks 702 and one redundant bank 704.

[0041] The I / O circuit 407 can be configured to direct eight pieces of data to or from eight working banks, respectively. In some implementations shown in FIG. 7, at the data input, the I / O circuit 407 is configured to direct eight input data (e.g., write data: gwd<7:0>, gwd<15:8>, gwd<23:16>, gwd<31:24>, gwd<39:32>, gwd<47:40>, gwd<55:48>, and gwd<63:56>) to eight working banks (i.e., eight main banks 702 and one redundant bank 704) of the nine banks, e.g., seven main banks 702 and one redundant bank 704. In some implementations shown in Figure 8, at the data output, the I / O circuit 407 is configured to direct eight output data (e.g., read data: grd<7:0>, grd<15:8>, grd<23:16>, grd<31:24>, grd<39:32>, grd<47):40>, grd<55:48>, and grd<63:56>) from eight of the nine banks, e.g., seven main banks 702 and one redundant bank 704. As shown in Figures 7 and 8, in some implementations, the I / O circuit 407 is coupled to each pair of adjacent banks, so that the I / O circuit 407 is configured to direct one write data (gwd) to either bank of the pair of adjacent banks or one read data (grd) from either bank of the pair of adjacent banks. The pair of adjacent banks can be either both main banks 702, or one main bank 702 and one redundant bank 704. In some implementations, the redundant bank 704 is coupled to two main banks 702 via the I / O circuitry 407. The redundant bank 704 is coupled to two main banks 702 (B1_H and B2_L) by the I / O circuitry 407 in the middle of the eight main banks 702 as shown in Figures 7 and 8, respectively, but it will be understood that in some examples, the redundant bank 704 may be coupled to any two main banks 702 by the I / O circuitry 407, respectively, or to only one main bank 702 (e.g., B0_L or B3_H) at the end of the eight main banks 702.

[0042] The I / O circuitry 407 may be implemented with one or more MUX arrays. As shown in FIG. 7, in some implementations, the I / O circuitry 407 of the memory device 700 includes a write MUX array 707. The write MUX array 707 may include a set of nine write MUXes 708 each coupled to eight main banks 702 and one redundant bank 704 for data input. Each write MUX 708 may include an output (Out), two inputs (A and B), and a selection port (S). The output of each write MUX 708 is coupled to a respective bank 702 or 704. The selection port of the write MUX 708 may be configured to receive a write select signal (red_en_b0_l_wt, ..., red_en_b12_wt, ..., or red_en_b3_h_wt) indicating the selection of one input (A or B). For example, a positive bias write select signal, i.e., a write select signal, when enabled, may select input B.

[0043] In some implementations, except for the write MUX 708 coupled to two main banks 702 (B0_L and B3_H) at both ends (i.e., coupled to only one other main bank 702), each write MUX 708 coupled to a respective main bank 702 has two inputs configured to input two data, each including one write data intended for the respective main bank 702 and another write data intended for an adjacent main bank 702. For example, the write MUX 708 coupled to B0_H may have input A configured to input write data gwd<15:8> and input B configured to input write data gwd<7:0>.

[0044] With respect to the write MUX 708 coupled to the redundant bank 704, it may have two inputs configured to input two pieces of data, each including one write data intended for one adjacent main bank 702 and another write data intended for another adjacent main bank 702. For example, the write MUX 708 coupled to the RED may have an input A configured to input write data gwd<31:24> and an input B configured to input write data gwd<39:32>.

[0045] For a write MUX 708 coupled at its ends to two main banks 702 (B0_L and B3_H), one of its inputs may be configured to input one portion of the write data intended for the respective main bank 702, and another of its inputs may be configured to input a signal indicating data inhibition due to bank failure, such as the system voltage Vdd, such that each write data can be coupled to two inputs of two adjacent banks and input to either input of the two adjacent banks.

[0046] In some implementations, as shown in FIG. 8, the I / O circuitry 407 of the memory device 700 includes a read MUX array 807. The read MUX array 807 may include a set of eight read MUXes 804 coupled to the eight main banks 702 and one redundant bank 704 for data output. Each read MUX 804 may include an output (Out), two inputs (A and B), and a selection port (S). The selection port of the read MUX 804 may be configured to receive a read select signal (red_en_b0_l_rd, ... or red_en_b3_h_rd) indicating the selection of one input (A or B). For example, a positively biased read select signal, i.e., when the read select signal is enabled, input B may be selected.

[0047] In some implementations, each read MUX 804 has two inputs coupled to two adjacent banks. For example, the leftmost read MUX 804 may have input A coupled to B0_L and input B coupled to B0_H. The middle read MUX 804 may have input A coupled to B1_H and input B coupled to RED. In other words, each bank 702 or 704, except for the two main banks 702 (B0_L and B3_H) at both ends, may be respectively coupled to the inputs of two read MUXs 804. The output of each read MUX 804 may be configured to output one data from either input A or B, i.e., one of the data stored in the two adjacent banks, based on a respective read selection signal. For example, the read data gwd<7:0> output from the leftmost read MUX 804 can be from either B0_L or B0_H, and the read data gwd<31:24> output from the middle read MUX 804 can be from either B1_H or RED.

[0048] As described above with respect to FIGS. 7 and 8, the I / O circuitry 407 may be coupled to each pair of adjacent banks and configured to direct data to or from either bank of each pair of adjacent banks. Although an exemplary design of the write MUX array 707 and the read MUX array 807 in the I / O circuitry 407 is described above with respect to the memory device 700, which has eight main banks 702 and one redundant bank 704, a similar design may generally be applied to a memory device having N main banks and M redundant banks, where N and M are each positive integers and N is greater than M. Based on the design of the redundant banks in the memory cell array and the MUX array in the I / O circuitry, a flexible data shifting-based repair scheme may be implemented. The I / O control logic may be coupled to the I / O circuitry and configured to determine N working banks from the N main banks and the M redundant banks based on bank failure information indicating K failed main banks of the N main banks. The N working banks may include K redundant banks of the M redundant banks, where K is a positive integer less than or equal to M. The I / O control logic 412 may be further configured to control the I / O circuitry to direct K of the N pieces of data to or from the K redundant banks, respectively.

[0049] 9, the I / O control logic 412 may include read redundancy enable logic 902, write redundancy enable logic 904, and working bank logic 906. Each logic 902, 904, or 906 may be implemented by a microprocessor, a microcontroller (also known as a microcontroller unit (MCU)), a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA), a programmable logic device (PLD), a state machine, gate logic, discrete hardware circuitry, and other suitable hardware, firmware, and / or software configured to perform various functions described in more detail below. In some implementations, one or more of the read redundancy enable logic 902, write redundancy enable logic 904, and working bank logic 906 are implemented in a content addressable memory (CAM).

[0050] In some implementations, the working bank logic 906 is coupled to the register 414 and configured to obtain bank failure information indicating one or more of the faulty main banks of the main banks of the memory device (e.g., memory device 700), e.g., K faulty main banks of the N main banks. During post-manufacturing testing, faulty (non-functional) memory cells may be detected from the memory device, and each main bank including at least one faulty memory cell may be identified as a faulty main bank. In some implementations, the bank failure information indicates each of the faulty main banks of the memory device and is stored in the memory device, e.g., in the register 414. Thus, each memory device may have its own bank failure information. Before operating the memory device, the working bank logic 906 may obtain the bank failure information from the register 414 and determine the N working banks of the memory device that can be used for data input and output. According to some implementations, the number (N) of working banks is the same as the number (N) of simultaneous input / output data (e.g., 8 in memory device 700). That is, the working bank logic 906 can replace K failed main banks with the same number (K) of redundant banks such that the N working banks can include K redundant banks and N K main banks. In the memory device 700, one failed main bank of the eight main banks 702 can be replaced with a redundant bank 704 to form eight working banks, as determined by the working bank logic 906 of the I / O control logic 412.

[0051] Based on the determined N working banks, the read redundancy enable logic 902, the write redundancy enable logic 904 can be configured to control the I / O circuitry 407 to direct K of the N data to or from the K redundant banks, respectively. In some implementations, for data input, the write redundancy enable logic 904 is coupled to a write MUX 708 in a write MUX array 707 of the I / O circuitry 407 and configured to provide a plurality of write select signals 905 to the write MUX 708. For example, the write redundancy enable logic 904 is coupled to nine write MUXes 708 of the I / O circuitry 407 and configured to provide nine write select signals (e.g., red_en_b0_l_wt,..., red_en_b12_wt..., and red_en_b3_h_wt) to the nine write MUXes 708, respectively, based on the determined eight working banks. In some implementations, for data output, the read redundancy enable logic 902 is coupled to a read MUX 804 in the read MUX array 807 of the I / O circuit 407 and configured to provide multiple read select signals 903 to the read MUX 804. For example, the read redundancy enable logic 902 is coupled to eight read MUXs 804 and configured to provide eight read select signals (e.g., red_en_b0_l_rd, ..., and red_en_b3_h_rd) to the eight read MUXs 804, respectively, based on the determined eight working banks. In some implementations, the read redundancy enable logic 902 and the write redundancy enable logic 904 also provide synchronization signals to the strobe clocks of the read MUXs 804 and the write MUXs 708, respectively, to align the data and select signals.

[0052] Each selection signal can be enabled (e.g., positively biased) or disabled (e.g., negatively biased) based on the K failed main banks. In some implementations, if a first bank of a pair of adjacent banks is one of the K failed main banks, the read redundancy enable logic 902 and the write redundancy enable logic 904 are configured to control the I / O circuitry 407 to direct data to or from a second bank of the pair of adjacent banks. That is, the I / O control logic 412 is configured, according to some implementations, to select one bank of each pair of adjacent banks based on the bank failure information and control the I / O circuitry 407 to direct data to or from the selected bank of each pair of adjacent banks.

[0053] 7, at the data input, the write redundancy enable logic 904 can be configured to control a first write MUX 708 coupled to a first bank (i.e., the failed main bank) to input data from an input A of the first write MUX 708 and inhibit data from being output to the first bank. Instead, the write redundancy enable logic 904 controls a second write MUX 708 coupled to a second bank (e.g., the main bank 702 or the redundant bank 704 adjacent to the first bank) to allow data to be input from an input B of the second write MUX 708 and output data to the second bank. That is, data intended for the failed main bank can be redirected to an adjacent bank, either the main bank 702 or the redundant bank 704, by the write MUX 708 coupled to the failed main bank as controlled by the write redundancy enable logic 904. The same operation can be applied to each pair of adjacent banks such that the data input is shifted between adjacent banks.

[0054] For example, assuming B0_L is the failed main bank, the write redundancy enable logic 904 may enable red_en_b0_l_wt and red_en_b0_h_wt, such that Vdd is input from input B to B0_L and gwd<7:0> is redirected from input B to input B0_H. To shift the data input, the write redundancy enable logic 904 may also enable red_en_b1_l_wt and red_en_b1_h_wt, such that gwd<15:8> is redirected from input B to input B1_L and gwd<23:16> is redirected from input B to input B1_H. The write redundancy enable logic 904 may further disable red_en_b12_wt, such that gwd<31:24> is redirected from input A to input RED. That is, the input data may be shifted from the failed main bank B0_L to the redundant bank RED accordingly. For the other main banks B2_L, B2_H, B3_L, and B3_H, input data shifting may not be required so that the write redundancy enable logic 904 can disable red_en_b2_l_wt, red_en_b2_h_wt, red_en_b3_l_wt, and red_en_b3_h_wt. As a result, each of B2_L, B2_H, B3_L, and B3_H can still input data from input A without data shifting.

[0055] 8, at the data output, the read redundancy enable logic 902 can be configured to control the read MUX 804 coupled to the first and second banks (i.e., the failed main bank and the main bank 702 or redundant bank 704 adjacent to the failed main bank) to enable the output of data from the second bank (e.g., the main bank 702 or redundant bank 704 adjacent to the failed main bank). That is, data intended for the failed main bank can be redirected from the adjacent bank, either the main bank 702 or the redundant bank 704, by the read MUX 804 controlled by the read redundancy enable logic 902. The same operation can be applied to each pair of adjacent banks such that the data output is shifted between the adjacent banks.

[0056] For example, assuming B0_L is the failed main bank, the read redundancy enable logic 902 can enable red_en_b0_1_rd such that grd<7:0> is redirected and output from B0_H coupled to input B. To shift the data output, the read redundancy enable logic 902 can also enable red_en_b0_h_rd, red_en_b1_l_rd, and red_en_b1_h_rd such that grd<15:8> is redirected and output from B1_L coupled to input B, grd<23:16> is redirected and output from B1_H coupled to input B, and grd<31:24> is redirected and output from RED coupled to input B. That is, the output data can be shifted from the failed main bank B0_L to the redundant bank RED accordingly. For the other main banks B2_L, B2_H, B3_L, and B3_H, no output data shift is required, and the read redundancy enable logic 902 can disable red_en_b2_l_rd, red_en_b2_h_rd, red_en_b3_l_rd, and red_en_b3_h_rd. As a result, data can still be output from input A from B2_L, B2_H, B3_L, and B3_H without data shifting.

[0057] 10A-10C show further examples of a faulty main bank repair scheme using a redundant bank 704 implemented by a memory device 700 according to some aspects of the disclosure. FIG. 10A shows the case where all of the eight main banks 702 are working banks, i.e., there are no faulty main banks identified by post-manufacturing testing. In this case, the first eight data (0, ..., and 7) are directed to or from the eight main banks 702, respectively, while the redundant bank 704 may not be used, i.e., no data (labeled "x"). Similarly, the second eight data (8 ..., and 15) may again be directed to or from the eight main banks 702, respectively, while the redundant bank 704 may remain unused, i.e., no data (labeled "x").

[0058] 10B and 10C show the case where one of the eight main banks 702 is a faulty main bank identified by post-manufacturing testing. As shown in FIG. 10B, in one example where B2_H is a faulty main bank, the first four (1, 2, 3, and 4) of the first eight data may be directed to or from the four corresponding working main banks B0_L, B0_H, B1_L, and B1_H, respectively, which are separated from B2_H by the redundant bank 704. Data (5) intended for B2_H may be redirected to the adjacent working main bank B2_L, and data (4) intended for B2_L may be redirected to the redundant bank 704 (data shifting left). B2_H may be unused. That is, data shifting may occur between B2_H and the redundant bank 704. The last two (6 and 7) of the first eight data can be directed to or from the corresponding two working main banks B3_L and B3_H, respectively, without data shifting. In another example where B0_L is the faulty main bank, the first four (8, 9, 10, and 11) of the second eight data can be redirected to or from the adjacent working main banks B0_H, B1_L, and B1_H and the redundant bank 704 (shifting data to the right), respectively. B0_L can be unused. That is, data shifting can occur between B0_L and the redundant bank 704. The last four (12, 13, 14, and 15) of the second eight data can be directed to or from the corresponding four working main banks B2_L, B2_H, B3_L, and B3_H, respectively, without data shifting.

[0059] As shown in FIG. 10C, in one example where B1_L is a faulty main bank, the first two (0 and 1) of the first eight data may be directed to or from the two corresponding working main banks B0_L and B0_H, respectively. The next two (2 and 3) of the first eight data may be redirected to or from the adjacent working main bank B1_H and the redundant bank 704 (data shifting to the right), respectively. B1_L may be unused. That is, data shifting may occur between B1_L and the redundant bank 704. The last four (4, 5, 6, and 7) of the second eight data may be directed to or from the corresponding four working main banks B2_L, B2_H, B3_L, and B3_H, respectively, without data shifting. In another example where B2_L is the faulty main bank, the first four (8, 9, 10, and 11) of the second eight data pieces are directed to or from the corresponding working main banks B0_L, B0_H, B1_L, and B1_H, and are separated from B2_L by the redundant bank 704. The data (12) intended for B2_L can be redirected to or from the redundant bank 704 (data shifts left), and B2_L can go unused. That is, data shifting can occur between B2_L and the redundant bank 704. The last three (13, 14, and 15) of the second eight data pieces can be directed to or from the corresponding three working main banks B2_H, B3_L, and B3_H, respectively, without data shifting.

[0060] FIG. 11 illustrates a flowchart of an example method 1100 for operating a memory device having a failed main bank and a redundant bank in accordance with some aspects of the disclosure. The memory device may be any suitable memory device disclosed herein. Method 1100 may be implemented by I / O control logic 412. It is understood that the operations illustrated in method 1100 are not exhaustive and that other operations may be performed before, after, or during any of the illustrated operations as well. Additionally, some of the operations may be performed simultaneously or in a different order than that illustrated in FIG. 11.

[0061] 11, the method 1100 begins at operation 1102 where bank failure information is obtained that indicates a faulty main bank among the plurality of main banks. The faulty main bank may be identified by post-manufacturing testing of the memory device. For example, the working bank logic 906 may obtain the bank failure information from the register 414 before operating the memory device.

[0062] The method 1100 proceeds to operation 1104, as shown in FIG. 11, where a plurality of working banks are determined from the plurality of main banks and redundant banks based on the bank failure information. The plurality of working banks may include a redundant bank. For example, the working bank logic 906 may determine a working bank that includes a redundant bank and a remaining main bank.

[0063] The method 1100 proceeds to operation 1106, as shown in FIG. 11, where one bank of each pair of adjacent banks of the plurality of banks is selected based on the bank failure information. According to some implementations, the selected bank is a working bank. For example, the working bank logic 906 may select one working bank of each pair of adjacent banks based on the bank failure information.

[0064] The method 1100 proceeds to operation 1108, as shown in FIG. 11, where the directing of data to or from a selected bank of each pair of adjacent banks is controlled. To control the directing of data, according to some implementations, a first bank of one pair of adjacent banks is determined to be a failed main bank and data is directed to or from a second bank of the pair of adjacent banks. In one example, the write redundancy enable logic 904 can control the first write MUX 708 to inhibit outputting data to the first bank and control the second write MUX 708 to enable outputting data to the second bank. In another example, the read redundancy enable logic 902 can control the read MUX 804 to enable outputting data from the second bank.

[0065] FIG. 12 illustrates a flowchart of another exemplary method 1200 for operating a memory device having a failed main bank and a redundant bank, in accordance with some aspects of the disclosure. The memory device may be any suitable memory device disclosed herein. Method 1200 may be implemented by I / O control logic 412. It is understood that the operations illustrated in method 1200 are not exhaustive, and other operations may be performed before, after, or between any of the illustrated operations as well. Additionally, some of the operations may be performed simultaneously or in a different order than that illustrated in FIG. 12.

[0066] 12, method 1200 begins at operation 1202, where bank failure information is obtained that indicates K failed main banks among the N main banks. K may be a positive integer less than or equal to N. The K failed main banks may be identified by post-manufacturing testing of the memory device. For example, working bank logic 906 may obtain the bank failure information from register 414 before operating the memory device.

[0067] The method 1200 proceeds to operation 1204, as shown in FIG. 12. Here, N working banks are determined from the N main banks and the M redundant banks based on the bank failure information. The N working banks may include K redundant banks of the M redundant banks. For example, the working bank logic 906 may determine the N working banks including the K redundant banks and the remaining main bank. In some implementations, M is equal to 1, and one working bank is selected from each pair of adjacent banks of the N main banks and redundant banks based on the bank failure information.

[0068] The method 1200 proceeds to operation 1206, as shown in Figure 12, where K of the N pieces of data are directed to or from the K redundant banks, respectively. In some implementations, M is equal to 1, and one of the K pieces of data is directed to or from a selected working bank of each pair of adjacent banks of the N main and redundant banks.

[0069] FIG. 13 illustrates a schematic diagram of an example memory device 1300 including multiple planes 1302 according to some aspects of the disclosure. The multiple planes 1302 may be included in a die 1301. In some implementations, the planes 1302 may be independent of each other in performing read, program, or erase operations. For example, each plane 1302 may be configured to independently perform a read operation in response to receiving a read control signal from the control logic 413. In some implementations, each plane 1302 may cover local buffering of read and program data and may process operations in parallel, thus increasing the speed of operation. To enable its independent operation, each plane 1302 may include a set of blocks 304 of the memory cell array 301 and a set of peripheral circuits, such as page buffers / sense amplifiers 404, column decoders / bit line drivers 406, and row decoders / word line drivers 408.

[0070] In some other implementations, the planes 1302 can be configured to perform read, program, or erase operations in series. For example, a read, program, or erase operation may be performed one at a time on multiple planes 1302 in response to receiving a corresponding control signal from the control logic 413.

[0071] FIG. 14A illustrates an example layout of a plane 1302 according to some aspects of the disclosure. FIG. 14B illustrates a schematic diagram of an example data bus in the plane 1302 of FIG. 14A according to some aspects of the disclosure. In some implementations, memory cells in the plane 1302 can be divided into multiple sections (referred to herein as plane sections). The plane 1302 can include a page buffer / sense amplifier 404 divided into multiple portions 1406 (referred to herein as page buffer / sense amplifier portions 1406). Each page buffer / sense amplifier portion 1406 can correspond to a plane section in the plane 1302 and can be configured to read data from and program (write) data to memory cells in the plane section according to control signals from the control logic 413.

[0072] As shown in FIG. 14A, the page buffer / sense amp 404 includes four physically separated portions 1406a, 1406b, 1406c, and 1406d (e.g., quarters). It is understood that the number of portions is not limited to four and may be any integer greater than one (e.g., 2, 3, 4, 5, 6, etc.), e.g., two equal portions. The page buffer / sense amp 404 may include multiple storage units (e.g., latches, caches, or registers) for temporarily storing (buffering) one or more pages of data to be read from or written to memory cells in the plane 1302. In some implementations, each portion 1406a, 1406b, 1406c, or 1406d has the same size, i.e., one quarter of the page buffer / sense amp 404. For example, the page buffer / sense amp 404 may store 16K bytes of data and each portion 1406a, 1406b, 1406c, or 1406d may store 4K bytes of data.

[0073] In some implementations, the global data bus 1418 may be coupled to each page buffer / sense amplifier portion 1406a, 1406b, 1406c, or 1406d, respectively. With joint reference to FIG. 14A and FIG. 14B, the global data bus 1418 may branch at each junction 1401, 1402, 1404a, or 1404b to form its branched data bus. For example, the global data bus 1418 may branch into two plane branched data buses 1403a and 1403b at junction 1401. The plane branched data bus 1403a may branch into two section branched data buses 1405a and 1405b at junction 1402. The section branched data bus 1405a may branch into two section sub-branched data buses 1407a and 1407b at junction 1404a. Similarly, section branched data bus 1405b may branch into two section sub-branched data buses 1407c and 1407d at junction 1404b, such that global data bus 1418 may be coupled to respective page buffer / sense amplifier sections 1406a, 1406b, 1406c, or 1406d via one or more of the branched data buses (e.g., 1403a, 1405a, 1405b, 1407a, 1407b, 1407c, and 1407d).

[0074] In some implementations, the plane 1302 may include a row decoder / word line driver 408 that may be divided into multiple row decoder / word line driver portions. Each row decoder / word line driver portion may correspond to a planar section in the plane 1302 and may be controlled by control logic 413 and configured to select a block 304 of the memory cell array 301 in the planar section and to select a word line 318 of the selected block 304.

[0075] In some implementations, the plane 1302 may include a column decoder / bit line driver 406 that may be divided into multiple column decoder / bit line driver portions. Each column decoder / bit line driver portion may correspond to a plane section in the plane 1302 and may be controlled by control logic 413 and configured to select one or more NAND memory strings 308 in the plane section by applying bit line voltages generated from a voltage generator 410.

[0076] 15A illustrates a block diagram of an example memory device 1500 including a first level memory unit having multiple second level memory units and I / O circuits, according to some aspects of the disclosure. For example, the memory device 1500 may include an array of memory cells including a first level memory unit 1514. The first level memory unit 1514 may include second level memory units 1515a and 1515b. Each second level memory unit 1515a or 1515b may include one or more groups of banks, each group of banks including N main banks and a redundant bank for simultaneous data input and / or data output.

[0077] Each second level memory unit 1515a or 1515b may be coupled to a respective page buffer / sense amplifier 404 (or a respective page buffer / sense amplifier portion 1406), a respective column decoder / bit line driver 406 (or a respective column decoder / bit line driver portion 1506), and a respective row decoder / word line driver 408 (or a respective row decoder / word line driver portion 1504).

[0078] As shown in FIG. 15A, the first level memory unit 1514 may include an I / O circuit 407, an I / O control logic 412, and a register 414. The I / O circuit 407 and the I / O control logic 412 may be shared by the second level memory units 1515a and 1515b. Each second level memory unit 1515a or 1515b may correspond to one or more respective registers 414 configured to store bank failure information of the corresponding second level memory unit 1515a or 1515b. In some implementations, one or more of the I / O circuit 407, the I / O control logic 412, and the register 414 may be located outside the first level memory unit 1514 (e.g., in a peripheral area of ​​the first level memory unit 1514).

[0079] In some implementations, the I / O circuitry 407 may be coupled to a first level data bus 1510. The first level data bus 1510 may branch at a junction 1511 to form two branched data buses including branched data buses 1512a and 1512b. As a result, the I / O circuitry 407 may be coupled to the page buffer / sense amplifier 404 (or the page buffer / sense amplifier portion 1406) and the column decoder / bit line driver 406 (or the column decoder / bit line driver portion 1506) in the second level memory unit 1515a or 1515b via the first level data bus 1510 and the branched data buses 1512a or 1512b, respectively. The I / O circuitry 407 may be configured to direct N data to or from N working banks in the second level memory unit 1515a or 1515b via the first level data bus 1510 and the branched data buses 1512a or 1512b, respectively.

[0080] The I / O control logic 412 is coupled to the I / O circuit 407 and may be configured to determine N working banks from the N main banks and redundant banks in the second level memory unit 1515a or 1515b based on the bank failure information indicating a failed main bank among the N main banks. The I / O control logic 412 may control the I / O circuit 407 to direct the N data to or from the N working banks, respectively. The I / O control logic 412 has been described above with reference to FIG. 9 and the same description will not be repeated here.

[0081] In some implementations, the first level memory unit 1514 may be a die including multiple planes, and each second level memory unit 1515a or 1515b may be a corresponding plane within the die. The first level data bus 1510 may be a global data bus within the die. The I / O circuitry 407 may be coupled to the global data bus and may be configured to direct N data to or from N working banks within the corresponding planes via the global data bus and one or more branch data buses within the corresponding planes. An example is shown with reference to Figures 15B-15D, where the first level memory unit 1514 is a die, the second level memory units 1515a or 1515b are planes, the first level data bus 1510 is a global data bus, and the I / O circuitry 407 is coupled to the global data bus.

[0082] In some implementations, the first level memory unit 1514 may be a plane including multiple planar sections, and each second level memory unit 1515a or 1515b may be a corresponding planar section in the plane. The first level data bus 1510 may be a planar bifurcated data bus in the plane. The I / O circuitry 407 may be coupled to the planar bifurcated data bus and may be configured to direct N data to or from N working banks in the corresponding planar section via the planar bifurcated data bus and the section bifurcated data bus, respectively. An example is shown with reference to FIG. 16A, where the first level memory unit 1514 is a plane, the second level memory unit 1515a or 1515b is a planar section, the first level data bus 1510 is a planar bifurcated data bus, and the I / O circuitry 407 is coupled to the planar bifurcated data bus.

[0083] In some implementations, the first level memory unit 1514 may be a plane including multiple planar sections, and each second level memory unit 1515a or 1515b may be a corresponding planar section in the plane. The first level data bus 1510 may be a section branch data bus in the plane. The I / O circuitry 407 may be coupled to the section branch data bus and configured to direct N data to or from N working banks in the corresponding planar sections via the section branch data bus and the section sub-branch data bus. An example is shown below with reference to Figures 16B and 16D. The first level memory unit 1514 is a plane, the second level memory unit 1515 is a planar section, the first level data bus 1510 is a section branch data bus, and the I / O circuitry 407 is coupled to the section branch data bus.

[0084] 15B illustrates a block diagram of an exemplary memory device 1530 including a die having multiple planes and I / O circuitry (e.g., I / O circuitry 407) in accordance with some aspects of the disclosure. The die (e.g., die 1301) may include multiple planes 1302a and 1302b. The memory device 1530 may include components similar to components of any suitable memory device disclosed herein, and similar descriptions will not be repeated here.

[0085] In some implementations, the control logic 413 may include global I / O control logic configured to control data input and output via the global data bus 1418. For example, the control logic 413 may control buffering of data input / output to or from the global data bus 1418 and may perform integrity checks on the input / output data. In some examples, registers 414 may also be included within the control logic 413.

[0086] I / O control logic 412 and I / O circuitry 407 may be shared by planes 1302a and 1302b. I / O circuitry 407 may be coupled to a global data bus 1418. Global data bus 1418 may branch at junction 1401 to form plane branched data buses 1403a and 1403b. I / O circuitry 407 may be configured to direct N data to or from N working banks in planes 1302a or 1302b via global data bus 1418 and plane branched data buses 1403a or 1403b, respectively.

[0087] FIG. 15C illustrates a block diagram of another exemplary memory device 1550 including a die having multiple planes and I / O circuitry (e.g., I / O circuitry 407) according to some aspects of the disclosure. FIG. 15D illustrates a schematic diagram of an exemplary data bus in the memory device 1550 of FIG. 15C according to some aspects of the disclosure. The die (e.g., die 1301) of FIG. 15C-FIG. 15D can include multiple planes 1302a and 1302b, with each plane 1302a or 1302b including multiple planar sections 1502a, 1502b, 1502c, and 1502d. I / O control logic 412 and I / O circuitry 407 can be shared by planes 1302a and 1302b (e.g., can also be shared by planar sections 1502a, 1502b, 1502c, and 1502d of each plane 1302a or 1302b). Memory device 1550 may include components similar to those of any suitable memory device disclosed herein, and similar descriptions will not be repeated here.

[0088] 15C-15D, the I / O circuitry 407 may be coupled to a global data bus 1418. The global data bus 1418 may branch at a junction 1401 to form plane branched data buses 1403a and 1403b. With respect to the plane 1302a, the plane branched data bus 1403a may branch at a junction 1402a to form section branched data buses 1405a, 1405b, 1405c, and 1405d. As a result, the I / O circuitry 407 may be coupled to each plane section 1502a, 1502b, 1502c, or 1502d of the plane 1301a and configured to direct N data to or from N working banks in each plane section 1502a, 1502b, 1502c, or 1502d via the global data bus 1418, the plane branch data bus 1403a, and the section branch data bus 1405a, 1405b, 1405c, or 1405d, respectively.

[0089] With respect to plane 1302b, plane branched data bus 1403b may branch at junction 1402b to form section branched data buses 1405e, 1405f, and 1405g. Section branched data bus 1405g may branch at junction 1404 to form section sub-branched data buses 1407a and 1407b. As a result, I / O circuit 407 may be coupled to plane section 1502a or 1502b of plane 1302b and configured to direct N data to or from N working banks in plane section 1502a or 1502b via global data bus 1418, plane branched data bus 1403b, and section branched data bus 1405e or 1405f, respectively. Additionally, the I / O circuitry 407 may be coupled to plane section 1502c or 1502d of plane 1302b and configured to direct N data to or from N working banks in plane section 1502c or 1502d, respectively, via the global data bus 1418, plane branch data bus 1403b, section branch data bus 1405g, and section sub-branch data bus 1407a or 1407b.

[0090] 16A-16D show schematic diagrams of example memory devices 1610, 1620, 1630, and 1640, each including multiple planes and multiple I / O circuits, according to some aspects of the disclosure. Referring to FIG. 16A, the memory device 1610 may include components similar to those of any suitable memory device disclosed herein, and similar descriptions will not be repeated here. In FIG. 16A, each plane 1302a or 1302b may include a respective I / O circuit 407a or 407b. Although the memory device 1610 includes one I / O control logic 412 shared by the multiple planes 1302a and 1302b, in some implementations, each plane 1302a or 1302b may include (1) a respective I / O control logic 412 coupled to the respective I / O circuit 407a or 407b, and (2) one or more respective registers 414 coupled to the respective I / O control logic 412.

[0091] With respect to the plane 1302a, the I / O circuitry 407a (as well as the respective I / O control logic 412 and respective registers 414, if present in the plane 1302a) may be shared by the plane sections 1502a, 1502b, 1502c, and 1502d of the plane 1302a. The I / O circuitry 407a may be coupled to the plane bifurcated data bus 1403a. The I / O circuitry 407a may be coupled to each plane section 1502a, 1502b, 1502c, or 1502d of the plane 1302a, and may be configured to direct N data to or from N working banks in each plane section 1502a, 1502b, 1502c, or 1502d, respectively, via the plane bifurcated data bus 1403a and the section bifurcated data bus 1405a, 1405b, 1405c, or 1405d.

[0092] With respect to plane 1302b, I / O circuitry 407b (as well as respective I / O control logic 412 and respective registers 414, if present in plane 1302b) may be shared by plane sections 1502a, 1502b, 1502c, and 1502d of plane 1302b. I / O circuitry 407b may be coupled to plane branched data bus 1403b. I / O circuitry 407b may be coupled to plane section 1502a or 1502b in plane 1302b and configured to direct N data to or from N working banks in plane section 1502a or 1502b via plane branched data bus 1403b and section branched data bus 1405e or 1405f, respectively. Further, the I / O circuit 407b may be coupled to the plane section 1502c or 1502d of the plane 1302b and may be configured to direct N data to or from the N working banks in the plane section 1502c or 1502d, respectively, via the plane branch data bus 1403b, the section branch data bus 1405g, and the section sub-branch data bus 1407a or 1407b.

[0093] 16B, memory device 1620 may include components similar to those of any suitable memory device disclosed herein, and similar descriptions will not be repeated here. In FIG. 16B, plane 1302a may include I / O circuitry 407a shared by planar sections 1405a-d of plane 1302a. Plane 1302b may include I / O circuits 407b, 407c, and 407d.

[0094] With respect to plane 1302b, I / O circuit 407b (and respective I / O control logic 412 and respective registers 414, if present in plane 1302b) may be shared by plane sections 1502c and 1502d of plane 1302b. I / O circuit 407b may be coupled to section branch data bus 1405g. I / O circuit 407b may be coupled to plane section 1502c or 1502d of plane 1302b and configured to direct N data to or from N working banks in plane section 1502c or 1502d via section branch data bus 1405g and section sub-branch data bus 1407a or 1407b, respectively. I / O circuit 407c may be coupled to section branch data bus 1405f. The I / O circuit 407c may be coupled to the plane section 1502b of the plane 1302b and configured to direct N pieces of data, respectively, to or from the N working banks in the plane section 1502b via the section branch data bus 1405f. The I / O circuit 407d may be coupled to the section branch data bus 1405e. The I / O circuit 407d may be coupled to the plane section 1502a of the plane 1302b and configured to direct N pieces of data, respectively, to or from the N working banks in the plane section 1502a via the section branch data bus 1405e.

[0095] 16C, the memory device 1630 may include components similar to those of any suitable memory device disclosed herein, and similar descriptions will not be repeated here. The plane 1302a may include I / O circuits 407a, 407b, 407c, and 407d corresponding to the plane sections 1502a, 1502b, 1502c, and 1502d in the plane 1302a, respectively. The I / O circuit 407a may be coupled to the plane section 1502a of the plane 1302a and configured to direct N pieces of data to or from the N working banks in the plane section 1502a via the section branch data bus 1405a, respectively. The I / O circuit 407b may be coupled to the plane section 1502b of the plane 1302a and configured to direct N pieces of data to or from the N working banks in the plane section 1502b via the section branch data bus 1405b, respectively. I / O circuitry 407c may be coupled to planar section 1502c of plane 1302a and configured to direct N pieces of data, respectively, to or from N working banks in planar section 1502c via section branch data bus 1405c. I / O circuitry 407d may be coupled to planar section 1502d of plane 1302a and configured to direct N pieces of data, respectively, to or from N working banks in planar section 1502d via section branch data bus 1405d.

[0096] Plane 1302b may include I / O circuits 407e, 407f, 407g, and 407h corresponding to planar sections 1502a, 1502b, 1502c, and 1502d in plane 1302b, respectively. I / O circuit 407e may be coupled to planar section 1502a of plane 1302b and configured to direct N pieces of data to or from N working banks in planar section 1502a, respectively, via section branch data bus 1405e. I / O circuit 407f may be coupled to planar section 1502b of plane 1302b and configured to direct N pieces of data to or from N working banks in planar section 1502b, respectively, via section branch data bus 1405f. The I / O circuit 407g may be coupled to the plane section 1502c of the plane 1302b and configured to direct N pieces of data to or from the N working banks in the plane section 1502c via the section sub-branch data bus 1407a, respectively. The I / O circuit 407h may be coupled to the plane section 1502d of the plane 1302b and configured to direct N pieces of data to or from the N working banks in the plane section 1502d via the section sub-branch data bus 1407b, respectively.

[0097] 16D, memory device 1640 may include components similar to those of any suitable memory device disclosed herein, and similar descriptions will not be repeated here. In FIG. 16D, plane 1302a may include I / O circuitry 407a shared by planar sections 1502a, 1502b, 1502c, and 1502d of plane 1302a. Plane 1302b may include I / O circuitry 407b and 407c.

[0098] With respect to plane 1302b, plane branched data bus 1403b may branch at junction 1402b to form section branched data buses 1405e and 1405f. Section branched data bus 1405e may branch at junction 1404a to form section sub-branched data buses 1407a and 1407b. Section branched data bus 1405f may branch at junction 1404b to form section sub-branched data buses 1407c and 1407d. I / O circuitry 407b (as well as respective I / O control logic 412 and respective registers 414, if present in plane 1302b) may be shared by plane sections 1502a and 1502b of plane 1302b. I / O circuitry 407b may be coupled to section branched data bus 1405e. The I / O circuit 407b may be coupled to the plane section 1502a or 1502b of the plane 1302b and configured to direct N data to or from N working banks in the plane section 1502a or 1502b via the section branch data bus 1405e and the section sub-branch data bus 1407a or 1407b, respectively.

[0099] I / O circuitry 407c (and, if present in plane 1302b, the respective I / O control logic 412 and respective registers 414) may be shared by plane sections 1502c and 1502d of plane 1302b. I / O circuitry 407c may be coupled to section branch data bus 1405f. I / O circuitry 407d may be coupled to plane section 1502c or 1502d of plane 1302b and configured to direct N data to or from N working banks in plane section 1502c or 1502d via section branch data bus 1405f and section sub-branch data bus 1407c or 1407d, respectively.

[0100] 17 illustrates a schematic diagram of an example memory device 1700 that uses a write MUX array having multiple write sub-arrays to implement a failed main bank repair scheme at the data input in accordance with some aspects of the disclosure. The memory device 1700 can include components similar to those of any suitable memory device described herein, and similar descriptions will not be repeated here.

[0101] In some implementations, memory device 1700 may include an array of memory cells including P groups of banks, where P may be a positive integer. Each group of banks includes N main banks 702 (e.g., N=8) and a redundant bank 704 for simultaneous data input / output, with P redundant banks included and shared among the P groups of banks. I / O circuitry 407 may be coupled to the P groups of banks in memory device 1700, for example, via page buffer / sense amplifier 404 and column decoder / bit line driver 406 (or page buffer / sense amplifier portion 1406 and column decoder / bit line driver portion 1506). In some implementations shown in FIG. 17, at data input (e.g., a write operation), the page buffer / sense amplifier 404 and column decoder / bit line driver 406 (or the page buffer / sense amplifier portion 1406 and the column decoder / bit line driver portion 1506) may include nine drivers 706, each coupled to eight main banks 702 and one redundant bank 704 in each group of banks.

[0102] The I / O circuitry 407 may include N+1 outputs coupled to the N main banks 702 and redundant banks 704 in each group of banks via a data bus 1701 and a set of wiring. The set of wiring may include wirings 1702, 1704, 1706, 1708, 1710, 1712, 1714, 1716, and 1718. For example, the outputs of the I / O circuitry 407 may be coupled to each bank via a respective data line of the data bus 1701 and a respective wire in the set of wiring.

[0103] In some implementations, the I / O circuitry 407 may be located in a first level memory unit 1514 and shared by multiple second level memory units 1515a and 1515b, as shown in Figure 15A. The data bus 1701 may be the first level data bus 1510 of Figure 15A. The set of wiring may include a branched data bus 1512a or 1512b depending on which second level memory unit 1515a or 1515b the N main banks 702 and redundant bank 704 are located in.

[0104] In some implementations, the I / O circuitry 407 may be located on a die and shared by multiple planes (e.g., as shown in Figures 15B-15D). For example, the data bus 1701 may be the global data bus 1418 shown in Figure 15B. The set of wiring may include the plane branched data bus 1403a or 1403b shown in Figure 15B, depending on which plane the N main banks 702 and redundant bank 704 are located on. In another example, the data bus 1701 may be the global data bus 1418 shown in Figure 15C or Figure 15D. The set of wiring may include one or more of the plane branched data buses 1403a or 1403b, the section branched data buses 1405a-1405g, and the section sub-branched data buses 1407a or 1407b shown in FIG. 15D, depending on which section of the plane 1302a or the plane 1302b the N main banks 702 and redundant banks 704 are located in.

[0105] In some implementations, the I / O circuit 407 may be arranged in a plane and shared by multiple plane sections in the plane. For example, the I / O circuit 407 in FIG. 17 may be the I / O circuit 407a or 407b in FIG. 16A. Also, the data bus 1701 may be the plane branched data bus 1403a or 1403b shown in FIG. 16A. The set of wiring may include the section branched data bus 1405a-1405g and / or the section sub-branched data bus 1407a or 1407b shown in FIG. 16A, depending on which section of the plane 1302a or the plane 1302b the N main banks 702 and the redundant bank 704 are arranged in. In another example, the I / O circuit 407b in FIG. 17 may be the I / O circuit 407b in FIG. 16D. The data bus 1701 may be the section branched data bus 1405e in the plane 1302b in FIG. 16D. The set of wiring may include the section sub-branch data bus 1407a or 1407b shown in FIG. 16D, depending on the plane section 1502a or 1502b of the plane 1302b in which the N main banks 702 and the redundant bank 704 are arranged. In yet another example, the I / O circuit 407c of FIG. 17 may be the I / O circuit 407c of FIG. 16D. Also, the data bus 1701 may be the section branch data bus 1405f of the plane 1302b of FIG. 16D. The set of wiring may include the section sub-branch data bus 1407c or 1407d shown in FIG. 16D, depending on which plane section 1502c or 1502d of the plane 1302b in which the N main banks 702 and the redundant bank 704 are arranged.

[0106] The I / O circuitry 407 may include a write MUX array 707. In some implementations, the write MUX array 707 may include P write subarrays 1720 (e.g., a first write subarray, a second write subarray, ..., and a Pth write subarray) that are applied in series. Various example structures of each write subarray 1720 are described in more detail below with reference to Figures 18A, 18D, and 19A.

[0107] FIG. 18A illustrates a schematic diagram of an example memory device 1800 that implements a failed main bank repair scheme at the data input using a write MUX array with two write sub-arrays according to some aspects of the disclosure. The memory device 1800 may include components similar to those of any suitable memory device described herein, and similar descriptions will not be repeated here. In some implementations, the memory device 1800 may include an array of memory cells including P groups of P=2 banks, e.g., group 0 and group 1. Each group of banks may include N main banks 702 (e.g., N=8) and one redundant bank 704 for simultaneous data input / output, and thus two redundant banks 704 are included and shared by the group of two banks.

[0108] In some implementations shown in FIG. 18A , the write MUX array 707 of the I / O circuit 407 may include a first write subarray 1720a and a second write subarray 1720b. Each write subarray 1720a or 1720b may include a redundant write MUX 1881 and N main write MUXes 1880 (e.g., N=8). The redundant write MUX 1881 may be disposed between the N main write MUXes 1880 in each write subarray 1720a or 1720b. Each main write MUX 1880 and each redundant write MUX 1881 may include a first input A, a second input B, a selection port S, and an output Out, respectively. The redundant write MUX 1881 in the second write subarray 1720b may further include a first redundant input C, while the redundant write MUX 1881 in the first write subarray 1720a does not include a redundant input.

[0109] In some implementations, each of the first write subarray 1720a and the second write subarray 1720b may have a structure similar to the write MUX array 707 shown in FIG. 7. However, the redundant write MUX 1881 of the second write subarray 1720b may further include a first redundant input C, whereas the write MUX of the write MUX array 707 of FIG. 7 does not include a redundant input. In some implementations, two instances of the write MUX array 707 of FIG. 7 may be cascaded in series and modified to form the write MUX array 707 of FIG. 18A having two write subarrays 1720a and 1720b. In general, P instances of the write MUX array 707 of FIG. 7 may be cascaded in series and modified to form a write MUX array having P write subarrays.

[0110] For the first write sub-array 1720a, the output of each main write MUX 1880 is coupled via a corresponding signal line (e.g., 1811, 1812, 1813, 1814, 1816, 1817, 1818, or 1819) to a first input A of a corresponding main write MUX 1880 in the second write sub-array 1720b. The output of the redundant write MUX 1881 in the first write sub-array 1720a is coupled via signal line 1815 to a redundant input C of the redundant write MUX 1881 in the second write sub-array 1720b. A first input A of each main write MUX 1880 in the first write sub-array 1720a is coupled to a corresponding I / O data line (e.g., 1801, 1802, 1803, 1804, 1806, 1807, 1808, or 1809) and configured to receive corresponding data from the corresponding I / O data line.

[0111] For the second write sub-array 1720b, the outputs of the N main write MUXes 1880 and redundant write MUXes 1881 are coupled via signal lines 1821, 1822, 1823, 1824, 1825, 1826, 1827, 1828, and 1829 to the N main banks 702 and redundant banks 704 in the corresponding group of banks, respectively.

[0112] For each write subarray 1720a or 1720b, the first input A and the second input B of the redundant write MUX 1881 are respectively coupled to the first inputs A of two adjacent main write MUXes 1880 in the same write subarray. The second input B of each main write MUX 1880 in each write subarray 1720a or 1720b is coupled to the Vdd signal line or the first input A of the adjacent main write MUX 1880 in the same write subarray. The Vdd signal line may be configured to receive a system voltage Vdd. For example, for each main write MUX 1880 located at the left or right end of each write subarray 1720a or 1720b, the second input B of the respective main write MUX 1880 is coupled to the Vdd signal line. For each main write MUX 1880 to the left of redundant write MUX 1881 (not the left-most main write MUX), the second input B of the respective main write MUX 1880 is coupled to the first input A of the adjacent main write MUX 1880 to its left. For each main write MUX 1880 to the right of redundant write MUX 1881 (not the right-most main write MUX), the second input B of the respective main write MUX 1880 is coupled to the first input A of the adjacent main write MUX 1880 to its right.

[0113] The select port S of each main write MUX 1880 can be configured to receive a write select signal indicating the selection of one input (A or B). For example, when the positive biased write select signal, i.e., write select signal, of each main write MUX 1880 is enabled, the second input B can be selected. When the negative biased write select signal, i.e., write select signal, of each main write MUX 1880 is disabled, the first input A can be selected. In some implementations, the write select signal of each main write MUX 1880 in the first write sub-array 1720a can be red1_en_b0_l_wt, red1_en_b0_h_wt, red1_en_b1_l_wt, red1_en_b1_h_wt, red1_en_b2_l_wt, red1_en_b2_h_wt, red1_en_b3_b3_l_wt, or red1_en_b3_b3_h_wt. The write select signal for each main write MUX 1880 in the second write sub-array 1720b may be red2_en_b0_l_wt, red2_en_b0_h_wt, red2_en_b1_l_wt, red2_en_b1_h_wt, red2_en_b2_l_wt, red2_en_b2_h_wt, red2_en_b3_l_en_wt, or red2_en_b3_h_wt.

[0114] The select port S of each redundant write MUX 1880 can be configured to receive a write select signal indicating the selection of one input (A, B, C, or any other available redundant input). For example, a first level of the write select signal (indicating the write select signal is invalid) can select the first input A, a second level of the write select signal can select the second input B, a third level of the write select signal can select the first redundant input C, and so on. In some implementations, the write select signal of the redundant write MUX 1881 in the first write sub-array 1720a can be red1_en_b12_wt. The write select signal of the redundant write MUX 1881 in the second write sub-array 1720b can be red2_en_b12_wt.

[0115] In some implementations, each main write MUX 1880 or redundant write MUX 1881 may be configured as a hold unit with memory capabilities. The hold unit may be configured to temporarily store a previous output signal and continue to output the previous output signal in the current clock cycle regardless of what the current input is. For example, the write select signal may be configured to have a particular voltage or current level (referred to herein as a hold level), such that the main write MUX 1880 or redundant write MUX 1881 may become a hold unit in response to receiving a write select signal having a hold level. Exemplary applications of hold units are described below with reference to Figures 18B-18C and 19B-19C.

[0116] 18B-18C illustrate an exemplary failed main bank repair scheme in a data input implemented by the memory device 1800 of FIG. 18A according to some aspects of the present disclosure. With reference to FIG. 18B, assume that group 0 and group 1 include a total of two failed main banks. As shown in table 1856, the two failed main banks may be distributed to group 0 (e.g., B0_L and B0_H in group 0 are failed main banks). FIG. 18B is described herein with combined reference to FIG. 9 and FIG. 18A.

[0117] In some implementations, the working bank logic 906 of the I / O control logic 412 is coupled to the register 414 and configured to obtain bank failure information indicating two failed main banks from group 0. The working bank logic 906 can determine 2×N working banks from group 0 and group 1 that can be used for data input and output. That is, the working bank logic 906 can replace the two failed main banks with the same number of redundant banks such that the 2×N working banks can include two redundant banks from group 0 and group 1 and 2×N−2 main banks.

[0118] Based on the determined 2×N working banks, the write redundancy enable logic 904 can be configured to control the I / O circuitry 407 to direct the 2×N data to the 2×N working banks, respectively. For example, the write redundancy enable logic 904 is coupled to each main write MUX 1880 and each redundant write MUX 1881 of each write sub-array 1720a or 1720b. The write redundancy enable logic 904 is configured to provide a plurality of write select signals 903 to the main write MUX 1880 and the redundant write MUX 1881 in each write sub-array 1720a or 1720b based on the determined 2×N working banks.

[0119] Assume that the 1N pieces of data including (0,0), (0,1), ..., and (0,7) (N=8) are intended to be stored in the N main banks of group 0, and the 2N pieces of data including (1,0), (1,1), ..., and (1,7) are intended to be stored in the N main banks of group 1. The data write order in FIG. 18B is from group 0 to group 1. The first row of table 1850 indicates that the 1N pieces of data are loaded onto I / O signal lines 1801-1804 and 1806-1809, respectively, with clock signal 0 (clk0). The second row of table 1850 also indicates that the 2N pieces of data are loaded onto I / O signal lines 1801-1804 and 1806-1809, respectively, with clock signal 1 (clk1).

[0120] Initially, at clk0, the firstN data (0,0), (0,1), ..., and (0,7) are input to the main write MUX 1880 of the first write sub-array 1720a via I / O signal lines 1801-1804 and 1806-1809, respectively, as shown in the first row of table 1850.

[0121] At clk1, since B0_L of group 0 is the failed main bank, the write redundancy enable logic 904 can enable red1_en_b0_l_wt, ..., and red1_en_b1_h_wt, so that each main write MUX 1880 to the left of the redundant write MUX 1881 in the first write sub-array 1720a can input data from its second input B to achieve one bank right data shift. That is, data (0,0), (0,1), and (0,2) are shifted right by one bank by the first write sub-array 1720a as shown in the first row of table 1852, and output by signal lines 1812-1814, respectively. As shown in the first row of table 1852, the write redundancy enable logic 904 can further disable red1_en_b12_wt such that (0,3) is redirected to the redundant write MUX 1881 of the first write sub-array 1720a and output by signal line 1815. As a result, each data (0,0), (0,1), (0,2), or (0,3) is shifted right by one bank by the first write sub-array 1720a at clk1. For the other data (0,4), (0,5), (0,6), and (0,7), no shifting of input data may be required, allowing the write redundancy enable logic 904 to disable red1_en_b2_l_wt, red1_en_b2_h_wt, red1_en_b3_l_wt, and red1_en_b3_h_wt. Then, each main write MUX 1880 on the right side of the redundant write MUX 1881 can input data from the first input A without data shifting, and data (0,4), (0,5), (0,6), and (0,7) are output by the first write sub-array 1720a via signal lines 1816-1819, respectively, as shown in the first row of table 1852. As a result, at clk1, the 1N data (0,0), (0,1), (0,2), (0,3), (0,4), (0,5), (0,6), and (0,7) are input to the second write sub-array 1720b via signals 1812-1819, respectively.For example, on clk1, data (0,3) is input via signal line 1815 to the redundant input C of the redundant write MUX 1881 in the second write sub-array 1720b.

[0122] Also, at clk1, the 2Nth data (1,0), (1,1), ..., and (1,7) are input to the main write MUX 1880 of the first write sub-array 1720a via I / O signal lines 1801-1804 and 1806-1809, respectively, as shown in the second row of table 1850.

[0123] At clock signal 2 (clk2), since B0_H of group 0 is also a failed main bank, the write redundancy enable logic 904 can enable red2_en_b0_h_wt, red2_en_b1_l_wt, and red2_en_b1_h_wt, so that the corresponding main write MUX 1880 on the left side of the redundant write MUX 1881 of the second write sub-array 1720b can input data (0,0) and (0,1) from the second input B to achieve one bank right data shift. That is, as shown in the first row of table 1854, the data (0,0) and (0,1) are again shifted right by one bank and output from signal lines 1823 and 1824, respectively. The write redundancy enable logic 904 can further disable red2_en_b12_wt, and the data (0,2) is redirected from the first input A to the redundant write MUX 1881 of the second write sub-array 1720b and output by signal line 1825, as shown in the first row of table 1854. As a result, at clk2, each data (0,0), (0,1), or (0,2) is shifted right by one bank by the second write sub-array 1720b, as shown in the first row of table 1854. For other data (0,4), (0,5), (0,6), and (0,7), input data shifting may not be required, and data (0,4), (0,5), (0,6), and (0,7) are output by the second write sub-array 1720b, respectively, without data shifting via signal lines 1826-1829, as shown in the first row of table 1854. As a result, at clk2, data (0,0), (0,1), (0,2), (0,4), (0,5), (0,6), and (0,7) from the 1N pieces of data are output to the seven working banks of group 0 via signal lines 1823 to 1829, respectively. That is, data (0,0), (0,1), (0,2), (0,4), (0,5), (0,6), and (0,7) from the 1N pieces of data are stored in the seven working banks of group 0, as shown in the second row of 1856.

[0124] Also, at clk2, the 2Nth data (1,0), (1,1), ..., and (1,7) are output from the first write subarray 1720a without data shifting via signal lines 1811-1814 and 1816-1819, respectively, as shown in the second row of table 1852. The write redundancy enable logic 904 can generate a write select signal (e.g., red1_en_b12_wt with a hold level) for the redundant write MUX 1881 of the first write subarray 1720a, with a hold level, such that the redundant write MUX 1881 of the first write subarray 1720a is configured as a hold unit that holds the previous output signal regardless of the current input. Thus, the redundant write MUX 1881 of the first write subarray 1720a can still output data (0,3) via signal lines 1815 at clk2 (e.g., the same as clk1), as shown in the second row of table 1852. That is, data (0, 3) is still input to the redundant input C of the redundant write MUX 1881 of the second write sub-array 1720b via signal line 1815 (e.g., the same as clk1). Thus, as shown in the second row of table 1852, at clk2, the 2N data are combined with data (0, 3) from the 1N data and input to the second write sub-array 1720b, respectively.

[0125] At clock signal 3 (clk3), the 2Nth data (1,0), (1,1), ..., and (1,7) are output by the second write sub-array 1720b without data shifting via signal lines 1821-1824 and 1826-1829, respectively, as shown in the second row of table 1854. The write redundancy enable logic 904 can further enable red2_en_b12_wt to a third level, causing the redundant write MUX 1881 of the second write sub-array 1720b to select the output from redundant input C and output data (0,3) via signal line 1825, as shown in the second row of table 1854. That is, at clk3, as shown in the first row of table 1856, the 2N pieces of data (1,0), (1,1), ..., and (1,7) are output and stored in the N main banks of group 1, and the 1N pieces of data to data (0,3) are output and stored in the redundant bank of group 1.

[0126] Referring to FIG. 18C, assume that B0_L and B0_H of group 0 are the failed main banks, as shown in table 1866 (same as table 1856 of FIG. 18B). Similar to FIG. 18B, the first N pieces of data including (0,0), (0,1), ..., and (0,7) (N=8) are intended to be stored in the N main banks of group 0, and the second N pieces of data including (1,0), (1,1), ..., and (1,7) are intended to be stored in the N main banks of group 1. The difference between FIG. 18B and FIG. 18C includes that the data write order of FIG. 18B is from group 0 to group 1, while the data write order of FIG. 18C is from group 1 to group 0. FIG. 18C is described herein with combined reference to FIG. 9 and FIG. 18A.

[0127] The first row of table 1860 in FIG. 18C indicates that 2N pieces of data (1,0), (1,1), ..., and (1,7) are loaded onto I / O signal lines 1801-1804 and 1806-1809 in FIG. 18A at clk0. That is, at clk0, the 2N pieces of data are input to main write MUX 1880 of first write sub-array 1720a via I / O signal lines 1801-1804 and 1806-1809, respectively.

[0128] In clk1, since there is no faulty main bank in group 1, the 2Nth data (1,0), (1,1), ..., and (1,7) are output from the first write sub-array 1720a without data shifting via signal lines 1811-1814 and 1816-1819, respectively, as shown in the first row of table 1862.

[0129] Furthermore, at clk1, 1N pieces of data (0,0), (0,1), ..., and (0,7) are loaded onto I / O signal lines 1801-1804 and 1806-1809, respectively. That is, at clk1, the 1N pieces of data are input to the main write MUX 1880 of the first write sub-array 1720a via the I / O signal lines 1801-1804 and 1806-1809, respectively.

[0130] At clk2, the 2N pieces of data (1,0), (1,1), ..., and (1,7) already input to the second write sub-array 1720b at clk1 may not yet be processed by the second write sub-array 1720b. Since B0_L and B0_H of group 0 are the failed main banks, the 2N pieces of data continue to be input to the second write sub-array 1720b to wait for data from the 1N pieces of data, so that the 2N pieces of data can be written to the main bank of group 1 while the data from the 1N pieces of data can be written to the redundant bank of group 1 at the same time.

[0131] Specifically, at clk2, the write redundancy enable logic 904 can generate a write select signal with a hold level for each main write MUX 1880 of the first write sub-array 1720a, so that each main write MUX 1880 of the first write sub-array 1720a is configured as a hold unit to hold the previous output signal of clk1 regardless of the current input. That is, at clk2, the 2N data (1,0), (1,1), ..., and (1,7) are still output from the N main write MUXes 1880 of the first write sub-array 1720a respectively without data shifting via the signal lines 1811-1814 and 1816-1819 as shown in the second row of table 1862. Meanwhile, the write redundancy enable logic 904 can generate a write select signal having a first level for the redundant write MUX 1881 of the first write sub-array 1720a (e.g., the write redundancy enable logic 904 can disable red1_en_b12_wt for the redundant write MUX 1881), so that the data (0,3) from the 1N data is redirected from its input A to the redundant write MUX 1881 of the first write sub-array 1720a as shown in the second row of table 1862 and output by signal line 1815 (with one bank right data shift). In this case, in clk2, not only the data (0,3) from the 1N data, but also the 2N data (1,0), (1,1), ..., and (1,7) are combined and input to the second write sub-array 1720b via signal lines 1811-1819, respectively.

[0132] Also, on clk2, the 1N pieces of data (0,0), (0,1), ..., and (0,7) are not processed by the main write MUX 1880 of the first write sub-array 1720a (but data (0,3) is processed by the redundant write MUX 1881 of the first write sub-array 1720a as described above). As shown in the third row of table 1860, the 1N pieces of data are loaded onto I / O signal lines 1801-1804 and 1806-1809, respectively.

[0133] At clk3, the 2N pieces of data (1,0), (1,1), ..., and (1,7) and the data (0,3) from the 1N pieces of data are output from the N main write MUXs 1880 and the redundant write MUXs 1881 of the second write subarray 1720b without data shifting via the signal lines 1821-1829 as shown in the first row of table 1864. That is, at clk3, the 2N pieces of data (1,0), (1,1), ..., and (1,7) are output and stored in the N main banks of group 1, and the data (0,3) from the 1N pieces of data is output and stored in the redundant bank of group 1 as shown in the first row of table 1866.

[0134] Also, in clk3, since B0_L of group 0 is the failed main bank, data (0,0), (0,1), and (0,2) are shifted right by one bank by the first write subarray 1720a as shown in the third row of table 1862, and output by signal lines 1812-1814, respectively. For other data (0,4), (0,5), (0,6), and (0,7), shifting of input data may not be necessary. Data (0,4), (0,5), (0,6), and (0,7) are output by the first write subarray 1720a without data shifting via signal lines 1816-1819, respectively, as shown in the third row of table 1862. As a result, on clk3, the 1N data (0,0), (0,1), (0,2), (0,4), (0,5), (0,6), and (0,7) are input to the second write sub-array 1720b via signal lines 1812-1814 and 1816-1819, respectively.

[0135] At clock signal 4 (clk4), since B0_H of group 0 is also a failed main bank, data (0,0) and (0,1) are again shifted right by one bank by the second write subarray 1720b as shown in the second row of table 1864, and output by signal lines 1823 and 1824, respectively. As shown in the second row of table 1864, data (0,2) is redirected from its input A to the redundant write MUX 1881 of the second write subarray 1720b, and output by signal line 1825 with a right data shift of one bank. As a result, each data (0,0), (0,1), or (0,2) is shifted right by one bank by the second write subarray 1720b at clk4. For other data (0,4), (0,5), (0,6), and (0,7), shifting of input data may not be required, and data (0,4), (0,5), (0,6), and (0,7) are output by the second write subarray 1720b without data shifting via signal lines 1826-1829, respectively, as shown in the second row of table 1864. As a result, at clk4, data (0,0), (0,1), (0,2), (0,4), (0,5), (0,6), and (0,7) from the 1N data are output to the seven working banks of group 0 via signal lines 1823-1829, respectively. That is, from the 1Nth data, data (0,0), (0,1), (0,2), (0,4), (0,5), (0,6), and (0,7) are stored in the seven working banks of group 0, as shown in the second row of table 1866.

[0136] FIG. 18D illustrates a schematic diagram of another exemplary memory device 1890 that implements a failed main bank repair scheme at the data input using a write MUX array having two write subarrays according to some aspects of the disclosure. The memory device 1890 may include components similar to those of any suitable memory device described herein (e.g., memory device 1800 of FIG. 18A), and similar descriptions will not be repeated here. As an example, each of group 0 and group 1 of FIG. 18D may include N main banks 702 with N=4 and one redundant bank 704 for simultaneous data input / output. The write MUX array 707 of the I / O circuit 407 may include a first write subarray 1720a and a second write subarray 1720b. Each write subarray 1720a or 1720b may include a redundant write MUX 1881 and N main write MUXes 1880 with N=4.

[0137] The redundant write MUX 1881 may be located to the left or right of the N main write MUXes 1880 in each write subarray 1720a or 1720b. One of the first and second inputs of the redundant write MUX 1881 in each write subarray 1320a or 1320b is coupled to the first input A of the adjacent main write MUX 1880 in the same write subarray, and the other of the first and second inputs of the redundant write MUX 1881 is coupled to a Vdd signal line. For example, as shown in FIG. 18D, the redundant write MUX 1881 is located to the right of the N main write MUXes 1880 in each write subarray 1720a or 1720b. The first input A of the redundant write MUX 1881 is coupled to the first input A of the adjacent main write MUX 1880 on the left. The second input B of the redundant write MUX 1881 is coupled to a Vdd signal line.

[0138] FIG. 19A illustrates a schematic diagram of an example memory device 1900 that implements a failed main bank repair scheme at the data input using a write MUX array with three write sub-arrays according to some aspects of the disclosure. The memory device 1900 may include components similar to those of any suitable memory device described herein, and similar descriptions will not be repeated here. In some implementations, the memory device 1900 may include an array of memory cells including P groups of P=3 banks, e.g., group 0, group 1, and group 2. Each group of banks may include N main banks 702 (e.g., N=4) and one redundant bank 704 for simultaneous data input / output, and thus three redundant banks 704 are included and shared by these three groups of banks.

[0139] 19A may include a first write subarray 1720a, a second write subarray 1720b, and a third write subarray 1720c. Each write subarray 1720a, 1720b, or 1720c may include a redundant write MUX 1881 and N main write MUXes 1880 (e.g., N=4). The redundant write MUX 1881 in the second write subarray 1720b may include a redundant input C, and the redundant write MUX 1881 in the third write subarray 1720c may include redundant inputs C and D.

[0140] For the first write subarray 1720a, the output of each main write MUX 1880 is coupled to a first input A of a corresponding main write MUX 1880 in the second write subarray 1720b via a corresponding signal line (e.g., 1913, 1914, 1916, or 1917). The output of the redundant write MUX 1881 in the first write subarray 1720a is coupled to a redundant input C of the redundant write MUX 1881 in the second write subarray 1720b via signal line 1915, and also to a redundant input D of the redundant write MUX 1881 in the third write subarray 1720c via signal line 1925b. Signal line 1915 is connected to signal line 1925b. A first input A of each main write MUX 1880 in the first write sub-array 1720a is coupled to a corresponding I / O data line (e.g., 1903, 1904, 1906, or 1907) and configured to receive corresponding data from the corresponding I / O data line.

[0141] For the second write subarray 1720b, the output of each main write MUX 1880 is coupled to a first input A of a corresponding main write MUX 1880 in the third write subarray 1720b via a corresponding signal line (e.g., 1923, 1924, 1926, or 1927). The output of the redundant write MUX 1881 of the second write subarray 1720b is coupled to a redundant input C of the redundant write MUX 1881 of the third write subarray 1720c via signal line 1925a.

[0142] For the third write sub-array 1720c, the outputs of the N main write MUXes 1880 and redundant write MUXes 1881 are coupled via signal lines 1933, 1934, 1935, 1936, and 1937, respectively, to the N main banks 702 and redundant banks 704 in the corresponding group of banks.

[0143] For each write subarray 1720a, 1720b, or 1720c, the first input A and the second input B of the redundant write MUX 1881 are respectively coupled to the first inputs A of two adjacent main write MUXes 1880 in the same write subarray. The second input B of each main write MUX 1880 in each write subarray 1720a, 1720b, or 1720c is coupled to the Vdd signal line or the first input A of the adjacent main write MUX 1880 in the same write subarray. For example, for each main write MUX 1880 located at a respective end of each write subarray 1720a, 1720b, or 1720c, the second input B of the respective main write MUX 1880 is coupled to the Vdd signal line. For each main write MUX 1880 to the left of the redundant write MUX 1881 (except the left-most main write MUX 1880), the second input B of the respective main write MUX 1880 is coupled to the first input A of the adjacent main write MUX 1880 to the left. For each main write MUX 1880 to the right of the redundant write MUX 1881 (except the right-most main write MUX), the second input B of the respective main write MUX 1880 is coupled to the first input A of the adjacent main write MUX 1880 to the right.

[0144] The select port S of each main write MUX 1880 can be configured to receive a write select signal indicating the selection of one input (A or B). In some implementations, the write select signal of each main write MUX 1880 in the first write sub-array 1720a can be red1_en_b0_l_wt, red1_en_b0_h_wt, red1_en_b1_l_wt, or red1_en_b1_h_wt. The write select signal of each main write MUX 1880 in the second write sub-array 1720b can be red2_en_b0_l_wt, red2_en_b0_h_wt, red2_en_b1_l_wt, or red2_en_b1_h_wt. The write select signal for each main write MUX 1880 in the third write sub-array 1720c may be red3_en_b0_l_wt, red3_en_b0_h_wt, red3_en_b1_l_wt, or red3_en_b1_h_wt.

[0145] The select port S of each redundant write MUX 1880 can be configured to receive a write select signal indicating the selection of one input (A, B, C, D, or any other available input). For example, a first level of the write select signal (indicating that the write select signal is invalid) may select the first input A, a second level of the write select signal may select the second input B, a third level of the write select signal may select the redundant input C, and a fourth level of the write select signal may select the redundant input D. In some implementations, the write select signals of the redundant write MUXes 1881 in the first write sub-array 1720a, the second write sub-array 1720b, and the third write sub-array 1720c may be red1_en_b01_wt, red2_en_b01_wt, and red3_en_b01_wt, respectively.

[0146] 19B-19C illustrate an exemplary failed main bank repair scheme in a data input implemented by the memory device 1900 of FIG. 19A according to some aspects of the present disclosure. With reference to FIG. 19B, assume that group 0, group 1, and group 2 may include a total of three failed main banks. As shown in table 1956, the three failed main banks may be distributed in group 0 (e.g., B0_L, B0_H, and B1_L in group 0 are failed main banks). FIG. 19B is described herein with combined reference to FIG. 9 and FIG. 19A.

[0147] In some implementations, the working bank logic 906 of the I / O control logic 412 is coupled to the register 414 and configured to obtain bank failure information indicating three failed main banks from group 0. The working bank logic 906 can determine 3×N working banks from group 0, group 1, and group 3 that can be used for input and output of data. That is, the working bank logic 906 can replace the three failed main banks with an equal number of redundant banks, such that the 3×N working banks can include three redundant banks and 3×N−3 main banks in group 0, group 1, and group 2.

[0148] Based on the determined 3×N working banks, the write redundancy enable logic 904 can be configured to control the I / O circuitry 407 to direct the 3×N data to the 3×N working banks, respectively. For example, the write redundancy enable logic 904 is coupled to the main write MUX 1880 and the redundant write MUX 1881 of each write sub-array 1720a, 1720b, or 1720c, and is configured to provide a plurality of write select signals 903 to the main write MUX 1880 and the redundant write MUX 1881 in each write sub-array 1720a, 1720b, or 1720c based on the determined 3×N working banks.

[0149] Assume that the 1st N pieces of data including (0,0), (0,1), (0,2), and (0,3) (N=4) are intended to be stored in the N main banks of group 0, the 2nd N pieces of data including (1,0), (1,1), (1,2), and (1,3) are intended to be stored in the N main banks of group 1, and the 3rd N pieces of data including (2,0), (2,1), (2,2), and (2,3) are intended to be stored in the N main banks of group 2. The data write order in FIG. 19B is from group 0 to group 1 to group 2. FIG. 19B shows a table 1950 including the 1st N pieces of data loaded into I / O signal lines 1903, 1904, 1906, and 1907, respectively, at clk0. Table 1950 also includes a 2Nth number of pieces of data that are loaded onto I / O signal lines 1903, 1904, 1906, and 1907, respectively, at clk1. Table 1950 further includes a 3Nth number of pieces of data that are loaded onto I / O signal lines 1903, 1904, 1906, and 1907, respectively, at clk2.

[0150] Initially, at clk0, the firstN data (0,0), (0,1), (0,2), and (0,3) are input to the main write MUX 1880 of the first write sub-array 1720a via I / O signal lines 1903, 1904, 1906, and 1907, respectively, as shown in the first row of table 1950.

[0151] At clk1, since B0_L of group 0 is the failed main bank, data (0,0) and (0,1) from the 1N data are shifted right by one bank by the first write subarray 1720a and output via signal lines 1914-1915, respectively, as shown in the first row of table 1952. For other data (0,2) and (0,3), input data shift may not be required, and data (0,2) and (0,3) are output by the first write subarray 1720a without data shift via signal lines 1916 and 1917, respectively, as shown in the first row of table 1952. As a result, at clk1, the 1N data (0,0), (0,1), (0,2), and (0,3) are input to the second write subarray 1720b via signals 1914-1917, respectively. For example, at clk1, data (0,1) is input to redundant input C of redundant write MUX 1881 in the second write sub-array 1720b via signal line 1915, and to redundant input D of redundant write MUX 1881 in the third write sub-array 1720b via signal line 1925b.

[0152] Also, at clk1, the 2Nth data (1,0), (1,1), (1,2), and (1,3) are input to the main write MUX 1880 of the first write sub-array 1720a via I / O signal lines 1903, 1904, 1906, and 1907, respectively, as shown in the second row of table 1950.

[0153] In clk2, since B0_H of group 0 is also a failed main bank, data (0,0) from the N data is redirected from input A to the redundant write MUX 1881 of the second write subarray 1720b and output by the redundant write MUX 1881 of the second write subarray 1720b via signal line 1925a (with one bank right data shift) as shown in the first row of table 1954. For the other data (0,2) and (0,3), no input data shift may be required, and data (0,2) and (0,3) are output by the second write subarray 1720b without data shift via signal lines 1926 and 1927, respectively, as shown in the first row of table 1954. As a result, data (0,0), (0,2), and (0,3) from the 1Nth data are output by the second write sub-array 1720b via signal lines 1925a, 1926, and 1927, respectively, as shown in the first row of table 1954.

[0154] The write redundancy enable logic 904 may generate a write select signal having a hold level (e.g., red1_en_b01_wt having a hold level) for the redundant write MUX 1881 of the first write subarray 1720a. As a result, the redundant write MUX 1881 of the first write subarray 1720a is configured as a hold unit, holds its previous output signal of clk1, and continues to output data (0,1) via signal line 1915 at clk2. Thus, at clk2, data (0,1) is still input to the redundant input C of the redundant write MUX 1881 of the second write subarray 1720b via signal line 1915 and to the redundant D of the redundant write MUX 1881 of the third write subarray 1720c via signal line 1925b. As a result, at clk2, the 1N data (0,0), (0,1), (0,2), and (0,3) are input to the third write sub-array 1720b via signal lines 1925a, 1925b, 1926, and 1927, respectively, as shown in the first row of table 1954.

[0155] Also, at clk2, the 2N pieces of data (1,0), (1,1), (1,2), and (1,3) are output from the first write subarray 1720a without data shifting via signal lines 1913, 1914, 1916, and 1917, respectively, as shown in the second row of table 1952. As described above, at clk2, data (0,1) is still input to the redundant input C of the redundant write MUX 1881 of the second write subarray 1720b via signal line 1915. As a result, at clk2, data (0,1) from the 2N pieces of data and the 1N pieces of data are input to the second write subarray 1720b via signal lines 1913-1917, respectively, as shown in the second row of table 1952.

[0156] Also, on clk2, the 3Nth data (2,0), (2,1), (2,2), and (2,3) are input to the main write MUX 1880 of the first write sub-array 1720a via I / O signal lines 1903, 1904, 1906, and 1907, respectively, as shown in the third row of table 1950.

[0157] At clk3, since B1_L of group 0 is also a failed main bank, data (0,2) from the 1N data is redirected from input B to the redundant write MUX 1881 of the third write subarray 1720c and output by the redundant write MUX 1881 via signal line 1935 (with one bank left data shift), as shown in the first row of table 1955. For data (0,3), input data shift may not be required. As shown in the first row of table 1955, data (0,3) is output by the third write subarray 1720c via signal line 1937 without data shift. As a result, at clk3, data (0,2) and (0,3) from the 1N data are output to the two working banks of group 0 via signal lines 1935 and 1937, respectively. That is, data (0,2) and (0,3) from the 1Nth data are stored in the two working banks of group 0, as shown in the last row of table 1956.

[0158] Also, at clk3, the 2N data (1,0), (1,1), (1,2), and (1,3) are output from the N main write MUXes 1880 of the second write subarray 1720b without data shifting via signal lines 1923, 1924, 1926, and 1927, respectively, as shown in the second row of table 1954. Furthermore, the redundant write MUX 1881 of the first write subarray 1720a is still configured as a holding unit that holds the output signal before clk2 and still outputs data (0,1) from the 1N data via signal line 1915. Thus, data (0,1) is still input to the redundant input C of the redundant write MUX 1881 of the second write subarray 1720b via signal line 1915, and to the redundant D of the redundant write MUX 1881 of the third write subarray 1720c via signal line 1925b. Also, the redundant write MUX 1881 of the second write subarray 1720b is configured as a holding unit, holds the previous output signal of clk2, and outputs data (0,0) from the 1N data via signal line 1925a at clk3. Thus, data (0,0) is still input to the redundant input C of the redundant write MUX 1881 of the third write subarray 1720c via signal line 1925a. As a result, at clk3, the 2N data and data (0,0) and (0,1) from the 1N data are input to the third write subarray 1720c via signal lines 1913, 1924, 1925a, 1925b, 1926, and 1927, respectively, as shown in the second row of table 1954.

[0159] Also, at clk3, the 3N data (2,0), (2,1), (2,2), and (2,3) are output from the N main write MUXes 1880 of the first write subarray 1720a without data shifting via signal lines 1913, 1914, 1916, and 1917, respectively, as shown in the second row of table 1952. As described above, data (0,1) is still input to the redundant input C of the redundant write MUX 1881 of the second write subarray 1720b via signal line 1915 at clk3. As a result, at clk3, data (2,0), (2,1), (0,1), (2,2), and (2,3) are input to the second write subarray 1720b via signal lines 1913-1917, respectively, as shown in the second row of table 1952.

[0160] At clk4, the 2N data (1,0), (1,1), (1,2), and (1,3) are output from the N main write MUXes 1880 of the third write sub-array 1720c, respectively, without data shifting via signal lines 1933, 1934, 1936, and 1937, as shown in the second row of table 1955. The write redundancy enable logic 904 can enable red3_en_b01_wt up to the third level, so that the redundant write MUX 1881 of the third write sub-array 1720c selects data (0,0) from its redundant input C and outputs data (0,0) via signal lines 1935, as shown in the second row of table 1955. As a result, at clk4, the 2N pieces of data are combined with data (0,0) from the 1N pieces of data, and the 2N pieces of data and data (0,0) are output to the five working banks of group 1 via signal lines 1933-1937, respectively. That is, as shown in the second row of table 1956, the 2N pieces of data and data (0,0) from the 1N pieces of data are stored in the five working banks of group 1.

[0161] Also, at clk4, the 3N data (2,0), (2,1), (2,2), and (2,3) are output from the N main write MUXes 1880 of the second write subarray 1720b, respectively, without data shifting via signal lines 1923, 1924, 1926, and 1927, as shown in the third row of table 1954. At clk4, the redundant write MUX 1881 of the first write subarray 1720a is also configured as a holding unit that holds the output signal before clk3 and still outputs data (0,1) from the 1N data via signal lines 1915 and 1925b. That is, data (0,1) is still input to the redundant D of the redundant write MUX 1881 of the third write subarray 1720c via signal line 1925b. As a result, at clk4, the 3Nth data is combined with data (0,1) from the 1Nth data, so that the 3Nth data and data (0,1) are output to the third write sub-array 1720c via signal lines 1923, 1924, 1925b, 1926, and 1927, respectively, as shown in the third row of table 1954.

[0162] At clock signal 5 (clk5), the 3N data (2,0), (2,1), (2,2), and (2,3) are output from the N main write MUXes 1880 of the third write subarray 1720c without data shifting via signal lines 1933, 1934, 1936, and 1937, respectively, as shown in the third row of table 1955. The write redundancy enable logic 904 can enable red3_en_b01_wt to a fourth level, as shown in the third row of table 1955, causing the redundant write MUX 1881 of the third write subarray 1720c to select data (0,1) from its redundant input D and output data (0,1) via signal line 1935. As a result, at clk5, the 3N data and data (0,1) from the 1N data are output to the five working banks of group 2 via signal lines 1933-1937, respectively. That is, as shown in the first row of table 1956, data (0,1) from the 3Nth data and the 1Nth data are stored in the five working banks of group 2.

[0163] Referring to FIG. 19C, assume that the first N pieces of data including (0,0), (0,1), (0,2), and (0,3) (N=4) are intended to be stored in the N main banks of group 0, the second N pieces of data including (1,0), (1,1), (1,2), and (1,3) are intended to be stored in the N main banks of group 1, and the third N pieces of data including (2,0), (2,1), (2,2), and (2,3) are intended to be stored in the N main banks of group 2 (e.g., similar to that of FIG. 19B). The difference between FIG. 19(b) and FIG. 19(c) includes that in FIG. 19C, group 0 has two failed main banks (e.g., B0_L, B1_L) and group 1 has one failed main bank (e.g., B1_L), while in FIG. 19B, group 0 has three failed main banks.

[0164] 19C shows a table 1960 including a 1N number of pieces of data loaded onto I / O signal lines 1903, 1904, 1906, and 1907, respectively, at clk0. Table 1960 also includes a 2N number of pieces of data loaded onto I / O signal lines 1903, 1904, 1906, and 1907, respectively, at clk1. Table 1960 further includes a 3N number of pieces of data loaded onto I / O signal lines 1903, 1904, 1906, and 1907, respectively, at clk2.

[0165] Initially, at clk0, the firstN data (0,0), (0,1), (0,2), and (0,3) are input to the main write MUX 1880 of the first write sub-array 1720a via I / O signal lines 1903, 1904, 1906, and 1907, respectively, as shown in the first row of table 1960.

[0166] At clk1, the firstN data (0,0), (0,1), (0,2), and (0,3) are output from the N main write MUXes 1880 of the first write sub-array 1720a, respectively, without data shifting via signal lines 1913, 1914, 1916, and 1917, as shown in the first row of table 1962.

[0167] At clk2, since B1_L of group 0 is the failed main bank, the redundant write MUX 1881 of the second write sub-array 1720b selects data (0,2) from its input B via signal line 1925a and outputs data (0,2), as shown in the first row of table 1964. As a result, data (0,2) is shifted left by one bank by the second write sub-array 1720b at clk2. For other data (0,0), (0,1), and (0,3), no input data shift may be required. Then, data (0,0), (0,1), and (0,3) are output by the second write sub-array 1720b without data shifting via signal lines 1923, 1924, and 1927, respectively, as shown in the first row of table 1964. As a result, at clk2, the first N data (0,0), (0,1), (0,2), and (0,3) are input to the third write subarray 1720c via signal lines 1923, 1924, 1925a, and 1927, respectively. For example, at clk2, data (0,2) is input to the redundant input C of the redundant write MUX 1881 in the third write subarray 1720c via signal line 1925a.

[0168] Also, on clk2, the 2Nth data (1,0), (1,1), (1,2), and (1,3) are output from the N main write MUXes 1880 of the first write subarray 1720a without data shifting via signal lines 1913, 1914, 1916, and 1917, respectively, as shown in the second row of table 1962. Also, on clk2, the 3Nth data (2,0), (2,1), (2,2), and (2,3) are input to the main write MUXes 1880 of the first write subarray 1720a without data shifting via I / O signal lines 1903, 1904, 1906, and 1907, respectively, as shown in the third row of table 1960.

[0169] In clk3, since B0_L of group 0 is also a failed main bank, data (0,0) and (0,1) from the 1N data are shifted right by one bank by the third write subarray 1720c, respectively, as shown in the first row of table 1965, and output via signal lines 1924 and 1935. For data (0,3), shifting of input data may not be required. As shown in the first row of table 1965, data (0,3) is output by the third write subarray 1720c without data shifting via signal line 1937. As a result, in clk3, data (0,0), (0,1), and (0,3) of the 1N data are output to the three working banks of group 0 via signal lines 1934, 1935, and 1937, respectively. That is, data (0,0), (0,1), and (0,3) from the 1Nth data are stored in the three working banks of group 0, as shown in the last row of table 1966.

[0170] Also, at clk3, the secondN data (1,0), (1,1), (1,2), and (1,3) are output from the N main write MUXes 1880 of the second write subarray 1720a without data shifting via signal lines 1923, 1924, 1926, and 1927, respectively, as shown in the second row of table 1964. The redundant write MUX 1881 of the second write subarray 1720b is configured as a holding unit, and is configured to hold the previous output signal of clk2 and output data (0,2) via signal line 1925a at clk3. Thus, data (0,2) is still input to the redundant input C of the redundant write MUX 1881 of the third write subarray 1720b via signal line 1925a. That is, on clk3, data (1,0), (1,1), (0,2), (1,2), and (1,3) are input to the third write sub-array 1720b via signal lines 1923, 1924, 1925a, 1926, and 1927, respectively, as shown in the second row of table 1964.

[0171] Also, on clk3, the third N pieces of data (2,0), (2,1), (2,2), and (2,3) are output from the N main write MUXes 1880 of the first write sub-array 1720a, respectively, without data shifting via signal lines 1913, 1914, 1916, and 1917, as shown in the third row of table 1962.

[0172] At clk4, since B1_L of group 1 is also a failed main bank, data (1,2) may be shifted one bank left by the redundant write MUX 1881 of the third write subarray 1720c and output via signal line 1935, as shown in the second row of table 1965. For data (1,0), (1,1), and (1,3), shifting of input data may not be required. Data (1,0), (1,1), and (1,3) are output by the third write subarray 1720c without data shifting via signal lines 1933, 1934, and 1937, respectively, as shown in the second row of table 1965. As a result, at clk4, the 2Nth data (1,0), (1,1), (1,2), and (1,3) are output to the four working banks of group 1 via signal lines 1933-1935, and 1937, respectively. That is, the 2Nth data (1,0), (1,1), (1,2), and (1,3) are stored in the four working banks of group 1, as shown in the second row of table 1966.

[0173] Also, at clk4, the third N data (2,0), (2,1), (2,2), and (2,3) are output from the N main write MUXes 1880 of the second write subarray 1720a, respectively, without data shifting via signal lines 1923, 1924, 1926, and 1927, as shown in the third row of table 1964. The redundant write MUX 1881 of the second write subarray 1720b is also configured as a holding unit, which holds the previous output signal of clk3, and continues to output data (0,2) via signal line 1925a at clk4. Thus, data (0,2) is still input to the redundant input C of the redundant write MUX 1881 of the third write subarray 1720b via signal line 1925a. That is, at clk4, data (2,0), (2,1), (0,2), (2,2), and (2,3) are input to the third write sub-array 1720c via signal lines 1923, 1924, 1925a, 1926, and 1927, respectively, as shown in the third row of table 1964.

[0174] At clk5, the 3N pieces of data (2,0), (2,1), (2,2), and (2,3) are output from the N main write MUXes 1880 of the third write subarray 1720c without data shifting via signal lines 1933, 1934, 1936, and 1937, respectively, as shown in the third row of table 1965. The redundant write MUX 1881 of the third write subarray 1720c selects data (0,2) from its redundant input C and outputs data (0,2) via signal line 1935, as shown in the third row of table 1965. As a result, at clk5, the 3N pieces of data and data (0,2) of the 1N pieces of data are output to the five working banks of group 3 via signal lines 1933 to 1937, respectively. That is, as shown in the first row of table 1966, data (0,2) from the 3Nth data and the 1Nth data is stored in the five working banks of group 3.

[0175] FIG. 20 illustrates a schematic diagram of an example memory device 2000 that uses a read MUX array with multiple read subarrays to implement a failed main bank repair scheme at the data output, according to some aspects of the disclosure. In some implementations illustrated in FIG. 20, at the data output (e.g., a read operation), the page buffer / sense amplifier 404 and the column decoder / bit line driver 406 (or the page buffer / sense amplifier portion 1406 and the column decoder / bit line driver portion 1506) may include nine sense amplifiers 802 coupled to eight main banks 702 and one redundant bank 704, respectively. The memory device 2000 may include components similar to those of any suitable memory device described herein (e.g., the memory device 1700 of FIG. 17), and similar descriptions will not be repeated here.

[0176] The I / O circuit 407 may include N+1 inputs respectively coupled to the N main banks 702 and redundant banks 704 in each group of banks via a data bus 1701 and a wiring set including wires 1702, 1704, 1706, 1708, 1710, 1712, 1714, 1716, and 1718. For example, each bank may be coupled to an input of the I / O circuit 407 via a respective data line of the data bus 1701 and a respective wire in the wiring set. The I / O circuit 407 may include a read MUX array 807. Under the control of the I / O control logic 412, the read MUX array 807 may be configured to respectively direct P×N data from the P×N working banks in the P groups of banks. In some implementations, the read MUX array 807 may include P read subarrays 2020 (e.g., a first read subarray, a second read subarray, ..., and a Pth read subarray) that are applied in series. An exemplary structure of each read subarray 2020 is described in more detail below with reference to Figures 21A, 21C, and 22A.

[0177] FIG. 21A illustrates a schematic diagram of an example memory device 2100 that uses a read MUX array with two read subarrays to implement a failed main bank repair scheme at the data output, according to some aspects of the disclosure. The memory device 2100 may include components similar to those of any suitable memory device described herein, and similar descriptions will not be repeated here. In some implementations, the memory device 2100 may include an array of memory cells including P groups of P=2 banks, e.g., group 0 and group 1. Each group of banks may include N main banks 702 (e.g., N=8) and one redundant bank 704 for simultaneous data input / output, and thus two redundant banks 704 are included and shared by the group of two banks.

[0178] 21A, the read MUX array 807 of the I / O circuit 407 may include a first read subarray 2020a and a second read subarray 2020b that are applied in series. Each read subarray 2020a or 2020b may include N read MUXes 2180 (e.g., including a read MUX 2180a, a read MUX 2180b, etc.). Each read MUX 2180 may include a first input A, a second input B, a selection port S, and an output Out.

[0179] In some implementations, each read subarray 2020a or 2020b can have a structure similar to the read MUX array 807 of Figure 8. For example, two instances of the read MUX array 807 of Figure 8 can be cascaded in series and modified to form the read MUX array 807 of Figure 21A. In general, P instances of the read MUX array 807 of Figure 8 can be cascaded in series and modified to form a read MUX array having P read subarrays.

[0180] With respect to the first read subarray 2020a, the first input A of each read MUX 2180 in the first read subarray 2020a is coupled to a corresponding main bank 702 via a corresponding signal line (e.g., 2101, 2102, 2103, 2104, 2106, 2107, 2108, or 2109). The output of each read MUX 2180 in the first read subarray 2020a is coupled to the first input A of a corresponding read MUX 2180 in the second read subarray 2020b via a corresponding signal line (e.g., 2111, 2112, 2113, 2114, 2116, 2117, 2118, or 2119).

[0181] With respect to the second read subarray 2020b, the output of each read MUX 2180 in the second read subarray 2020b is coupled to a corresponding I / O data line (e.g., 2121, 2122, 2123, 2124, 2126, 2127, 2128, or 2129) and configured to output corresponding data to the corresponding I / O data line.

[0182] For each read subarray 2020a or 2020b, the selection port S of each read MUX 2180 can be configured to receive a read select signal indicating the selection of one input (A or B). For example, a positive biased read select signal for each read MUX 2180, i.e., the read select signal is enabled, can select the second input B. The second input B of each read MUX 2180 in read subarray 2020a or 2020b is coupled to the first input A of an adjacent read MUX 2180 in the same read subarray, or is coupled to the redundant bank 704 via a corresponding signal line (e.g., 2105 or 2115). Signal line 2115 is connected to signal line 2105 and coupled to the redundant bank 704.

[0183] For example, in each group of banks, the redundant bank 704 may be disposed between the N main banks 702, and the N main banks 702 may be divided into two sets of main banks (e.g., a left set of main banks and a right set of main banks located to the left and right of the redundant bank 704, respectively). The N read MUXes 2180 in each read subarray 2020a or 2020b may be divided into a left set of read MUXes 2180 and a right set of read MUXes 2180 corresponding to the left set of main banks and the right set of main banks, respectively. In each read subarray 2020a or 2020b, the second input B of the first read MUX (e.g., read MUX 2180b) in the left set of read MUXs 2180 is coupled to the redundant bank 704 via signal line 2105 or 2115, and the second input B of each remaining read MUX 2180 in the left set of read MUXs 2180 is coupled to the first input A of the adjacent read MUX 2180 on the right. The second input B of the first read MUX (e.g., read MUX 2180a) in the right set of read MUXs 2180 is coupled to the redundant bank 704 via signal line 2105 or 2115, and the second input B of each remaining read MUX 2180 in the right set of read MUXs 2180 is coupled to the first input A of the adjacent read MUX 2180 on the left.

[0184] FIG. 21B illustrates an exemplary failed main bank repair scheme in data output implemented by the memory device 2100 of FIG. 21A according to some aspects of the disclosure. Assume that group 0 and group 1 contain a total of two failed main banks. As shown in table 2156, the two failed main banks may be distributed to group 0 (e.g., B0_L and B0_H in group 0 are failed main banks). FIG. 21B is described herein with combined reference to FIG. 20 and FIG. 21A.

[0185] In some implementations, the working bank logic 906 of the I / O control logic 412 is coupled to the register 414 and configured to obtain bank failure information indicating two failed main banks from group 0. The working bank logic 906 can determine 2×N working banks from group 0 and group 1 available for data input and output. Based on the determined 2×N working banks, the read redundancy enable logic 902 can be configured to control the I / O circuitry 407 to direct the 2×N data from the 2×N working banks, respectively. For example, the read redundancy enable logic 902 is coupled to each read MUX 2180 and configured to provide multiple read select signals 905 to the read MUX 2180 in each read sub-array 2020a or 2020b based on the determined 2×N working banks. For example, the plurality of read select signals 905 may be selected from red1_en_b0_l_rd, red1_en_b0_h_rd, red1_en_b1_l_rd, red1_en_b1_h_rd, red1_en_b2_l_rd, red1_en_b2_h_rd, red1_en_b3_l_rd, and red1_en_b3_h_rd for the read MUX 2180 in the first read sub-array 2020a. h_rd, and for the read MUX2180 in the second read sub-array 2020b, it may include red2_en_b0_l_rd, red2_en_b0_h_rd, red2_en_b1_l_rd, red2_en_b1_h_rd, red2_en_b2_l_rd, red2_en_b2_h_rd, red2_en_b3_l_rd, and red2_en_b3_h_rd.

[0186] Seven data (N=8) including (0,0), (0,1), (0,2), (0,4), ..., and (0,7) from the 1N data are stored in the seven working banks of group 0 as shown in table 2156, and the 2N data including (1,0), (1,1), ..., and (1,7) and the data (0,3) from the 1N data are stored in the N+1 working bank of group 1. The data read order in FIG. 21B is from group 0 to group 1. Table 2150 shows that seven data including (0,0), (0,1), (0,2), (0,4), ..., and (0,7) from the 1N data are read from the seven working banks of group 0, respectively, and loaded to signal lines 2103 to 2109 by clk0. Table 2150 also shows that data (0,3) from the 2N data and 1N data are read from the N+1 working banks of group 1, respectively, and loaded onto signal lines 2101-2109 with clk1.

[0187] Initially, at clk0, seven data from the 1stN, (0,0), (0,1), (0,2), (0,4), ..., and (0,7), are input to the read MUX 2180 of the first read subarray 2020a via signal lines 2103 to 2109, respectively, as shown in table 2150.

[0188] At clk1, since B0_H in group 0 is the failed main bank, the read redundancy enable logic 902 may enable red1_en_b0_l_rd, ..., and red1_en_b1_h_rd, allowing each read MUX 2180 in the left set of read MUXes 2180 in the first read subarray 2020a to input data from its input B with the data shifted left by one bank. That is, as shown in table 2152, data (0,0), (0,1), and (0,2) are shifted left by one bank and output by signal lines 2112-2114, respectively. For the other data (0,4), (0,5), (0,6), and (0,7), no shifting of the input data may be required and the read redundancy enable logic 902 may disable red1_en_b2_l_rd, ..., and red1_en_b3_h_rd, allowing each read MUX 2180 in the right set of read MUXes 2180 in the first read sub-array 2020a to input data from input A without data shifting. The data (0,4), (0,5), (0,6), and (0,7) are then output by signal lines 2116-2119, respectively, as shown in table 2152.

[0189] Also, in clk1, the 2Nth data and data (0, 3) from the 1Nth data are input to the read MUX 2180 of the first read subarray 2020a via signal lines 2101 to 2109, respectively, as shown in table 2150. For example, data (0, 3) from the 1Nth data is input to the read MUXes 2180a and 2180b of the first read subarray 2020a via signal line 2105. Since signal line 2115 is connected to signal line 2105, data (0, 3) is also input to the read MUXes 2180a and 2180b of the second read subarray 2020b via signal line 2115. As a result, on clk1, the first N data (0,0), (0,1), (0,2), (0,3), (0,4), (0,5), (0,6) and (0,7) are input to the second read subarray 2020b via signals 2112-2119, respectively.

[0190] At clk2, since B0_L of group 0 is also a failed main bank, the read redundancy enable logic 902 may enable red1_en_b0_l_rd, ..., and red1_en_b1_h_rd, allowing each read MUX 2180 in the left set of read MUXes 2180 in the second read subarray 2020b to input data from its input B with the data shifted left by one bank. That is, data (0,0), (0,1), (0,2), and (0,3) are shifted left by one bank as shown in table 2154 and output by I / O data lines 2121-2124, respectively. For the other data (0,4), (0,5), (0,6), and (0,7), no shifting of the input data may be required. Then, data (0,4), (0,5), (0,6), and (0,7) are output by the second read sub-array 2020b without data shifting via signal lines 2126-2129, respectively, as shown in table 2154. As a result, the 1N data are successfully output from the read MUX array 807.

[0191] Also, at clk2, the 2N pieces of data are output by the read MUX 2180 of the first read sub-array 2020a, without data shifting, via signal lines 2111-2114 and 2116-2109, respectively, as shown in table 2152. The 2N pieces of data are input to the read MUX 2180 of the second read sub-array 2020a, via signal lines 2111-2114 and 2116-2119, respectively.

[0192] As shown in table 2154, at clk3, the 2Nth data are output by the read MUX 2180 of the second read sub-array 2020b via signal lines 2121-2124 and 2126-2129 respectively without data shifting. As a result, the 2Nth data are successfully output from the read MUX array 807.

[0193] 21C illustrates a schematic diagram of another exemplary memory device 2190 that uses a read MUX array having two read subarrays to implement a failed main bank repair scheme at the data output in accordance with some aspects of the disclosure. The memory device 2190 can include components similar to those of any suitable memory device described herein (e.g., the memory device 2100 of FIG. 21A), and similar descriptions will not be repeated here.

[0194] 21C may include N=4 main banks 702 and one redundant bank 704 for simultaneous data input / output. The read MUX array 807 of the I / O circuit 407 may include a first read subarray 2020a and a second read subarray 2020b. Each read subarray 2020a or 2020b may include N=4 read MUXes 2180.

[0195] In each group of banks shown in FIG. 21C, the N main banks 702 may be located to the left of the redundant bank 704 and may be referred to as the left set of main banks. The N read MUXes 2180 in each read subarray 2020a or 2020b may be referred to as the left set of read MUXes 2180 corresponding to the left set of main banks. In each read subarray 2020a or 2020b, the second input B of the first read MUX (e.g., read MUX 2180b) in the left set of read MUXes 2180 is coupled to the redundant bank 704 via signal line 2105 or 2115. The second input B of each remaining read MUX 2180 in the left set of read MUXes 2180 is coupled to the first input A of its adjacent read MUX 2180 to the right.

[0196] In some other implementations, the N main banks 702 can be located to the right of the redundant bank 704, and the N main banks 702 can be referred to as a right set of main banks. The N read MUXes 2180 in each read subarray 2020a or 2020b can be referred to as a right set of read MUXes 2180 corresponding to the right set of main banks. In each read subarray 2020a or 2020b, the second input B of the first read MUX (e.g., read MUX 2180a) in the right set of read MUXes 2180 is coupled to the redundant bank 704 via signal line 2105 or 2115. The second input B of each remaining read MUX 2180 in the right set of read MUXes 2180 is coupled to the first input A of the adjacent read MUX 2180 on the left.

[0197] FIG. 22A illustrates a schematic diagram of an example memory device 2200 that implements a failed main bank repair scheme at the data output using a read MUX array with three read subarrays according to some aspects of the disclosure. The memory device 2200 may include components similar to those of any suitable memory device described herein, and similar descriptions will not be repeated here. In some implementations, the memory device 2200 may include an array of memory cells including P groups of P=3 banks, e.g., group 0, group 1, and group 2. Each group of banks may include N main banks 702 (e.g., N=4) and one redundant bank 704 for simultaneous data input / output, and thus three redundant banks 704 are included in and shared by these three groups of banks. The read MUX array 807 of the I / O circuit 407 may include a first read subarray 2020a, a second read subarray 2020b, and a third read subarray 2020c. Each read sub-array 2020a, 2020b, or 2020c may include N (e.g., N=4) read MUXes 2180. Each read MUX 2180 may include a first input A, a second input B, a selection port S, and an output Out.

[0198] With respect to the first read subarray 2020a, the first input A of each read MUX 2180 in the first read subarray 2020a is coupled to a corresponding main bank 702 via a corresponding signal line (e.g., 2203, 2204, 2206, or 2207). The output of each read MUX 2180 in the first read subarray 2020a is coupled to a first input A of a corresponding read MUX 2180 in the second read subarray 2020b via a corresponding signal line (e.g., 2213, 2214, 2216, or 2217). With respect to the second read subarray 2020b, the output of each read MUX 2180 in the second read subarray 2020b is coupled to a first input A of a corresponding read MUX 2180 in the third read subarray 2020c via a corresponding signal line (e.g., 2223, 2224, 2226, or 2227). With respect to the third read sub-array 2020c, the output of each read MUX 2180 in the third read sub-array 2020c is coupled to a corresponding I / O data line (e.g., 2233, 2234, 2236, or 2237) and configured to output corresponding data to the corresponding I / O data line.

[0199] For each read subarray 2020a, 2020b, or 2020c, the select port S of each read MUX 2180 may be configured to receive a read select signal indicating the selection of one input (A or B). The second input B of each read MUX 2180 in read subarray 2020a, 2020b, or 2020c is coupled to the first input A of an adjacent read MUX 2180 in the same read subarray or is coupled to the redundant bank 704 via a corresponding signal line (e.g., 2205, 2215, or 2225). Signal lines 2215 and 2225 are connected to signal line 2205 and coupled to the redundant bank 704.

[0200] For example, in each read subarray 2020a, 2020b, or 2020c, the second input B of the first read MUX 2180 (e.g., read MUX 2180b) in the left set of read MUXs 2180 is coupled to the redundant bank 704 via signal line 2205, 2215, or 2225. The second input B of each remaining read MUX 2180 in the left set of read MUXs 2180 is coupled to the first input A of its adjacent read MUX 2180 to the right. The second input B of the first read MUX in the right set of read MUXs 2180 (e.g., read MUX 2180a) is coupled to the redundant bank 704 via signal line 2205, 2215, or 2225. The second input B of each remaining read MUX 2180 in the right set of read MUXs 2180 is coupled to the first input A of its adjacent read MUX 2180 to the left.

[0201] 22B-22C show an exemplary failed main bank repair scheme in data output implemented by the memory device of FIG. 21A according to some aspects of the present disclosure. With reference to FIG. 22B, assume that group 0, group 1, and group 2 include a total of three failed main banks. As shown in table 2256, the three failed main banks may be distributed to group 0 (e.g., B0_L, B0_H, and B1_L in group 0 are failed main banks). FIG. 22B is described herein with combined reference to FIG. 9, FIG. 20, and FIG. 22A.

[0202] In some implementations, the working bank logic 906 of the I / O control logic 412 is coupled to the register 414 and configured to obtain bank failure information indicating three failed main banks from group 0. The working bank logic 906 can determine 3×N working banks from group 0, group 1, and group 2 available for data input and output. Based on the determined 3×N working banks, the read redundancy enable logic 902 can be configured to control the I / O circuitry 407 to direct the 3×N data from the 3×N working banks, respectively. For example, the read redundancy enable logic 902 is coupled to each read MUX 2180 and configured to provide a plurality of read select signals 905 to read the MUX 2180 in each read sub-array 2020a, 2020b, or 2020c based on the determined 3×N working banks. For example, the multiple read selection signals 905 may include red1_en_b0_l_rd, red1_en_b0_h_rd, red1_en_b1_l_rd, and red1_en_b1_h_rd for the read MUX 2180 in the first read subarray 2020a, red2_en_b0_l_rd, red2_en_b0_h_rd, red2_en_b1_l_rd, and red2_en_b1_h_rd for the read MUX 2180 in the second read subarray 2020b, and red3_en_b0_l_rd, red3_en_b0_h_rd, red3_en_b1_l_rd, and red3_en_b1_h_rd for the read MUX 2180 in the third read subarray 2020c.

[0203] Suppose that data (0,2) and (0,3) from the 1N data (N=4) are stored in two working banks of group 0, the 2N data including (1,0), (1,1), (1,2), and (1,3), and the data (0,0) from the 1N data are stored in the N+1 working banks of group 1, as shown in table 2256, and the 3N data including (2,0), (2,1), (2,2), and (2,3), and the data (0,1) from the 1N data are stored in the N+1 working banks of group 2. The data reading order in FIG. 22B is from group 0 to group 1 and then to group 2.

[0204] Table 2250 shows that of the 1Nth data, data (0,2) and (0,3) are read from two working banks of group 0, respectively, and loaded to signal lines 2205 and 2207 at clk0. Table 2250 also shows that data (0,0) from the 2Nth data and the 1Nth data are read from the N+1th working banks of group 1, respectively, and loaded to signal lines 2203-2107 at clk1. Table 2250 further shows that data (0,1) from the 3Nth data and the 1Nth data are read from the N+1th working banks of group 2, respectively, and loaded to signal lines 2203-2107 at clk2.

[0205] Initially, at clk0, data (0,2) and (0,3) from the 1st N data are input to the read MUX 2180 of the first read subarray 2020a via signal lines 2205 and 2207, respectively, as shown in table 2250.

[0206] In clk1, since B1_L of group 0 is the failed main bank, the data (0,2) input to the read MUX 2180a in the first read subarray 2020a may be shifted one bank to the right and output by the read MUX 2180a via signal line 2216, as shown in table 2252. For data (0,3), no shifting of the input data may be required, allowing the corresponding read MUX 2180 in the set of right read MUXes 2180 in the first read subarray 2020a to select data (0,3) from its input A without data shifting. Then, the data (0,2) and (0,3) are output by signal lines 2216 and 2217, respectively, as shown in table 2252.

[0207] Also, in clk1, as shown in table 2250, the 2N pieces of data and data (0,0) from the 1N pieces of data are input to the read MUX 2180 of the first read subarray 2020a via the signal lines 2203 to 2207. For example, data (0,0) from the 1N pieces of data is input to the read MUX 2180a and 2180b of the first read subarray 2020a via the signal line 2205. Since the signal line 2215 is connected to the signal line 2205, the data (0,0) is also input to the read MUX 2180a and 2180b of the second read subarray 2020b via the signal line 2215. As a result, in clk1, the data (0,0), (0,2), and (0,3) of the 1N pieces of data are input to the second read subarray 2020b via the signals 2215 to 2217, respectively.

[0208] In clk2, since B0_H of group 0 is the failed main bank, data (0,0) may be shifted one bank left and output by read MUX 2180b in the second read subarray 2020b via signal line 2224, as shown in table 2254. For data (0,2) and (0,3), no input data shift may be required, such that the corresponding read MUX 2180 in the right set of read MUXes 2180 in the second read subarray 2020b obtains data (0,2) and (0,3) from input A without data shift. Then, data (0,0), (0,2), and (0,3) are output from signal lines 2224, 2226, and 2227, respectively, as shown in table 2254.

[0209] Also, at clk2, the 2N pieces of data are output by the read MUX 2180 of the first read subarray 2020a, without data shifting, via signal lines 2213, 2214, 2216, and 2217, respectively, as shown in table 2252. The 2N pieces of data are input to the read MUX 2180 of the second read subarray 2020b, via signal lines 2213, 2214, 2216, and 2217, respectively.

[0210] Also, in clk2, the 3Nth data and data (0,1) from the 1Nth data are input to the read MUX 2180 of the first read subarray 2020a via the signal lines 2203 to 2207, as shown in table 2250. For example, data (0,1) from the 1Nth data is input to the read MUXs 2180a and 2180b of the first read subarray 2020a via the signal line 2205. Since the signal line 2225 is connected to the signal line 2205, the data (0,1) is also input to the read MUXs 2180a and 2180b of the third read subarray 2020c via the signal line 2225. As a result, on clk2, data (0,0), (0,1), (0,2), and (0,3) from the 1Nth data are input to the third read subarray 2020c via signals 2224-2227, respectively, as shown in table 2254.

[0211] At clk3, since B0_L of group 0 is also a failed main bank, data (0,0) and (0,1) may be shifted one bank left and output by the corresponding read MUX 2180 in the third read subarray 2020c via I / O data lines 2233 and 2234, as shown in table 2255. For data (0,2) and (0,3), input data shifting may not be required, and the corresponding read MUX 2180 in the third read subarray 2020b may output data (0,2) and (0,3) without data shifting via I / O data lines 2236 and 2237, respectively, as shown in table 2255. As a result, the 1N data are successfully output from the read MUX array 807.

[0212] Also, at clk3, the 2Nth data are output by the read MUX 2180 of the second read sub-array 2020b, respectively, without data shifting, via signal lines 2223, 2224, 2226, and 2227, as shown in table 2254. The 2Nth data are input to the read MUX 2180 of the third read sub-array 2020c, respectively, via signal lines 2223, 2224, 2226, and 2227.

[0213] Also, at clk3, the 3Nth data are output by the read MUX 2180 of the first read subarray 2020a without data shifting via signal lines 2213, 2214, 2216, and 2217, respectively, as shown in table 2252. The 3Nth data are input to the read MUX 2180 of the second read subarray 2020b via signal lines 2213, 2214, 2216, and 2217, respectively.

[0214] As shown in table 2255, at clk4, the 2Nth data are output by the read MUX 2180 of the third read sub-array 2020c, respectively, without data shifting, via data lines 2233, 2234, 2236, and 2237. As a result, the 2Nth data are successfully output from the read MUX array 807.

[0215] Also, at clk4, the 3Nth data are output by the read MUX 2180 of the second read sub-array 2020b, respectively, without data shifting, via signal lines 2223, 2224, 2226, and 2227, as shown in table 2254. The 3Nth data are input to the read MUX 2180 of the third read sub-array 2020c, respectively, via signal lines 2223, 2224, 2226, and 2227.

[0216] As shown in table 2255, at clk5, the 3Nth data are output by the read MUX 2180 of the third read sub-array 2020c, respectively, without data shifting, via data lines 2233, 2234, 2236, and 2237. As a result, the 3Nth data are successfully output from the read MUX array 807.

[0217] Referring to FIG. 22C, assume that group 0, group 1, and group 2 include a total of three faulty main banks. As shown in table 2266, the three faulty main banks may include B0_L and B1_L of group 0 and B1_L of group 1. FIG. 22C is described herein with combined reference to FIG. 22A. Table 2266 shows that data (0,0), (0,1), and (0,3) from the 1Nth data (N=4) are stored in the three working banks of group 0, the 2Nth data including (1,0), (1,1), (1,2), and (1,3) are stored in the N working banks of group 1, and the 3Nth data including (2,0), (2,1), (2,2), (2,3), and data (0,2) from the 1Nth data are stored in the N+1 working banks of group 2, as shown in table 2266. The data reading order in FIG. 22C is from group 0 to group 1 to group 2.

[0218] Table 2260 shows that data (0,0), (0,1), and (0,3) from the 1Nth data are read from the three working banks of group 0, respectively, and loaded onto signal lines 2204, 2205, and 2207 at clk0. Table 2260 also shows that the 2Nth data are read from the N working banks of group 1, respectively, and loaded onto signal lines 2203-2105 and 2207 at clk1. Table 2260 further shows that data (0,2) from the 3Nth data and the 1Nth data are read from the N+1 working banks of group 2, respectively, and loaded onto signal lines 2203-2107 at clk2.

[0219] Initially, at clk0, data (0,0), (0,1), and (0,3) from the first N data are input to the read MUX 2180 of the first read sub-array 2020a via signal lines 2204, 2205, and 2207, respectively, as shown in table 2260.

[0220] In clk1, since B0_L of group 0 is the failed main bank, data (0,0) and (0,1) may be shifted left by one bank by the first read subarray 2020a and output via signal lines 2213-2214, as shown in table 2262. For data (0,3), as shown in table 2262, input data shift may not be required, and the first read subarray 2020a can output data (0,3) via signal line 2217 without data shift. As a result, in clk1, data (0,0), (0,1), and (0,3) are output by signal lines 2213, 2214, and 2217, respectively, as shown in table 2262.

[0221] Also, in clk1, as shown in table 2260, 2N pieces of data are input to the read MUX 2180 of the first read sub-array 2020a via signal lines 2203 to 2205 and 2207, respectively.

[0222] In clk2, for data (0,0), (0,1), and (0,3), no input data shift may be required, and as shown in table A2264, the second read subarray 2020b outputs data (0,0), (0,1), and (0,3) without any data shift via signal lines 2223, 2224, and 2227, respectively.

[0223] In clk2, since B1_L of group 1 is the failed main bank, data (1,2) of the 2N data may be shifted right by one bank by read MUX 2180a in the first read subarray 2020a and output via signal line 2216, as shown in table 2262. For data (1,0), (1,1), and (1,3), shifting of input data may not be required, such that the first read subarray 2020a may output data (1,0), (1,1), and (1,3) without data shifting via signal lines 2213-2214 and 2227, respectively. As a result, data (1,0), (1,1), (1,2), and (1,3) are output by signal lines 2213-2214 and 2216-227, respectively, as shown in table 2262.

[0224] Also, in clk2, data (0,2) from the 3Nth data and the 1Nth data are input to the read MUX 2180 of the first read subarray 2020a via signal lines 2203-2207, respectively, as shown in table 2260. For example, data (0,2) from the 1Nth data is input to the read MUXes 2180a and 2180b of the first read subarray 2020a via signal line 2205. Since the signal line 2225 is connected to the signal line 2205, the data (0,2) is also input to the read MUXes 2180a and 2180b of the third read subarray 2020c via the signal line 2225. As a result, on clk2, data (0,0), (0,1), (0,2), and (0,3) from the 1Nth data are input to the third read subarray 2020c via signal lines 2224-2225 and 2227, respectively, as shown in table 2264.

[0225] In clk3, since B1_L of group 0 is also a failed main bank, data (0,2) from the 1N data may be shifted right by one bank by the read MUX 2180a of the third read subarray 2020c and output via I / O data line 2236, as shown in table 2265. For data (0,0), (0,1), and (0,3), input data shifting may not be required, so the third read subarray 2020c may select data (0,0), (0,1), and (0,3) from input A without data shifting via I / O data lines 2233-2234 and 2237, respectively, as shown in table 2265, and output data (0,0), (0,1), and (0,3). As a result, the 1N data are successfully output from the read MUX array 807.

[0226] Also, at clk3, the 2Nth data are output by the read MUX 2180 of the second read sub-array 2020b, respectively, without data shifting, via signal lines 2223, 2224, 2226, and 2227, as shown in table 2264. The 2Nth data are input to the read MUX 2180 of the third read sub-array 2020c, respectively, via signal lines 2223, 2224, 2226, and 2227.

[0227] Also, at clk3, the 3Nth data are output by the read MUX 2180 of the first read sub-array 2020a without data shifting via signal lines 2213, 2214, 2216, and 2217, respectively, as shown in table 2262. The 3Nth data are input to the read MUX 2180 of the second read sub-array 2020b via signal lines 2213, 2214, 2216, and 2217, respectively.

[0228] As shown in table 2265, at clk4, the 2Nth data are output by the read MUX 2180 of the third read subarray 2020c through the data lines 2233, 2234, 2236, and 2237, respectively, without data shifting. As a result, the 2Nth data are successfully output from the read MUX array 807. Also, at clk4, as shown in table 2264, the 3Nth data are output by the read MUX 2180 of the second read subarray 2020b through the signal lines 2223, 2224, 2226, and 2227, respectively, without data shifting. The 3Nth data are input to the read MUX 2180 of the third read subarray 2020c through the signal lines 2223, 2224, 2226, and 2227, respectively.

[0229] As shown in table 2265, at clk5, the 3Nth data are output by the read MUX 2180 of the third read sub-array 2020c, respectively, through data lines 2233, 2234, 2236, and 2237, without data shifting. As a result, the 3Nth data are successfully output from the read MUX array 807.

[0230] 17-22C above, an exemplary general structure of an I / O circuit 407 in a memory device is disclosed herein. The memory device may include an array of memory cells including P groups of banks. Each group of banks may include N main banks 702 and a redundant bank 704 for simultaneous data input / output, such that P redundant banks are included and shared by the P groups of banks.

[0231] In some implementations, the array of memory cells includes a first level memory unit, which includes a plurality of second level memory units, one of which includes the P groups of banks. The I / O circuitry 407 and the I / O control logic 412 are shared by the plurality of second level memory units. For example, the first level memory unit is a die including a plurality of planes. The second level memory unit including the P groups of banks is a plane within the die, and the plane includes P×N working banks from the P groups of banks. The I / O circuitry 407 is coupled to a global data bus and configured to direct the P×N data to and from the P×N working banks within the plane via the global data bus and one or more branch data buses within the plane, respectively.

[0232] The I / O circuit 407 may include a write MUX array 707. In some implementations, the write MUX array 707 may include P write sub-arrays that are applied in series. For example, a write sub-array in the write MUX array 707 may be represented as a pth write sub-array, where p is a positive integer and 1≦p≦P. Each write sub-array in the write MUX array 707 may include a redundant write MUX 1881 and N main write MUXes 1880. Each main write MUX 1880 and each redundant write MUX 1881 may include a first input A, a second input B, a selection port S, and an output, respectively.

[0233] For 2≦p≦P, the redundant write MUX 1881 in the pth write subarray may further include p−1 redundant inputs. For example, as shown in FIG. 19A , the redundant write MUX 1881 in the first write subarray may include no redundant inputs, the redundant write MUX 1881 in the second write subarray may include a first redundant input C, the redundant write MUX 1881 in the third write subarray may include a first redundant input C and a second redundant input D, etc.

[0234] When 1 ≤ p < P, the output of each main write MUX 1880 in the p-th write sub-array is coupled to the first input A of the corresponding main write MUX 1880 in the (p + 1)-th write sub-array. Also, when 1 ≤ p < P, the output of the redundant write MUX 1881 in the p-th write sub-array is coupled to the q-th redundant input of the corresponding redundant write MUX 1881 in each (p + q)-th write sub-array where 1 ≤ q ≤ P - p, and q is a positive integer. When p = P, the outputs of the N main write MUXes 1880 and redundant write MUXes 1881 in the p-th write sub-array are respectively coupled to the N main banks 702 and redundant banks 704 within the corresponding group of banks.

[0235] When p = 1, the first input A of each main write MUX 1880 in the p-th write sub-array is coupled to the corresponding I / O data line and is configured to receive corresponding data from the corresponding I / O data line. When 1 ≤ p ≤ P, the second input B of each main write MUX 1880 in the p-th write sub-array is coupled to the Vdd signal line or the first input A of the corresponding adjacent main write MUX 1880 in the p-th write sub-array.

[0236] In some implementations, as shown in FIGS. 18A and 19A, the redundant write MUX 1881 in the p-th write sub-array 1720 is disposed between the N main write MUXes 1880 in the p-th write sub-array. When 1 ≤ p ≤ P, the first input A and the second input B of the redundant write MUX 1881 in the p-th write sub-array are respectively coupled to the first inputs of two adjacent main write MUXes 1880 in the p-th write sub-array.

[0237] In some other implementations, the redundant write MUX1881 in the p-th write sub-array is arranged on the side of the N main write MUX1880s in the p-th write sub-array, as shown in FIG. 18D. When 1 ≦ p ≦ P, one of the first input A and the second input B of the redundant write MUX1881 in the p-th write sub-array is coupled to the first input A of the adjacent main write MUX1880 in the p-th write sub-array. The other of the first input A and the second input B of the redundant write MUX1881 in the p-th write sub-array is coupled to the Vdd signal line.

[0238] Furthermore, the I / O circuit 407 may include a read MUX array 807 coupled to each group of the banks and configured to direct the P×N data from the P×N working banks respectively. The read MUX array 807 can include P read sub-arrays applied in series, each read sub-array can include N read MUX2180s, and each read MUX2180 includes a first input A, a second input B, a selection port S, and an output Out respectively. For example, the read sub-arrays in the read MUX array 807 can be represented as the p-th read sub-array where 1 ≦ p ≦ P.

[0239] When 1 ≦ p < P, the output of each read MUX2180 in the p-th read sub-array is coupled to the first input A of the corresponding read MUX2180 in the (p + 1)-th read sub-array. When p = P, the output of each read MUX2180 in the p-th read sub-array is coupled to the corresponding I / O data line and is configured to output the corresponding data to the corresponding I / O data line.

[0240] When p = 1, the first input A of each read MUX2180 in the p-th read sub-array is coupled to the corresponding main bank in the N main banks. When 1 ≦ p ≦ P, the second input B of each read MUX2180 in the p-th read sub-array is coupled to the redundant bank or the first input A of the corresponding adjacent read MUX2180 in the p-th read sub-array.

[0241] In some implementations, assume that the P groups of banks include K failed main banks, where K is a positive integer less than or equal to P (1≦K≦P). The K failed main banks may be distributed from the P groups of banks to a single group of banks (or two or more groups of banks). The I / O control logic 412 may be configured to determine P×N working banks from the P groups of banks based on the bank failure information indicating the K failed main banks from the P groups of banks. The P×N working banks may include K redundant banks of the P redundant banks. The I / O control logic 412 may be further configured to control the I / O circuitry 407 to direct the P×N data to or from the P×N working banks, respectively.

[0242] For example, assume that a first group of banks includes K failed main banks and another group of banks does not include the failed main banks. The I / O control logic 412 can be configured to (1) direct K of the 1N pieces of data to or from the K redundant banks, (2) direct the remaining NK pieces of data of the 1N pieces of data to or from the NK working main banks of the first group of banks, and (3) direct other data intended to be stored in the other groups of banks to or from the respective working main banks of the other groups of banks.

[0243] FIG. 23 illustrates a flowchart of an example method 2300 for operating a memory device implementing a failed main bank repair scheme in data input / output in accordance with some aspects of the disclosure. The memory device may be any suitable memory device disclosed herein. The method 2300 may be implemented by the I / O control logic 412. It is understood that the operations illustrated in the method 2300 may not be exhaustive and that other operations may be performed before, after, or between the illustrated operations as well. Additionally, some of the operations may be performed simultaneously or in a different order than that illustrated in FIG. 23.

[0244] 23, the method 2300 begins at operation 2302 where bank failure information is obtained that indicates K failed main banks from the P group of banks. The K failed main banks may be identified by post-manufacturing testing of the memory device. For example, the working bank logic 906 may obtain the bank failure information from the register 414 before operating the memory device.

[0245] The method 2300 proceeds to operation 2304, as shown in Figure 23, where P x ​​N working banks are determined from the P groups of banks based on the bank failure information. For example, the working bank logic 906 may determine the P x ​​N working banks including K redundant banks from the P groups of banks and the remaining main bank.

[0246] The method 2300, as shown in FIG. 23, proceeds to operation 2306 where the P×N data are directed to or from the P×N working banks, respectively.

[0247] According to one aspect of the disclosure, a memory device includes an array of memory cells, an I / O circuit, and an I / O control logic coupled to the I / O circuit. The array of memory cells includes P groups of banks. Each group of banks includes N main banks and a redundant bank such that P redundant banks are included in and shared by the P groups of banks, where P and N are each a positive integer. The I / O circuit is coupled to the P groups of banks and configured to direct the P×N data to or from the P×N working banks, respectively. The I / O control logic is configured to determine the P×N working banks from the P groups of banks based on bank failure information indicating K failed main banks from the P groups of banks. The P×N working banks include K redundant banks of the P redundant banks, where K is a positive integer less than or equal to P. The I / O control logic is also configured to control the I / O circuit to direct the P×N data to or from the P×N working banks, respectively.

[0248] In some implementations, the I / O circuit includes a write MUX array coupled to each group of banks and configured to direct P×N data to P×N working banks respectively.

[0249] In some implementations, the write MUX array includes P write sub-arrays applied in series. Each write sub-array includes a redundant write MUX and N main write MUXs.

[0250] In some implementations, each main write MUX and each redundant write MUX includes a first input, a second input, and an output respectively. The redundant write MUX in the p-th write sub-array within the write MUX array further includes p - 1 redundant inputs for 2 ≤ p ≤ P, where p is a positive integer.

[0251] In some implementations, when 1 ≤ p < P, the output of each main write MUX in the p-th write sub-array is coupled to the first input of the corresponding main write MUX in the (p + 1)-th write sub-array. The output of the redundant write MUX in the p-th write sub-array is coupled to the q-th redundant input of the corresponding redundant write MUX in each (p + q)-th write sub-array for 1 ≤ q ≤ P - p, where q is a positive integer. When p = P, the outputs of the N main write MUXs and the redundant write MUXs in the p-th write sub-array are coupled to the N main banks and the redundant banks respectively.

[0252] In some implementations, when p = 1, the first input of each main write MUX in the p-th write sub-array is coupled to the corresponding I / O data line and is configured to receive the corresponding data from the corresponding I / O data line. When 1 ≤ p ≤ P, the second input of each main write MUX in the p-th write sub-array is coupled to the Vdd signal line or the first input of the corresponding adjacent main write MUX in the p-th write sub-array.

[0253] In some implementations, for 1 ≦ p ≦ P, the redundant write MUX in the p-th write sub-array is arranged between the N main write MUXes in the p-th write sub-array. The first input and the second input of the redundant write MUX in the p-th write sub-array are respectively coupled to the first inputs of two adjacent main write MUXes in the p-th write sub-array.

[0254] In some implementations, for 1 ≦ p ≦ P, the redundant write MUX in the p-th write sub-array is arranged beside the N main write MUXes in the p-th write sub-array. One of the first and second inputs of the redundant write MUX in the p-th write sub-array is coupled to the first input of an adjacent main write MUX in the p-th write sub-array. The other of the first and second inputs of the redundant write MUX in the p-th write sub-array is coupled to the Vdd signal line.

[0255] In some implementations, the I / O circuit includes a read MUX array coupled to each group of banks and configured to direct P×N data from P×N working banks respectively.

[0256] In some implementations, the read MUX array includes P read sub-arrays applied in series. Each read sub-array includes N read MUXes. Each read MUX includes a first input, a second input, and an output respectively.

[0257] In some implementations, for 1 ≦ p < P, the output of each read MUX in the p-th read sub-array is coupled to the first input of the corresponding read MUX in the (p + 1)-th read sub-array, where p is a positive integer. For p = P, the output of each read MUX in the p-th read sub-array is coupled to the corresponding I / O data line and is configured to output the corresponding data to the corresponding I / O data line.

[0258] In some implementations, if p=1, a first input of each read MUX in the pth read subarray is coupled to a corresponding main bank in the N main banks. If 1≦p≦P, a second input of each read MUX in the pth read subarray is coupled to a redundant bank or a first input of a corresponding adjacent read MUX in the pth read subarray.

[0259] In some implementations, the K failed main banks are distributed from the P groups of banks to one or more groups of banks.

[0260] In some implementations, the array of memory cells includes a first level memory unit that includes a plurality of second level memory units, one of which includes the P groups of banks, and I / O circuitry and I / O control logic are shared by the plurality of second level memory units.

[0261] In some implementations, the first level memory unit is a die including multiple planes. The second level memory unit including the P groups of banks is a plane within the die, the plane including P×N working banks from the P groups of banks. The I / O circuitry is coupled to the global data bus and configured to direct the P×N data to and from the P×N working banks in the plane via the global data bus and one or more branch data buses, respectively, in the plane.

[0262] In some implementations, N = 4 or 8. The memory device includes a 3D NAND flash memory device.

[0263] According to another aspect of the disclosure, a system includes a memory device configured to store data and a memory controller coupled to the memory device and configured to control the memory device. The memory device includes an array of memory cells, an I / O circuit, and an I / O control logic coupled to the I / O circuit. The array of memory cells includes P groups of banks. Each group of banks includes N main banks and a redundant bank such that P redundant banks are included in and shared by the P groups of banks. P and N are each positive integers. The I / O circuit is coupled to the P groups of banks and configured to direct the P×N data to or from the P×N working banks, respectively. The I / O control logic is configured to determine the P×N working banks from the P groups of banks based on bank failure information indicating K failed main banks from the P groups of banks. The P×N working banks include K redundant banks of the P redundant banks. K is a positive integer less than or equal to P. The I / O control logic is also configured to control the I / O circuit to direct the P×N data to or from the P×N working banks, respectively.

[0264] In some implementations, the system further includes a host coupled to the memory controller and configured to transmit or receive data.

[0265] In some implementations, the I / O circuitry includes a write MUX array coupled to each group of banks and configured to direct the P×N data to the P×N working banks, respectively.

[0266] In some implementations, the write MUX array includes P serially applied write sub-arrays, each of which includes a redundant write MUX and N main write MUXes.

[0267] In some implementations, each main write MUX and each redundant write MUX includes a first input, a second input, and an output, respectively. The redundant write MUX in the p-th write sub-array of the write MUX array further includes p - 1 redundant inputs for 2 ≤ p ≤ P, where p is a positive integer.

[0268] In some implementations, when 1 ≤ p < P, the output of each main write MUX in the p-th write sub-array is coupled to the first input of the corresponding main write MUX in the (p + 1)-th write sub-array. The output of the redundant write MUX in the p-th write sub-array is coupled to the q-th redundant input of the corresponding redundant write MUX in each (p + q)-th write sub-array for 1 ≤ q ≤ Pp, where q is a positive integer. When p = P, the outputs of the N main write MUXes and redundant write MUXes in the p-th write sub-array are coupled to the N main banks and redundant banks, respectively.

[0269] In some implementations, when p = 1, the first input of each main write MUX in the p-th write sub-array is coupled to the corresponding I / O data line and is configured to receive corresponding data from the corresponding I / O data line. When 1 ≤ p ≤ P, the second input of each main write MUX in the p-th write sub-array is coupled to the Vdd signal line or the first input of the corresponding adjacent main write MUX in the p-th write sub-array.

[0270] In some implementations, when 1 ≤ p ≤ P, the redundant write MUX in the p-th write sub-array is disposed between the N main write MUXes in the p-th write sub-array. The first input and the second input of the redundant write MUX in the p-th write sub-array are respectively coupled to the first inputs of two adjacent main write MUXes in the p-th write sub-array.

[0271] In some implementations, when 1 ≦ p ≦ P, the redundant write MUX in the p-th write sub-array is arranged on the side of the N main write MUXs in the p-th write sub-array. One of the first and second inputs of the redundant write MUX in the p-th write sub-array is coupled to the first input of the adjacent main write MUX in the p-th write sub-array. The other of the first and second inputs of the redundant write MUX in the p-th write sub-array is coupled to the Vdd signal line.

[0272] In some implementations, the I / O circuit includes a read MUX array coupled to each group of banks and configured to direct P×N data from P×N working banks respectively.

[0273] In some implementations, the read MUX array includes P read sub-arrays applied in series. Each read sub-array includes N read MUXs. Each read MUX includes a first input, a second input, and an output respectively.

[0274] In some implementations, when 1 ≦ p < P, the output of each read MUX in the p-th read sub-array is coupled to the first input of the corresponding read MUX in the (p + 1)-th read sub-array, where p is a positive integer. When p = P, the output of each read MUX in the p-th read sub-array is coupled to the corresponding I / O data line and is configured to output the corresponding data to the corresponding I / O data line.

[0275] In some implementations, when p = 1, the first input of each read MUX in the p-th read sub-array is coupled to the corresponding main bank in the N main banks. When 1 ≦ p ≦ P, the second input of each read MUX in the p-th read sub-array is coupled to the redundant bank or the first input of the corresponding adjacent read MUX in the p-th read sub-array.

[0276] In some implementations, the K failed main banks are distributed from the P groups of banks to one or more groups of banks.

[0277] In some implementations, the array of memory cells includes a first level memory unit that includes a plurality of second level memory units, one of which includes the P groups of banks, and I / O circuitry and I / O control logic are shared by the plurality of second level memory units.

[0278] In some implementations, the first level memory unit is a die including multiple planes. The second level memory unit including the P groups of banks is a plane within the die, the plane including P×N working banks from the P groups of banks. The I / O circuitry is coupled to the global data bus and configured to direct the P×N data to and from the P×N working banks in the plane via the global data bus and one or more branch data buses, respectively, in the plane.

[0279] In some embodiments, N=4 or 8. The memory device includes a 3D NAND flash memory device.

[0280] According to yet another aspect of the present disclosure, a method of operating a memory device is provided. The memory device includes an array of memory cells. The array of memory cells includes P groups of banks. Each group of banks includes N main banks and redundant banks, such that P redundant banks are included in the P groups of banks, where P and N are each positive integers. P×N working banks are determined from the P groups of banks based on bank failure information indicating K failed main banks from the P groups of banks. The P×N working banks include K redundant banks of the P redundant banks, where K is a positive integer less than or equal to P. The P×N data are respectively directed to or from the P×N working banks.

[0281] In some implementations, bank failure information indicating K failed main banks is obtained.

[0282] In some implementations, P is 2 or greater.

[0283] In some implementations, the K failed main banks are distributed from the P groups of banks to one or more groups of banks.

[0284] In some implementations, each of the P redundant banks is shared by P groups of banks.

[0285] In some implementations, the memory device further includes I / O circuitry. The I / O circuitry includes a write MUX array and a read MUX array respectively coupled to each group of banks. The write MUX array includes P write sub-arrays that are applied in series. The read MUX array includes P read sub-arrays that are applied in series. Directing the P×N data includes directing the P×N data respectively to the P×N working banks via the P write sub-arrays, and directing the P×N data from the P×N working banks respectively via the P read sub-arrays.

[0286] In some implementations, N = 4 or 8. The memory device includes a 3D NAND flash memory device.

[0287] The foregoing description of specific implementations may be readily modified and / or adapted for various applications. Therefore, such adaptations and modifications are intended to be within the meaning and range of equivalents of the disclosed implementations, based on the teaching and guidance presented herein.

[0288] The breadth and scope of the present disclosure should not be limited by any of the above-described exemplary implementations, but should be defined only in accordance with the following claims and their equivalents. [Explanation of symbols]

[0289] 108 Host 106 Memory Controller 104 Memory Devices 302 Peripheral Circuit 301 Memory Cell Array Page 404 Buffer Sense Amplifier 406 Column Decoder / Bit Line Driver 407 I / O circuit 408 Row Decoder / Word Line Driver 410 Voltage Generator 412 I / O Control Logic 413 Control Logic 414 Register 417 Data I / O 506 Main Pre-Decoder 508 Redundant Pre-Decoder 707 Write MUX Array 807 Read MUX Array 1515a Second Level Memory Unit 1514 First Level Memory Unit 1502a Plane Section 1502b Plane Section 1502c Plane Section 1502d Plane Section 1500 Memory Device 1514 First Level Memory Unit 1515a Second Level Memory Unit 1515b Second Level Memory Unit 1510 First Level Data Bus 1511 Junction 1512a bifurcated data bus 1512b bifurcated data bus 1418 Global Data Bus 1401 Junction 1302a plane 1302b plane 1407a Branched Data Bus 1407b Branched Data Bus 1403a Planar branched data bus 1403b Planar branched data bus 1405a~1405g Section branch data bus 1405f Section Branch Data Bus 1720 Write Subarray 1800 Memory Device 1720a 1st write sub-array 1720b Second write sub-array 1880 Main Write MUX 1881 Redundant Write MUX 906 Working Bank Logic 704 Redundant Bank< / j>

Claims

1. An array of memory cells including P groups of banks, wherein each group of banks includes N main banks and M redundant banks, where each of P, N, and M is a positive integer and N is greater than M, the array, and An input / output (I / O) circuit coupled to the P groups of banks and configured to direct P×N data to, or from, P×N working banks, wherein one of the M redundant banks is coupled to at least two of the N main banks via the I / O circuit, the I / O circuit, and I / O control logic coupled to the I / O circuit, the I / O control logic In response to K main banks of the P groups of banks failing, determining the P×N working banks including K redundant banks of the P×M redundant banks, where K is a positive integer less than or equal to P, and A memory device configured to control the I / O circuit to direct P×N data to, or from, the P×N working banks, respectively.

2. The memory device of claim 1, wherein the I / O circuit includes a write multiplexer (MUX) array coupled to each group of banks and configured to direct the P×N data to the P×N working banks, respectively.

3. The memory device of claim 2, wherein the write MUX array includes P write sub-arrays applied in series, M = 1, and each write sub-array includes a redundant write MUX and N main write MUXs.

4. Each main write MUX and each redundant write MUX each include a first input, a second input, and an output, and The redundant write MUX in the p-th write sub-array of the write MUX array further includes p - 1 redundant inputs for 2 ≤ p ≤ P, where p is a positive integer, the memory device of claim 3.

5. When 1 ≤ p < P, The output of each main write MUX in the p-th write sub-array is coupled to the first input of the corresponding main write MUX in the (p + 1)-th write sub-array, an output of the redundant write MUX in the pth write subarray is coupled to a qth redundant input of a corresponding redundant write MUX in each (p+q)th write subarray, where 1≦q≦Pp, and q is a positive integer; If p=P, The memory device of claim 4 , wherein outputs of the N main write MUXes and the redundant write MUXes in the pth write sub-array are coupled to the N main banks and the M redundant banks, respectively.

6. When p=1, a first input of each main write MUX in the p-th write sub-array is coupled to a corresponding I / O data line and configured to receive corresponding data from the corresponding I / O data line; For 1≦p≦P, 5. The memory device of claim 4, wherein a second input of each main write MUX in the pth write sub-array is coupled to a Vdd signal line or to a first input of a corresponding adjacent main write MUX in the pth write sub-array.

7. For 1≦p≦P, the redundant write MUX in the p-th write sub-array is disposed between the N main write MUXs in the p-th write sub-array; 5. The memory device of claim 4, wherein a first input and a second input of the redundant write MUX in the pth write sub-array are respectively coupled to first inputs of two adjacent main write MUXes in the pth write sub-array.

8. For 1≦p≦P, the redundant write MUX in the p-th write sub-array is disposed on a side of the N main write MUXs in the p-th write sub-array; one of the first and second inputs of the redundant write MUX in the pth write subarray is coupled to a first input of an adjacent main write MUX in the pth write subarray; The memory device of claim 4 , wherein the other of the first and second inputs of the redundant write MUX in the pth write sub-array is coupled to a Vdd signal line.

9. 2. The memory device of claim 1, wherein the I / O circuitry includes a read multiplexer (MUX) array coupled to each group of banks and configured to direct P×N data from each of the P×N working banks.

10. The read MUX array includes P read sub-arrays applied in series, each read sub-array includes N read MUXs, and each read MUX includes a first input, a second input, and an output respectively. The memory device according to claim 9.

11. When 1 ≤ p < P, The output of each read MUX in the p-th read sub-array is coupled to the first input of the corresponding read MUX in the (p + 1)-th read sub-array, where p is a positive integer. When p = P, The output of each read MUX in the p-th read sub-array is coupled to the corresponding I / O data line and is configured to output the corresponding data to the corresponding I / O data line. The memory device according to claim 10.

12. When p = 1, The first input of each read MUX in the p-th read sub-array is coupled to the corresponding main bank in the N main banks. When 1 ≤ p ≤ P, The second input of each read MUX in the p-th read sub-array is coupled to the M redundant banks or the first input of the corresponding adjacent read MUX in the p-th read sub-array. The memory device according to claim 11.

13. The K failed main banks are distributed among one or more groups of banks from the P groups of banks. The memory device according to claim 1.

14. The memory device according to claim 1, wherein the memory device includes a three-dimensional (3D) NAND flash memory device.

15. A memory device configured to store data, An array of memory cells including P groups of banks, each group of banks includes N main banks and M redundant banks, where P, N, and M are each positive integers, and N is greater than M. An array, An input / output (I / O) circuit coupled to the P groups of banks and configured to direct P×N data to or from P×N working banks respectively. One of the M redundant banks is coupled to at least two of the N main banks via the I / O circuit. An I / O circuit, and I / O control logic coupled to the I / O circuit. determining, in response to K main banks of the P groups of banks failing, the P×N working banks including K redundant banks of the P×M redundant banks, where K is a positive integer less than or equal to P; and I / O control logic configured to control the I / O circuitry to direct the P×N data to or from each of the P×N working banks. a memory controller coupled to the memory device and configured to control the memory device.

16. The system of claim 15, wherein the I / O circuitry includes a write multiplexer (MUX) array coupled to each group of banks and configured to direct the P×N data to each of the P×N working banks, the write MUX array including P write sub-arrays applied in series, where M=1, and each write sub-array including a redundant write MUX and N main write MUXes.

17. 1. A method of operating a memory device including an array of memory cells, the array of memory cells including P groups of banks, each group of banks including N main banks and M redundant banks, each of P, N, and M being positive integers, N being greater than M, one of the M redundant banks being coupled to at least two of the N main banks, the method comprising: determining P×N working banks including K redundant banks of the P×M redundant banks in response to K main banks of the P groups of banks failing, where K is a positive integer less than or equal to P; and directing said P×N data to or from said P×N working banks, respectively.

18. 20. The method of claim 17, further comprising obtaining bank failure information indicating the K failed main banks, the K failed main banks being distributed across one or more groups of banks from the P groups of banks.

19. 20. The method of claim 17, wherein each of the P x ​​M redundant banks is coupled to at least two main banks of the P groups of banks.

20. the memory device further includes input / output (I / O) circuitry; the I / O circuitry includes a write multiplexer (MUX) array and a read MUX array respectively coupled to each group of banks; the write MUX array includes P write sub-arrays applied in series; the read MUX array includes P read subarrays applied in series; Directing the P×N data items includes: directing the P×N data via the P write sub-arrays to the P×N working banks, respectively; and directing the P×N data from the P×N working banks through the P read subarrays, respectively.

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