Design method and program

The design method discretizes firing times and weights in spiking neural networks, improving power efficiency and learning accuracy by converting mathematical models into circuit models for efficient hardware implementation.

JP7605303B2Active Publication Date: 2024-12-24NEC CORP
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Patent Information

Application Number
JP2023523783
Authority / Receiving Office
JP · JP
Patent Type
Patents
Current Assignee / Owner
Filing Date
2021-05-26
Publication Date
2024-12-24
Estimated Expiration
2041-05-26

AI Technical Summary

Technical Problem

Spiking neural networks face challenges in achieving high learning accuracy when firing times are discretized, leading to reduced power efficiency and increased computational complexity.

Method used

A design method that discretizes the firing times and weights of spiking neurons in a mathematical model, followed by converting it into a circuit model, allowing for efficient hardware implementation while maintaining high learning accuracy.

Benefits of technology

The method enables discretized firing times in spiking neural networks, enhancing power efficiency and learning accuracy without the need for relearning.

✦ Generated by Eureka AI based on patent content.

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Abstract

This design method comprises determining at least one of a firing time increment of a spike generator, the minimum increment of a current value output by a synapse circuit, a firing threshold voltage of the spike generator, the capacitance of a capacitor that simulates a membrane potential, the firing time increment of a mathematical model, and the weighting increment of the mathematical model such that the product of the firing time increment of the mathematical model and the weighting increment of the mathematical model is equal to a value obtained by dividing the product of the firing time increment of the spike generator and the minimum increment of the current value output by the synapse circuit by the product of the firing threshold voltage of the spike generator and the capacitance of the capacitor.
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Description

[Technical field]

[0001] The present invention relates to a design method and program Regarding. [Background technology]

[0002] One type of neural network is the Spiking Neural Network (SNN) (see, for example, Patent Document 1). The Spiking Neural Network is expected to be a highly power-efficient neural network in that it transmits information between spiking neurons using binary signals called spikes. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] International Publication No. 2020 / 241356 Summary of the Invention [Problem to be solved by the invention]

[0004] When implementing spiking neurons in hardware, circuits with discretized firing times are considered to be advantageous in terms of ease of manufacturing and power efficiency. On the other hand, models with discretized firing times generally tend to have low learning accuracy.

[0005] An example of the object of the present invention is to provide a design method and program The purpose of this project is to provide [Means for solving the problem]

[0006] According to a first aspect of the present invention, a design method includes the steps of: A computer calculates a step width of a firing time by a spike generator in a circuit model of a spiking neuron in which the firing time by a spike generator and the output current value of a synapse circuit are discretized, a product of a step width of a firing time in a mathematical model of a spiking neuron in which the firing time and a weight for an input to the spiking neuron model are discretized, a step width of a weight in the mathematical model, and a minimum step width of an output current value of the synapse circuit, by a computer simulating a firing threshold voltage in the spike generator and a membrane potential in the circuit model. calculating a minimum step width of the output current value of the synapse circuit by dividing the product of the step width of the firing time in the mathematical model, the step width of the weight in the mathematical model, and the step width of the firing time by the spike generator by the product of the firing threshold voltage in the spike generator and the capacitance of the capacitor; calculating a minimum step width of the output current value of the synapse circuit by dividing the product of the step width of the firing time in the mathematical model, the step width of the weight in the mathematical model, and the step width of the firing time by the spike generator by the product of the firing threshold voltage in the spike generator and the capacitance of the capacitor; calculating the capacitance of the capacitor by dividing the product of the step width of the firing time by the spike generator and the minimum step width of the output current value of the synapse circuit by the product of the step width of the firing time in the mathematical model, the step width of the weight in the mathematical model and the firing threshold voltage in the spike generator; calculating the weight step size in the mathematical model as a product of the step size of the firing time of the spike generator and the minimum step size of the output current value of the synapse circuit divided by the product of the step size of the firing time of the spike generator and the minimum step size of the output current value of the synapse circuit, the step size of the firing time of the spike generator divided by the product of the step size of the firing time of the mathematical model, the firing threshold voltage of the spike generator and the capacitance of the capacitor;training a spiking neural network using a spiking neuron model in which neither the firing time nor the weight is discretized; and converting the trained spiking neural network using the spiking neuron model in which neither the firing time nor the weight is discretized into a spiking neural network using a mathematical model of spiking neurons in which the firing times and weights are discretized, wherein the spiking neural network using the mathematical model of spiking neurons in which the firing times and weights are discretized is implemented in hardware of a spiking neural network using a circuit model of spiking neurons in which the firing times and current values ​​are discretized.

[0007] According to a second aspect of the present invention, a program is provided that causes a computer to A step width of a firing time by a spike generator in a circuit model of a spiking neuron in which the firing time by a spike generator and the output current value of a synapse circuit are discretized is defined as a product of a step width of a firing time in a mathematical model of a spiking neuron in which the firing time and a weight for an input to the spiking neuron model are discretized, a step width of a weight in the mathematical model, and a minimum step width of an output current value of the synapse circuit, a firing threshold voltage in the spike generator and a capacitance of a capacitor simulating a membrane potential in the circuit model are defined as a step width of a firing time by the spike generator in a circuit model of a spiking neuron in which the firing time and a weight for an input to the spiking neuron model are discretized, a minimum step width of the output current value of the synapse circuit divided by a product of the step width of the firing time in the mathematical model, the step width of the weight in the mathematical model, and the step width of the firing time by the spike generator, the minimum step width of the output current value of the synapse circuit divided by a product of the firing threshold voltage in the spike generator and the capacitance of the capacitor; calculating the capacitance of the capacitor as a value obtained by dividing the product of the step width of the firing time by the spike generator and the minimum step width of the output current value of the synapse circuit by the product of the step width of the firing time in the mathematical model, the step width of the weight in the mathematical model, and the firing threshold voltage in the spike generator; calculating the step width of the firing time in the mathematical model as a value obtained by dividing the product of the step width of the firing time by the spike generator and the minimum step width of the output current value of the synapse circuit by the product of the step width of the firing time in the mathematical model, the step width of the weight in the mathematical model, and the firing threshold voltage in the spike generator; calculating the product of the step size of the firing time of the spike generator and the minimum step size of the output current value of the synapse circuit divided by the product of the step size of the firing time of the spike generator and the minimum step size of the output current value of the synapse circuit, the step size of the firing time of the spike generator divided by the product of the step size of the firing time of the mathematical model, the firing threshold voltage of the spike generator, and the capacitance of the capacitor;The present invention executes the steps of: training a spiking neural network using a spiking neuron model in which neither the firing time nor the weight is discretized; and converting the trained spiking neural network using the spiking neuron model in which neither the firing time nor the weight is discretized into a spiking neural network using a mathematical model of spiking neurons in which the firing times and weights are discretized, so that the spiking neural network using the mathematical model of spiking neurons in which the firing times and weights are discretized is implemented in hardware of a spiking neural network using a circuit model of spiking neurons in which the firing times and current values ​​are discretized. Effect of the Invention

[0008] According to the present invention, it is possible to discretize the firing time, and the learning accuracy is relatively high. [Brief description of the drawings]

[0009] [Figure 1] FIG. 1 is a diagram illustrating an example of a mathematical model of a spiking neuron to be discretized according to an embodiment. [Diagram 2] FIG. 1 is a diagram showing an example of the time evolution of a membrane potential of a spiking neuron according to an embodiment. [Diagram 3] FIG. 1 is a diagram illustrating an example of a circuit model of a spiking neuron according to an embodiment. [Figure 4] FIG. 1 is a diagram illustrating an example of firing times in a spiking neural network according to an embodiment. [Diagram 5] FIG. 1 is a diagram illustrating an example of a processing procedure in a design method according to an embodiment. [Figure 6] 4 is a flowchart illustrating an example of a process in a design method according to the embodiment. [Figure 7] FIG. 1 is a schematic block diagram illustrating a configuration of a computer according to at least one embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0010] The following describes embodiments of the present invention, but the following embodiments do not limit the scope of the invention. Furthermore, not all of the combinations of features described in the embodiments are necessarily essential to the solution of the invention. FIG. 1 is a diagram showing an example of a mathematical model of a spiking neuron to be discretized.

[0011] In a spiking neuron, an internal state called the membrane potential evolves over time in response to spikes. In Figure 1, the membrane potential is v i (l)In Fig. 1, a hierarchical neural network is assumed, and the i-th spiking neuron in the l-th layer is shown. However, the structure of a spiking neural network is not limited to a hierarchical structure. membrane potential v i (l) (t) is the firing threshold V th When it reaches this value, the spiking neuron outputs a spike.

[0012] Figure 2 shows an example of the time evolution of the membrane potential of a spiking neuron. The horizontal axis of the graph in Figure 2 shows time, and the vertical axis shows the membrane potential. In Figure 2, the membrane potential is expressed as v i (l) It is written as follows. The spiking neuron in Figure 2 is activated at time t2. *(l-1) , t1 *(l-1) , t3 *(l-1) Each of these receives a spike input from a spiking neuron in the l-1th layer. After a spike is input, the membrane potential continues to change at a rate that depends on the weighting set for each spiking neuron that outputs the spike. In addition, the rate of change of the membrane potential for each spike input is linearly added.

[0013] time t k *(l) In Fig. 2, the membrane potential of the spiking neuron exceeds the firing threshold V th When the input reaches 1, the spiking neuron fires. The firing causes the membrane potential to become 0, and thereafter the membrane potential does not change even if a spike is received. The time at which a spiking neuron fires is called the firing time, or spike time.

[0014] In the following description, it is assumed that the firing time, the spike output time of the spiking neuron on the spike output side, and the spike input time of the spiking neuron on the spike input side are the same. However, there may be a non-negligible delay between the spike output time of the spiking neuron on the spike output side and the spike input time of the spiking neuron on the spike input side. In that case, the delay time may be shown in the formula.

[0015] Furthermore, the membrane potential after firing is not limited to the above-mentioned one that does not change from the potential 0. For example, after a predetermined time has elapsed since firing, the membrane potential may be changed in response to the input of a spike. The change in membrane potential before firing in a mathematical model of a spiking neuron can be expressed as the differential equation in equation (1).

[0016]

number

[0017] v i (l) (t) denotes the membrane potential of the i-th spiking neuron in the l-th layer at time t. w ij (l) represents the weight for a spike from the jth spiking neuron in the l-1th layer to the ith spiking neuron in the lth layer. θ represents a step function and is expressed as in equation (2).

[0018]

number

[0019] t j *(l-1) denotes the firing time of the j-th spiking neuron in the l-1-th layer. Let us consider implementing the above-mentioned mathematical model of a spiking neuron in hardware. The mathematical model of the spiking neuron to be the target of the design method according to the embodiment is not limited to that shown in formula (1). For example, the design method according to the embodiment can be similarly applied to a general leaky integrate-and-fire neuron.

[0020] Figure 3 shows an example of a circuit model of a spiking neuron. The circuit model here is a circuit that implements the model. In the circuit model of FIG. 3, when a spike due to a pulse signal or a step signal is input to a synapse circuit, the synapse circuit continues to output a weighted current.

[0021] The currents output by the synapse circuits are summed and flow into a capacitor, which generates a potential across the capacitor. This potential across the capacitor simulates the membrane potential. The spike generator compares the potential of the capacitor with a predefined firing threshold, and when the potential of the capacitor reaches the firing threshold, the spike generator outputs a spike.

[0022] A single spike generator may be configured to output a spike only once, or a single spike generator may be configured to fire multiple times by resetting the potential of a capacitor when a spike is generated. The change in membrane potential before firing in a circuit model of a spiking neuron can be expressed as the differential equation in equation (3).

[0023]

number

[0024] C indicates the capacitance of the capacitor. I ij (l)(t) denotes the current value for simulating the change in membrane potential due to a spike from the j-th spiking neuron in the l-1-th layer to the i-th spiking neuron in the l-th layer.

[0025] When the presence or absence of a current is expressed using the step function θ of equation (2), equation (3) is transformed into equation (4).

[0026]

number

[0027] I ij (l) represents the current value when the synapse circuit outputs current. The current is switched on and off by "θ(tt j *(l-1) )" so the current value I ij (l) is treated as a constant whose value can be updated by learning. Therefore, unlike the case of (3), in (4), "I ij (l) " There is no "(t)" added to it.

[0028] Consider discretizing the spike generator firing time and the synapse circuit weights in the configuration of Figure 3. A circuit in which these are discretized is considered to be advantageous in terms of ease of manufacturing and power efficiency. Discretization here is also called quantization.

[0029] On the other hand, in general, models with discretized time tend to have low learning accuracy. It is also thought that the accuracy of learning will be low when learning spiking neurons using a circuit model with discretized time. In the mathematical model of a spiking neuron shown in equation (1), if time is discretized and expressed in time steps, the membrane potential can be expressed as equation (5).

[0030]

number

[0031] In equation (5), time is expressed in time steps, and t takes integer values ​​such as 0, 1, 2, . . . Membrane potential at time t, v i (l) (t) is the membrane potential at time t-1, v i (l) (t-1) is the change per unit time of the time step, Σ j (w ij (l) θ(tt j *(l-1) ))". When the mathematical model shown in equation (5) is implemented in the circuit model shown in FIG. 3, it is expressed as equation (6).

[0032]

number

[0033] In equation (6), the sum of the current values ​​is multiplied by the unit time "1" to get "Σ j (I ij (l) “(t)” indicates the change in charge on the capacitor between time t-1 and time t. When learning is performed using a model in which time is discretized and expressed as time steps, as in equation (6), the accuracy of learning may be reduced.

[0034] In addition, the accuracy of the calculations of the spiking neural network may differ depending on the time width of the unit time in the time step in the undiscretized time. The shorter the time width of the unit time, the higher the accuracy of the calculations.

[0035] On the other hand, when discretizing the firing time in a spike generator to match the time interval of the unit time in the time step, if the time interval of the unit time is shortened, a spike generator with a short firing time interval is required. In this case, therefore, there is a trade-off between the accuracy of the spiking neural network's calculations and the requirements for the spike generator.

[0036] In addition, when discretizing the firing time in a spike generator, if the interval between firing times is constant regardless of the unit time of the time step, shortening the unit time may increase the number of time steps required for calculation. Increasing the number of steps increases the calculation time and power consumption. Therefore, in this case, there is a trade-off between the accuracy of the spiking neural network's calculations and the calculation time and power consumption.

[0037] Figure 4 shows an example of firing times in a spiking neural network. The horizontal axis of the graph in Figure 4 indicates time, which is the elapsed time from the first firing of a spiking neuron in the input layer. The unit of time on the horizontal axis is milliseconds (ms). The vertical axis indicates the identification numbers of the spiking neurons in the input layer, hidden layer, and output layer, respectively.

[0038] In the example in Figure 4, time is expressed in time steps, with the unit time being 2 milliseconds. Six steps after the first firing of the spiking neuron in the input layer, the first firing of the spiking neuron in the output layer occurs.

[0039] Here, we assume that the time-discretized mathematical model is configured with a time step unit time of 2 ms, as shown in Figure 4, and that the time-discretized circuit model is also configured with the step size of the spike generator's firing time set to 2 ms. From this state, consider the case where the unit time of the time step in the mathematical model is set to 1 millisecond.

[0040] In this case, it is possible to replace the spike generator of the circuit model with one that has a firing time interval of 1 millisecond. By replacing the spike generator, the circuit model can obtain calculation results in the same time as the mathematical model. On the other hand, preparing a spike generator with a short firing time interval and replacing the spike generator are burdensome.

[0041] Alternatively, it is possible to use the spike generator of the circuit model with a firing time interval of 2 ms as is, in which case there is no need to prepare a new spike generator or replace the spike generator. On the other hand, if the firing time interval becomes twice the unit time of the time step, the calculation time in the circuit model will be twice as long as that in the mathematical model. Also, if the charge stored in the capacitor exceeds the capacity of the capacitor due to the longer calculation time, it will be necessary to replace the capacitor or the synapse circuit.

[0042] In this way, whether the interval of the spike generator's firing time is adjusted to the unit time in the time step or is kept constant regardless of the unit time, there are advantages and disadvantages depending on the length of the unit time. After learning using a discretized circuit model, if the time width of the unit time is changed, re-learning is required, which places a burden on the person in charge of learning.After learning using a discretized mathematical model, if the time width of the unit time is changed, re-learning is also required, which places a burden on the person in charge of learning.

[0043] Therefore, in the design method according to the embodiment, learning is performed using a non-discretized mathematical model, and then the learned mathematical model is implemented in a circuit model in which the firing times of spike generators and the weights of synaptic circuits are discretized. Fig. 5 is a diagram showing an example of a processing procedure in a design method according to an embodiment. A device such as a computer may automatically or semi-automatically perform the processing in Fig. 5. Alternatively, the processing in Fig. 5 may be performed by a person, such as a designer of a spiking neural network using a computer.

[0044] 5, a device or a person trains a non-discretized model of a spiking neural network (step S11). Model training here refers to adjusting parameter values ​​of the model by machine learning. Next, a device or a person determines parameter values ​​for implementing the learned model in the discretized circuit (step S12). Now, by introducing the parameter β of the scale of the firing threshold into equation (1), we obtain equation (7).

[0045]

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[0046] In equation (7), the parameter β acts as a coefficient that adjusts the rate of change of the membrane potential. By adjusting the value of the parameter β, the weight W ij (l) without having to change the value of i (l) You can adjust how quickly it reaches its firing threshold. The parameter β can be used as a parameter for adjusting the scale of the membrane potential illustrated in Fig. 2. When designing the circuit model, the value of the parameter β can be set according to the firing threshold set in the spike generator.

[0047] For example, the normalized ignition threshold value V th = 1 corresponds to 1 volt (V), whereas if a spike generator is used whose firing threshold is set to 5 volts, the value of parameter β can be set to 5. In the example of Figure 2, the voltage value shown on the vertical axis is scaled by 5 times according to the setting of β=5, so that the weight w ij (l) This allows the voltage values ​​to be consistent with time without having to change the value of to adjust the slope of the graph line.

[0048] For equation (7), the weight W ij(l) and firing time t j *(l-1) By discretizing, we obtain equation (8).

[0049]

number

[0050] W (min) indicates the weight step size. W ij (level,l) is the weight step size W (min) Indicates the integer to be multiplied. W (min) W ij (level,l) Then, the weight W shown in Eq. (7) ij (l) is rounded off by discretization.

[0051] Δt (model) indicates the firing time interval in the mathematical model. t j (step,l-1) is the firing time step size Δt (model) Indicates the integer to be multiplied. t j (step,l-1) t (model) Then, the firing time t j *(l-1) is rounded off by discretization.

[0052] Equation (8) is further subjected to a scale transformation to transform the time scale in the mathematical model into the time scale in the circuit model. This scale transformation is shown in equation (9).

[0053]

number

[0054] In equation (9), the time in the mathematical model is denoted as t, and the time in the circuit model is denoted as t'. Δt (Circuit)indicates the interval of firing times in the circuit model. Δt (model) and Δt (Circuit) By applying equation (9) to the relationship between

[0055]

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[0056] By using equations (9) and (10) to convert the time scale of equation (8) from the time scale in the mathematical model to the time scale in the circuit model, equation (11) is obtained.

[0057]

number

[0058] In equation (11), the right-hand side of "Δt (model) / Δt (Circuit) If we put all the " in front of Σ and then rewrite "t'" as "t", we get equation (12).

[0059]

number

[0060] In addition, for equation (4), the current value I ij (l) (t) and firing time t j *(l-1) By discretizing, we obtain equation (13).

[0061]

number

[0062] I (min) indicates the step size of the current value. I ij (level,l) is the step size of the current value I (min) Indicates the integer to be multiplied. I (min) I ij (level,l) The current value I shown in equation (4) ij (l) (t) is rounded down by discretization.

[0063] Let us consider the conditions for equations (12) and (13) to be equivalent. In equation (13), "(d / dt)v i (l) Substituting equation (12) for “(t)” and expanding and rearranging the individual equations before summing over j, we obtain equation (14).

[0064]

number

[0065] W ij (level,l) and I ij (level,l) are both integers due to discretization, and W ij (level,l) =I ij (level,l) It is. ij (level,l) =I ij (level,l) The condition for equation (14) to hold when takes any integer value is expressed as equation (15).

[0066]

number

[0067] 5, a device or a person determines the value of each parameter so as to satisfy formula (15). For example, a device or a person may determine the parameter value so as to maximize the recognition performance and power efficiency of the spiking neural network under the constraints of formula (15).

[0068] When the specifications of the hardware for implementing the spiking neuron model are determined, a device or a person may input the specifications of the hardware into equation (15) to determine the parameter values ​​for discretizing the mathematical model. For example, consider the case where the hardware specifications are determined as follows.

[0069] Current value interval: I (min) =5[nA] Firing threshold: β=0.5[V] The capacitance of the hidden layer capacitor: C (hidden) =300[fF] Capacitance of the output capacitor: C (output) =300[fF] Firing time step size: Δt (circuit) = 10 [ns]

[0070] In this case, inputting the specification values ​​into equation (15) results in equation (16).

[0071]

number

[0072] The device or person is (model) W (min) =3.33 10 -4 Δt satisfies (model) and W (min) So, in order to maximize the recognition performance and power efficiency of the spiking neural network, we set Δt (model) and W (min) The value of may be determined.

[0073] When the required specifications for the parameter values ​​of the discretization of the mathematical model are determined, the device or a person may input the required specifications into the formula (15) and determine the hardware specifications so as to satisfy the obtained conditions. The parameter values ​​of the discretization of the mathematical model are, for example, Δt (model) and the value of w (min) The hardware specifications are, for example, (min)The value of , the value of , the value of C, and Δt (circuit) The value is If the parameter values ​​shown in equation (15) for both the mathematical model and the circuit model have not been determined, a device or a person may determine the parameter values ​​for discretizing the mathematical model based on the performance required for the spiking neural network, and input the determined parameter values ​​into equation (15) to determine the hardware specifications.

[0074] After step S12 in FIG. 5, a device or a person converts the trained spiking neural network into a mathematical model in which the weights and firing times are discretized (step S13). Specifically, the device or a person converts each of the spiking neuron models included in the trained spiking neural network into a mathematical model in which the weights and firing times are discretized (step S14). (model) and w (min) The spiking neuron models are replaced with discretized models of spiking neurons so that the value of is satisfied. The connections between the spiking neuron models are the same as those in the spiking neural network before conversion.

[0075] Next, the device or the person designs a circuit model of the spiking neural network by converting the mathematical model in which the weights and firing times are discretized into a circuit model in which the current values ​​and firing times are discretized (step S14). Specifically, the device or the person converts each of the spiking neuron models in the mathematical model in which the weights and firing times are discretized into the I (min) ,β,C,and,Δt (circuit) The spiking neuron models are replaced with circuit models of spiking neurons so that the value of is satisfied. The connections between the spiking neuron models are the same as those in the spiking neural network before conversion. After step S14, the person or device ends the process of FIG.

[0076] After the process of Fig. 5, the trained spiking neural network may be implemented in hardware by an apparatus automatically or semi-automatically generating a circuit model of the spiking neural network designed in the process of Fig. 5. Alternatively, a person may use an apparatus to generate a circuit model of the spiking neural network designed in the process of Fig. 5, thereby implementing the trained spiking neural network in hardware.

[0077] As described above, at least one of the increment width of the firing time by the spike generator, the minimum increment width of the output current value of the synapse circuit, the firing threshold voltage of the spike generator, the capacitance of the capacitor, the increment width of the firing time in the mathematical model, or the increment width of the weighting in the mathematical model is determined so that the product of the increment width of the firing time in the mathematical model and the increment width of the weighting in the mathematical model is equal to the product of the product of the increment width of the firing time by the spike generator and the minimum increment width of the output current value of the synapse circuit divided by the product of the firing threshold voltage of the spike generator and the capacitance of the capacitor that simulates the membrane potential.

[0078] Using the parameter values ​​obtained by this design method, a trained spiking neural network in which the firing times and weights are not discretized can be converted into a spiking neural network based on a numerical model in which the firing times and weights are discretized, and further converted into a spiking neural network based on a circuit model in which the current values ​​and weights are discretized. According to this design method, the accuracy of learning is relatively high in that learning can be performed on a spiking neural network whose firing times and weights are not discretized, and the firing times in a trained neural network can be discretized.

[0079] In addition, the step size of the firing time in the mathematical model and the step size of the weight in the mathematical model are determined based on the specifications of the step size of the firing time by the spike generator, the minimum step size of the output current value of the synapse circuit, the firing threshold voltage in the spike generator, and the capacitance of the capacitor.

[0080] According to this design method, when the specifications of the circuit model of a spiking neural network are determined, it is possible to determine design parameter values ​​of the mathematical model of the spiking neural network so as to match the specifications of the circuit model of the spiking neural network.

[0081] In addition, based on the required specifications of the step size of the firing time in the mathematical model and the step size of the weight in the mathematical model, the step size of the firing time by the spike generator, the minimum step size of the output current value of the synapse circuit, the firing threshold voltage in the spike generator, and the capacitance of the capacitor are determined.

[0082] According to this design method, when the required specifications for a spiking neural network based on a mathematical model in which firing times and weights are discretized are determined, it is possible to determine the specifications of the circuit model of the spiking neural network so that it is consistent with the required specifications.

[0083] The design method further includes training a spiking neural network using a spiking neuron model in which neither the firing time nor the weight is discretized. The step size of the firing time in the mathematical model and the step size of the weight in the mathematical model are design values ​​for converting a trained spiking neural network using a spiking neuron model in which neither the firing time nor the weight is discretized into a spiking neural network using a mathematical model of spiking neurons in which the firing time and the weight are discretized. The step size of the firing time by the spike generator, the minimum step size of the output current value of the synapse circuit, the firing threshold voltage in the spike generator, and the capacitance of the capacitor simulating the membrane potential are design values ​​for implementing a spiking neural network using a mathematical model of spiking neurons in which the firing time and the weight are discretized in hardware of a spiking neural network using a circuit model of spiking neurons in which the firing time and the current value are discretized.

[0084] Using the parameter values ​​obtained by this design method, a trained spiking neural network in which the firing times and weights are not discretized can be converted into a spiking neural network based on a numerical model in which the firing times and weights are discretized, and further converted into a spiking neural network based on a circuit model in which the current values ​​and weights are discretized. According to this design method, the accuracy of learning is relatively high in that learning can be performed on a spiking neural network whose firing times and weights are not discretized, and the firing times in a trained neural network can be discretized.

[0085] 6 is a flowchart showing an example of processing in a design method according to an embodiment of the present invention. The design method shown in FIG. 6 includes determining parameter values ​​(step S611). In determining the parameter values ​​(step S611), at least one of the step size of the firing time by the spike generator, the minimum step size of the output current value of the synapse circuit, the firing threshold voltage in the spike generator, the capacitance of the capacitor, the step size of the firing time in the mathematical model, or the step size of the weight in the mathematical model is determined so that the product of the step size of the firing time in the mathematical model and the step size of the weight in the mathematical model is equal to the product of the step size of the firing time by the spike generator and the minimum step size of the output current value of the synapse circuit divided by the product of the firing threshold voltage in the spike generator and the capacitance of the capacitor that simulates the membrane potential.

[0086] Using the parameter values ​​obtained by the design method shown in Figure 6, a trained spiking neural network in which the firing times and weights are not discretized can be converted into a spiking neural network based on a numerical model in which the firing times and weights are discretized, and further converted into a spiking neural network based on a circuit model in which the current values ​​and weights are discretized. According to the design method shown in Figure 6, the accuracy of learning is relatively high in that learning can be performed on a spiking neural network whose firing times and weights are not discretized, and the firing times in a trained neural network can be discretized.

[0087] FIG. 7 is a schematic block diagram illustrating a computer configuration according to at least one embodiment. In the configuration shown in FIG. 7, a computer 700 includes a CPU (Central Processing Unit) 710, a main memory device 720, an auxiliary memory device 730, and an interface 740.

[0088] The computer 700 may execute one or more of the processes in FIG. 5 and FIG. 6, or a part of them. In this case, each of the above-mentioned processes is stored in the auxiliary storage device 730 in the form of a program. The CPU 710 reads the program from the auxiliary storage device 730, loads it in the main storage device 720, and executes the above-mentioned processes according to the program. The CPU 710 also secures a storage area for the above-mentioned processes in the main storage device 720 according to the program. The interface 740 has a communication function, and performs communication according to the control of the CPU 710, thereby executing communication for the above-mentioned processes. The interface 740 has a display device and an input device, and displays various images according to the control of the CPU 710, thereby executing interaction with the user for the above-mentioned processes.

[0089] 5 is executed by the computer 700, each process from steps S11 to S14 is stored in the form of a program in the auxiliary storage device 730. The CPU 710 reads the program from the auxiliary storage device 730, loads it in the main storage device 720, and executes the above-mentioned process in accordance with the program.

[0090] Furthermore, the CPU 710 allocates a storage area for the processing of FIG. 5 in the main storage device 720 in accordance with the program.

[0091] 6 is executed by the computer 700, the process of step S611 is stored in the form of a program in the auxiliary storage device 730. The CPU 710 reads the program from the auxiliary storage device 730, loads it in the main storage device 720, and executes the above process in accordance with the program.

[0092] Furthermore, the CPU 710 allocates a storage area for the processing of FIG. 6 in the main storage device 720 in accordance with the program.

[0093] Note that a program for executing all or part of the processing in Fig. 5 and the processing in Fig. 6 may be recorded on a computer-readable recording medium, and the program recorded on the recording medium may be read into a computer system and executed to perform the processing of each part. Note that the term "computer system" here includes the OS (Operating System) and hardware such as peripheral devices. Furthermore, the term "computer-readable recording medium" refers to portable media such as flexible disks, optical magnetic disks, ROMs (Read Only Memory), and CD-ROMs (Compact Disc Read Only Memory), as well as storage devices such as hard disks built into computer systems. The above-mentioned program may be for realizing part of the above-mentioned functions, or may be capable of realizing the above-mentioned functions in combination with a program already recorded in the computer system.

[0094] Although an embodiment of the present invention has been described in detail above with reference to the drawings, the specific configuration is not limited to this embodiment, and designs that do not deviate from the gist of the present invention are also included. [Industrial Applicability]

[0095] The present invention may be applied to a design method and a recording medium. [Explanation of symbols]

[0096] 700 Computers 710 CPU 720 Main storage 730 Auxiliary storage 740 Interface

Claims

1. A computer comprising: calculating an interval of a firing time by a spike generator in a circuit model of a spiking neuron in which the firing time by a spike generator and the output current value of a synapse circuit are discretized, as a value obtained by dividing a product of an interval of a firing time in a mathematical model of a spiking neuron in which the firing time and a weight for an input to the spiking neuron model are discretized, an interval of a weight in the mathematical model, and a minimum interval of an output current value of the synapse circuit, by a product of an firing threshold voltage in the spike generator and a capacitance of a capacitor simulating a membrane potential in the circuit model; calculating a minimum step size of the output current value of the synapse circuit by dividing a product of a step size of the firing time in the mathematical model, a step size of the weight in the mathematical model, and a step size of the firing time by the spike generator by a product of a firing threshold voltage in the spike generator and a capacitance of the capacitor; calculating a firing threshold voltage in the spike generator as a value obtained by dividing a product of an interval of a firing time by the spike generator and a minimum interval of an output current value of the synapse circuit by a product of an interval of a firing time in the mathematical model, an interval of a weight in the mathematical model, and a capacitance of the capacitor; calculating the capacitance of the capacitor by a value obtained by dividing the product of the step size of the firing time of the spike generator and the minimum step size of the output current value of the synapse circuit by the product of the step size of the firing time in the mathematical model, the step size of the weight in the mathematical model, and the firing threshold voltage in the spike generator; Calculating the interval of the firing time in the mathematical model by dividing the product of the interval of the firing time by the spike generator and the minimum interval of the output current value of the synapse circuit by the product of the interval of the weight in the mathematical model, the firing threshold voltage in the spike generator, and the capacitance of the capacitor; and calculating a step size of the weight in the mathematical model by dividing a product of a step size of the firing time of the spike generator and a minimum step size of the output current value of the synapse circuit by a product of a step size of the firing time in the mathematical model, a firing threshold voltage in the spike generator, and a capacitance of the capacitor; and A spiking neural network is trained using a spiking neuron model in which neither the firing time nor the weights are discretized; Converting the trained spiking neural network using a spiking neuron model in which neither the firing time nor the weight is discretized into a spiking neural network using a mathematical model of spiking neurons in which the firing time and the weight are discretized; Including, The spiking neural network using the mathematical model of spiking neurons in which firing times and weights are discretized is implemented in hardware of a spiking neural network using a circuit model of spiking neurons in which firing times and current values ​​are discretized. Design method.

2. Calculating the step size of the firing time by the spike generator in a circuit model of a spiking neuron in which the firing time by the spike generator and the output current value of a synapse circuit are discretized, as a value obtained by dividing the product of the step size of the firing time in a mathematical model of a spiking neuron in which the firing time and the weight for the input to the spiking neuron model are discretized, the step size of the weight in the mathematical model, and the minimum step size of the output current value of the synapse circuit by the product of the firing threshold voltage in the spike generator and the capacitance of a capacitor simulating a membrane potential in the circuit model; calculating a minimum step size of the output current value of the synapse circuit by dividing a product of a step size of the firing time in the mathematical model, a step size of the weight in the mathematical model, and a step size of the firing time by the spike generator by a product of a firing threshold voltage in the spike generator and a capacitance of the capacitor; calculating a firing threshold voltage in the spike generator as a value obtained by dividing a product of an interval of a firing time by the spike generator and a minimum interval of an output current value of the synapse circuit by a product of an interval of a firing time in the mathematical model, an interval of a weight in the mathematical model, and a capacitance of the capacitor; calculating the capacitance of the capacitor by a value obtained by dividing the product of the step size of the firing time of the spike generator and the minimum step size of the output current value of the synapse circuit by the product of the step size of the firing time in the mathematical model, the step size of the weight in the mathematical model, and the firing threshold voltage in the spike generator; Calculating the interval of the firing time in the mathematical model by dividing the product of the interval of the firing time by the spike generator and the minimum interval of the output current value of the synapse circuit by the product of the interval of the weight in the mathematical model, the firing threshold voltage in the spike generator, and the capacitance of the capacitor; and calculating a step size of the weight in the mathematical model by dividing a product of a step size of the firing time of the spike generator and a minimum step size of the output current value of the synapse circuit by a product of a step size of the firing time in the mathematical model, a firing threshold voltage in the spike generator, and a capacitance of the capacitor; To do at least one of the following: The computer, determining an interval of the firing time in the mathematical model and an interval of the weight in the mathematical model based on the specifications of an interval of the firing time by the spike generator, a minimum interval of the output current value of the synapse circuit, an firing threshold voltage in the spike generator, and a capacitance of the capacitor; The design method of claim 1 , comprising:

3. Calculating the step size of the firing time by the spike generator in a circuit model of a spiking neuron in which the firing time by the spike generator and the output current value of a synapse circuit are discretized, as a value obtained by dividing the product of the step size of the firing time in a mathematical model of a spiking neuron in which the firing time and the weight for the input to the spiking neuron model are discretized, the step size of the weight in the mathematical model, and the minimum step size of the output current value of the synapse circuit by the product of the firing threshold voltage in the spike generator and the capacitance of a capacitor simulating a membrane potential in the circuit model; calculating a minimum step size of the output current value of the synapse circuit by dividing a product of a step size of the firing time in the mathematical model, a step size of the weight in the mathematical model, and a step size of the firing time by the spike generator by a product of a firing threshold voltage in the spike generator and a capacitance of the capacitor; calculating a firing threshold voltage in the spike generator as a value obtained by dividing a product of an interval of a firing time by the spike generator and a minimum interval of an output current value of the synapse circuit by a product of an interval of a firing time in the mathematical model, an interval of a weight in the mathematical model, and a capacitance of the capacitor; calculating the capacitance of the capacitor by a value obtained by dividing the product of the step size of the firing time of the spike generator and the minimum step size of the output current value of the synapse circuit by the product of the step size of the firing time in the mathematical model, the step size of the weight in the mathematical model, and the firing threshold voltage in the spike generator; Calculating the interval of the firing time in the mathematical model by dividing the product of the interval of the firing time by the spike generator and the minimum interval of the output current value of the synapse circuit by the product of the interval of the weight in the mathematical model, the firing threshold voltage in the spike generator, and the capacitance of the capacitor; and calculating a step size of the weight in the mathematical model by dividing a product of a step size of the firing time of the spike generator and a minimum step size of the output current value of the synapse circuit by a product of a step size of the firing time in the mathematical model, a firing threshold voltage in the spike generator, and a capacitance of the capacitor; To do at least one of the following: The computer, determining an interval of the firing time of the spike generator, a minimum interval of the output current value of the synapse circuit, a firing threshold voltage of the spike generator, and a capacitance of the capacitor, based on required specifications of an interval of the firing time in the mathematical model and an interval of the weight in the mathematical model; The design method of claim 1 , comprising:

4. The intervals of the firing times in the mathematical model and the intervals of the weights in the mathematical model are design values ​​for converting the trained spiking neural network using a spiking neuron model in which neither the firing times nor the weights are discretized into a spiking neural network using a mathematical model of spiking neurons in which the firing times and the weights are discretized, the step size of the firing time by the spike generator, the minimum step size of the output current value of the synapse circuit, the firing threshold voltage in the spike generator, and the capacitance of the capacitor simulating the membrane potential are design values ​​for implementing the spiking neural network using a mathematical model of spiking neurons in which the firing times and weights are discretized in hardware of a spiking neural network using a circuit model of spiking neurons in which the firing times and current values ​​are discretized; The design method according to any one of claims 1 to 3.

5. On the computer, calculating an interval of a firing time by a spike generator in a circuit model of a spiking neuron in which the firing time by a spike generator and the output current value of a synapse circuit are discretized, as a value obtained by dividing a product of an interval of a firing time in a mathematical model of a spiking neuron in which the firing time and a weight for an input to the spiking neuron model are discretized, an interval of a weight in the mathematical model, and a minimum interval of an output current value of the synapse circuit, by a product of an firing threshold voltage in the spike generator and a capacitance of a capacitor simulating a membrane potential in the circuit model; calculating a minimum step size of the output current value of the synapse circuit by dividing a product of a step size of the firing time in the mathematical model, a step size of the weight in the mathematical model, and a step size of the firing time by the spike generator by a product of a firing threshold voltage in the spike generator and a capacitance of the capacitor; calculating a firing threshold voltage in the spike generator as a value obtained by dividing a product of an interval of a firing time by the spike generator and a minimum interval of an output current value of the synapse circuit by a product of an interval of a firing time in the mathematical model, an interval of a weight in the mathematical model, and a capacitance of the capacitor; calculating the capacitance of the capacitor by a value obtained by dividing the product of the step size of the firing time of the spike generator and the minimum step size of the output current value of the synapse circuit by the product of the step size of the firing time in the mathematical model, the step size of the weight in the mathematical model, and the firing threshold voltage in the spike generator; Calculating the interval of the firing time in the mathematical model by dividing the product of the interval of the firing time by the spike generator and the minimum interval of the output current value of the synapse circuit by the product of the interval of the weight in the mathematical model, the firing threshold voltage in the spike generator, and the capacitance of the capacitor; and calculating a step size of the weight in the mathematical model by dividing a product of a step size of the firing time of the spike generator and a minimum step size of the output current value of the synapse circuit by a product of a step size of the firing time in the mathematical model, a firing threshold voltage in the spike generator, and a capacitance of the capacitor; and A spiking neural network is trained using a spiking neuron model in which neither the firing time nor the weights are discretized; Converting the trained spiking neural network using a spiking neuron model in which neither the firing time nor the weight is discretized into a spiking neural network using a mathematical model of spiking neurons in which the firing time and the weight are discretized; Run the command, The spiking neural network using the mathematical model of spiking neurons in which firing times and weights are discretized is implemented in hardware of a spiking neural network using a circuit model of spiking neurons in which firing times and current values ​​are discretized. program.

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