Sealing structure for display element and display device

Abstract

The present disclosure provides a sealing structure for a display element and a display device, the sealing structure for a display element including a base substrate, a display element disposed on a surface of the base substrate, and a sealing layer covering the display element, the sealing layer including a second inorganic layer, an organic layer, and a first inorganic layer capable of reducing the amount of trapped charge, which are sequentially stacked along a direction approaching the display element.

Description

[Technical field]

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS This application claims priority from Chinese patent application No. 201821322872.X, filed with the China Patent Office on August 16, 2018, the entire contents of which are incorporated herein by reference.

[0002] The present disclosure relates to the field of sealing technology, and in particular to a sealing structure for a display element and a display device. [Background technology]

[0003] With the continuous development of display technology, the application of display elements is becoming more and more widespread, and in order to extend the service life of display elements, the sealing problem of display elements has attracted more and more attention. Summary of the Invention

[0004] This disclosure provides the following technical solutions:

[0005] In one embodiment, a sealing structure for a display element is provided, the sealing structure for a display element includes a base substrate, a display element disposed on a surface of the base substrate, and a sealing layer covering the display element, the sealing layer including a second inorganic layer, an organic layer, and a first inorganic layer capable of reducing an amount of charge capture, which are sequentially stacked along a direction approaching the display element.

[0006] In one example, the first inorganic layer is a nitrogen oxide layer having an atomic percentage of oxygen greater than 15%.

[0007] In one example, the first inorganic layer has a thickness of less than 1 μm.

[0008] In one example, the organic layer has a thickness in the range of 1 μm to 20 μm.

[0009] In one example, the second inorganic layer has a thickness of less than 1 μm.

[0010] In one example, the sealing layer further includes an organic buffer layer disposed between the first inorganic layer and the organic layer, and the thickness of the organic buffer layer is in the range of 0.1 μm to 0.3 μm.

[0011] In one example, the encapsulation structure further includes a barrier layer, the barrier layer covering the encapsulation layer.

[0012] In one example, the first inorganic layer comprises a silicon oxynitride layer.

[0013] In one example, the organic layer includes an epoxy resin layer.

[0014] In one example, the second inorganic layer includes at least one of a silicon nitride layer, a silicon dioxide layer, a silicon oxynitride layer, and an aluminum oxide layer.

[0015] In one example, the display element includes a thin film transistor array layer disposed on the base substrate, a light-emitting unit disposed on the opposite side of the thin film transistor array layer to the base substrate, and a protective layer covering the light-emitting unit.

[0016] In another embodiment, a display device is provided that includes the above-described encapsulation structure for a display element. [Brief description of the drawings]

[0017] The drawings described herein are used to provide further understanding of the present disclosure and constitute a part of the present disclosure, but the schematic examples and their descriptions are used only to interpret the present disclosure and do not constitute inappropriate limitations on the present disclosure.

[0018] [Figure 1] 1 is a schematic diagram of a sealing structure of a display element according to an embodiment of the present disclosure. [Diagram 2] FIG. 13 is another schematic diagram of a sealing structure of a display element according to an embodiment of the present disclosure. [Diagram 3] FIG. 11 is yet another schematic diagram of a sealing structure of a display element according to an embodiment of the present disclosure. [Figure 4A] 1 is a flowchart for manufacturing an array substrate according to an embodiment of the present disclosure. [Figure 4B] 1 is a flowchart for manufacturing an array substrate according to an embodiment of the present disclosure. [Figure 4C] 1 is a flowchart for manufacturing an array substrate according to an embodiment of the present disclosure. [Figure 4D] 1 is a flowchart for manufacturing an array substrate according to an embodiment of the present disclosure. [Figure 4E] 1 is a flowchart for manufacturing an array substrate according to an embodiment of the present disclosure. [Figure 4F] 1 is a flowchart for manufacturing an array substrate according to an embodiment of the present disclosure. [Figure 4G] 1 is a flowchart for manufacturing an array substrate according to an embodiment of the present disclosure. [Figure 4H] 1 is a flowchart for manufacturing an array substrate according to an embodiment of the present disclosure. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0019] In order to further explain the sealing structure of the display element and the display device according to the embodiments of the present disclosure, a detailed description will be given below in conjunction with the specification drawings.

[0020] In the related art, a thin film encapsulation process is generally used to encapsulate an organic light emitting diode (hereinafter, abbreviated as OLED) display element. This thin film encapsulation process is a process of forming an encapsulation thin film on the surface of an OLED display element, and by using the thin film encapsulation process to encapsulate an OLED display element, not only can a good encapsulation effect be achieved, but the encapsulation layer formed is relatively thin, which is advantageous for making the OLED display element thinner.

[0021] However, in the related art, when thin film encapsulation technology is used to encapsulate a display element, the encapsulation thin film that is in direct contact with the display element has a defect that it has relatively high positive and negative charges, and is prone to trap carriers in the light-emitting units of the OLED display element and become the center of charge trapping, thereby affecting the operating voltage and normal display of the display element.

[0022] The object of the present disclosure is to provide a sealing structure for a display element and a display device to solve the problem in the sealing structure of the related art that the sealing layer is prone to becoming the center of charge capture, thereby affecting the operating voltage and normal display of the display element.

[0023] As shown in Fig. 1, an embodiment of the present disclosure provides an encapsulation structure for a display element. The encapsulation structure for a display element includes a base substrate 1, a display element 19 disposed on a surface of the base substrate 1, and an encapsulation layer 20 covering the display element 19. The encapsulation layer 20 includes a second inorganic layer 203, an organic layer 202, and a first inorganic layer 201 capable of reducing the amount of trapped electric charges, which are sequentially stacked along a direction approaching the display element 19.

[0024] Specifically, the specific manufacturing process of the above encapsulation structure is as follows. A first inorganic layer 201 is formed on the display element 19 by using a plasma enhanced chemical vapor deposition (PECVD) method or an atomic layer deposition (ALD) method. The first inorganic layer 201 has a relatively low charge trapping ability, so that the amount of charge trapped in the display element can be reduced. Then, a polymer monomer deposition method (Vitex) or an ink jet printing method (IJP) is used to form an organic layer 202 on the first inorganic layer 201, or a hybrid organic layer is formed by using PECVD. Finally, a second inorganic layer 203 may be formed on the organic layer 202 by using PECVD or ALD. It should be noted that when the encapsulation layer 20 covering the display element 19 is manufactured by the above method, the first inorganic layer 201, the organic layer 202, and the second inorganic layer 203 formed can all meet the requirement of efficient water and oxygen blocking.

[0025] According to the specific structure and manufacturing process of the above encapsulation structure, in the encapsulation structure for a display element according to the embodiment of the present disclosure, the encapsulation layer 20 covering the display element 19 includes a second inorganic layer 203, an organic layer 202, and a first inorganic layer 201 capable of reducing the amount of trapped charge, which are sequentially stacked along a direction approaching the display element 19. Since the first inorganic layer 201 contacts the display element 19 and can reduce the amount of trapped charge, the encapsulation structure according to this embodiment can better reduce the amount of trapped charge in the display element by the encapsulation layer, and therefore can better ensure the operating voltage and normal display of the display element.

[0026] In the above embodiment, the first inorganic layer 201 may be, for example, a nitrogen oxide layer with an atomic percentage of oxygen element greater than 15%.

[0027] In the related art, silicon nitride is very resistant to the diffusion of impurity elements such as oxygen, sodium, boron, and the like, and water, so that when sealing the display element 19, the inorganic layer in contact with the display element 19 is often made of silicon nitride. However, silicon nitride has silicon dangling bonds, which increase with an increase in nitrogen content, so that the manufactured silicon nitride thin film exhibits very high dielectric constant and tensile stress under certain conditions, and nitrogen-rich (SiNx) thin film has the defect of having very high positive and negative charges, which can become a charge trapping center, making it disadvantageous for direct contact with the display element 19.

[0028] In the above embodiment, the first inorganic layer 201 is a nitrogen oxide layer with an atomic percentage of oxygen element greater than 15%, so that the content of oxygen element in the first inorganic layer 201 is relatively high, and thus the contents of other elements in the first inorganic layer 201 are effectively reduced. Typically, when silicon oxynitride is used to fabricate the first inorganic layer, the atomic percentage of oxygen element in the first inorganic layer is greater than 15%, so that the contents of silicon element and nitrogen element in the first inorganic layer are both reduced, and thus the above defects caused by the relatively high contents of silicon element and nitrogen element are overcome, and the operating voltage and normal display of the display element 19 are better guaranteed.

[0029] Furthermore, in the above embodiment, the thicknesses of the first inorganic layer 201, the organic layer 202 and the second inorganic layer 203 may be set according to actual needs. For example, the thickness of the first inorganic layer 201 may be less than 1 μm. For example, the thickness of the organic layer 202 may be in the range of 1 μm to 20 μm. For example, the thickness of the second inorganic layer 203 may be less than 1 μm.

[0030] In the above embodiment, by making the first inorganic layer 201, the organic layer 202 and the second inorganic layer 203 have the above thicknesses, it is possible to ensure that each layer provides an efficient water and oxygen blocking effect, and it is also possible to limit the thickness of the entire sealing layer 20 to a relatively thin range, which is advantageous in terms of thinning the sealing structure of the display element 19 while ensuring the sealing effect.

[0031] 2, in the above embodiment, the encapsulation layer 20 may further include an organic buffer layer 204 disposed between the first inorganic layer 201 and the organic layer 202. Typically, the thickness of the organic buffer layer 204 is in the range of 0.1 μm to 0.3 μm.

[0032] The organic buffer layer 204 may be deposited by using PECVD. The thickness of the organic buffer layer 204 may be, for example, in the range of 0.1 μm to 0.3 μm. The relatively thin thickness of the organic buffer layer 204 is more advantageous in shortening the deposition time and narrowing the interface difference between the organic layer and the inorganic layer compared to the relatively thick organic layer 202. In addition, the organic buffer layer 204 is deposited by a combination of PECVD and a mask cover having a specific opening, so that the relatively thin organic buffer layer 204 is more advantageous in the subsequent mask cleaning operation.

[0033] It should be noted that when fabricating the organic buffer layer 204, the organic buffer layer 204 can be completed in the same process chamber as the first inorganic layer 201, i.e., the same process flow can be adopted, thereby reducing the time required for substrate transfer and alignment, and the manufacturing process of the first inorganic layer 201 and the manufacturing process of the organic buffer layer 204 are continuous, reducing defects at the interface between the first inorganic layer 201 and the organic layer 202, and obtaining the first inorganic layer 201 and the organic buffer layer 204 with better quality.

[0034] Moreover, the above-mentioned organic buffer layer 204 may be made of various materials. For example, plasma polymerized PP (polypropylene)-hexamethyldisiloxane (HMDSO) may be selected to make the organic buffer layer 204. When the organic buffer layer 204 is solidified, a plasma (e.g., oxygen-containing plasma, fluorine-containing plasma, etc.) is passed through the process chamber to solidify the organic buffer layer 204, so as to realize precise and timely control over the surface properties of the organic buffer layer 204.

[0035] It should be noted that the solidification process of the organic buffer layer 204 may be performed in a PECVD chamber or in a pre-treatment chamber of the IJP process for fabricating the organic layer 202. Considering factors such as the process time interval between the organic layer 202 and the organic buffer layer 204 and the change in contact angle characteristics over time, an appropriate selection may be made according to the equipment status of the production line. If the process time interval is short, the solidification of the organic buffer layer 204 may be performed in a PECVD chamber. If the process time interval is long, the solidification of the organic buffer layer 204 may be performed in a pre-treatment chamber of the IJP process to ensure good contact angle characteristics.

[0036] In addition, in order to better control phenomena such as unevenness and flow of ink edges of the fabricated organic buffer layer 204, plasma solidification with different concentrations may be performed in separate regions when solidifying the organic buffer layer 204. For example, the concentration of plasma passed through the edge region of the organic buffer layer 204 may be lower than the concentration of plasma passed through the central region. Alternatively, when solidifying the organic buffer layer 204, different plasmas may be passed through separate regions, for example, oxygen-containing plasma may be passed through the central region of the organic buffer layer 204 and fluorine-containing plasma may be passed through the edge region.

[0037] Furthermore, in order to better ensure the sealing effect on the display element 19, in the above embodiment, the sealing structure of the display element 19 may further include a barrier layer 21, which covers the sealing layer 20, as shown in FIG.

[0038] Specifically, in order to further improve the sealing effect of the display element 19, after completing the fabrication of the sealing layer 20, a barrier layer 21 may be fabricated on the sealing layer 20 so as to continue to cover the sealing layer 20, thereby better isolating the display element 19 from the outside world and achieving a better sealing effect for the entire display element 19. The barrier layer 21 may be fabricated by adopting a flexible material such as polyethylene terephthalate (PET), polyethylene naphthalate (PEN), etc.

[0039] Furthermore, the above-mentioned first inorganic layer 201, organic layer 202 and second inorganic layer 203 may be made of various materials. The materials used for each layer will be briefly introduced below.

[0040] The first inorganic layer 201 may include a silicon oxynitride layer. Typically, the first inorganic layer 201 may be fabricated using silicon oxynitride.

[0041] The organic layer 202 may include an epoxy resin layer. Typically, the organic layer 202 may be manufactured using an epoxy resin-based organic material. When the organic layer 202 is manufactured using an epoxy resin-based organic material, the organic layer 202 is preferably solidified by heating and irradiating visible light. It should be noted that when manufacturing the encapsulation layer 20, the organic buffer layer 204 does not need to be manufactured, that is, after completing the manufacture of the first inorganic layer 201, the organic layer 202 may be directly manufactured on the first inorganic layer 201 by an inkjet printing process using an epoxy resin-based organic material.

[0042] The second inorganic layer 203 may include at least one of a silicon nitride layer, a silicon dioxide layer, a silicon oxynitride layer, and an aluminum oxide layer. Typically, the second inorganic layer 203 may be fabricated using silicon nitride, silicon dioxide, silicon oxynitride, and / or aluminum oxide materials, and the specific fabrication process may be deposition using PECVD.

[0043] It should be noted that when both the first inorganic layer 201 and the second inorganic layer 203 are made of silicon oxynitride, the first inorganic layer 201 is in contact with the display element 19, so the atomic percentage of oxygen element in the first inorganic layer 201 is, for example, greater than 15%, but the second inorganic layer 203 is relatively far from the display element 19, so the content of oxygen element in the second inorganic layer 203 is not specifically required. For example, in the first inorganic layer 201, the atomic percentage of oxygen element is 18%, the atomic percentage of nitrogen element is 32%, and the atomic percentage of silicon element is 50%. In the second inorganic layer 203, the atomic percentage of oxygen element is 5%, the atomic percentage of nitrogen element is 40%, and the atomic percentage of silicon element is 55%.

[0044] Exemplarily, the thicknesses and materials of the first inorganic layer 201 (TFE1), the organic layer 202 (TFE2), and the second inorganic layer 203 (TFE3) are as shown in Table 1. [Table 1]

[0045] Furthermore, as shown in FIG. 1, in the above embodiment, the display element 19 may specifically include a thin film transistor array layer 191 disposed on a base substrate 1, a light-emitting unit 192 disposed on the opposite side of the thin film transistor array layer 191 to the base substrate 1, and a protective layer (not shown) covering the light-emitting unit 192.

[0046] Specifically, the base substrate 1 may be selected from a glass substrate or a flexible substrate. The thin film transistor array layer 191 disposed on the base substrate 1 includes a thin film transistor array and various control circuits. The light emitting unit 192 may include an anode, R, G, B light emitting layers distributed in an array, and a cathode. The light emitting unit 192 may be manufactured by deposition. The protective layer may also be manufactured by deposition, but is preferably made of an organic material capable of absorbing ultraviolet light. The protective layer is mainly used to reduce plasma damage to the light emitting unit and the effect of ultraviolet light on the light emitting unit during the manufacturing process of the encapsulation layer.

[0047] Fabricating the thin film transistor array layer 191 on the base substrate 1 forms an array substrate. The array substrate may be specifically a low-temperature polysilicon thin film field effect transistor array substrate. In the manufacturing process of such a low-temperature polysilicon thin film field effect transistor array substrate, generally 8 to 9 masking processes are required. Hereinafter, the manufacturing process of the low-temperature polysilicon thin film field effect transistor array substrate will be described with reference to FIG. 4A to FIG. 4H. Note that the low-temperature polysilicon thin film field effect transistors included in the low-temperature polysilicon thin film field effect transistor array substrate are generally formed in a display area, and the display area generally further includes a plurality of data lines and a plurality of gate lines distributed in an array.

[0048] As shown in FIG. 4A, a silicon nitride thin film and a silicon dioxide thin film are sequentially deposited on the entire base substrate 1 by PECVD to form a buffer layer 2 composed of silicon nitride and silicon dioxide. Then, an amorphous silicon thin film is formed on the buffer layer 2 by PECVD or other chemical or physical vapor deposition methods, and the amorphous silicon is crystallized into a polysilicon thin film by laser annealing (ELA) or solid phase crystallization (SPC) methods. Then, a conventional masking process is adopted to form a pattern of a photoresist layer on the polysilicon thin film, and the photoresist layer is used as an etching barrier layer, and the polysilicon thin film not protected by the photoresist layer is etched by plasma to form a polysilicon active layer 4 and a polysilicon storage capacitor 3. A low concentration ion doping is performed on the transistor channel in the polysilicon active layer 4 by an ion implantation process, and a conductive channel required for a thin film transistor is formed in the polysilicon active layer 4.

[0049] As shown in FIG. 4B, a photoresist 5 made of a photosensitive material is formed on the polysilicon active layer 4 by a masking process to protect the polysilicon active layer 4 from ion intrusion. A high-concentration ion implantation process is performed on the polysilicon storage capacitor 3 that is not protected by the photoresist layer, and the polysilicon storage capacitor 3 is converted into a low-resistance doped polysilicon thin film. In the subsequent process steps shown in FIG. 4C to FIG. 4G, a second plate of the capacitor consisting of a gate electrode insulating layer and a gate electrode metal thin film is formed only on the polysilicon storage capacitor 3, so that the photoetching process for forming the second plate of the capacitor, which is the only subsequent photoetching process for the polysilicon storage capacitor 3, is not shown in FIG. 4C to FIG. 4G.

[0050] As shown in FIG. 4C, the photoresist 5 on the polysilicon active layer 4 is removed by a photoresist stripping process, and a silicon dioxide thin film or a composite thin film of silicon dioxide and silicon nitride is deposited by PECVD to form a gate electrode insulating layer 6 on the entire polysilicon storage capacitor 3, the polysilicon active layer 4, and the buffer layer 2. One or more low-resistance metal thin films are deposited on the gate electrode insulating layer 6 by a physical vapor deposition method such as magnetron sputtering, and a gate electrode 7 is formed by a photoetching process. The gate electrode metal thin film may be a single-layer metal thin film such as Al, Cu, Mo, Ti, or an aluminum-neodymium alloy (AlNd), or may be a multi-layer metal thin film such as Mo / Al / Mo or Ti / Al / Ti. The gate electrode 7 is used as an ion implantation barrier layer to perform ion doping on the polysilicon active layer 4, and an electrode contact region of a low impedance source electrode and a drain electrode is formed in the region of the polysilicon active layer 4 not blocked by the gate electrode 7.

[0051] As shown in Figure 4D, a silicon dioxide thin film and a silicon nitride thin film are sequentially deposited by PECVD on the entire surface including the gate electrode 7 to form an interlayer insulating layer 8. The interlayer insulating layer 8 is etched by a masking and etching process to form a source electrode contact hole 15 and a drain electrode contact hole 16.

[0052] As shown in FIG. 4E, a magnetron sputtering technique is used to deposit one or more low-resistance metal thin films on the interlayer insulating layer 8 and the source electrode contact hole 15 and the drain electrode contact hole 16, and a masking and etching process is used to form the source electrode 9 and the drain electrode 10. The source electrode 9 and the drain electrode 10 form ohmic contacts with the polysilicon active layer 4 through the source electrode contact hole 15 and the drain electrode contact hole 16, respectively. Rapid thermal annealing or furnace annealing is used to activate the doped ions in the polysilicon active layer 4 to form an effective conductive channel in the polysilicon active layer 4 under the gate electrode 7. It should be noted that the metal thin films for forming the above source electrode 9 and drain electrode 10 can be single-layer metal thin films such as Al, Cu, Mo, Ti or AlNd, or multi-layer metal thin films such as Mo / Al / Mo or Ti / Al / Ti.

[0053] As shown in Figure 4F, a silicon nitride thin film is deposited by PECVD on the entire surface including the source electrode 9 and the drain electrode 10, and a passivation layer 11 including via holes 17 is formed by a masking and etching process. A hydrogenation process is performed by rapid thermal annealing or furnace annealing to repair defects inside and at the interface of the polysilicon active layer 4. Another masking process is performed to form an organic planarization layer 18 having via holes similar to the via holes 17 on the passivation layer 11, filling the recessed parts of the device surface to form a flat surface.

[0054] As shown in FIG. 4G, a transparent conductive thin film is deposited on the organic planarization layer 18 and the via hole 17 by magnetron sputtering, and the transparent conductive thin film is etched by a photoetching process to form the pixel electrode 12 in the pixel area on the via hole 17 and a part of the organic planarization layer 18. Then, a photosensitive organic material similar to the organic planarization layer 18 is coated on the organic planarization layer 18 and the pixel electrode 12, and a part of the pixel electrode 12 is exposed by a final masking process to form the pixel definition layer 13 shown in FIG. 4H. The pixel definition layer 13 covers the organic planarization layer 18 and a part of the pixel electrode 12. It should be noted that the transparent conductive thin film for forming the pixel electrode 12 may be a single-layer oxide conductive thin film such as indium tin oxide (ITO) or indium zinc oxide (IZO), or may be a composite thin film such as ITO / Ag / ITO or IZO / Ag.

[0055] As can be seen from the manufacturing process of FIGS. 4A to 4H, the low temperature polysilicon thin film field effect transistor array substrate shown in FIG. 4H can be formed through at least eight to nine photo-etching processes.

[0056] Another embodiment of the present disclosure further provides a display device including the sealing structure for a display element according to the above embodiment.

[0057] The sealing structure of the display element of the above embodiment can better reduce the impact of charge trapping on the display element and better ensure the operating voltage and normal display of the display element, so when the display device of this embodiment includes the above-mentioned sealing structure of the display element, it also has the above-mentioned effects.

[0058] Unless otherwise defined, technical or scientific terms used in this disclosure should have their ordinary meaning as understood by a person of ordinary skill in the art to which this disclosure belongs. The terms "first", "second" and similar terms used in this disclosure do not denote any order, quantity or importance, but are merely used to distinguish different components. Similar terms such as "comprise" or "include" mean that the part or item appearing after the term includes the listed parts or items appearing before the term and their equivalents, but do not exclude other parts or items. Similar terms such as "connected" or "connected to each other" are not necessarily limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Top", "bottom", "left", "right", etc. are used only to indicate relative positional relationships, and when the absolute position of the objects being described is changed, the relative positional relationships may be changed accordingly.

[0059] It will be understood that when a component, such as a layer, film, region, or substrate is referred to as being "on" or "under" another component, the component may be "directly on" or "directly below" the other component, or there may be intermediate components.

[0060] In the description of specific embodiments above, the specific features, structures, materials, or characteristics can be combined in any suitable manner in any one or more embodiments or examples.

[0061] The above are merely specific embodiments of the present disclosure, and the scope of protection of the present disclosure is not limited thereto. Anyone with ordinary knowledge in the art can easily think of changes or replacements within the technical scope disclosed in the present disclosure, and all of these changes or replacements should be included in the scope of protection of the present disclosure. Therefore, the scope of protection of the present disclosure should be based on the scope of protection of the attached claims.

Claims

1. A sealing structure for a display element, A display device comprising: a base substrate; a display element disposed on a surface of the base substrate; and a sealing layer covering the display element; the sealing layer includes a second inorganic layer, an organic layer, and a first inorganic layer capable of reducing an amount of trapped electric charges, which are sequentially stacked along a direction approaching the display element; the first inorganic layer is in contact with the display element; the first inorganic layer is a nitrogen oxide layer having an atomic percentage of oxygen greater than 18%; The sealing layer further includes an organic buffer layer disposed between the first inorganic layer and the organic layer, The organic buffer layer has a thickness in the range of 0.1 μm to 0.3 μm.

2. The sealing structure for a display element according to claim 1 , wherein the thickness of the first inorganic layer is less than 1 μm.

3. 3. The sealing structure for a display element according to claim 1, wherein the organic layer has a thickness in the range of 1 [mu]m to 20 [mu]m.

4. The sealing structure for a display element according to claim 1 , wherein the second inorganic layer has a thickness of less than 1 μm.

5. The sealing structure for a display element according to claim 1 , further comprising a barrier layer, the barrier layer covering the sealing layer.

6. The sealing structure for a display element according to claim 1 , wherein the first inorganic layer includes a silicon oxynitride layer.

7. The sealing structure for a display element according to claim 1 , wherein the organic layer includes an epoxy resin layer.

8. The sealing structure for a display element according to claim 1 , wherein the second inorganic layer includes at least one of a silicon nitride layer, a silicon dioxide layer, a silicon oxynitride layer, and an aluminum oxide layer.

9. The display element comprises: a thin film transistor array layer disposed on the base substrate; a light-emitting unit disposed on the opposite side of the thin film transistor array layer from the base substrate; a protective layer covering the light-emitting unit; The sealing structure for a display element according to claim 1 , comprising:

10. A display device comprising the sealing structure for a display element according to claim 1 .

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