Integrating MRAM into MOL for high speed 1T1M cells

Abstract

A memory cell is provided in which a bottom electrode of a magnetoresistive random access memory (MRAM) device is connected to one of the source / drain contact structures of a transistor, and a bottom contact structure is connected to the other of the source / drain contact structure of the transistor. In this application, the MRAM device and the bottom contact structure reside in the middle of the line (MOL) rather than the back end of the line (BEOL). Furthermore, the bottom electrode of the MRAM device and the lower portion of the bottom contact structure reside within the same dielectric material (i.e., the MOL dielectric material).

Description

[Technical field]

[0001] The present invention relates to a memory cell, and more particularly to a memory cell including one transistor (1T) and one magnetoresistive random access memory (MRAM) device, and a method for manufacturing such a cell. [Background technology]

[0002] MRAM is a non-volatile random access memory technology that stores data by means of magnetic memory elements. These elements are typically formed of two ferromagnetic plates, each capable of retaining magnetization, separated by a thin dielectric layer (i.e., tunnel barrier). One of the two plates is permanently magnetized with a fixed polarity (i.e., magnetic reference layer), while the magnetization of the other plate can change with an external magnetic field to store memory (i.e., magnetic free layer). Such a configuration is called a magnetic tunnel junction (MTJ) pillar.

[0003] In state-of-the-art or neuromorphic computing systems, MRAM devices are embedded in the back-end-of-line (BEOL), which sits above the front-end-of-line (FEOL) that contains one or more transistors. The interconnect resistance from the MRAM devices embedded in the BEOL to the transistors present in the FEOL is high. High interconnect resistance is detrimental to memory speed.

[0004] Therefore, there is a need for MRAM devices to provide memory cells connected to transistors with low wiring resistance. Summary of the Invention

[0005] A memory cell is provided in which a bottom electrode of the MRAM device is connected to one of the source / drain contact structures of the transistor and a bottom contact structure is connected to the other of the source / drain contact structure of the transistor. In an embodiment of the present invention, the MRAM device and the bottom contact structure are in the middle of the line (MOL) rather than in the BEOL as in typical prior art structures. Furthermore, the bottom electrode of the MRAM device and the lower portion of the bottom contact structure are in the same dielectric material (i.e., the MOL dielectric material).

[0006] In one aspect of the invention, a memory cell having low interconnect resistance is provided. In one aspect of the invention, the memory cell includes a FEOL level including a gate structure spanning a semiconductor fin, with source / drain structures disposed on either side of the gate structure and a source / drain contact structure disposed on each source / drain structure. A MOL level is located above the FEOL level and includes an MRAM device and a bottom contact structure, with a bottom electrode of the MRAM device contacting one of the source / drain contact structures located on one side of the gate structure and the bottom contact structure contacting the other of the source / drain contact structures located on the other side of the gate structure. A BEOL level is located above the MOL level and includes a first top contact structure contacting a surface of the bottom contact structure and a second top contact structure contacting a surface of a top electrode of the MRAM device.

[0007] In another aspect of the invention, a method for forming a memory cell having low interconnect resistance is provided. In one embodiment, the method includes forming a FEOL level including a gate structure spanning a semiconductor fin, with source / drain structures disposed on either side of the gate structure and a source / drain contact structure disposed on each source / drain structure. A dielectric material layer of a MOL level is then formed above the FEOL level. A bottom electrode of the MRAM device is then formed in the dielectric material layer and contacts one of the source / drain contact structures located on one side of the gate structure. A magnetic tunnel junction (MTJ) pillar and a top electrode of the MRAM device are then formed above the bottom electrode. A bottom contact structure is then formed contacting the other of the source / drain contact structures located on the other side of the gate structure, with a bottom portion of the bottom contact structure being recessed in the dielectric material layer. A back-end-of-line (BEOL) level is then formed above the MOL level, including a first top contact structure contacting a surface of the bottom contact structure and a second top contact structure contacting a surface of the top electrode of the MRAM device. [Brief description of the drawings]

[0008] [Figure 1A] FIG. 2 illustrates various cross sections described herein, where XX is a cross section along the length of the semiconductor fins and YY is a cross section perpendicular to and between adjacent pairs of semiconductor fins and within one of the source / drain regions. [Figure 1B] FIG. 2 is a cross-sectional view taken along line XX of an exemplary structure that may be used in one embodiment of the present invention, the exemplary structure including a plurality of semiconductor fins extending upward from a surface of a substrate, a plurality of gate structures oriented perpendicular to and spanning a portion of each semiconductor fin, a source / drain structure located adjacent each gate structure, and a source / drain contact structure on each source / drain structure. [Figure 1C] FIG. 1C is a cross-sectional view of the exemplary structure shown in FIG. [Figure 2A]FIG. 2 is a cross-sectional view along line XX of the exemplary structure of FIG. 1B after forming a bottom electrode contacting one of the source / drain contact structures of a first gate structure of the plurality of gate structures, the bottom electrode being embedded in a dielectric material layer. [Figure 2B] FIG. 2B is a cross-sectional view of the exemplary structure shown in FIG. 2A. [Figure 3A] XX cross-sectional view of the example structure of FIG. 2A after forming a multi-layer magnetic tunnel junction (MTJ) material stack on the dielectric material layer and the buried bottom electrode, and forming a top electrode layer on the MTJ material stack. [Figure 3B] FIG. 3B is a cross-sectional view of the exemplary structure shown in FIG. 3A. [Figure 4A] XX cross-sectional view of the example structure of FIG. 3A after patterning the top electrode layer and the MTJ material stack to provide a top electrode and an MTJ pillar, respectively, on at least the buried bottom electrode. [Figure 4B] FIG. 4B is a cross-sectional view of the exemplary structure shown in FIG. 4A. [Figure 5A] XX cross-sectional view of the example structure of FIG. 4A after forming a dielectric material spacer laterally adjacent to the MTJ pillar and the top electrode. [Figure 5B] FIG. 5B is a cross-sectional view of the exemplary structure shown in FIG. 5A. [Figure 6A] XX cross-sectional view of the example structure of FIG. 5A after forming an organic planarization layer (OPL) with contact openings that physically expose the other surfaces of the source / drain contact structures of the first gate structure. [Figure 6B] FIG. 6B is a cross-sectional view of the exemplary structure shown in FIG. 6A. [Figure 7A] FIG. XX is a cross-sectional view of the example structure of FIG. 6A after removing the OPL. [Figure 7B] FIG. 7B is a cross-sectional view of the exemplary structure shown in FIG. 7A. [Figure 8A] XX cross-sectional view of the exemplary structure of FIG. 7A after forming a conductive metal-containing layer and a contact metal-containing layer. [Figure 8B]FIG. 8B is a YY cross-sectional view of the exemplary structure shown in FIG. 8A. [Figure 9A] 8B is a cross-sectional view of the example structure of FIG. 8A taken along line XX after recessing both the contact metal-containing layer and the conductive metal-containing layer. [Figure 9B] FIG. 9B is a YY cross-sectional view of the exemplary structure shown in FIG. 9A. [Figure 10A] FIG. 9B is a cross-sectional view taken along line XX of the example structure of FIG. 9A after forming a hard mask cap on the recessed contact metal-containing layer and the recessed conductive metal-containing layer. [Figure 10B] FIG. 10B is a YY cross-sectional view of the exemplary structure shown in FIG. 10A. [Figure 11A] FIG. 10B is a cross-sectional view of the example structure of FIG. 10A after forming another OPL, followed by patterning another OPL, a hardmask, a recessed contact metal-containing layer, and a recessed conductive metal-containing layer present in the source / drain regions. [Figure 11B] FIG. 11B is a YY cross-sectional view of the exemplary structure shown in FIG. [Figure 12A] FIG. 11B is a cross-sectional view of the exemplary structure of FIG. 11A taken along line XX after removing another OPL. [Figure 12B] FIG. 12B is a YY cross-sectional view of the exemplary structure shown in FIG. 12A. [Figure 13A] 12B is a cross-sectional view of the example structure of FIG. 12A taken along line XX after forming a low-k dielectric constant fill material and planarizing the low-k dielectric constant fill material. [Figure 13B] FIG. 13B is a YY cross-sectional view of the exemplary structure shown in FIG. 13A. [Figure 14A] XX cross-sectional view of the example structure of FIG. 13A after forming a BEOL dielectric material layer having an upper contact structure formed therein. [Figure 14B] FIG. 14B is a cross-sectional view of the exemplary structure shown in FIG. 14A. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0009] Embodiments of the present invention will now be described in more detail with reference to the following discussion and drawings, in which it is noted that the drawings are provided for illustrative purposes only and, as such, are not drawn to scale, and that like and corresponding elements are referred to by like reference numerals.

[0010] In the following description, numerous specific details are set forth, such as particular structures, components, materials, dimensions, processing steps and techniques, to provide an understanding of various embodiments of the present invention. However, those skilled in the art will understand that various embodiments of the present invention may be practiced without these specific details. In other instances, well-known structures or processing steps have not been described in detail to avoid obscuring the present invention.

[0011] When an element, as a layer, region, or substrate, is referred to as being "on" or "above" another element, it will be understood that it may be directly on the other element, or that intervening elements may also be present. In contrast, when an element is referred to as being "directly on" or "directly above" another element, there are no intervening elements present. Also, when an element is referred to as being "below" or "below" another element, it will be understood that it may be directly below the other element, or that intervening elements may be present. In contrast, when an element is referred to as being "directly below" or "directly below" another element, there are no intervening elements present.

[0012] One solution to the problems mentioned in the background section is to move the MRAM device to a MOL located between the FEOL and the BEOL. Such a solution is not easy to implement and creates different problems than those mentioned above. For example, the ion beam etching used to form the MTJ pillars of the MRAM device can damage the gate structure or the source / drain contact structure or both. Also, a thick FEOL dielectric material is typically required, which significantly increases the height of the source / drain contact structure, which in turn results in undesirably high source / drain contact resistance. An embodiment of the present invention provides a memory cell in which a bottom electrode of the MRAM device is connected to one of the source / drain contact structures of the transistor and a bottom contact structure is connected to the other of the source / drain contact structures of the transistor. In the memory cell of the present invention, the MRAM device and the bottom contact structure are both in the MOL. Also, in the memory cell of the present invention, the bottom electrode of the MRAM device and the lower portion of the bottom contact structure are in the same dielectric material (i.e., the MOL dielectric material).

[0013] Before describing the invention in detail, reference is first made to FIG. 1A, which illustrates various cross sections that will now be described. In FIG. 1A, element 16 refers to the gate structures, element 12 refers to the semiconductor fins, and element 26 refers to the source / drain contact structures. As shown, the gate structures 16 are oriented perpendicular to the semiconductor fins 12. Also, for a central gate structure 16, source / drain contact structures 26 are disposed on either side of the gate structure 16. In FIG. 1A, XX is a cross section along the length of one of the semiconductor fins 12, and YY is a cross section perpendicular to and between adjacent pairs of semiconductor fins and within one of the source / drain regions. As known to those skilled in the art, a first source / drain region is located on one side of the gate structure (i.e., the first side) and a second source / drain region is located on the other side of the gate structure (i.e., the second side), the first side being opposite the second side.

[0014] 1B-1C, an exemplary structure that may be used in accordance with an embodiment of the present invention is shown. The exemplary structure shown in FIG. 1B-1C resides in a FEOL and includes a plurality of semiconductor fins 12 extending upward from a surface of a substrate 10, a plurality of gate structures 16 oriented perpendicular to and spanning a portion of each semiconductor fin 12, a source / drain structure 24 located adjacent each gate structure 16, and a source / drain contact structure 26 on each source / drain structure 24.

[0015] As shown in Figure 1B, a gate cap 20 may be present on each gate structure 16, and gate spacers 18 may be present on the sidewalls of each gate structure 16 and, if present, each gate cap 20. As shown in Figure 1C, in some embodiments of the invention, source / drain structures 24 located between each gate structure 16 may be merged. Also, as shown in Figure 1C, a trench isolation structure 14 may be present laterally adjacent each semiconductor fin 12, and a FEOL dielectric material 22 may be laterally adjacent the merged source / drain structures 24 and source / drain contact structures 26 in the illustrated embodiment.

[0016] The exemplary structures shown in Figures 1B-1C can be formed utilizing processes known to those skilled in the art. For example, a gate-first process or a gate-last process can be used to form the exemplary structures shown in Figures 1B-1C. Details regarding the processes used to form the exemplary structures shown in Figures 1B-1C are not presented so as to not obscure the method of the present invention.

[0017] In some embodiments of the present invention, the substrate 10 may be composed of a semiconductor material having semiconducting properties. Exemplary semiconductor materials that may be used as the substrate 10 include, but are not limited to, silicon (Si), germanium (Ge), silicon germanium alloy (SiGe), silicon carbide (SiC), silicon germanium carbide (SiGeC), III-V compound semiconductors, or II-VI compound semiconductors. III-V compound semiconductors are materials that include at least one element from group III of the periodic table of elements and at least one element from group V of the periodic table of elements, and II-VI compound semiconductors are materials that include at least one element from group III of the periodic table of elements and at least one element from group VI of the periodic table of elements.

[0018] In other embodiments of the present invention, substrate 10 may be comprised of an insulator such as, for example, silicon dioxide or boron nitride, In such embodiments, a handle substrate (not shown) may be disposed below the insulator that provides substrate 10.

[0019] The semiconductor fin 12 is composed of a semiconductor material similar to that defined above for the substrate 10. In some embodiments, the semiconductor fin 12 is composed of a semiconductor material that is compositionally the same as the substrate 10. In other embodiments, the semiconductor fin 12 is composed of a semiconductor material that is compositionally different than the substrate 10.

[0020] As used herein, a "semiconductor fin" refers to a semiconductor material that includes a pair of vertical sidewalls that are parallel to one another. As used herein, a surface is "vertical" if a vertical plane exists from which the surface does not deviate by more than three times the square root of the surface's root mean square roughness. In one embodiment, each semiconductor fin 12 has a height of 20 nm to 200 nm, a width of 5 nm to 30 nm, and a length of 20 nm to 50 μm. Other heights or widths or lengths, or combinations thereof, below or above the ranges stated herein can also be used in the present invention. Each semiconductor fin 12 is spaced apart from its nearest neighboring semiconductor fin 12 by a pitch of 20 nm to 100 nm, the pitch being measured from a point on one semiconductor fin to exactly the same point on the adjacent semiconductor fin. Also, each semiconductor fin 12 is oriented parallel to one another. An opening or gap exists between each of a pair of adjacent semiconductor fins 12.

[0021] The semiconductor fin 12 can be formed by patterning an upper semiconductor material portion of a base semiconductor substrate. Such patterning can include, for example, lithography and etching or a sidewall image transfer (SIT) process. The base semiconductor substrate can be a bulk semiconductor substrate (i.e., a substrate entirely composed of at least one semiconductor material) or a Semiconductor On Insulator (SOI) substrate composed of an upper semiconductor material layer, an insulator material, and a handle substrate. When an SOI substrate is used as the base semiconductor substrate, the upper semiconductor material layer is patterned to provide a semiconductor fin 12 extending upward from the insulator material of the SOI substrate.

[0022] The trench isolation structures 14 may be comprised of a trench dielectric material, such as, for example, silicon dioxide. The trench isolation structures 14 may be formed by depositing a trench dielectric material in the gaps present between each of the semiconductor fins 12 and then performing an etch-back process on the deposited trench dielectric material. In some embodiments, the formation of the trench isolation structures 14 may be omitted.

[0023] Each gate structure 16 includes a gate dielectric material layer, not shown, and a gate conductor layer, also not shown. Each gate structure 16 forms a component of a transistor. In some embodiments, the gate dielectric material layer is disposed entirely below the gate conductor layer. In other embodiments, the gate dielectric material layer is present on the sidewalls and bottom wall of the gate conductor layer.

[0024] The gate dielectric material layer may be comprised of a gate dielectric material such as, for example, an oxide, a nitride, or an oxynitride, or a combination thereof. In one example, the gate dielectric material providing the gate dielectric material layer may be a high-k material having a dielectric constant greater than 4.0. All dielectric constants are measured in vacuum unless otherwise stated. Exemplary high-k dielectrics include HfO2, ZrO2, La2O3, Al2O3, TiO2, SrTiO3, LaAlO3, Y2O3, HfO x N y , ZrO x N y , LaO x N y , AlO x N y , TiO x N y , SrTiO x N y , LaAlO x N y , Y2O x N y , SiON, SiN xExamples of suitable gate dielectric materials include, but are not limited to, SiO 2 , their silicates, and their alloys. Each value of x is independently between 0.5 and 3, and each value of y is independently between 0 and 2. In some embodiments, a multi-layer gate dielectric structure including different gate dielectric materials, such as silicon dioxide and a high-k gate dielectric, can be formed and used as the gate dielectric material layer. The gate dielectric material layer can be formed by any deposition process including, for example, chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), physical vapor deposition (PVD), sputtering, or atomic layer deposition (ALD). In one embodiment of the present invention, the gate dielectric material providing the gate dielectric material layer can have a thickness in the range of 1 nm to 10 nm. Other thicknesses below or above the aforementioned thickness ranges can also be used for the gate dielectric material layer.

[0025] The gate conductor layer can be composed of a gate conductor material. Examples of gate conductor materials used in providing the gate conductor layer include doped polysilicon, elemental metals (e.g., tungsten, titanium, tantalum, aluminum, nickel, ruthenium, palladium, and platinum), alloys of at least two elemental metals, elemental metal nitrides (e.g., tungsten nitride, aluminum nitride, and titanium nitride), metal silicides (e.g., tungsten silicide, nickel silicide, and titanium silicide), or combinations of multilayer structures thereof. The gate conductor layer can be formed by any deposition process, including, for example, CVD, PECVD, PVD, sputtering, or ALD. The gate conductor layer can have a thickness of 25 nm to 150 nm, although other thicknesses are possible and can be used as the thickness of the gate conductor layer.

[0026] When present, the gate cap 20 is comprised of a cap gate material such as, for example, silicon dioxide, silicon nitride, or silicon oxynitride. The gate cap 20 may be formed utilizing a deposition process such as, for example, CVD, PECVD, PVD, sputtering, or ALD. The gate cap 20 may have a thickness between 10 nm and 50 nm, although other thicknesses are possible and may be used as the gate cap 20 thickness.

[0027] The gate spacers 18 may be comprised of a gate spacer dielectric material such as, for example, silicon dioxide, silicon nitride, silicon oxynitride, etc. The gate spacers 18 may be comprised of a gate spacer material that is the same or different in composition as the gate cap material that provides the gate cap 20. The gate spacers 18 may be formed by a deposition process followed by a spacer etch.

[0028] The FEOL dielectric material 22 may be comprised of any dielectric material, such as, for example, silicon dioxide, undoped silicate glass (USG), fluorosilicate glass (FSG), borophosphosilicate glass (BPSG), a spin-on low-k dielectric layer, a chemical vapor deposition (CVD) low-k dielectric layer, or any combination thereof. As used herein, the term "low-k" refers to a dielectric material having a dielectric constant less than 4.0. In another embodiment, the FEOL dielectric material 22 may be a self-planarizing material, such as spin-on glass (SOG), or a spin-on low-k dielectric material, such as SiLK™. The FEOL dielectric material 22 may be formed utilizing a deposition process, including, for example, CVD, PECVD, evaporation, or spin-on coating.

[0029] Source / drain structures 24 are epitaxially grown from the exposed surfaces of semiconductor fin 12 and are comprised of semiconductor materials and dopants as defined above. The semiconductor material providing source / drain structures 24 may be compositionally the same as or different from the semiconductor material providing semiconductor fin 12. Source / drain structures 24 may have at least one facet.

[0030] The dopants present in the source / drain structures 24 may be either p-type or n-type dopants. The term "p-type" refers to the addition of an impurity to an intrinsic semiconductor that creates a deficiency of valence electrons. In silicon-containing semiconductor materials, examples of p-type dopants, or impurities, include, but are not limited to, boron, aluminum, gallium, and indium. "N-type" refers to the addition of an impurity to an intrinsic semiconductor that contributes free electrons. In silicon-containing semiconductor materials, examples of n-type dopants, or impurities, include, but are not limited to, antimony, arsenic, and phosphorus. In one embodiment of the present invention, the concentration of n-type or p-type dopants in the source / drain structures 24 is greater than 1×10 18 atoms / cm 3 From 1×10 21 atoms / cm 3 can range up to 1×10 21 atoms / cm 3 or 1×10 18 atoms / cm 3 Dopant concentrations below are also envisioned.

[0031] The source / drain contact structures 26 are typically comprised of a metal silicide, such as, for example, tungsten silicide, nickel silicide, or platinum silicide. The metal silicide may be formed utilizing a conventional metal semiconductor alloy formation process. The source / drain contact structures 26 may have a top surface that is coplanar with the top surface of the FEOL dielectric material 22. In addition to a metal silicide, the source / drain contact structures 26 may be comprised of a contact metal or a contact metal alloy. The contact metal may include copper, aluminum, tungsten, or cobalt. The contact metal or contact metal alloy that provides the source / drain contact structures 26 may be formed by a deposition process, such as, for example, CVD, PECVD, PVD, sputtering, or plating.

[0032] 2A-2B, the exemplary structure of FIGS. 1B-1C is shown after formation of a bottom electrode 30 contacting one of the source / drain contact structures 26 of a first gate structure of the plurality of gate structures 16 (i.e., the central gate structure shown in FIG. 2A), the bottom electrode 30 being embedded in a dielectric material layer 28. Although the formation of a single bottom electrode 30 is described and illustrated herein, multiple bottom electrodes 30 may be formed, each of which contacts one of the source / drain contact structures of a particular gate structure 16.

[0033] Dielectric material layer 28 is comprised of a MOL dielectric material, such as, for example, silicon dioxide, undoped silicate glass (USG), fluorosilicate glass (FSG), borophosphosilicate glass (BPSG), a spin-on low-k dielectric layer, a chemical vapor deposition (CVD) low-k dielectric layer, or any combination thereof, as defined above. In another embodiment, a self-planarizing material, such as spin-on glass (SOG), or a spin-on low-k dielectric material, such as SiLK™, can be used as the MOL dielectric material. Using a self-planarizing dielectric material as dielectric material layer 28 can eliminate the need to perform a subsequent planarization step. In an embodiment, dielectric material layer 28 can be formed utilizing a deposition process, including, for example, CVD, PECVD, evaporation, or spin-on coating. In some embodiments, deposition of dielectric material layer 28 is followed by a planarization process (e.g., chemical mechanical polishing (CMP) or grinding) and / or an etch-back process. Dielectric material layer 28 can be of the same composition as FEOL dielectric material 22, or of a different composition. The dielectric material layer 28 has a thickness sufficient to prevent damage to the gate structure 16 or the source / drain contact structures 26, or both, during subsequent formation of the MTJ pillars. In one example, the dielectric material layer 28 has a thickness of 20 nm to 100 nm.

[0034] After forming the dielectric material layer 28, an opening is formed in the dielectric material layer 28 to physically expose one surface of the source / drain contact structure 26 of a first gate structure (i.e., the central gate structure shown in FIG. 2A) of the plurality of gate structures 16. The opening may be formed by lithography and etching. The opening has a critical dimension (CD) smaller than a CD of the underlying source / drain contact structure 26. Furthermore, the opening formed in the dielectric material layer 28 physically exposes one surface of the source / drain contact structure 26 associated with one gate structure (i.e., the central gate structure shown in FIG. 2A) of the plurality of gate structures 16. The opening may have a cylindrical shape.

[0035] Next, a bottom electrode 30 is formed within the opening present in the dielectric material layer 28. The bottom electrode 30 may be comprised of a conductive material such as, for example, Ta, TaN, Ti, TiN, Ru, RuN, RuTa, RuTaN, Co, CoWP, CoN, W, WN, or any combination thereof. The bottom electrode 30 may be formed by a deposition process such as, for example, sputtering, CVD, or PECVD. The deposition of the conductive material providing the bottom electrode 30 may be followed by a planarization process such as, for example, CMP or grinding.

[0036] 3A-3B, the example structure of FIGS. 2A-2B is shown after forming a multi-layer magnetic tunnel junction (MTJ) material stack 32 on the dielectric material layer 28 and the buried bottom electrode 30, and forming a top electrode layer 42 on the MTJ material stack 32. In some embodiments, a hard mask layer 44 may be formed on the top electrode layer 42, as shown in FIGS. 3A-3B.

[0037] The MTJ material stack 32 includes at least a magnetic pinned layer, a tunnel barrier layer, and a magnetic free layer. In some embodiments, as shown in FIGS. 3A-3B, the MTJ material stack 32 is a bottom-pinned MTJ material stack including, from bottom to top, a magnetic pinned layer 36, a tunnel barrier layer 38, and a magnetic free layer 40. An optional metal seed layer 34 may also be present in the bottom-pinned MTJ material stack. The bottom-pinned MTJ material stack may include a non-magnetic spacer layer (not shown) located on the magnetic free layer 40, a second magnetic free layer (not shown) located on the non-magnetic spacer layer, or an MTJ cap layer (not shown) located on the magnetic free layer 40 or on the second magnetic free layer, or a combination thereof.

[0038] In another embodiment (not shown), the MTJ stack is a top-pinned MTJ material stack including, from bottom to top, a magnetic free layer, a tunnel barrier layer, and a magnetic pinned layer, in which the order of elements 36 and 40 is reversed from that shown in Figures 3A-3B. In such an embodiment, the top-pinned MTJ material stack may include an optional metal seed layer located below the magnetic free layer, a non-magnetic spacer layer located on the magnetic free layer, a second magnetic free layer located on the non-magnetic spacer layer, or an MTJ cap layer located on the magnetic pinned layer, or combinations thereof.

[0039] The various material layers of the MTJ material stack 32 may be formed using one or more deposition processes, such as, for example, sputtering, plasma-enhanced atomic layer deposition (PEALD), PECVD, or PVD.

[0040] The optional metallic seed layer 34 may be comprised of platinum (Pt), palladium (Pd), nickel (Ni), rhodium (Rh), iridium (Ir), rhenium (Re), or alloys or multilayers thereof. In one embodiment, the optional metallic seed layer 34 is comprised of platinum (Pt).

[0041] The magnetic pinned layer 36 has a fixed magnetization. The magnetic pinned layer 36 can be composed of a metal or metal alloy (or stack thereof) including one or more metals that exhibit high spin polarization. In an alternative embodiment, exemplary metals for the formation of the magnetic pinned layer 36 include iron, nickel, cobalt, chromium, boron, or manganese. Exemplary metal alloys can include the metals exemplified above. In another embodiment, the magnetic pinned layer 36 can be a multi-layer arrangement having (1) high spin polarization regions formed from metals or metal alloys or both using the metals listed above, and (2) regions constructed of one or more materials that exhibit strong perpendicular magnetic anisotropy (strong PMA). Examples of strong PMA materials that can be used include metals such as cobalt, nickel, platinum, palladium, iridium, or ruthenium, and can be arranged as alternating layers. The strong PMA region may include an alloy that exhibits a strong PMA, with example alloys including cobalt-iron-terbium, cobalt-iron-gadolinium, cobalt-chromium-platinum, cobalt-platinum, cobalt-palladium, iron-platinum, or iron-palladium, or combinations thereof. The alloys may be arranged as alternating layers. In one embodiment, combinations of these materials and regions may also be used as the magnetic pinned layer 36.

[0042] The tunnel barrier layer 38 is made of an insulating material and is formed with a thickness to provide an adequate tunnel resistance. Exemplary materials for the tunnel barrier layer 38 include magnesium oxide, aluminum oxide, and titanium oxide, or materials with higher electrical tunnel conductance, such as semiconductors or low bandgap insulators.

[0043] The magnetic free layer 40 may be composed of a magnetic material (or a stack of magnetic materials) whose magnetization direction can be changed relative to the magnetization direction of the magnetic pinned layer 36. Exemplary magnetic materials for the magnetic free layer 40 include alloys and / or multilayers of cobalt, iron, cobalt-iron alloys, nickel, nickel-iron alloys, cobalt-iron-boron alloys.

[0044] When present, the nonmagnetic metallic spacer layer is composed of a nonmagnetic metal or metal alloy, allows magnetic information to be transmitted therethrough, and also magnetically couples the two magnetic free layers such that the first and second magnetic free layers are always parallel at equilibrium. The nonmagnetic metallic spacer layer allows for spin torque switching between the first and second magnetic free layers.

[0045] If present, the second magnetic free layer can include one of the magnetic materials described above for magnetic free layer 40. In one embodiment, the second magnetic free layer is composed of the same magnetic material as magnetic free layer 40. In another embodiment, the second magnetic free layer is composed of a magnetic material that is different in composition than magnetic free layer 40.

[0046] If present, the MTJ cap layer may be composed of Nb, NbN, W, WN, Ta, TaN, Ti, TiN, Ru, Mo, Cr, V, Pd, Pt, Rh, Sc, Al, or other refractory metal or conductive metal nitrides. The MTJ cap layer may have a thickness between 2 nm and 25 nm, although other thicknesses are possible and may be used in the present invention as the MTJ cap layer thickness.

[0047] The top electrode layer 42 may be composed of a conductive material such as, for example, Ta, TaN, Ti, TiN, Ru, RuN, RuTa, RuTaN, Co, CoWP, CoN, W, WN, or any combination thereof. The conductive material providing the top electrode layer 42 may be the same in composition as the conductive material providing the bottom electrode 30, or may be different in composition. In an embodiment of the invention, the top electrode layer 42 may have a thickness of 100 nm to 500 nm, although other thicknesses are possible and may be used as the thickness of the top electrode layer 42. The top electrode layer 42 may be formed by a deposition process such as, for example, sputtering, PEALD, PECVD, or PVD.

[0048] As described above, a hard mask layer 44 may be formed on the top electrode layer 42. The hard mask layer 44 may be comprised of any hard mask material including, for example, silicon dioxide, silicon nitride, or silicon oxynitride, or combinations thereof. The hard mask layer 44 may be formed using a deposition process such as, for example, PEALD, PECVD, or PVD. The hard mask layer 44 may have a thickness between 10 nm and 50 nm, although other thicknesses are possible and may be used for the hard mask layer 44.

[0049] 4A-4B, the exemplary structure of FIGS. 3A-3B is shown after the top electrode layer 42 and the MTJ stack material 32 have been patterned to provide a top electrode 42P and an MTJ pillar 32P, respectively, over at least the buried bottom electrode 30. In embodiments in which a hardmask layer 44 is present, the hardmask layer 44 is patterned at this point to provide a hardmask 44P over the top electrode 42P.

[0050] The patterning of the optional hard mask layer 44, the top electrode layer 42, and the MTJ material stack 32 includes an ion beam etch (IBE) process. In some embodiments, as shown in FIG. 4A, the top portion of the dielectric material layer 28 is removed, i.e., recessed, during this patterning step. In such embodiments, a mesa portion 28M of the dielectric material layer 28 is formed. The mesa portion 28M of the dielectric material layer 28 has a top surface located above the recessed portion of the dielectric material layer 28. In an embodiment of the invention, the dielectric material layer 28 including the mesa portion 28M is thicker than the recessed portion of the dielectric material layer 28. Due to the thickness of the dielectric material layer 28, no damage occurs to the underlying gate structure 16 or the source / drain contact structure 26, or both. As shown in FIG. 4A, the MTJ pillar 32P is located on the mesa portion 28M of the dielectric material layer 28.

[0051] The remaining, i.e., unpatterned, portions of the MTJ material stack 32 provide the MTJ pillar 32P. In one example, as shown in FIG. 4A, the MTJ pillar 32P is a bottom-pinned MTJ structure and includes, from bottom to top, a metal seed layer portion 34P (i.e., the remaining unetched portion of the metal seed layer 34), a magnetic pinned layer portion 36P (i.e., the remaining unetched portion of the magnetic pinned layer 36), a tunnel barrier layer portion 38P (i.e., the remaining unetched portion of the tunnel barrier layer 38), and a magnetic free layer portion 40P (i.e., the remaining unetched portion of the magnetic free layer 40). In another example (not shown), the MTJ pillar 32P is a top-pinned MTJ structure and includes, from bottom to top, a magnetic free layer portion 40P, a tunnel barrier layer portion 38P, and a magnetic pinned layer portion 36P. In either embodiment (bottom-pinned MTJ structure or top-pinned MTJ structure), the MTJ pillar 32P can include the remaining portions of any other layers present in the MTJ material stack 32.

[0052] The MTJ pillar 32P, the top electrode 42P, and the hard mask 44P, if present, may be cylindrical, although other asymmetric shapes are possible and may be used in embodiments of the present invention as the shapes of the MTJ pillar 32P, the top electrode 42P, and the hard mask 44P, if present. To avoid undesired re-sputtering of the metal particles of the bottom electrode 30 onto the sidewalls of the MTJ pillar 32P, the CD of the MTJ pillar 32P, the top electrode 42P, and the hard mask 44P, if present, are made to be equal to or larger than the CD of the bottom electrode 30.

[0053] Typically, the MTJ pillar 32P, the top electrode 42P, and, if present, the hard mask 44P have outermost sidewalls that are vertically aligned with one another. In an embodiment in which a mesa portion 28M of the dielectric material layer 28 is formed, the MTJ pillar 32P, the top electrode 42P, and, if present, the hard mask 44P have outermost sidewalls that are vertically aligned with the outermost sidewall of the mesa portion 28M of the dielectric material layer 28.

[0054] 5A-5B, the exemplary structure of FIGS. 4A-4B is shown after forming a dielectric material spacer 46 laterally adjacent to the MTJ pillar 32P, the top electrode 42P, and, if present, the hard mask 44P. The dielectric material spacer 46 encapsulates and surrounds the MTJ pillar 32P, the top electrode 42P, and, if present, the hard mask 44P. In some embodiments, as shown in FIG. 5A, the lower portion of the dielectric material spacer 46 resides along the sidewall of the mesa portion 28M of the dielectric material layer 28. In such embodiments, the mesa portion 28M of the dielectric material layer 28 is encapsulated and surrounded by the lower portion of the dielectric material spacer 46.

[0055] The dielectric material spacer 46 is composed of a dielectric material that is different in composition from the dielectric material layer 28 and the hard mask layer 44. The dielectric material providing the dielectric material spacer 46 can provide passivation to the MTJ pillar 32P and the top electrode 42P. In one embodiment, the dielectric material spacer 46 is composed of silicon nitride. In another embodiment, the dielectric material spacer 46 can be composed of a dielectric material that includes atoms of silicon, carbon, and hydrogen. In some embodiments, in addition to atoms of carbon and hydrogen, the dielectric material spacer 46 can include atoms of at least one of nitrogen and oxygen. In other embodiments, in addition to atoms of silicon, nitrogen, carbon, and hydrogen, the dielectric material spacer 46 can include atoms of boron. In one example, the dielectric material spacer 46 can be composed of an nBLOK dielectric material that includes atoms of silicon, carbon, hydrogen, nitrogen, and oxygen. In an alternative example, the dielectric material spacer 46 can be composed of a SiBCN dielectric material that includes atoms of silicon, boron, carbon, hydrogen, and nitrogen.

[0056] The dielectric material spacers 46 may be formed by deposition, such as CVD or PECVD, followed by a spacer etch, such as reactive ion etching (RIE). The dielectric material spacers 46 may have a top surface that is coplanar with either the top surface of the hard mask 44P or the top surface of the top electrode 42P if the hard mask 44P is omitted.

[0057] 6A-6B, the exemplary structure of FIGS. 5A-5D is shown after formation of an organic planarization layer (OPL) 50 having contact openings 52 formed therein that physically expose the other surface of the source / drain contact structures 26 of the first gate structure (i.e., the middle gate structure shown in FIG. 6A). In an embodiment of the invention, a bottom electrode 30 contacts the source / drain contact structures 26 located on one side of the gate structure 16, and the contact openings 52 physically expose the source / drain contact structures 26 located on the opposite side of the same gate structure 16.

[0058] The OPL 50 is composed of an organic polymer, which may include polyacrylate resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, unsaturated polyester resin, polyphenyl ether resin, polyphenylene sulfide resin, or benzocyclobutene (BCB). The OPL may be formed using a deposition process, such as, for example, CVD, PECVD, or spin-on coating. The OPL 50 has a height that extends above a top surface of the hard mask 44P, or above a top surface of the top electrode 42P if the hard mask 44P is omitted.

[0059] The contact opening 52 may be formed by lithography and etching. Due to differences in etch selectivity between the OPL 50 and the dielectric material layer 28, the contact opening 52 present in the dielectric material layer 28 may have tapered sidewalls (i.e., inwardly tapered sidewalls when measured from top to bottom), as shown in Figures 6A and 6B. In some embodiments, the contact opening 52 is disposed in a recessed portion of the dielectric material layer 28 that is laterally adjacent to the mesa portion 28M of the dielectric material layer 28 that embeds the bottom electrode 30.

[0060] 7A-7B, the example structure of Figures 6A-6B is shown after removal of OPL 50. OPL layer 50 can be removed utilizing any material removal process, such as, for example, ashing.

[0061] 8A-8B, the exemplary structure of Figures 7A-7B is shown after forming a conductive metal-containing layer 54 and a contact metal-containing layer 56. In some embodiments, the conductive metal-containing layer 54 can be omitted.

[0062] The conductive metal-containing layer 54 is a continuous layer formed on all physically exposed surfaces of the exemplary structure shown in FIGS. 7A-7B, including within the contact openings 52 formed in the dielectric material layer 28. The conductive metal-containing layer 54 is comprised of a conductive liner material, such as, for example, Ta, TaN, Ti, TiN, Ru, RuN, RuTa, RuTaN, W, or WN. In some embodiments, the conductive metal-containing layer 54 may include a material stack of conductive liner materials. In one example, the conductive liner material may be comprised of a stack of Ta / TaN. The conductive metal-containing layer 54 may be formed utilizing a deposition process, such as, for example, CVD, PECVD, PVD, or sputtering. The conductive metal-containing layer 54 may have a thickness of 1 nm to 15 nm, although other thicknesses of the conductive metal-containing layer 54 are possible and may be used as the thickness of the conductive metal-containing layer 54 in embodiments of the present invention.

[0063] The contact metal-containing layer 56 includes any contact metal or contact metal alloy suitable for subtractive etching. Examples of materials suitable for such subtractive etching include, but are not limited to, ruthenium (Ru), aluminum (Al), or palladium (Pd). Typically, the contact metal-containing layer 56 is compositionally distinct from the conductive metal-containing layer 54. The contact metal-containing layer 56 may be formed utilizing a deposition process, such as, for example, CVD, PECVD, plating, or sputtering. The contact metal-containing layer 56 is a continuous layer that resides over the entire conductive metal-containing layer 54. In embodiments in which the conductive metal-containing layer 54 is omitted, the contact metal-containing layer 56 is a continuous layer that is formed over all physically exposed surfaces of the exemplary structure shown in FIGS. 7A-7B, including within the contact opening 52 formed in the dielectric material layer 28. As shown, a lower portion of the contact metal-containing layer 56 resides within the contact opening 52 that resides in the dielectric material layer 28 that also contains the bottom electrode 30. The lower portion of the contact metal-containing layer 56 present in the contact opening 52 may have inwardly tapered sidewalls, as described above.

[0064] 9A-9B, the exemplary structure of FIGS. 8A-8B is shown after recessing both the contact metal-containing layer 56 and the conductive metal-containing layer 54, or only the contact metal-containing layer 56 if the conductive metal-containing layer 54 is omitted. Recessing may include first planarizing the contact metal-containing layer 56 and then performing a recess etch. The remaining contact metal-containing layer 56 may be referred to as the recessed contact metal-containing layer 56R, and the remaining conductive metal-containing layer 54 may be referred to as the recessed conductive metal-containing layer 54R. The recessed contact metal-containing layer 56R and the recessed conductive metal-containing layer 54R have top surfaces that are coplanar with one another. The top surfaces of the recessed contact metal-containing layer 56R and the recessed conductive metal-containing layer 45R are at least below the top surface of the top electrode 42P.

[0065] 10A-10B, the exemplary structure of FIGS. 9A-9B is shown after forming a hardmask cap 58 on the recessed contact metal-containing layer 56R and the recessed conductive metal-containing layer 54R. The hardmask cap 58 includes any hardmask material and is compositionally distinct from the hardmask 44P and the dielectric material spacers 46 present on the top electrode 42P. The hardmask cap 58 may be formed by a deposition process followed by a planarization process such as, for example, CMP. The hardmask cap 58 typically has a top surface that is coplanar with the top surface of the dielectric material spacers 46.

[0066] 11A-11B, the example structure of FIGS. 10A-10B is shown after forming another OPL 60P and then patterning the another OPL 60P, hard mask 58, recessed contact metal-containing layer 56R, and recessed conductive metal-containing layer 54R in the source / drain regions (i.e., along cross section YY as shown in FIG. 11B). The another OPL 60P can be composed of one of the materials described above for OPL 50, and the OPL 60P can be formed utilizing one of the deposition processes described above for forming OPL 50.

[0067] Patterning can be performed by lithography and etching. Each remaining (i.e., unetched) portion of the hard mask 58 can be referred to as a patterned hard mask cap 58P, each remaining (i.e., unetched) portion of the recessed contact metal-containing layer 56R can be referred to as a lower contact structure 56S, and each remaining (i.e., unetched) portion of the recessed conductive metal-containing layer 54R can be referred to herein as a conductive metal-containing liner 54L. In FIG. 12B, the lower structures 56S that are not present in the contact openings 52 present in the dielectric material layer 28 represent dummy structures and are not utilized for electrical connection. As can be seen in FIG. 12B, the patterned structure including the patterned hard mask cap 58P and the lower contact structures 56S can have tapered sidewalls (in this case, the taper is outward from top to bottom).

[0068] 11A , the entire lower portion of the lower contact structure 56S present in the contact opening 52 and the bottom electrode 30 are located in the dielectric material layer 28. It should be noted that the entire bottom electrode 30 is located in the dielectric material layer 28, including the mesa portion 28M, while the entire lower portion of the lower contact structure 56S present in the contact opening 52 is located in the entire recess of the dielectric material layer 28, and the dielectric material layer 28, including the mesa portion 28M, has a height (i.e., vertical thickness) that exceeds the recess of the dielectric material layer 28.

[0069] 12A-12B, the example structure of Figures 11A-11B is shown after removal of the additional OPL 60P. The additional OPL 60P can be removed utilizing any material removal process, such as, for example, ashing.

[0070] 13A-13B, the exemplary structure of FIGS. 12A-12B is shown after forming the low-k dielectric fill material 62 and planarizing the low-k dielectric fill material 62. The term "low-k" has the meaning defined above, i.e., a dielectric material having a dielectric constant less than 4.0. In some embodiments, the low-k dielectric fill material 62 comprises a Si-based dielectric material. The Si-based dielectric material can be either silica-based (e.g., SiOCH) or silsesquioxane (SSQ)-based (e.g., hydrogen-SSQ or methyl-SSQ). Other low dielectrics can be used as the low-k dielectric fill material 62, such as non-Si-based dielectric materials (i.e., polymers or amorphous carbon). The low-k dielectric fill material 62 can be formed utilizing a deposition process, such as, for example, CVD, PECVD, or spin-on coating. Planarization of the deposited low-k dielectric fill material 62 can be performed by CMP or grinding. After planarization, low-k dielectric fill material 62 has a top surface that is coplanar with the top surface of each patterned hardmask cap 58 P. Dielectric fill material 62 and dielectric material layer 28 reside in the MOL.

[0071] 14A-14B, the example structure of FIGS. 13A-13B is shown after forming a BEOL dielectric material layer 64 having top contact structures (66X, 66Y) formed thereon. The BEOL dielectric material layer 64 may include one of the dielectric materials described above for the dielectric material layer 28. The BEOL dielectric material layer 64 may be formed utilizing a deposition process such as, for example, CVD, PECVD, or spin-on coating.

[0072] The upper contact structures (66X, 66Y) are formed by forming a pair of contact openings in the BEOL dielectric material layer 64, one of which extends to a surface of the lower contact structure 56S that contacts the source / drain structure 26, and the other contact opening extends to a surface of the top electrode 44P. The pair of contact openings may be formed by lithography and etching. Each contact opening is then filled with a contact metal or a contact metal alloy. Exemplary contact metals include copper, aluminum, or tungsten. An exemplary contact metal alloy is a copper-aluminum alloy.

[0073] As shown, the first upper contact structure 66X contacts a surface of the lower contact structure 56S which in turn contacts one surface of the source / drain contact structure 26, while the second upper contact structure 66Y contacts a surface of the top electrode 42P located on the MTJ pillar 32P.

[0074] 14A-14B show a memory cell (i.e., 1T1M) according to the present invention. The memory cell includes a FEOL including a gate structure (middle gate structure 16) spanning the semiconductor fin 12, with source / drain structures 24 disposed on either side of the gate structure 16 and a source / drain contact structure 26 disposed on each source / drain structure 24. A MOL level is located above the FEOL level and includes an MRAM device (including bottom electrode 30, MTJ pillar 32P, and top electrode 42P) and a bottom contact structure 56S, with the bottom electrode 30 of the MRAM device contacting one of the source / drain contact structures (i.e., the source / drain contact structure 26 on the right side of the middle gate structure 16) and the bottom contact structure 56S contacting the other source / drain contact structure on the other side of the gate structure 16 (i.e., the source / drain contact structure 26 on the left side of the middle gate structure 16). The BEOL level is located above the MOL level and includes a first upper contact structure 66X that contacts a surface of the lower contact structure 56S and a second upper contact structure 66Y that contacts a surface of the top electrode 42P of the MRAM device. Such memory cells have low wiring resistance and therefore high memory speed.

[0075] While the present invention has been particularly shown and described with respect to preferred embodiments thereof, it will be understood by those skilled in the art that the foregoing and other changes in form and detail may be made therein without departing from the scope of the invention. It is therefore intended that the present invention not be limited to the exact forms and details described and illustrated, but fall within the scope of the appended claims.

Claims

1. a front end of line (FEOL) level including a gate structure spanning the semiconductor fin with source / drain structures disposed on either side of the gate structure and a source / drain contact structure disposed on each source / drain structure; a middle-of-the-line (MOL) level above the FEOL, the MRAM device including a magnetoresistive random access memory (MRAM) device and a bottom contact structure, a bottom electrode of the MRAM device contacting one of the source / drain contact structures on one side of the gate structure, and the bottom contact structure contacting the other of the source / drain contact structures on the other side of the gate structure; a back-end-of-line (BEOL) level located above the MOL level and including a first upper contact structure contacting a surface of the lower contact structure and a second upper contact structure contacting a surface of a top electrode of the MRAM device; Including, the MOL level includes a dielectric material layer having a mesa portion and a recessed portion, a lower portion of the lower contact structure is embedded in the recessed portion of the dielectric material layer, and the bottom electrode is embedded within a region of the dielectric material layer that includes the mesa portion. Memory cell.

2. The memory cell of claim 1 , wherein the MRAM device further comprises a magnetic tunnel junction (MTJ) pillar in contact with the bottom electrode, the MTJ pillar being located on the mesa portion of the layer of dielectric material.

3. 3. The memory cell of claim 2, further comprising a dielectric material spacer encapsulating and surrounding the MTJ pillar and the top electrode, a portion of the dielectric material spacer contacting a sidewall of the mesa portion of the dielectric material layer.

4. The memory cell of claim 2 , wherein the MTJ pillar is a bottom-pin MTJ structure.

5. The memory cell of claim 2 , wherein the MTJ pillar is a top-pin MTJ structure.

6. 2. The memory cell of claim 1, further comprising a conductive metal-containing liner disposed between said lower contact structure and said other of said source / drain structures located on said other side of said gate structure, said conductive metal-containing liner having a top surface coplanar with a top surface of said lower contact structure.

7. The memory cell of claim 6 , wherein the top surface of the conductive metal-containing liner is located below a top surface of the top electrode of the MRAM device.

8. The memory cell of claim 1 , wherein a lower portion of the lower contact structure has tapered sidewalls.

9. The memory cell of claim 1 , wherein said first and second upper contact structures are located partially in a BEOL dielectric material layer located above said MOL level.

10. 3. The memory cell of claim 2, wherein both the MTJ pillar and the top electrode have a first critical dimension, and the bottom electrode has a second critical dimension that is smaller than the first critical dimension.

11. The memory cell of claim 2 , wherein both the MTJ pillar and the top electrode are cylindrical.

12. 1. A method of forming a memory cell, comprising the steps of: forming a front end of line (FEOL) level including a gate structure spanning the semiconductor fin with source / drain structures disposed on either side of the gate structure and a source / drain contact structure disposed on each source / drain structure; forming a middle-of-line (MOL) level of dielectric material layer over the FEOL level; forming a bottom electrode of a magnetoresistive random access memory (MRAM) device in the layer of dielectric material contacting one of the source / drain contact structures located on one side of the gate structure; forming a magnetic tunnel junction (MTJ) pillar and a top electrode of the MRAM device above the bottom electrode; forming a lower contact structure contacting the other of the source / drain contact structures located on the other side of the gate structure, the lower portion of the lower contact structure being embedded in the dielectric material layer; forming a back end of line (BEOL) level above the MOL level, the BEOL level including a first upper contact structure contacting a surface of the lower contact structure and a second upper contact structure contacting a surface of a top electrode of the MRAM device; Including, forming the MTJ pillar and the top electrode forming a MTJ material stack and a top electrode layer; patterning the MTJ material stack and the top electrode layer using ion beam etching; Including, during the ion beam etching, a recess is formed in a portion of the dielectric material layer that is disposed laterally adjacent to the bottom electrode, and the lower portion of the lower contact structure is embedded in the recessed portion of the dielectric material layer. method.

13. The method of claim 12 , further comprising forming a dielectric material spacer encapsulating and surrounding the MTJ pillar and the top electrode.

14. forming the lower contact structure; forming a contact opening in the layer of dielectric material physically exposing the other surface of the source / drain contact structure located on the other side of the gate structure; forming a conductive metal-containing layer on the dielectric material layer, including within and along the sidewalls of the contact opening, and above a top portion of the top electrode; forming a contact metal-containing layer on the conductive metal-containing layer; recessing the contact metal-containing layer and the conductive metal-containing layer to a height below a height of the top electrode; forming a hard mask cap over the recessed contact metal-containing layer; patterning the hard mask cap, the recessed contact metal-containing layer, and the recessed conductive metal-containing layer located on the other side of the gate structure; The method of claim 12, comprising:

15. 15. The method of claim 14, wherein the contact opening has tapered sidewalls, and the lower portion of the lower contact structure embedded in the layer of dielectric material has tapered sidewalls.

16. The method of claim 12 , wherein the MTJ pillar is a bottom-pinned MTJ structure.

17. The method of claim 12 , wherein the MTJ pillar is a top-pin MTJ structure.

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