Magnetic structures in integrated circuit package supports

Abstract

To provide magnetic structures in integrated circuit (IC) package supports, as well as related methods and devices.SOLUTION: An IC package support 100 includes: a conductive line 140; a magnetic structure 150 around the conductive line 140; and material stubs 148 at side faces of the magnetic structure. The conductive line 110 may serve as an inductor trace. The magnetic structure 150 may include a first portion 118 and a second portion 128. The first portion 118 may surround bottom and side faces of the conductive line 110, while the second portion 128 may be at a top face of the conductive line 110. The first portion 118 and the second portion 128 of the magnetic structure 150 may include a magnetic material, such as a magnetic paste or ink. The material stubs 148 may be disposed at side faces of the magnetic structure 150. The material stubs 148 may include copper 104 and nickel 106.SELECTED DRAWING: Figure 1

Description

[Background technology]

[0001] The performance of some integrated circuit (IC) elements, such as inductors, can be enhanced through the use of magnetic materials. [Brief description of the drawings]

[0002] BRIEF DESCRIPTION OF THE DRAWINGS The following detailed description will be readily understood by reading it in conjunction with the accompanying drawings, in which: FIG. 1 is a block diagram of a semiconductor memory device according to an embodiment of the present invention;

[0003] [Figure 1] 1 is a side cross-sectional view of an exemplary integrated circuit (IC) package support including a magnetic structure according to various embodiments.

[0004] [Figure 2A] 2A-2D illustrate stages in an exemplary process for manufacturing the IC package support of FIG. 1 according to various embodiments. [Figure 2B] 2A-2D illustrate stages in an exemplary process for manufacturing the IC package support of FIG. 1 according to various embodiments. [Figure 2C] 2A-2D illustrate stages in an exemplary process for manufacturing the IC package support of FIG. 1 according to various embodiments. [Figure 2D] 2 illustrates stages in an exemplary process for manufacturing the IC package support of FIG. 1 according to various embodiments. [Figure 2E] 2A-2D illustrate stages in an exemplary process for manufacturing the IC package support of FIG. 1 according to various embodiments. [Figure 2F] 2 illustrates stages in an exemplary process for manufacturing the IC package support of FIG. 1 according to various embodiments. [Figure 2G] 2A-2D illustrate stages in an exemplary process for manufacturing the IC package support of FIG. 1 according to various embodiments. [Figure 2H]2A-2D illustrate stages in an exemplary process for manufacturing the IC package support of FIG. 1 according to various embodiments. [Figure 2I] 2A-2D illustrate stages in an exemplary process for manufacturing the IC package support of FIG. 1 according to various embodiments. [Figure 2J] 2A-2D illustrate stages in an exemplary process for manufacturing the IC package support of FIG. 1 according to various embodiments. [Figure 2K] 2A-2D illustrate stages in an exemplary process for manufacturing the IC package support of FIG. 1 according to various embodiments. [Figure 2L] 2A-2D illustrate stages in an exemplary process for manufacturing the IC package support of FIG. 1 according to various embodiments. [Figure 2M] 2A-2D illustrate stages in an exemplary process for manufacturing the IC package support of FIG. 1 according to various embodiments. [Figure 2N] 2A-2D illustrate stages in an exemplary process for manufacturing the IC package support of FIG. 1 according to various embodiments. [Figure 2O] 2A-2D illustrate stages in an exemplary process for manufacturing the IC package support of FIG. 1 according to various embodiments.

[0005] [Diagram 3] FIG. 2 is a top view of a wafer and die that may be included in an IC package having an IC package support according to any of the embodiments disclosed herein.

[0006] [Figure 4] FIG. 2 is a side cross-sectional view of an IC device that may be included in an IC package having an IC package support according to any of the embodiments disclosed herein.

[0007] [Diagram 5] 1 is a side cross-sectional view of an IC package that may include any of the IC package supports disclosed herein.

[0008] [Figure 6]FIG. 2 is a side cross-sectional view of an IC device assembly that may include an IC package support according to any of the embodiments disclosed herein.

[0009] [Figure 7] FIG. 2 is a block diagram of an example electrical device that may include an IC package support according to any of the embodiments disclosed herein. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0010] Disclosed herein are magnetic structures in integrated circuit (IC) package supports and related methods and devices. For example, in some embodiments, an IC package support (e.g., a package substrate or interposer) can include conductive lines, a magnetic structure around the conductive lines, and material stubs on the sides of the magnetic structure.

[0011] Magnetic structures may improve the electrical performance of some IC assemblies. For example, inductors reinforced with magnetic structures (e.g., magnetic material reinforced inductors) may be used in package substrates or other IC package supports to improve power delivery performance. However, conventional techniques for forming such magnetic structures (e.g., conventional paste printing) may provide inadequate dimensional control (e.g., in both lateral dimensions and thickness) for desired applications. Designers relying on such techniques must include large keep-out zones around such structures to mitigate the risk of bridging and increasing the footprint of the structure in both x- and y-directions and z-directions. Planarization may be performed to control the thickness of the magnetic structures, but such processes are expensive and traditionally not compatible with high volume manufacturing (HVM). Furthermore, the minimum achievable thickness of conventional magnetic structures may be high enough to require the use of high aspect ratio vias on the same layer. Such vias may be difficult to manufacture (e.g., due to limitations of laser drilling, cleaning the vias, and filling the metal) and may create reliability issues (e.g., due to increased crack risk resulting from the small diameter of the vias at the bottom).

[0012] Various of the embodiments disclosed herein may provide process flows and structures that may address one or more of the issues highlighted above and may be compatible with HVM processes. The IC package supports disclosed herein may be particularly beneficial for ultra-mobile computing devices such as laptops and tablets with very thin form factors. The manufacturing techniques disclosed herein may allow magnetically enhanced inductors to be used anywhere on the IC package support, rather than being limited to the surface of the IC package support as required by some previous approaches. Furthermore, the manufacturing techniques disclosed herein may avoid exposing the magnetic material to damaging desmear, plating and / or etching chemistries, allowing for higher quality magnetic structures than previously possible. The IC package supports 100 disclosed herein may include magnetic structures with any desired thickness or thickness asymmetry relative to the embedded inductor traces, allowing for improved performance.

[0013] In the following detailed description, reference is made to the accompanying drawings, which form a part of this specification, in which like reference characters refer to like parts throughout and in which embodiments that may be implemented are shown by way of example. It is to be understood that other embodiments may be utilized and structural or logical changes may be made without departing from the scope of the present disclosure. Therefore, the following detailed description is not to be taken in a limiting sense.

[0014] Various operations may be described as multiple separate acts or operations, in a sequence that is most helpful in understanding the claimed subject matter. However, the order of description should not be construed as implying that these operations are necessarily order dependent. In particular, these operations need not be performed in the order presented. The described operations may be performed in a different order than in the described embodiment. Various additional operations may be performed and / or the described operations may be omitted in additional embodiments.

[0015] For purposes of this disclosure, the phrase "A and / or B" means (A), (B) or (A and B). For purposes of this disclosure, the phrase "A, B and / or C" means (A), (B), (C), (A and B), (A and C), (B and C) or (A, B and C). The drawings are not necessarily to scale. While many of the drawings show rectilinear structures with flat walls and square corners, this is for ease of illustration only, and actual devices made using these techniques will exhibit rounded corners, surface roughness and other features.

[0016] The description uses the phrases "in one embodiment" or "in an embodiment." Each of the phrases may refer to one or more of the same or different embodiments. Furthermore, terms such as "comprising," "including," and "having" used with respect to the embodiments of the present disclosure are synonymous. As used herein, "package" and "IC package" are synonymous. When used to describe a range of dimensions, the phrase "between X and Y" refers to the range inclusive of X and Y. For convenience, the phrase "FIG. 2" may be used to refer to the collection of drawings, FIG. 2A through FIG. 2O.

[0017] FIG. 1 illustrates an IC package support 100 (e.g., a package substrate or interposer) having a magnetic structure 150 therein. The IC package support 100 may have a first side 146 with conductive contacts 142 exposed to the solder resist 134 through openings 138 and an opposing second side 144 with conductive contacts 140 exposed to the solder resist 132 through openings 136. In some embodiments, the conductive contacts 142 may be suitable for a first level interconnect (FLI), such as a solder bump, and the conductive contacts 140 may be suitable for a second level interconnect (SLI), such as a solder ball, or vice versa. For example, FLI (not shown) may electrically couple the IC package support 100 to one or more dies, other active or passive devices, or an interposer. SLI (not shown) may couple the IC package support 100 to a circuit board (e.g., a motherboard), an interposer, or a package substrate. As shown, IC package support 100 may be a "coreless" support. In some embodiments, conductive contacts 142 and / or conductive contacts 140 may be a nickel-palladium-gold surface finish. Such an embodiment may be advantageous over an embodiment in which conductive contacts 142 / 140 are an organic solder protection (OSP) finish because contacts with a nickel-palladium-gold surface finish may be electrically tested while still protecting the contacts from oxidation (requiring OSP finished contacts to be clean prior to testing).

[0018] A number of dielectric layers 112 may be arranged between the first side 146 and the second side 144. The dielectric layers 112 may include any suitable dielectric material. For example, the dielectric layers 112 may be a build-up film (e.g., an organic polymer-based dielectric film) or a glass cloth impregnated with a dielectric material (a "prepreg" material). As shown, one or more interconnect structures 108 may be embedded in the dielectric layers 112 including conductive lines and vias. The interconnect structures 108 may provide electrical paths between the conductive contacts 142, between the conductive contacts 140, between the conductive contacts 140 and 142, and / or between the conductive contacts 140 / 142 and elements within the IC package support 100.

[0019] One particular element in the IC package support 100 to which the interconnect structure 108 may be coupled is an inductor 162. The inductor 162 may include one or more conductive lines 110 surrounded by a magnetic structure 150. The conductive lines 110 may function as inductor traces. The magnetic structure 150 may include a first portion 118 and a second portion 128. The first portion 118 may surround the bottom and sides of the conductive line 110 as shown, while the second portion 128 may be on the top surface of the conductive line 110. The first portion 118 and the second portion 128 of the magnetic structure 150 may include a magnetic material such as a magnetic paste or ink (e.g., a resin material having magnetic particles in a polymer matrix, such as iron particles in an epoxy or other polymer matrix).

[0020] The material stub 148 may be disposed on a side of the magnetic structure 150. The material stub 148 may include copper 104 and nickel 106. In some embodiments, the thickness 152 of the nickel 106 may be between 3 microns and 10 microns (e.g., between 4 microns and 6 microns) and the thickness 154 of the copper 104 may be between 3 microns and 15 microns (e.g., between 3 microns and 12 microns or between 5 microns and 10 microns). The width 158 of the material stub 148 may be greater than or equal to 10 microns (e.g., greater than or equal to 15 microns). Although the element 104 is referred to herein as "copper 104," copper is merely an example of a material that may function as the element 104, and in other embodiments, non-copper laser-stop materials such as other metals or metal oxide materials may be used. Similarly, although element 106 is referred to herein as "nickel 106," nickel is merely an example of a material that may function as element 106; in other embodiments, other materials may be used that have associated etching chemistries that do not damage the material of magnetic structure 150 (e.g., any metal or metal oxide material that can be etched away with a different chemistry than the first metal).

[0021] As shown, the material stub 148 may be included in one dielectric layer 112, while the conductive line 110 may be included in an adjacent dielectric layer 112. In some embodiments, the surface of the conductive line 110 may be flush with the surface of the material stub 148. For example, the bottom surface of the nickel 106 in the material stub 148 may be flush with the top surface of the conductive line 110 (and may be flush with the interface between the two associated dielectric layers 112). As shown, the first portion 118 and the second portion 128 of the magnetic structure 150 may each have a tapered shape that narrows toward the conductive line 110. In some embodiments, the slope of the taper of the first portion 118 and the second portion 128 may be between 10 percent and 30 percent (e.g., between 15 percent and 25 percent). As shown, the material stub 148 may contact the second portion 128 of the magnetic structure 150. In some embodiments, the thickness 156 of the conductive lines 110 may be between 5 microns and 50 microns (e.g., between 10 microns and 40 microns). In some embodiments, the height 166 of the magnetic structure 150 may be between 50 microns and 250 microns (e.g., between 100 microns and 250 microns), and the heights of the first portion 118 and the second portion 128 may be the same or different. In some embodiments, the interconnect structure 108 and the conductive lines 110 may include a metal, such as copper.

[0022] In some embodiments, the material stub 148 may be an artifact of a particular manufacturing process described in FIG. 2. The manufacturing process described in FIG. 2 may also be associated with various features of the interconnect structure 108 included in the IC package support 100. For example, as shown, the interconnect structure 108 may include a via 122 that extends throughout the associated dielectric layer 112. As shown, such a via 122 may be tapered and have a minor side flush with the bottom surface of the material stub 148 and the top surface of the conductive line 110. In another example, the interconnect structure 108 may include a via 130 that extends throughout the associated dielectric layer 112 and into an adjacent dielectric layer 112 such that the minor side of the via 130 is in a different dielectric layer 112 than the major side of the via 130. Additionally, such a via 130 may be at least partially flush with the second portion 128 of the magnetic structure 150. In particular, the second portion 128 of the magnetic structure 150 may terminate at an interface between two adjacent dielectric layers 112, and the via 130 may extend through the same interface. The via 120 is another example of an interconnect structure 108 that extends across an associated dielectric layer 112 and into an adjacent dielectric layer 112, such that a smaller surface of the via 120 is in a different dielectric layer 112 than a larger surface of the via 120. Furthermore, the via 120 may be at least partially coplanar with the first portion 118 of the magnetic structure 150. In particular, the first portion 118 of the magnetic structure 150 may terminate at an interface between two adjacent dielectric layers 112, and the via 120 may extend through the same interface. The vias 120 and 130 may taper toward each other, such that the first portion 118 and the second portion 128 of the magnetic structure 150 may taper toward each other.

[0023] 2A-2O illustrate stages in an exemplary process for manufacturing the IC package support 100 (e.g., package substrate or interposer) of FIG. 1 according to various embodiments. Although the operations of FIG. 2 may be illustrated with reference to a particular embodiment of the IC package support 100 and magnetic structure 150 disclosed herein, the method may be used to form any suitable IC package support 100 and / or magnetic structure 150. Although the operations are illustrated once each and in a particular order in FIG. 2, they may be reordered and / or repeated as necessary (e.g., different operations are performed in parallel when manufacturing multiple IC package supports 100 and / or magnetic structures 150 simultaneously). The manufacturing process illustrated in FIG. 2 may advantageously enable the manufacture of an IC package support 100 having a completed magnetic structure 150 to which additional components (e.g., a die) may be bonded. Some previous manufacturing processes required a die to be attached to the IC package support, which required additional processing (e.g., deposition of additional magnetic material) before the magnetic structure was completed for an integrated magnetic structure. Such processes may result in low yields. This is because any error in the additional processing of the IC package support can mean the loss of an (expensive) die.

[0024] FIG. 2A shows an assembly including a carrier 102 on which a layer of copper 104 and a layer of nickel 106 are formed. A patterned layer of conductive material is also formed on the nickel 106, the patterned conductive material including interconnect structures 108 (e.g., pads or lines as shown) and one or more conductive lines 110 (which will be surrounded by a magnetic structure 150 as described further below). The carrier 102 may include any suitable material (e.g., silicon, glass, ceramic, etc.) for performing subsequent manufacturing operations and for providing mechanical stability during subsequent manufacturing operations. The copper 104 may be a foil layer on the carrier 102 and may have a thickness according to any of the thicknesses 154 disclosed herein. The nickel 106 may be blanket plated on the copper 104 and may have a thickness according to any of the thicknesses 156 disclosed herein. The interconnect structures 108 and conductive lines 110 of the assembly of FIG. 2A may be formed using any suitable technique (e.g., lithographic techniques).

[0025] 2B shows the assembly of FIG. 2A after providing dielectric layers 112-1 and 112-2 on the assembly and forming further interconnect structures 108 in and on top of the dielectric layers 112. The dielectric layers 112 may be provided in any suitable manner (e.g., by lamination of dielectric films) and the interconnect structures 108 of FIG. 2B may be formed using any suitable technique (e.g., a semi-additive process (SAP) in which a seed layer is formed, a photoresist is deposited and patterned to expose the seed layer, a conductive material is electroplated onto the seed layer, the photoresist is stripped, and a simple seed etch is performed). Although each of the different dielectric layers 112 in FIG. 2B (and each of the others in the accompanying drawings) are shown as having the same thickness, this is merely for ease of illustration and each of the different dielectric layers 112 in the IC package support 100 may have different thicknesses.

[0026] FIG. 2C shows the assembly of FIG. 2B after forming another dielectric layer 112-3 on the assembly and then forming a cavity 114 through the dielectric layer 112. As shown, the cavity 114 may expose the conductive lines 110 on the nickel 106. The cavity 114 may be formed using any suitable technique, such as laser drilling. In some embodiments, the sidewalls 116 of the cavity 114 may be angled to provide the cavity 114 with a narrowing taper toward the conductive lines 110. In some embodiments, a desmear operation may be performed after forming the cavity 114. In some embodiments where the dielectric layers 112-1, 112-2, and 112-3 are photoimageable dielectrics, the cavity 114 may be formed by selectively exposing and growing the dielectric layer 112, rather than by laser drilling, as is known in the art.

[0027] FIG. 2D illustrates the assembly of FIG. 2C after filling the cavities 114 with a magnetic material to form a first portion 118 of the magnetic structure 150. Although FIG. 2D illustrates the first portion 118 as extending through three dielectric layers 112, this is by way of example only, and in other embodiments, the first portion 118 may extend through any suitable number of dielectric layers 112 (e.g., two, three, four, or five dielectric layers 112). As noted above, the magnetic material may include a magnetic paste or ink. Filling the cavities 114 with the magnetic material may include applying the magnetic material to the cavities 114 with a tool similar to that used in some solder application applications. In some embodiments, filling the cavities 114 with the magnetic material may include stencil printing the magnetic material into the cavities 114. After the initial deposition, the magnetic material may be allowed to harden. The resulting assembly may then be polished to flatten the top surface. This polishing may remove some of the dielectric layer 112-3, but may not reach the interconnect structure 108 in the dielectric layer 112-3. The first portion 118 may have a top surface that is substantially flush with a top surface of the dielectric layer 112-3. Using the cavity 114 to control the shape and dimensions of the first portion 118 of the magnetic structure 150 may reduce the risk of magnetic paste bleeding and dimensional variations associated with conventional paste printing techniques. Furthermore, in some embodiments, forming the first portion 118 by using the cavity 114 may not require the use of a mask. Because conventional masks used to print magnetic paste typically leave significant paste residue on the mask after printing, avoiding the use of such a mask may reduce manufacturing complexity and improve reliability.

[0028] Figure 2E shows the assembly of Figure 2D after forming a dielectric layer 112-4 on the top surface of the assembly. As shown, the dielectric layer 112-4 may extend above the dielectric layer 112-3 and the first portion 118. The dielectric layer 112-4 may "seal" the first portion 118 and protect it from subsequent wet chemistry.

[0029] Figure 2F shows the assembly of Figure 2E after forming additional interconnect structures 108 within the assembly. These additional interconnect structures 108 may include vias 120, as described above. Vias 120 may extend through dielectric layer 112-4 to dielectric layer 112-3 and contact conductive pads / lines within dielectric layer 112-3.

[0030] FIG. 2G shows the assembly after removal of the carrier 102 from the assembly of FIG. 2F. In some embodiments, mechanical and / or chemical techniques may be used to remove the carrier 102, as known in the art. In some embodiments, if the assembly of FIG. 2G is sufficiently rigid (e.g., if the dielectric layer 112 in which the cavity 114 is formed is glass cloth-based), further processing may continue without attaching the assembly to another carrier to avoid handling or warping issues. In other embodiments where the assembly of FIG. 2G is not sufficiently rigid (e.g., if the entire dielectric layer 112 in which the cavity 114 is formed includes a build-up film), the assembly of FIG. 2G may be attached to another carrier or another semi-finished IC package support 100 (not shown) for further processing.

[0031] 2G and shows the assembly after patterning the nickel 106 and copper 104 such that the nickel 106 and copper 104 are only proximate to the conductive lines 110, as shown, and extend a distance beyond the lateral extent of the first portion 118. In some embodiments, the distance that the patterned copper 104 / nickel 106 extends beyond the lateral extent of the first portion 118 may take the form of any embodiment of the width 158 disclosed herein.

[0032] FIG. 2I shows the assembly of FIG. 2H after providing dielectric layers 112-5 and 112-6 on the assembly and forming additional interconnect structures 108 in and on top of the dielectric layers 112-5 and 112-6. The dielectric layers 112 may be provided in any suitable manner (e.g., by lamination of dielectric films) and the interconnect structures 108 of FIG. 2I may be formed using any suitable technique (e.g., SAP technique). In some embodiments, the additional interconnect structures 108 of the assembly of FIG. 2I may include vias 122 that may be included in the same dielectric layer 112-5 as the patterned copper 104 / nickel 106 (and thus in the same dielectric layer 112 as the material stubs 148 in the IC package support 100, as described further below).

[0033] FIG. 2J shows the assembly after forming another dielectric layer 112-7 on the assembly of FIG. 2I and then forming a cavity 124 through the dielectric layers 112-6 and 112-7 to the dielectric layer 112-5. As shown, the cavity 124 may expose the copper 104. The cavity 124 may be formed using any suitable technique, such as laser drilling (where the copper 104 may act as a laser stop). In some embodiments, the sidewalls 126 of the cavity 124 may be angled to provide the cavity 124 with a narrowing taper toward the conductive line 110. In some embodiments, a desmear operation may be performed after forming the cavity 124. In some embodiments where the dielectric layers 112-5, 112-6, and 112-7 are photoimageable dielectrics, the cavity 124 may be formed by selectively exposing and growing the dielectric layer 112, rather than laser drilling, as is known in the art.

[0034] 2K shows the assembly of FIG. 2J after removing the exposed copper 104 in the cavity 124 and then removing the exposed nickel 106 to leave a stub of material 148, as shown. Any suitable etching technique may be used to remove the copper 104 / nickel 106. In some embodiments, the etch chemistry used to remove the nickel 106 may not damage the underlying magnetic material of the first portion 118, while the etch chemistry used to remove the copper 104 would damage the magnetic material. Thus, the nickel 106 or other material may act to protect the underlying first portion 118 during these operations.

[0035] 2L illustrates the assembly of FIG. 2K after the cavity 124 of the assembly has been filled with a magnetic material to form a second portion 128 of the magnetic structure 150. Although FIG. 2L illustrates the second portion 128 as extending through three dielectric layers 112 (dielectric layers 112-5, 112-6, and 112-7), this is by way of example only and in other embodiments the second portion 128 may extend through any suitable number of dielectric layers 112 (e.g., two, three, four, or five dielectric layers 112). The magnetic material may be provided in the cavity 124 according to any suitable technique, such as any of the techniques described above with reference to FIG. 2D.

[0036] Figure 2M shows the assembly of Figure 2L after forming a dielectric layer 112-8 on the top surface of the assembly. As shown, the dielectric layer 112-8 may extend over the dielectric layer 112-7 and the second portion 128. The dielectric layer 112-8 may "seal" the second portion 128 and protect it from subsequent wet chemistry.

[0037] 2N illustrates the assembly of FIG. 2M after forming additional dielectric layers 112 (e.g., additional dielectric layer 112-9) and additional interconnect structures 108. These additional interconnect structures 108 may include vias 130, as described above. The vias 130 may extend through dielectric layer 112-8 to dielectric layer 112-7 and contact conductive pads / lines in dielectric layer 112-7. Although a particular arrangement of dielectric layers 112 and interconnect structures 108 is shown in FIG. 2N, this is by way of example only and any desired number and arrangement of dielectric layers 112 and interconnect structures 108 may be used.

[0038] Figure 2O shows the assembly after solder resist 132 and openings 136 therein have been provided to expose the conductive contacts on a second side 144 of the assembly of Figure 2N, and solder resist 134 and openings 138 therein have been provided to expose the conductive contacts on a first side 146. The resulting assembly may take the form of IC package support 100 of Figure 1.

[0039] The IC package supports 100 disclosed herein may be included in any suitable electronic component. Figures 3-7 show various examples of devices that may include any of the IC package supports 100 disclosed herein or that may be included in an IC package that also includes any of the IC package supports 100 disclosed herein.

[0040] FIG. 3 is a top view of a wafer 1500 and dies 1502 that may be included in an IC package including one or more IC package supports 100 according to any of the embodiments disclosed herein (e.g., described below with reference to FIG. 5). The wafer 1500 may be constructed from a semiconductor material and may include one or more dies 1502 having IC structures formed on the surface of the wafer 1500. Each of the dies 1502 may be a repeating unit of a semiconductor product including any suitable IC. After fabrication of the semiconductor product is completed, the wafer 1500 may undergo a singulation process in which the dies 1502 are separated from one another to provide separate "chips" of the semiconductor product. The dies 1502 may include one or more transistors (e.g., some of the transistors 1640 of FIG. 4 described below) and / or support circuitry for transferring electrical signals to the transistors and any other IC components. In some embodiments, wafer 1500 or die 1502 may include memory devices (e.g., random access memory (RAM) devices such as static RAM (SRAM) devices, magnetic RAM (MRAM) devices, resistive RAM (RRAM) devices, conductive bridge RAM (CBRAM) devices, etc.), logic devices (e.g., AND gates, OR gates, NAND gates, or NOR gates), or any other suitable circuit elements. Multiple of these devices may be combined on a single die 1502. For example, a memory array formed by multiple memory devices may be formed on the same die 1502 as a processing device (e.g., processing device 1802 of FIG. 7) or other logic configured to store information in the memory devices or execute instructions stored in the memory array.

[0041] FIG. 4 is a side cross-sectional view of an IC device 1600 that may be included in an IC package including one or more IC package supports 100 according to any of the embodiments disclosed herein (e.g., described below with reference to FIG. 5). One or more of the IC devices 1600 may be included in one or more dies 1502 (FIG. 3). The IC devices 1600 may be formed on a substrate 1602 (e.g., wafer 1500 of FIG. 3) and included in a die (e.g., die 1502 of FIG. 3). The substrate 1602 may be a semiconductor substrate comprised of a semiconductor material system, including, for example, an n-type or p-type material system (or a combination of both). The substrate 1602 may include, for example, a crystalline substrate formed using bulk silicon or a silicon-on-insulator (SOI) substructure. In some embodiments, the substrate 1602 may be formed using alternative materials. Such materials may or may not be combined with silicon including, but not limited to, germanium, indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide. Additional materials classified as II-VI, III-V, or IV may also be used to form the substrate 1602. A few examples of materials from which the substrate 1602 may be formed are described here, but any material that can serve as a foundation for the IC device 1600 may be used. The substrate 1602 may be part of a singulated die (e.g., die 1502 of FIG. 3) or a wafer (e.g., wafer 1500 of FIG. 3).

[0042] The IC device 1600 may include one or more device layers 1604 disposed on a substrate 1602. The device layer 1604 may include features of one or more transistors 1640 (e.g., metal oxide semiconductor field effect transistors (MOSFETs)) formed on the substrate 1602. The device layer 1604 may include, for example, one or more source and / or drain (S / D) regions 1620, a gate 1622 for controlling the flow of current in the transistor 1640 between the S / D regions 1620, and one or more S / D contacts 1624 for transferring electrical signals to / from the S / D regions 1620. The transistors 1640 may include additional features not shown for clarity, such as device isolation regions, gate contacts, etc. The transistors 1640 are not limited to the types and configurations shown in FIG. 4 and may include a variety of other types and configurations, such as, for example, planar transistors, non-planar transistors, or a combination of both. Planar transistors may include bipolar junction transistors (BJTs), heterojunction bipolar transistors (HBTs) or high electron mobility transistors (HEMTs). Non-planar transistors may include FinFET transistors such as double-gate or tri-gate transistors, and wrap-around or all-around gate transistors such as nanoribbon and nanowire transistors.

[0043] Each transistor 1640 may include a gate 1622 formed of at least two layers, a gate dielectric, and a gate electrode. The gate dielectric may include one layer or a stack of layers. The one or more layers may include silicon oxide, silicon dioxide, silicon carbide, and / or high-k dielectric materials. The high-k dielectric materials may include elements such as hafnium, silicon, oxygen, titanium, tantalum, lanthanum, aluminum, zirconium, barium, strontium, yttrium, lead, scandium, niobium, and zinc. Examples of high-k materials that may be used in the gate dielectric include, but are not limited to, hafnium oxide, hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate. In some embodiments, an annealing process may be performed on the gate dielectric to improve the quality of the gate dielectric when high-k materials are used.

[0044] A gate electrode may be formed on the gate dielectric and may include at least one p-type work function metal or n-type work function metal depending on whether the transistor 1640 is to be a p-type metal oxide semiconductor (PMOS) or n-type metal oxide semiconductor (NMOS) transistor. In some implementations, the gate electrode may consist of a stack of two or more metal layers, where one or more metal layers are work function metal layers and at least one metal layer is a fill metal layer. Additional metal layers, such as barrier layers, may be included for other purposes. For PMOS transistors, metals that may be used in the gate electrode include, but are not limited to, ruthenium, palladium, platinum, cobalt, nickel, conductive metal oxides (e.g., ruthenium oxide), and any of the metals described below with reference to NMOS transistors (e.g., for work function tuning). For NMOS transistors, metals that may be used in the gate electrode include, but are not limited to, hafnium, zirconium, titanium, tantalum, aluminum, alloys of these metals, carbides of these metals (e.g., hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, and aluminum carbide), and any of the metals mentioned above with reference to PMOS transistors (e.g., for work function tuning).

[0045] In some embodiments, when viewed as a cross-section of the transistor 1640 along the source-channel-drain direction, the gate electrode may comprise a U-shaped structure including a bottom portion substantially parallel to the surface of the substrate and two sidewall portions substantially perpendicular to the top surface of the substrate. In other embodiments, at least one of the metal layers forming the gate electrode may simply be a planar layer that is substantially parallel to the top surface of the substrate and does not include sidewall portions substantially perpendicular to the top surface of the substrate. In other embodiments, the gate electrode may comprise a combination of U-shaped and planar non-U-shaped structures. For example, the gate electrode may comprise one or more U-shaped metal layers formed on one or more planar non-U-shaped layers.

[0046] In some embodiments, a pair of sidewall spacers may be formed on opposing sides of the gate stack to surround the gate stack. The sidewall spacers may be formed from materials such as silicon nitride, silicon oxide, silicon carbide, carbon-doped silicon nitride, silicon oxynitride, etc. Processes for forming sidewall spacers are well known in the art and generally include deposition and etching process steps. In some embodiments, multiple spacer pairs may be used, for example, two, three, or four pairs of sidewall spacers may be formed on opposing sides of the gate stack.

[0047] The S / D regions 1620 may be formed in the substrate 1602 adjacent to the gates 1622 of each transistor 1640. The S / D regions 1620 may be formed using, for example, an implantation / diffusion process or an etching / deposition process. In the former process, dopants such as boron, aluminum, antimony, phosphorous, or arsenic may be ion-implanted into the substrate 1602 to form the S / D regions 1620. The ion-implantation process may be followed by an annealing process that activates the dopants and diffuses them further into the substrate 1602. In the latter process, the substrate 1602 may first be etched to form cavities at the locations of the S / D regions 1620. An epitaxial deposition process may then be performed to fill the cavities with the material used to fabricate the S / D regions 1620. In some implementations, the S / D regions 1620 may be fabricated using silicon alloys such as silicon germanium or silicon carbide. In some embodiments, the epitaxially deposited silicon alloy may be doped in situ with dopants such as boron, arsenic, or phosphorous. In some embodiments, the S / D regions 1620 may be formed using one or more alternative semiconductor materials, such as germanium or a III-V material or alloy. In further embodiments, one or more layers of metal and / or metal alloy may be used to form the S / D regions 1620.

[0048] Electrical signals, such as power and / or input / output (I / O) signals, may be transferred to and / or from devices (e.g., transistors 1640) in the device layer 1604 through one or more interconnect layers (shown in FIG. 4 as interconnect layers 1606-1610) disposed on the device layer 1604. For example, conductive features (e.g., gates 1622 and S / D contacts 1624) of the device layer 1604 may be electrically coupled with interconnect structures 1628 of the interconnect layers 1606-1610. The one or more interconnect layers 1606-1610 may form a metallization stack (also referred to as an “ILD” stack) 1619 of the IC device 1600.

[0049] The interconnect structures 1628 may be arranged within the interconnect layers 1606-1610 to transfer electrical signals according to a variety of designs (notably, the arrangement is not limited to the particular configuration of the interconnect structures 1628 shown in Figure 4). Although a particular number of interconnect layers 1606-1610 are shown in Figure 4, embodiments of the present disclosure include IC devices having more or fewer interconnect layers than are shown.

[0050] In some embodiments, the interconnect structures 1628 may include lines 1628a and / or vias 1628b filled with a conductive material, such as a metal. The lines 1628a may be arranged to transfer electrical signals in a direction of a plane that is substantially parallel to a surface of the substrate 1602 on which the device layer 1604 is formed. For example, the lines 1628a may transfer electrical signals in a direction into and out of the page from the perspective of FIG. 4. The vias 1628b may be arranged to transfer electrical signals in a direction of a plane that is substantially perpendicular to the surface of the substrate 1602 on which the device layer 1604 is formed. In some embodiments, the vias 1628b may electrically couple together the lines 1628a of different interconnect layers 1606-1610.

[0051] 4, the interconnect layers 1606-1610 can include a dielectric material 1626 disposed between interconnect structures 1628. In some embodiments, the dielectric material 1626 disposed between the interconnect structures 1628 in different ones of the interconnect layers 1606-1610 can have different compositions. In other embodiments, the composition of the dielectric material 1626 between the different interconnect layers 1606-1610 can be the same.

[0052] A first interconnect layer 1606 may be formed over the device layer 1604. As shown, in some embodiments, the first interconnect layer 1606 may include lines 1628a and / or vias 1628b. The lines 1628a of the first interconnect layer 1606 may be coupled to contacts (e.g., S / D contacts 1624) of the device layer 1604.

[0053] A second interconnect layer 1608 may be formed over the first interconnect layer 1606. In some embodiments, the second interconnect layer 1608 may include vias 1628b for coupling lines 1628a of the second interconnect layer 1608 with lines 1628a of the first interconnect layer 1606. Although the lines 1628a and vias 1628b are structurally depicted as lines within each interconnect layer (e.g., within the second interconnect layer 1608) for clarity, in some embodiments the lines 1628a and vias 1628b may be structurally and / or materially continuous (e.g., filled simultaneously during a dual damascene process).

[0054] The third interconnect layer 1610 (and additional interconnect layers, as needed) may be formed successively on the second interconnect layer 1608 according to techniques and configurations similar to those described in connection with the second interconnect layer 1608 or the first interconnect layer 1606. In some embodiments, interconnect layers "higher" in the metallization stack 1619 in the IC device 1600 (i.e., further away from the device layer 1604) may be thicker.

[0055] The IC device 1600 may include a solder resist material 1634 (e.g., polyimide or similar material) and one or more conductive contacts 1636 formed on the interconnect layers 1606-1610. In FIG. 4, the conductive contacts 1636 are shown to take the form of bond pads. The conductive contacts 1636 may be electrically coupled to the interconnect structure 1628 and may be configured to transfer electrical signals of the transistors 1640 to other external devices. For example, solder bonds may be formed on the one or more conductive contacts 1636 to mechanically and / or electrically couple a chip including the IC device 1600 to another component (e.g., a circuit board). The IC device 1600 may include additional or alternative structures for transferring electrical signals from the interconnect layers 1606-1610. For example, the conductive contacts 1636 may include other similar features (e.g., posts) that transfer electrical signals to external components.

[0056] 5 is a side cross-sectional view of an example IC package 1650 that may include one or more IC package supports 100 according to any of the embodiments disclosed herein. For example, the package substrate 1652 and / or the interposer 1657 may be an IC package support 100 according to any of the embodiments disclosed herein. In some embodiments, the IC package 1650 may be a system-in-package (SiP).

[0057] The package substrate 1652 may be formed of a dielectric material (e.g., ceramic, build-up film, epoxy film with filler particles therein, etc.) and may have conductive paths extending through the dielectric material between the surface 1672 and the surface 1674, or between different locations on the surface 1672 and / or between different locations on the surface 1674. These conductive paths may take the form of any of the interconnects 1628 described above with reference to FIG.

[0058] The package substrate 1652 may include conductive contacts 1663 that are coupled to conductive paths 1662 through the package substrate 1652 to enable circuitry in the die 1656 and / or interposer 1657 to be electrically coupled to various of the conductive contacts 1664 (or to other devices (not shown) included in the package substrate 1652).

[0059] The IC package 1650 may include an interposer 1657 coupled to a package substrate 1652 via conductive contacts 1661 of the interposer 1657, an FLI 1665, and conductive contacts 1663 of the package substrate 1652. The FLI 1665 shown in FIG. 5 is a solder bump, although any suitable FLI 1665 may be used. In some embodiments, the interposer 1657 may not be included in the IC package 1650, and instead the die 1656 may be directly coupled to the conductive contacts 1663 at the surface 1672 by the FLI 1665.

[0060] The IC package 1650 may include one or more dies 1656 coupled to an interposer 1657 via conductive contacts 1654 of the die 1656, FLIs 1658, and conductive contacts 1660 of the interposer 1657. The conductive contacts 1660 may be coupled to conductive paths (not shown) through the interposer 1657 to allow circuitry in the die 1656 to be electrically coupled to various of the conductive contacts 1661 (or to other devices (not shown) included in the interposer 1657). The FLIs 1658 shown in FIG. 5 are solder bumps, although any suitable FLIs 1658 may be used. As used herein, a "conductive contact" may refer to a portion of a conductive material (e.g., a metal) that serves as an interface between different components. A conductive contact may be recessed into, flush with, or extend away from a surface of a component, and may take any suitable form (e.g., a conductive pad or socket).

[0061] In some embodiments, an underfill material 1666 may be disposed between the package substrate 1652 and the interposer 1657 around the FLI 1665, and a mold compound 1668 may be disposed around the die 1656 and the interposer 1657 and in contact with the package substrate 1652. In some embodiments, the underfill material 1666 may be the same as the mold compound 1668. An exemplary material that may be used for the underfill material 1666 and the mold compound 1668 is an epoxy mold material, if desired. The SLIs 1670 may be coupled to the conductive contacts 1664. The SLIs 1670 shown in FIG. 5 are solder balls (e.g., for a ball grid array (BGA) configuration), although any suitable SLIs 16770 (e.g., pins in a pin grid array configuration or lands in a land grid array configuration) may be used. SLI 1670 may be used to couple IC package 1650 to another component, such as a circuit board (e.g., a motherboard), an interposer, or another IC package as known in the art and described below with reference to FIG. 6.

[0062] The die 1656 may take the form of any of the embodiments of die 1502 described herein (e.g., may include any of the embodiments of IC device 1600). In embodiments in which the IC package 1650 includes multiple die 1656, the IC package 1650 may be referred to as a multi-chip package (MCP). The die 1656 may include circuitry for performing any desired function. For example, one or more of the die 1656 may be a logic die (e.g., a silicon-based die) and one or more of the die 1656 may be a memory die (e.g., a high-bandwidth memory).

[0063] Although the IC package 1650 shown in FIG. 5 is a flip chip package, other package architectures may be used. For example, the IC package 1650 may be a BGA package, such as an embedded wafer level ball grid array (eWLB) package. In another example, the IC package 1650 may be a wafer level chip scale package (WLCSP) or a panel fan-out (FO) package. Although two dies 1656 are shown in the IC package 1650 of FIG. 5, the IC package 1650 may include any desired number of dies 1656. The IC package 1650 may include additional passive components, such as surface mounted resistors, capacitors, and inductors, disposed on either the first surface 1672 or the second surface 1674 of the package substrate 1652 or the surface of the interposer 1657. More generally, the IC package 1650 may include any other active or passive components known in the art.

[0064] 6 is a side cross-sectional view of an IC device assembly 1700 that may include one or more IC package supports 100 according to any of the embodiments disclosed herein. The IC device assembly 1700 includes a number of components disposed on a circuit board 1702 (which may be, for example, a motherboard). The IC device assembly 1700 includes components disposed on a first surface 1740 of the circuit board 1702 and an opposing second surface 1742 of the circuit board 1702. In general, the components may be disposed on one or both of the surfaces 1740 and 1742. Any of the IC packages described below with reference to the IC device assembly 1700 may take the form of any of the embodiments of the IC package 1650 described above with reference to FIG. 5 (e.g., may include one or more IC package supports 100 as package substrate 1652 or interposer 1657).

[0065] In some embodiments, the circuit board 1702 may be a printed circuit board (PCB) that includes multiple metal layers separated from one another by layers of dielectric material and interconnected by conductive vias. Any one or more of the metal layers may be formed in a desired circuit pattern to transfer electrical signals (optionally in conjunction with other metal layers) between components coupled to the circuit board 1702. In other embodiments, the circuit board 1702 may be a non-PCB substrate.

[0066] The IC device assembly 1700 shown in Figure 6 includes a package-on-interposer structure 1736 coupled to a first surface 1740 of a circuit board 1702 by a coupling component 1716. The coupling component 1716 may electrically and mechanically couple the package-on-interposer structure 1736 to the circuit board 1702 and may include solder balls (shown in Figure 6), male and female portions of a socket, adhesive, underfill material, and / or any other suitable electrical and / or mechanical coupling structure.

[0067] The package-on-interposer structure 1736 may include an IC package 1720 coupled to the package interposer 1704 by a coupling component 1718. The coupling component 1718 may take any suitable form for the application, such as those described above with reference to the coupling component 1716. Although a single IC package 1720 is shown in FIG. 6, multiple IC packages may be coupled to the package interposer 1704, and in fact additional interposers may be coupled to the package interposer 1704. The package interposer 1704 may provide an intermediate substrate used to bridge the circuit board 1702 and the IC package 1720. The IC package 1720 may be or include, for example, a die (die 1502 of FIG. 3), an IC device (e.g., IC device 1600 of FIG. 4), or any other suitable component. In general, the package interposer 1704 may spread connections to a wider pitch or re-route certain connections to different connections. For example, the package interposer 1704 may couple an IC package 1720 (e.g., a die) to a set of BGA conductive contacts of the mating component 1716 for coupling to the circuit board 1702. In the embodiment shown in FIG. 6, the IC package 1720 and the circuit board 1702 are attached to opposite sides of the package interposer 1704. In other embodiments, the IC package 1720 and the circuit board 1702 may be attached to the same side of the package interposer 1704. In some embodiments, three or more components may be interconnected by the package interposer 1704.

[0068] In some embodiments, the package interposer 1704 may be formed as a PCB including multiple metal layers separated from each other by layers of dielectric material and interconnected by conductive vias. In some embodiments, the package interposer 1704 may be formed of a polymeric material, such as epoxy, fiberglass reinforced epoxy, epoxy with inorganic fillers, ceramic material, or polyimide. In some embodiments, the package interposer 1704 may be formed of alternative rigid or flexible materials. Such materials may include the same materials mentioned above for semiconductor substrates, such as silicon, germanium, and other III-V and IV materials. The package interposer 1704 may include metal interconnects 1708 and vias 1710, including but not limited to through silicon vias (TSVs) 1706. The package interposer 1704 may further include embedded devices 1714, including both passive and active devices. Such devices may include, but are not limited to, capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, electrostatic discharge (ESD) devices, and memory devices. More complex devices such as radio frequency devices, power amplifiers, power management devices, antennas, arrays, sensors, and microelectromechanical systems (MEMS) devices may also be formed on the package interposer 1704. The package-on-interposer structure 1736 may take the form of any of the package-on-interposer structures known in the art.

[0069] The IC device assembly 1700 may include an IC package 1724 coupled to a first surface 1740 of the circuit board 1702 by a coupling component 1722. The coupling component 1722 may take the form of any of the embodiments described above with reference to the coupling component 1716, and the IC package 1724 may take the form of any of the embodiments described above with reference to the IC package 1720.

[0070] 6 includes a package-on-package structure 1734 coupled to a second surface 1742 of a circuit board 1702 by a coupling component 1728. The package-on-package structure 1734 may include an IC package 1726 and an IC package 1732 coupled together by a coupling component 1730 such that the IC package 1726 is disposed between the circuit board 1702 and the IC package 1732. The coupling components 1728 and 1730 may take the form of any of the embodiments of the coupling component 1716 described above, and the IC packages 1726 and 1732 may take the form of any of the embodiments of the IC package 1720 described above. The package-on-package structure 1734 may be configured according to any of the package-on-package structures known in the art.

[0071] 7 is a block diagram of an example electrical device 1800 that may include one or more IC package supports 100 according to any of the embodiments disclosed herein. Any suitable number of components of the electrical device 1800 may include one or more of the IC device assembly 1700, IC package 1650, IC device 1600, or die 1502 disclosed herein. Although multiple components are shown in FIG. 7 as being included in the electrical device 1800, any one or more of these components may be omitted or duplicated as appropriate for the application. In some embodiments, some or all of the components included in the electrical device 1800 may be mounted on one or more motherboards. In some embodiments, some or all of these components are fabricated on a single system-on-chip (SoC) die.

[0072] 7, but may include interface circuitry for coupling one or more components. For example, the electrical device 1800 may not include a display device 1806, but may include display device interface circuitry (e.g., connectors and driver circuits) to which the display device 1806 may be coupled. In another set of examples, the electrical device 1800 may not include an audio input device 1824 or an audio output device 1808, but may include audio input or output device interface circuitry (e.g., connectors and supporting circuits) to which the audio input device 1824 or the audio output device 1808 may be coupled.

[0073] The electrical device 1800 may include a processing device 1802 (e.g., one or more processing devices). As used herein, the term "processing device" or "processor" may refer to any device or portion of a device that processes electronic data from registers and / or memory and converts the electronic data into other electronic data that may be stored in registers and / or memory. The processing device 1802 may include one or more digital signal processors (DSPs), application specific integrated circuits (ASICs), central processing units (CPUs), graphics processing units (GPUs), cryptographic processors (dedicated processors that execute cryptographic algorithms in hardware), server processors, or any other suitable processing devices. The electrical device 1800 may include a memory 1804. The memory 1804 may itself include one or more memory devices, such as volatile memory (e.g., dynamic random access memory (DRAM)), non-volatile memory (e.g., read only memory (ROM)), flash memory, solid state memory, and / or a hard drive. In some embodiments, the memory 1804 may include memory that shares a die with the processing device 1802. This memory may be used as cache memory and may include embedded dynamic random access memory (eDRAM) or spin-transfer torque magnetic random access memory (STT-MRAM).

[0074] In some embodiments, the electrical device 1800 may include a communications chip 1812 (e.g., one or more communications chips). For example, the communications chip 1812 may be configured to manage wireless communications for the transfer of data to and from the electrical device 1800. The term "wireless" and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communications channels, etc. that may communicate data through the use of modulated electromagnetic radiation through a non-solid medium. Although the associated devices may not include wiring in some embodiments, the term does not imply that the associated devices do not include any wiring.

[0075] The communications chip 1812 may implement any of a number of wireless standards or protocols, including, but not limited to, Institute of Electrical and Electronics Engineers (IEEE) standards, including Wi-Fi (IEEE 802.11 family), IEEE 802.16 standard (e.g., IEEE 802.16-2005 amendment), Long Term Evolution (LTE) project with any amendments, updates and / or revisions (e.g., Advanced LTE project, Ultra Mobile Broadband (UMB) project (also referred to as "3GPP2"), etc.). Broadband Wireless Access (BWA) networks compatible with IEEE 802.16 are commonly referred to as WiMAX networks. This acronym stands for Worldwide Interoperability for Microwave Access and is a certification mark for products that have passed IEEE 802.16 standard compliance and interoperability testing. The communications chip 1812 may operate according to Global System for Mobile Communications (GSM), General Packet Radio Service (GPRS), Universal Mobile Telecommunications System (UMTS), High Speed ​​Packet Access (HSPA), Evolved HSPA (E-HSPA or LTE network). The communications chip 1812 may operate according to Enhanced Data for GSM Evolution (EDGE), GSM EDGE Radio Access Network (GERAN), Universal Terrestrial Radio Access Network (UTRAN) or Evolved UTRAN (E-UTRAN). The communications chip 1812 may operate according to Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Digital Enhanced Cordless Telecommunications (DECT), Evolution Data Optimized (EV-DO) and their derivatives, as well as any other wireless protocols designated as 3G, 4G, 5G and beyond. In other embodiments, the communications chip 1812 may operate according to other wireless protocols. The electrical device 1800 may include an antenna 1822 for facilitating wireless communication and / or for receiving other wireless communications (such as AM or FM radio transmissions).

[0076] In some embodiments, the communications chip 1812 may manage wired communications, such as electrical, optical, or any other suitable communications protocol (e.g., Ethernet). As noted above, the communications chip 1812 may include multiple communications chips. For example, a first communications chip 1812 may be dedicated to shorter-range wireless communications, such as Wi-Fi or Bluetooth, and a second communications chip 1812 may be dedicated to longer-range wireless communications, such as Global Positioning System (GPS), EDGE, GPRS, CDMA, WiMAX, LTE, EV-DO, or others. In some embodiments, the first communications chip 1812 may be dedicated to wireless communications, and the second communications chip 1812 may be dedicated to wired communications.

[0077] The electric device 1800 may include a battery / power circuitry 1814. The battery / power circuitry 1814 may include one or more energy storage devices (e.g., batteries or capacitors) and / or circuitry for coupling components of the electric device 1800 to an energy source (e.g., AC line power) separate from the electric device 1800.

[0078] The electrical device 1800 may include a display device 1806 (or corresponding interface circuitry as described above). The display device 1806 may include any visual indicator, such as a head-up display, a computer monitor, a projector, a touch screen display, a liquid crystal display (LCD), a light emitting diode display, or a flat panel display.

[0079] The electrical device 1800 may include an audio output device 1808 (or corresponding interface circuitry as described above). The audio output device 1808 may include any device that generates an audible indicator, such as a speaker, a headset or earbuds.

[0080] The electrical device 1800 may include an audio input device 1824 (or corresponding interface circuitry as described above). The audio input device 1824 may include any device that generates a signal representing sound, such as a microphone, a microphone array, or a digital device (e.g., a device with a Musical Instrument Digital Interface (MIDI) output).

[0081] The electrical device 1800 may include a GPS device 1818 (or corresponding interface circuitry as described above), which may be in communication with a satellite-based system and may receive the position of the electrical device 1800 in a manner known in the art.

[0082] The electrical device 1800 may include other output devices 1810 (or corresponding interface circuits as described above). Examples of other output devices 1810 may include an audio codec, a video codec, a printer, a wired or wireless transmitter for providing information to other devices, or additional storage devices.

[0083] The electrical device 1800 may include other input devices 1820 (or corresponding interface circuitry as described above). Examples of other input devices 1820 may include an accelerometer, a gyroscope, a compass, an imaging device, a keyboard, a cursor control device such as a mouse, a stylus, a touch pad, a barcode reader, a quick response (QR) code reader, any sensor, or a radio frequency identification (RFID) reader.

[0084] Electrical device 1800 may have any desired form factor, such as a handheld or mobile electrical device (e.g., a mobile phone, a smart phone, a mobile Internet device, a music player, a tablet computer, a laptop computer, a netbook computer, an ultrabook computer, a personal digital assistant (PDA), an ultra-mobile personal computer, etc.), a desktop electrical device, a server device or other networked computing component, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a vehicle control unit, a digital camera, a digital video recorder, or a wearable electrical device. In some embodiments, electrical device 1800 may be any other electronic device that processes data.

[0085] The following paragraphs provide various examples of the embodiments disclosed herein.

[0086] Example 1 is an integrated circuit (IC) package support that includes a conductive line, a magnetic structure around the conductive line, and a number of stubs of material on sides of the magnetic structure.

[0087] Example 2 includes the subject matter of example 1, further providing that the plurality of material stubs comprises a laser stopping material.

[0088] Example 3 includes the subject matter of any of Examples 1-2, further providing that the plurality of material stubs comprises copper.

[0089] Example 4 includes the subject matter described in example 3, further specifying that the copper of the plurality of material stubs has a thickness between 3 microns and 12 microns.

[0090] Example 5 includes the subject matter of any of Examples 3-4, further providing that the plurality of material stubs comprises nickel.

[0091] Example 6 includes the subject matter of example 5, further specifying that the nickel of the plurality of material stubs has a thickness between 3 microns and 10 microns.

[0092] Example 7 includes the subject matter of any of Examples 5-6, further providing that a surface of the conductive line is coplanar with a surface of the nickel of the plurality of material stubs.

[0093] Example 8 includes the subject matter of any of Examples 5-7, further providing that the nickel side of the plurality of material stubs is between the copper side of the plurality of material stubs and a side of the conductive line.

[0094] Example 9 includes the subject matter of any of Examples 1-2, further providing that the plurality of material stubs comprises nickel.

[0095] Example 10 includes the subject matter of example 9, further specifying that the nickel of the plurality of material stubs has a thickness between 3 microns and 10 microns.

[0096] Example 11 includes the subject matter of any of Examples 9-10, further providing that a surface of the conductive line is coplanar with a surface of the nickel of the plurality of material stubs.

[0097] Example 12 includes the subject matter of any of examples 1-11, further providing that a surface of the conductive line is coplanar with a surface of the plurality of material stubs.

[0098] Example 13 includes the subject matter of any of Examples 1-12, further providing that the magnetic structure has a first portion and a second portion, the first portion of the magnetic structure is on a top and a side of the conductive line, the second portion of the magnetic structure is on a bottom surface of the conductive line, and the first portion includes a tapered shape narrowing toward the conductive line.

[0099] Example 14 includes the subject matter of example 13, further providing that the second portion includes a tapered shape narrowing toward the conductive line.

[0100] Example 15 includes the subject matter of any of Examples 1-14, further providing that the magnetic structure has a height between 100 microns and 200 microns.

[0101] Example 16 includes the subject matter of any of Examples 1-15, further defining that the conductive line has a thickness between 10 microns and 40 microns.

[0102] Example 17 includes the subject matter of any of Examples 1 to 16, further including a first layer of dielectric material on a first surface of the magnetic structure and a second layer of dielectric material on a second surface of the magnetic structure, the second surface facing the first surface.

[0103] Example 18 includes the subject matter of any of Examples 1-17, further providing that the magnetic structure comprises magnetic particles embedded in a polymer matrix.

[0104] Example 19 includes the subject matter of any of Examples 1-18, further including a conductive via that is at least partially coplanar with the plurality of material stubs, the conductive via being embedded in a layer of dielectric material and extending between a top of the layer of dielectric material and a bottom of the layer of dielectric material.

[0105] Example 20 includes the subject matter of any of Examples 1-19, further including a conductive via that is at least partially coplanar with the magnetic structure, extending from a top of a layer of dielectric material past a bottom of the layer of dielectric material, the layer of dielectric material being on a surface of the magnetic structure.

[0106] Example 21 includes the subject matter of any of Examples 1 to 20, further providing that the IC package support is a package substrate.

[0107] Example 22 includes the subject matter of any of Examples 1-20, and further provides that the IC package support is an interposer.

[0108] Example 23 includes the subject matter of any of Examples 1-22, further providing that the conductive lines and magnetic structure are part of an inductor.

[0109] Example 24 includes the subject matter of example 23, further providing that the IC package support includes a plurality of inductors.

[0110] Example 25 is an integrated circuit (IC) package support comprising a conductive line and a magnetic structure surrounding the conductive line, the magnetic structure having a first portion and a second portion, the first portion of the magnetic structure being on a top and side surface of the conductive line and the second portion of the magnetic structure being on a bottom surface of the conductive line, the first portion including a tapered shape narrowing toward the conductive line, and the second portion including a tapered shape narrowing toward the conductive line.

[0111] Example 26 includes the subject matter of example 25, further providing that the magnetic structure has a height between 100 microns and 200 microns.

[0112] Example 27 includes the subject matter of any of Examples 25-26, further providing that the conductive line has a thickness between 10 microns and 40 microns.

[0113] Example 28 includes the subject matter of any of Examples 25-27, further including a first layer of dielectric material at a first surface of the magnetic structure and a second layer of dielectric material at a second surface of the magnetic structure, the second surface facing the first surface.

[0114] Example 29 includes the subject matter of any of Examples 25-28, further providing that the magnetic structure comprises magnetic particles embedded in a polymer matrix.

[0115] Example 30 includes the subject matter of any of Examples 25-29, further including a conductive via that is at least partially coplanar with the magnetic structure, the conductive via being embedded in a layer of dielectric material and extending between a top of the layer of dielectric material and a bottom of the layer of dielectric material.

[0116] Example 31 includes the subject matter of any of Examples 25-30, further including a conductive via that is at least partially coplanar with the magnetic structure, extending from a top of a layer of dielectric material beyond a bottom of the layer of dielectric material, the layer of dielectric material being on a surface of the magnetic structure.

[0117] Example 32 includes the subject matter of any of Examples 25 to 31, and further provides that the IC package support is a package substrate.

[0118] Example 33 includes the subject matter of any of Examples 25 to 31, and further provides that the IC package support is an interposer.

[0119] Example 34 includes the subject matter of any of examples 25-33, further providing that the conductive lines and magnetic structure are part of an inductor.

[0120] Example 35 includes the subject matter of example 34, further providing that the IC package support includes a plurality of inductors.

[0121] Example 36 is an integrated circuit (IC) package support that includes a conductive line, a magnetic structure around the conductive line, and a plurality of copper portions on sides of the magnetic structure.

[0122] Example 37 includes the subject matter of Example 36, further providing that the copper portion has a thickness between 3 microns and 12 microns.

[0123] Example 38 includes the subject matter of any of Examples 36-37, further providing that the copper portion contacts the magnetic structure and a dielectric material proximate to the magnetic structure.

[0124] Example 39 includes the subject matter of any of Examples 36-38, further providing that the magnetic structure has a first portion and a second portion, the first portion of the magnetic structure is on a top and side surface of the conductive line, the second portion of the magnetic structure is on a bottom surface of the conductive line, and the first portion includes a tapered shape narrowing toward the conductive line.

[0125] Example 40 includes the subject matter of example 39, further providing that the second portion includes a tapered shape narrowing toward the conductive line.

[0126] Example 41 includes the subject matter of any of Examples 39-40, further providing that the copper portion is proximate an interface between the first portion and the second portion.

[0127] Example 42 includes the subject matter of any of examples 36-41, further providing that the magnetic structure has a height between 100 microns and 200 microns.

[0128] Example 43 includes the subject matter of any of Examples 36-42, further providing that the conductive line has a thickness between 10 microns and 40 microns.

[0129] Example 44 includes the subject matter of any of examples 36-43, further including a first layer of dielectric material at a first surface of the magnetic structure and a second layer of dielectric material at a second surface of the magnetic structure, the second surface facing the first surface.

[0130] Example 45 includes the subject matter of any of Examples 36-44, further defining the magnetic structure comprising magnetic particles embedded in a polymer matrix.

[0131] Example 46 includes the subject matter of any of Examples 36-45, further including a conductive via that is at least partially coplanar with the copper portion, the conductive via being embedded in a layer of dielectric material and extending between a top of the layer of dielectric material and a bottom of the layer of dielectric material.

[0132] Example 47 includes the subject matter of any of Examples 36-46, further including a conductive via that is at least partially coplanar with the magnetic structure, extending from a top of the layer of dielectric material beyond a bottom of the layer of dielectric material, the layer of dielectric material being on a surface of the magnetic structure.

[0133] Example 48 includes the subject matter of any of Examples 36 to 47, further providing that the IC package support is a package substrate.

[0134] Example 49 includes the subject matter of any of Examples 36-47, and further provides that the IC package support is an interposer.

[0135] Example 50 includes the subject matter of any of examples 36-49, further providing that the conductive lines and magnetic structure are part of an inductor.

[0136] Example 51 includes the subject matter of example 50, further providing that the IC package support includes a plurality of inductors.

[0137] Example 52 is an integrated circuit (IC) package comprising a package support according to any of Examples 1 to 51 and one or more dies coupled to the package support.

[0138] Example 53 is a computing device comprising the IC package of Example 52 and a circuit board coupled to the IC package.

[0139] Example 54 includes the subject matter of example 53, further including an antenna coupled to the circuit board.

[0140] Example 55 includes the subject matter of any of Examples 53-54, further including a touch screen display coupled to the circuit board.

[0141] Example 56 is a method that includes any of the manufacturing methods disclosed herein. [Other possible items] [Item 1] A conductive wire; a magnetic structure surrounding the conductive line; and a plurality of stubs of material on the sides of the magnetic structure; 1. An integrated circuit (IC) package support comprising: [Item 2] 2. The IC package support of claim 1, wherein the plurality of material stubs comprises a laser stop material. [Item 3] 2. The IC package support of claim 1, wherein the plurality of material stubs comprises copper. [Item 4] 4. The IC package support of claim 3, wherein the plurality of material stubs comprises nickel. [Item 5] 5. The IC package support of claim 4, wherein a surface of the conductive line is flush with the nickel surfaces of the plurality of material stubs. [Item 6] 5. The IC package support of claim 4, wherein the nickel sides of the material stubs are between the copper sides of the material stubs and the conductive line sides. [Item 7] 2. The IC package support of claim 1, wherein the plurality of material stubs comprises nickel. [Item 8] 8. The IC package support of claim 7, wherein a surface of the conductive line is flush with the nickel surfaces of the plurality of material stubs. [Item 9] 2. The IC package support of claim 1, wherein a surface of the conductive line is flush with a surface of the plurality of material stubs. [Item 10] 2. The IC package support of claim 1, wherein the magnetic structure has a first portion and a second portion, the first portion of the magnetic structure being on a top and side surface of the conductive line, the second portion of the magnetic structure being on a bottom surface of the conductive line, and the first portion including a tapered shape narrowing toward the conductive line. [Item 11] A conductive wire; a magnetic structure around the conductive line; Equipped with the magnetic structure has a first portion and a second portion, the first portion of the magnetic structure being on a top and side surface of the conductive line, the second portion of the magnetic structure being on a bottom surface of the conductive line, the first portion including a tapered shape narrowing toward the conductive line, and the second portion including a tapered shape narrowing toward the conductive line; Integrated circuit (IC) package supports. [Item 12] a first layer of dielectric material on a first surface of the magnetic structure; a second layer of dielectric material on a second surface of the magnetic structure, the second surface facing the first surface; and Item 12. The IC package support of item 11, further comprising: [Item 13] Item 12. The IC package support of item 11, wherein the magnetic structure has magnetic particles embedded in a polymer matrix. [Item 14] a conductive via at least partially coplanar with the magnetic structure, the conductive via being embedded in a layer of dielectric material and extending between a top of the layer of dielectric material to a bottom of the layer of dielectric material; Item 12. The IC package support of item 11, further comprising: [Item 15] a conductive via that is at least partially coplanar with the magnetic structure, the conductive via extending from a top of a layer of dielectric material past a bottom of the layer of dielectric material, the layer of dielectric material being on a surface of the magnetic structure; Item 12. The IC package support of item 11, further comprising: [Item 16] A conductive wire; a magnetic structure surrounding the conductive line; and a plurality of copper portions on the sides of the magnetic structure; 1. An integrated circuit (IC) package support comprising: [Item 17] Item 17. The IC package support of item 16, wherein the copper portions are in contact with the magnetic structure and with a dielectric material proximate to the magnetic structure. [Item 18] 17. The IC package support of claim 16, wherein the magnetic structure has a first portion and a second portion, the first portion of the magnetic structure is on a top and side surface of the conductive line, the second portion of the magnetic structure is on a bottom surface of the conductive line, and the first portion includes a tapered shape narrowing toward the conductive line. [Item 19] Item 19. The IC package support of item 18, wherein the second portion includes a tapered shape that narrows toward the conductive line. [Item 20] Item 19. The IC package support of item 18, wherein the plurality of copper portions are proximate an interface between the first portion and the second portion.

Claims

1. A conductive wire; a magnetic structure surrounding the conductive line; a stub of material on a side of the magnetic structure; 1. An integrated circuit (IC) package support comprising:

2. The IC package support of claim 1 , wherein the material stub comprises a laser stopping material.

3. The IC package support of claim 1 , wherein the material stub comprises copper.

4. The IC package support of claim 3 wherein said stub of material comprises nickel.

5. The IC package support of claim 4 , wherein a surface of said conductive line is flush with a surface of said nickel of said material stub.

6. 5. The IC package support of claim 4, wherein said nickel side of said material stub is between said copper side of said material stub and a side of said conductive line.

7. The IC package support of claim 1 , wherein the material stub comprises nickel.

8. The IC package support of claim 7 , wherein a surface of said conductive line is flush with a surface of said nickel of said material stub.

9. The IC package support of claim 1 , wherein a surface of the conductive line is flush with a surface of the material stub.

10. 10. The IC package support of claim 1, wherein the magnetic structure has a first portion and a second portion, the first portion of the magnetic structure being on a top and side surface of the conductive line, the second portion of the magnetic structure being on a bottom surface of the conductive line, and the first portion including a tapered shape narrowing toward the conductive line.

11. The IC package support of claim 10, wherein the material stub is provided on a side of the second portion.

12. the second portion includes a tapered shape narrowing toward the conductive line; 12. An IC package support according to claim 10 or 11.

13. An IC package support as described in any one of claims 10 to 12, wherein the material stub is adjacent to the interface between the first portion and the second portion.

14. a first layer of dielectric material on a first surface of the magnetic structure; a second layer of dielectric material on a second surface of the magnetic structure, the second surface facing the first surface; and The IC package support of claim 1 further comprising:

15. The IC package support of claim 1 , wherein the magnetic structure comprises magnetic particles embedded in a polymer matrix.

16. a conductive via at least partially coplanar with the magnetic structure, the conductive via being embedded in a layer of dielectric material and extending between a top of the layer of dielectric material to a bottom of the layer of dielectric material; 16. The IC package support of claim 1 further comprising:

17. a conductive via that is at least partially coplanar with the magnetic structure, the conductive via extending from a top of a layer of dielectric material past a bottom of the layer of dielectric material, the layer of dielectric material being on a surface of the magnetic structure; 17. The IC package support of claim 1 further comprising:

18. The IC package support of claim 1 , wherein the stub of material contacts the magnetic structure and a dielectric material adjacent to the magnetic structure.

19. An IC package support as described in any one of claims 1 to 18, wherein the material stub is provided on a first one of the sides of the magnetic structure and a second one of the sides of the magnetic structure opposite the first one.

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