COMMUNICATION DEVICE, CONTROL METHOD, AND PROGRAM

Abstract

A technology is provided that assists in determining the positional relationship between communication devices such as semiconductor chips. [Solution] A first communication device is provided, comprising: a communication circuit including a first coil, which performs wireless communication with a second communication device via inductive coupling between the first coil and a second coil of a second communication device; and an application means for applying a plurality of voltage patterns to the first coil via the communication circuit, each voltage pattern including a first signal portion used to detect the number of bit errors in the second communication device, and the first signal portion of each voltage pattern having a different frequency characteristic.

Description

[Technical field]

[0001] The present invention relates to a communication device, a control method, and a program. [Background technology]

[0002] Technologies for performing wireless communication using coils between multiple semiconductor chips have been known for some time. For example, Patent Document 1 proposes an information processing device that exchanges information via short-range wireless communication between multiple semiconductor chips integrated horizontally.

[0003] Furthermore, a technique for generating a pseudo random signal (Pseudo Random Bit Sequence (PRBS)) is known (Non-Patent Document 1). [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Patent Publication No. 2021-87044 [Non-patent literature]

[0005] [Non-Patent Document 1] Yuzo Usui, “PRBS (Pseudo Random Signal)”, [online], August 28, 2017, Macnica, Inc., [Retrieved January 18, 2024], Internet<URL:https: / / www.macnica.co.jp / business / semiconductor / articles / basic / 124741 / > Summary of the Invention [Problem to be solved by the invention]

[0006] The positional relationship (distance, angle, etc.) between semiconductor chips may change due to an external force or the like.

[0007] The present invention has been made in view of the above circumstances, and has an object to provide a technique for supporting the determination of the positional relationship between communication devices such as semiconductor chips. [Means for solving the problem]

[0008] In order to solve the above problems, the present invention provides a first communication device comprising: a communication circuit including a first coil, the communication circuit performing wireless communication with a second communication device via inductive coupling between the first coil and a second coil of a second communication device; and application means for applying a plurality of voltage patterns to the first coil via the communication circuit, each voltage pattern including a first signal portion used to detect the number of bit errors in the second communication device, the first signal portion of each voltage pattern having different frequency characteristics. Effect of the Invention

[0009] According to the present invention, it is possible to assist in determining the positional relationship between communication devices such as semiconductor chips.

[0010] Other features and advantages of the present invention will become apparent from the accompanying drawings and the following detailed description of the preferred embodiments of the present invention. [Brief description of the drawings]

[0011] [Figure 1] FIG. 1 is a conceptual diagram of a communication system including a plurality of communication devices. [Diagram 2] FIG. 4 is a diagram showing another configuration example of the semiconductor chip 1. [Diagram 3] 3 is a diagram illustrating the coupling between the transmitting coil 30 and the receiving coil 40 using an equivalent circuit. [Figure 4] 4 is a conceptual diagram of a bias voltage in a receiving coil 40. FIG. [Diagram 5] 1A and 1B are diagrams illustrating wireless communication using inductive coupling between coils. [Figure 6]2 is a diagram showing an example of a frame format used by the semiconductor chip 1 for transmitting and receiving data. [Figure 7] FIG. 13 is a diagram showing an example of a format of an evaluation frame. [Figure 8] FIG. 13 is a diagram showing an example of an evaluation signal table for managing a plurality of evaluation signals (bit patterns). [Figure 9] 13 is a flowchart of an evaluation frame transmission process in the sensing process when a method of changing the bit pattern of an evaluation signal is used. [Figure 10] 13 is a flowchart of an evaluation value acquisition process, which is part of a sensing process, when a method of changing the bit pattern of an evaluation signal is used. [Figure 11] 13 is a flowchart of a positional relationship determination process in the sensing process. [Figure 12] 11A and 11B are diagrams for explaining a method of inverting a part of a voltage pattern. [Figure 13] FIG. 13 is a diagram showing an example of an inversion rule table for managing voltage inversion rules for evaluation signals. [Figure 14] 13 is a flowchart of an evaluation frame transmission process in the sensing process when a method of inverting a part of a voltage pattern is used. [Figure 15] 13 is a flowchart of an evaluation value acquisition process in the sensing process when a method of inverting a part of a voltage pattern is used. [Figure 16] A diagram explaining Return to Zero (RZ), Non Return to Zero Inversion (NRZI), and Manchester code. [Figure 17] FIG. 13 is a diagram showing an example of a line code table for managing a plurality of line codes; [Figure 18] 13 is a flowchart of an evaluation frame transmission process in the sensing process when a method of changing a transmission line code of an evaluation signal is used. [Figure 19] 13 is a flowchart of an evaluation value acquisition process in the sensing process when a method of changing a transmission path code of an evaluation signal is used. [Figure 20] FIG. 4A shows an example of an evaluation frame including an area for an evaluation signal ID, and FIG. 4B shows another example of the format of the evaluation frame. [Figure 21] 11A to 11C are diagrams for explaining various specific examples of determination regarding a positional relationship. [Figure 22] 11A to 11C are diagrams for explaining various specific examples of determination regarding a positional relationship. [Diagram 23] 11A to 11C are diagrams for explaining various specific examples of determination regarding a positional relationship. [Figure 24] 11A to 11C are diagrams for explaining various specific examples of determination regarding a positional relationship. [Diagram 25] 11A to 11C are diagrams for explaining various specific examples of determination regarding a positional relationship. [Figure 26] 11A to 11C are diagrams for explaining various specific examples of determination regarding a positional relationship. [Figure 27] 11A to 11C are diagrams for explaining various specific examples of determination regarding a positional relationship. [Figure 28] 11A to 11C are diagrams for explaining various specific examples of determination regarding a positional relationship. [Figure 29] 11A to 11C are diagrams for explaining various specific examples of determination regarding a positional relationship. [Diagram 30] 11A to 11C are diagrams for explaining various specific examples of determination regarding a positional relationship. [Diagram 31] 11A to 11C are diagrams for explaining various specific examples of determination regarding a positional relationship. [Diagram 32] 11A to 11C are diagrams for explaining various specific examples of determination regarding a positional relationship. [Diagram 33] 11A to 11C are diagrams for explaining various specific examples of determination regarding a positional relationship. [Diagram 34] FIG. 2 is a block diagram showing the functional configuration of the semiconductor chip 1. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0012] Hereinafter, the embodiments will be described in detail with reference to the accompanying drawings. Note that the following embodiments do not limit the invention according to the claims, and not all combinations of features described in the embodiments are essential to the invention. Two or more features among the multiple features described in the embodiments may be arbitrarily combined. In addition, the same reference numbers are used for the same or similar configurations, and duplicated descriptions are omitted.

[0013] <Communication system configuration> Fig. 1 is a conceptual diagram of a communication system composed of multiple communication devices. In the example of Fig. 1, the communication devices are semiconductor chips. Although two semiconductor chips (semiconductor chips 1a and 1b) are shown in Fig. 1, the number of semiconductor chips included in the communication system is not particularly limited, and three or more semiconductor chips may be included in the communication system.

[0014] In the following description, when it is not necessary to strictly distinguish between the individual semiconductor chips, the semiconductor chips included in the communication system will be referred to as "semiconductor chip 1." In this case, the components of the semiconductor chip 1 shown in Fig. 1 will be referred to collectively by their reference numerals without the alphabet, such as "processor 10." This also applies to Fig. 2, which will be described later.

[0015] The semiconductor chip 1 includes a processor 10, a memory 20 provided within the processor 10, a transmitting coil 30, a receiving coil 40, a transmitting conversion circuit 50, and a receiving conversion circuit 60. The semiconductor chip 1 operates with power supplied from a power supply device (not shown).

[0016] The processor 10 is, for example, a CPU, and executes programs to perform various processes. The memory 20 stores the programs executed by the processor 10, various information used by the processor, and the like.

[0017] In addition to the CPU, the processor 10 may include a logic circuit block configured to perform signal processing for a specific application. In this case, some or all of the processing described below as being executed by the processor 10 may be executed by the logic circuit block.

[0018] The transmitting conversion circuit 50 transmits data output from the processor 10 to the other semiconductor chip 1 through wireless communication utilizing inductive coupling between the transmitting coil 30 and the receiving coil 40 of the other semiconductor chip 1. The receiving conversion circuit 60 receives data from the other semiconductor chip 1 through wireless communication utilizing inductive coupling between the receiving coil 40 and the other semiconductor chip 1. Note that terms such as "near-field inductive coupling," "near-field magnetic coupling," "magnetic coupling," "electromagnetic induction," or "magnetic field resonance" may also be used as terms that have the same meaning as "inductive coupling."

[0019] In the example of Figure 1, the semiconductor chip 1 has a separate coil for transmission (transmission coil 30) and a coil for reception (reception coil 40). However, as shown in Figure 2, a configuration in which one coil is used for both transmission and reception may be adopted.

[0020] In the communication system shown in FIG. 2, the semiconductor chip 1 includes a coil 35 used for both transmission and reception, instead of the transmitting coil 30 and the receiving coil 40. Also, the semiconductor chip 1 includes a conversion circuit 55 having the functions of the transmitting conversion circuit 50 and the receiving conversion circuit 60, instead of the transmitting conversion circuit 50 and the receiving conversion circuit 60. When the semiconductor chip 1 in FIG. 2 transmits data, the conversion circuit 55 and the coil 35 play the same roles as the transmitting conversion circuit 50 and the transmitting coil 30 of the semiconductor chip 1 in FIG. 1. When the semiconductor chip 1 in FIG. 2 receives data, the conversion circuit 55 and the coil 35 play the same roles as the receiving conversion circuit 60 and the receiving coil 40 of the semiconductor chip 1 in FIG. 1.

[0021] In the following, unless otherwise specified, the semiconductor chip 1 will be described as having the configuration shown in Fig. 1. However, the following description also applies to the case where the semiconductor chip 1 has the configuration shown in Fig. 2. In this case, the following description of the transmitting conversion circuit 50 and the transmitting coil 30 corresponds to the description of the conversion circuit 55 and the coil 35 of the transmitting semiconductor chip 1. Also, the following description of the receiving conversion circuit 60 and the receiving coil 40 corresponds to the description of the conversion circuit 55 and the coil 35 of the receiving semiconductor chip 1.

[0022] <Equivalent circuit of the transmitting coil 30 and the receiving coil 40> 3 is a diagram illustrating the coupling between the transmitting coil 30 and the receiving coil 40 using an equivalent circuit. The transmitting coil 30 is represented by an equivalent circuit including an inductor Ltx, two resistors Rtx, and a capacitor Ctx. The receiving coil 40 is represented by an equivalent circuit including an inductor Lrx, two resistors Rrx, and a capacitor Crx.

[0023] In the equivalent circuit of the receiving coil 40, a bias voltage V B For example, as shown in Figure 4, a bias voltage V is applied to Port 2, which is the midpoint of a two-turn coil. B This is achieved by applying

[0024] The transmitter coil 30 of a particular semiconductor chip 1 is coupled to the receiver coil 40 of another nearby semiconductor chip 1. In addition, the transmitter coil 30 of a particular semiconductor chip 1 is also coupled to the receiver coil 40 of the same semiconductor chip 1. Thus, for example, the transmitter coil 30a of the semiconductor chip 1a shown in FIG. 1 is coupled to the receiver coil 40b of the semiconductor chip 1b and also to the receiver coil 40a of the semiconductor chip 1a. The coupling between any transmitter coil 30 and receiver coil 40 can be expressed by the equivalent circuit of FIG. 3, but the coupling coefficient changes depending on the positional relationship (distance, angle, etc.) between the transmitter coil 30 and the receiver coil 40.

[0025] In addition, when the semiconductor chip 1 has only one coil as shown in Figure 2, there is no coupling between the two coils within the same semiconductor chip, but coupling between the coils of two adjacent semiconductor chips 1 occurs in the same way as in the case of Figure 1.

[0026] In the communication system of FIG. 1, the semiconductor chip 1a and the semiconductor chip 1b are disposed close to each other so that a coil is coupled between the semiconductor chip 1a and the semiconductor chip 1b.

[0027] The memory 20 of the semiconductor chip 1 stores in advance identification information (ID) of each semiconductor chip 1 included in the communication system and information (coupling relationship information) indicating the coupling relationships between the semiconductor chips 1 in the communication system. Therefore, by referring to the coupling relationship information, the semiconductor chip 1 can identify other semiconductor chips 1 with which it can directly communicate by inductive coupling in the communication system. For example, in the communication system of Fig. 1, the semiconductor chip 1a can identify the semiconductor chip 1b as another semiconductor chip 1 with which it can directly communicate with the semiconductor chip 1a by referring to the coupling relationship information stored in the memory 20a.

[0028] <Wireless communication using inductive coupling between coils> The wireless communication using inductive coupling between coils will be described by taking as an example a case where the semiconductor chip 1a transmits data to the semiconductor chip 1b in the communication system of Fig. 1. In this case, the transmitting conversion circuit 50 and the transmitting coil 30 in Fig. 3 correspond to the transmitting conversion circuit 50a and the transmitting coil 30a of the semiconductor chip 1a, respectively. Also, the receiving conversion circuit 60 and the receiving coil 40 in Fig. 3 correspond to the receiving conversion circuit 60b and the receiving coil 40b of the semiconductor chip 1b, respectively.

[0029] The processor 10a outputs a bit string representing data to be transmitted as a digital signal (pulse string) represented by two voltage values, High and Low, to the transmitting conversion circuit 50a. The transmitting conversion circuit 50a performs waveform conversion processing, including voltage conversion and pulse waveform shaping, on the pulse string output from the processor 10a to convert Txdata and Generates TIFF0007613666000002.tif716. In the following explanation, TIFF0007613666000003.tif716 is sometimes written as "Txdata(bar)".

[0030] FIG. 5(a) is a diagram showing an example of Txdata, and FIG. 5(b) is a diagram showing an example of Txdata (bar). Txdata has the same pulse waveform as the pulse train output from the processor 10a. Txdata (bar) has a pulse waveform in which the High and Low of Txdata are inverted. In the following explanation, it is assumed that the High voltage of the pulse train output from the processor 10a and the High voltage of Txdata are both 1.2V. However, the High voltage of the pulse train output from the processor 10a and the High voltage of Txdata may be different.

[0031] The transmitting conversion circuit 50a applies a voltage corresponding to Txdata and Txdata (bar) to the transmitting coil 30a. In the example of FIG. 3, the transmitting conversion circuit 50a and the transmitting coil 30a are connected so that Txdata is applied to the upper port of the transmitting coil 30a and Txdata (bar) is applied to the lower port. When Txdata is High and Txdata (bar) is Low, the current Itx of the transmitting coil 30a flows from the upper side to the lower side of the inductor Ltx in FIG. 3. The current in this case corresponds to the period in FIG. 5(c) where the value of Itx is 5.0 mA. On the other hand, when Txdata is Low and Txdata (bar) is High, the current Itx of the transmitting coil 30a flows from the lower side to the upper side of the inductor Ltx in FIG. 3. The current in this case corresponds to the period in FIG. 5(c) where the value of Itx is −5.0 mA (the period in which the polarity is reversed compared to when Txdata is High and Txdata (bar) is Low).

[0032] When the current Itx flows through the transmitting coil 30a, a voltage corresponding to the transition of the current Itx is induced in the receiving coil 40b. The polarity of the induced voltage differs depending on whether the transition of Txdata is from Low to High or from High to Low.

[0033] 5(d) and 5(e) are diagrams showing examples of the waveform of the voltage induced in the receiving coil 40b. Vrx1 shown in FIG. 5(d) is the voltage observed at the upper port of the receiving coil 40b, and Vrx2 shown in FIG. 5(e) is the voltage observed at the lower port of the receiving coil 40b. Vrx1 is the bias voltage V B Vrx2 fluctuates in the positive direction with respect to the induced voltage corresponding to the rising edge of the waveform of the current Itx of the transmitting coil 30a, and in the negative direction with the induced voltage corresponding to the falling edge of the waveform of the current Itx. Vrx2 fluctuates in the opposite direction to Vrx1 according to the rising and falling edges of the waveform of the current Itx of the transmitting coil 30a. The amplitudes of Vrx1 and Vrx2 are proportional to the magnitude of the current Itx and the coupling coefficient between the transmitting coil 30a and the receiving coil 40b.

[0034] The voltages Vrx1 and Vrx2 of the receiving coil 40b are input to the receiving conversion circuit 60b. For example, a hysteresis comparator can be used as the receiving conversion circuit 60b. The receiving conversion circuit 60b generates a pulse train (Rxdata) represented by two values, High and Low, shown in FIG. 5(f), based on the voltages Vrx1 and Vrx2. The pulse train generated by the receiving conversion circuit 60b has a waveform corresponding to the pulse train output by the processor 10a. The receiving conversion circuit 60b inputs the generated pulse train to the processor 10b. In this way, the processor 10b can obtain a pulse train (Rxdata) corresponding to the pulse train (transmission signal) output by the processor 10a as a reception signal received via the receiving conversion circuit 60b.

[0035] The processor 10b can decode the pulse train input from the receiving conversion circuit 60b into a binary signal train (bit train) represented by 1 (High) or 0 (Low) by sampling it at a predetermined sampling frequency. In the example of Fig. 5, the sampling frequency is 1 GHz (hence, the sampling period is 1 nanosecond (ns)), and a bit train of "01101" is obtained.

[0036] In this manner, the semiconductor chip 1a and the semiconductor chip 1b can transmit and receive data via wireless communication that utilizes inductive coupling between the coils.

[0037] <Frame format for data transmission and reception> A frame having a predetermined format can be used for transmitting and receiving data between the semiconductor chips 1. Fig. 6 is a diagram showing an example of a frame format used by the semiconductor chip 1 for transmitting and receiving data. In the example of Fig. 6, the frame has a format including a preamble signal, a frame control signal, a frame length signal, a destination ID signal, a source ID signal, a data signal, and a frame check signal.

[0038] The preamble signal is composed of a predetermined signal sequence (for example, a bit sequence of a specific pattern such as "101101") that indicates the presence of a frame. By detecting the presence of the preamble signal, the processor 10 of the semiconductor chip 1 can detect that another semiconductor chip 1 is transmitting a frame.

[0039] The frame control signal is a signal that indicates the type of frame. Frame types include "information frame," "control frame," "management frame," and "evaluation frame." The frame format following the frame control signal differs depending on the frame type. Figure 6 corresponds to the case where the frame type is an information frame.

[0040] The frame length signal is a control signal that includes information about the length of a frame.

[0041] The destination ID signal indicates the identification information (ID) of the frame's destination semiconductor chip 1. For example, the destination ID signal of a frame transmitted from the semiconductor chip 1a to the semiconductor chip 1b includes a bit string indicating the ID of the semiconductor chip 1b.

[0042] The sender ID signal indicates the ID of the semiconductor chip 1 that transmits the frame. For example, the sender ID signal of a frame transmitted from the semiconductor chip 1a to the semiconductor chip 1b includes a bit string indicating the ID of the semiconductor chip 1a.

[0043] A data signal is a signal that contains the body of data (information) to be transmitted, and may also contain a sequence number that indicates the order of the data signal.

[0044] The frame check signal is a signal for checking whether or not there is an error in the received frame. For example, a cyclic redundancy check (CRC) code is used as the frame check signal. Upon receiving the frame check signal, the semiconductor chip 1 completes the reception of the frame.

[0045] <Sensing process overview and evaluation frame format> The semiconductor chip 1 can perform sensing processing. The sensing processing is processing in which the semiconductor chip 1 acquires an evaluation value representing the quality of wireless communication with another semiconductor chip 1, and judges the positional relationship between these two semiconductor chips 1 based on the acquired evaluation value. In the sensing processing, an evaluation frame is transmitted from one of the two semiconductor chips 1 to the other. Thus, the sensing processing includes processing in which the transmitting semiconductor chip 1 transmits an evaluation frame to the receiving semiconductor chip 1 (evaluation frame transmission processing), processing in which the receiving semiconductor chip 1 acquires an evaluation value (evaluation value acquisition processing), and processing in which the receiving semiconductor chip 1 judges the positional relationship (positional relationship judgment processing).

[0046] Fig. 7 is a diagram showing an example of the format of an evaluation frame. The evaluation frame is similar to the information frame in Fig. 6, but the frame control signal sets "evaluation frame" as the frame type. Moreover, the evaluation frame includes an evaluation signal (first signal portion) instead of a data signal.

[0047] The evaluation signal is a signal used by the semiconductor chip 1 to obtain an evaluation value of wireless communication. In this embodiment, a value based on the number of bit errors in the received evaluation signal is obtained as the evaluation value. The evaluation value based on the number of bit errors may be the number of bit errors itself, or may be a value calculated based on the number of bit errors, such as a bit error rate (BER) calculated by dividing the number of bit errors by the number of bits in the evaluation signal. In addition, a block error rate (BLER), a frame error rate (FER), a packet error rate (PER), and the like can also be used as an evaluation value based on the number of bit errors, as long as the value is calculated based on the number of bit errors so as to be an index of the number of bit errors in the evaluation signal. For example, when the evaluation value is the number of bit errors, the smaller the number of bit errors, the better the quality of wireless communication is considered to be. In addition, when the evaluation value is the BER, the smaller the BER, the better the quality of wireless communication is considered to be.

[0048] A predetermined signal sequence (e.g., a bit sequence of a specific pattern such as "11100111") is set in the evaluation signal. For example, the semiconductor chip 1 can detect the number of bit errors in the evaluation signal by comparing a known evaluation signal with an actually received evaluation signal, and obtain an evaluation value of the wireless communication.

[0049] As described above, the amplitudes of the voltages Vrx1 and Vrx2 input to the receiving conversion circuit 60 are proportional to the magnitude of the current Itx of the transmitting coil 30 and the coupling coefficient between the transmitting coil 30 and the receiving coil 40. When the amplitudes of Vrx1 and Vrx2 are small, the signal is more susceptible to noise and the like, and the probability of bit errors occurring in the received signal increases. Therefore, the number of bit errors in the evaluation signal changes according to the coupling coefficient. In addition, the coupling coefficient changes according to the positional relationship (distance or angle, etc.) between the two coils. As a result, the number of bit errors in the evaluation signal changes according to the positional relationship (distance or angle, etc.) between the two coils. Therefore, the evaluation value not only represents the quality of wireless communication, but also serves as an index regarding the positional relationship between the two semiconductor chips 1. For this reason, the semiconductor chip 1 can make a judgment regarding the positional relationship between the two semiconductor chips 1 based on the evaluation value. For example, when the evaluation value exceeds a predetermined threshold value, the semiconductor chip 1 can judge that the positional relationship between the two semiconductor chips 1 has shifted from the original desired positional relationship.

[0050] <Relationship between the frequency characteristics of voltage patterns and the probability of bit errors occurring> 5, the voltage (Txdata and Txdata(bar)) applied (input) to the transmitting coil 30 has a pattern representing the bit string to be transmitted. Therefore, the voltage pattern applied to the transmitting coil 30 has frequency characteristics according to the content (bit pattern) of the bit string to be transmitted.

[0051] Here, the coupling between the transmitting coil 30 and the receiving coil 40 has a frequency characteristic. Therefore, the probability of bit errors occurring in the received signal is affected not only by the coupling coefficient based on the positional relationship between the two coils described above, but also by the frequency characteristics of the voltage pattern applied to the transmitting coil 30a and the frequency characteristics of the coupling. Therefore, even if the positional relationship between the two coils does not change, a phenomenon may occur in which the frequency of bit errors is relatively high for a bit string transmitted by a specific voltage pattern and the frequency of bit errors is relatively low for a bit string transmitted by a different voltage pattern.

[0052] Therefore, the number of bit errors in the evaluation signal is affected by the frequency characteristics of the voltage pattern of the evaluation signal, which may result in a bias in the evaluation value based on the number of bit errors, thereby decreasing the accuracy of the determination of the positional relationship between the two semiconductor chips 1.

[0053] Therefore, below, we will explain a sensing process that includes a configuration that reduces the influence of bias in the evaluation value caused by frequency characteristics by using multiple evaluation signals with different frequency characteristics (more precisely, multiple voltage patterns with different frequency characteristics).

[0054] The sensing process of the present embodiment is not limited to a configuration using a plurality of evaluation signals with different frequency characteristics. Even if a configuration is adopted in which the frequency characteristics of the evaluation signals do not change, the acquired evaluation value can be used for determining the positional relationship.

[0055] <Sensing process using multiple evaluation signals with different frequency characteristics> In the following, sensing processing using a plurality of evaluation signals with different frequency characteristics will be described taking as an example a case where the semiconductor chip 1a transmits an evaluation frame to the semiconductor chip 1b in the communication system of FIG.

[0056] Methods for changing the frequency characteristics of the evaluation signal (more precisely, the frequency characteristics of the voltage pattern in which the evaluation signal is coded) include, for example, a method for changing the bit pattern of the evaluation signal, a method for inverting a part of the voltage pattern, and a method for changing the transmission line code of the evaluation signal. Below, the cases in which each method is used will be explained in order. It is also possible to use a combination of two or three of these three methods.

[0057] - Method of changing the bit pattern of the evaluation signal As described above, the voltage pattern has a frequency characteristic according to the bit pattern to be transmitted, so by changing the bit pattern among the multiple evaluation signals, it is possible to change the frequency characteristic among the multiple evaluation signals.

[0058] FIG. 8 is a diagram showing an example of an evaluation signal table that manages a plurality of evaluation signals (bit patterns). The evaluation signal table includes an index N, an evaluation signal ID, and an evaluation signal (bit pattern). In the example of FIG. 8, three types of evaluation signals are included in the evaluation signal table. A common evaluation signal table is pre-stored in the memory 20 of each semiconductor chip 1 in the communication system. That is, information on a plurality of bit patterns to be used is shared in advance among the plurality of semiconductor chips 1 included in the communication system.

[0059] 9 is a flowchart of an evaluation frame transmission process in the sensing process when using a method of changing the bit pattern of an evaluation signal. In this flowchart, evaluation frames including evaluation signals with different bit patterns are transmitted for each frame.

[0060] In S901, the processor 10a of the semiconductor chip 1a initializes an index N to 1.

[0061] In S902, in order to generate an evaluation frame (see FIG. 7), the processor 10a of the semiconductor chip 1a sets a predetermined bit string indicating the presence of a frame in a "preamble signal" of the evaluation frame.

[0062] In S903, the processor 10a sets a bit string representing the "evaluation frame" in the "frame control signal" of the evaluation frame. The processor 10a also refers to the evaluation signal table stored in the memory 20a and sets a bit string representing the evaluation signal ID corresponding to the current index N (for example, "1100" when N=1) in the "frame control signal" (second signal portion).

[0063] In S904, the processor 10a sets a bit string indicating the frame length of the evaluation frame in the "frame length signal" of the evaluation frame.

[0064] In S905, the processor 10a sets a bit string representing the ID of the semiconductor chip 1b, which is the destination of the evaluation frame, in the "destination ID signal" of the evaluation frame.

[0065] In S906, the processor 10a sets a bit string representing the ID of the semiconductor chip 1a in the "source ID signal" of the evaluation frame.

[0066] In S907, the processor 10a refers to the evaluation signal table stored in the memory 20a and sets a bit string representing the evaluation signal corresponding to the current index N (for example, "1100101000110101" when N=1) to the "evaluation signal" of the evaluation frame.

[0067] In S908, the processor 10a sets a check bit string (for example, a CRC code generated from the bit string constituting the frame) in the "frame check signal" of the evaluation frame.

[0068] In S909, the processor 10a transmits the evaluation frame to the semiconductor chip 1b. Specifically, the processor 10a applies Txdata and Txdata(bar) to the transmitting coil 30a by inputting a pulse sequence corresponding to the bit sequence of the evaluation frame to the transmitting conversion circuit 50. As a result, a voltage pattern corresponding to the bit sequence of the evaluation frame is applied (input) to the transmitting coil 30a, and wireless transmission of the evaluation frame is realized.

[0069] In S910, the processor 10a updates the index N by performing the calculation "N = (N mod Nmax) + 1". The maximum value (Nmax) of the index N is the number of evaluation signals (bit patterns) stored in the evaluation signal table, and is 3 in the example of FIG. 8. "(N mod Nmax)" means the remainder obtained by dividing N by Nmax. For example, when N = 1 and Nmax = 3, (N mod Nmax) = 1, so N is updated to 2. Thereafter, the process returns to S902, and the next evaluation frame is transmitted by the processes of S902 to S909. Since N has been updated, a bit pattern different from that of the previous evaluation frame is used for the "evaluation signal" of the next evaluation frame. When the evaluation signal table of FIG. 8 is used, N is updated in the order of 1, 2, 3, 1, 2, 3, . . . As a result, three types of bit patterns are used repeatedly in order as the evaluation signals.

[0070] Next, with reference to Fig. 10, an evaluation value acquisition process of the sensing process in the case of using a method of changing the bit pattern of the evaluation signal will be described. In S1001, the processor 10b of the semiconductor chip 1b judges whether or not a known preamble signal has been detected (i.e., whether or not the adjacent semiconductor chip 1a is transmitting a frame). Specifically, the processor 10b compares a bit sequence obtained by decoding a pulse sequence (Rxdata) supplied from the receiving conversion circuit 60b at a predetermined sampling frequency with the known preamble signal, and judges that the known preamble signal has been detected if the two match. The processor 10b repeats the process of S1001 until the preamble signal is detected. When the preamble signal is detected, the process proceeds to S1002.

[0071] In S1002, the processor 10b decodes the frame control signal following the preamble signal and determines whether the type of the frame is an evaluation frame. If the type of the frame is an evaluation frame, the process proceeds to S1004, and if not, the process proceeds to S1003. Note that if the type of the frame is an evaluation frame, the frame control signal also includes a bit string representing the evaluation signal ID, and therefore the evaluation signal ID is also obtained by decoding the frame control signal.

[0072] In S1003, the processor 10b performs appropriate processing according to the type of the frame, and then the process returns to S1001.

[0073] In S1004, the processor 10b decodes the frame length signal and confirms the length of the frame.

[0074] In S1005, the processor 10b decodes the destination ID signal and determines whether the frame is addressed to itself (whether the destination ID is the ID of the semiconductor chip 1b). If the frame is addressed to itself, the process proceeds to S1006, and if not, the process returns to S1001.

[0075] In S1006, the processor 10b decodes the source ID signal and acquires the ID of the semiconductor chip 1 that is the source of the frame. If the semiconductor chip 1a is the source of the frame, the ID of the semiconductor chip 1a is acquired.

[0076] In S1007, the processor 10b decodes the evaluation signal and acquires the decoded evaluation signal (the received bit string).

[0077] In S1008, the processor 10b acquires an evaluation value based on the evaluation signal ID and the decoded evaluation signal (received bit string). Specifically, the processor 10b refers to an evaluation signal table stored in the memory 20b and acquires a bit string corresponding to the evaluation signal ID (i.e., a correct bit string). The processor 10b then compares the acquired correct bit string with the received bit string to detect (count) the number of bit errors and acquires an evaluation value based on the number of bit errors. In the following description, the evaluation value based on the number of bit errors is assumed to be a BER as an example. The processor 10b records the acquired evaluation value in the memory 20b. At that time, the processor 10b records the reception time of the evaluation frame from which the evaluation value was acquired and the transmission source ID of the evaluation frame in association with the evaluation value. As a result, information indicating a time series change in the evaluation value corresponding to a specific transmission source is accumulated in the memory 20b.

[0078] In S1109, the processor 10b decodes the frame check signal and determines whether the evaluation frame has been received without error. The processor 10b may also transmit an Acknowledgement (ACK) signal (if the frame check is OK) or a Negative ACK (NACK) signal (if the frame check is NG) to the semiconductor chip 1b according to the determination result (frame check result). After that, the process returns to S1001.

[0079] Next, the positional relationship determination process of the sensing process will be described with reference to Fig. 11. The positional relationship determination process of Fig. 11 is executed in parallel with the evaluation value acquisition process of Fig. 10. Therefore, in parallel with the positional relationship determination process, acquisition of the evaluation value is repeatedly performed.

[0080] In S1101, the processor 10b of the semiconductor chip 1b determines whether a new evaluation value has been acquired by the evaluation value acquisition process. The processor 10b repeats the process of S1101 until a new evaluation value is acquired. When a new evaluation value is acquired, the process proceeds to S1102.

[0081] In S1102, the processor 10b calculates (obtains) a composite evaluation value by performing a calculation based on the most recently acquired multiple evaluation values ​​including the new evaluation value. The specific calculation method is not particularly limited, but for example, the processor 10b may calculate the average value of the multiple evaluation values ​​as the composite evaluation value, or may calculate the sum of the multiple evaluation values. As long as a value based on the number of bit errors detected in the most recent multiple evaluation signals can be obtained, the composite evaluation value can be calculated by any method. In the following, as an example, the composite evaluation value is assumed to be the average value (average BER) of multiple BERs. In addition, the number M (M≧2) of evaluation values ​​used to obtain the composite evaluation value is not particularly limited, but the larger the number M of evaluation values ​​used, the greater the effect of reducing the influence of bias on the evaluation value caused by the frequency characteristics. In addition, the case of M=1 is not excluded from this embodiment. Even if M=1, there is a possibility that the accuracy will be relatively lower than that in the case of M≧2, but it is still possible to make a judgment regarding the positional relationship based on one evaluation value.

[0082] The processor 10b may also store the calculated composite evaluation value in the memory 20b in association with the time when the evaluation frame corresponding to the latest evaluation value was received. This allows the time series change of the composite evaluation value to be recorded.

[0083] If the number of already acquired evaluation values ​​is smaller than M, the processor 10b may calculate a composite evaluation value based on all already acquired evaluation values, or may return the process to S1101 without calculating a composite evaluation value.

[0084] In S1103, the processor 10b performs a determination on the positional relationship based on the composite evaluation value. For example, when the composite evaluation value (average BER) exceeds a predetermined threshold (for example, 0.1), the semiconductor chip 1b can determine that the positional relationship between the semiconductor chip 1b and the semiconductor chip 1a has shifted from the original desired positional relationship. Various specific examples of the determination on the positional relationship will be described later.

[0085] In S1104, the processor 10b performs processing related to the determination result regarding the positional relationship. The processing here is not particularly limited, but for example, the processor 10b may transmit the determination result to an external management device (not shown). In this case, the external management device can recognize whether the positional relationship between the semiconductor chip 1b and the semiconductor chip 1a is the originally desired positional relationship based on the received determination result, and can warn the user as necessary. After that, the processing returns to S1101.

[0086] How to invert part of the voltage pattern As described with reference to Fig. 5, the processor 10b can decode the pulse train input from the receiving conversion circuit 60b into a binary signal train (bit train) represented by 1 (High) or 0 (Low) by sampling it at a predetermined sampling frequency. In the example of Fig. 5, the sampling frequency is 1 GHz (hence, the sampling period is 1 nanosecond (ns)), and a bit train of "01101" is obtained.

[0087] Here, the processor 10b does not need to perform sampling over the entire period (1 bit period) corresponding to each bit, but can decode the pulse train into a bit train by performing sampling at a specific timing (sampling timing) within the 1 bit period. For example, as shown by the arrow pointing from top to bottom in Fig. 12(a), the processor 10b can obtain the bit train "10011001" by performing sampling at a timing earlier than the center of the 1 bit period. In this case, even if the voltage is inverted during the period other than the sampling timing, the decoded bit train does not change.

[0088] FIG. 12(b) is a diagram showing an example in which the voltage of the latter half of the bit period is inverted for some bits. In FIG. 12(b), the periods indicated by left and right arrows (such as period 1201) indicate periods in which the voltage is inverted. Period 1201 is the latter half of the bit period corresponding to "1", and therefore should have a "High" voltage, but here it is inverted to "Low". However, since period 1201 is a period outside the sampling timing, "1" is obtained as the decoded bit, as in the case of FIG. 12(a). In the example of FIG. 12(b), voltage inversion occurs in the latter half of the bit period corresponding to "1" in the bit pattern of "10" and in the bit period corresponding to "0" in the bit pattern of "01".

[0089] When the voltage in a certain bit period in the voltage pattern is partially inverted, the frequency characteristic of the voltage pattern changes. Therefore, by partially inverting the voltage in the period outside the sampling timing, it is possible to change the frequency characteristic of the voltage pattern without changing the bit pattern.

[0090] In the example of Fig. 12(b), the period in which the voltage is inverted is the latter half (the last 50%) of one bit period, but the voltage can be inverted at any portion as long as it does not include the sampling timing. For example, if the receiving processor 10b is configured to perform sampling at a timing within 15% from the beginning of one bit period, the transmitting processor 10a can invert the voltage at any portion excluding the first 15% of the one bit period.

[0091] Fig. 13 is a diagram showing an example of an inversion rule table that manages the inversion rule of the voltage in the evaluation signal. The inversion rule table includes an index N and an inversion rule. In the example of Fig. 13, three types of inversion rules are included in the inversion rule table. An inversion rule table is stored in advance in the memory 20 of each semiconductor chip 1 of the communication system. Unlike the case of Fig. 8, different inversion rule tables may be stored in the semiconductor chip 1a and the semiconductor chip 1b.

[0092] Fig. 14 is a flowchart of the evaluation frame transmission process in the sensing process when using a method of inverting a part of the voltage pattern. In Fig. 14, Nmax is the number of inversion rules stored in the inversion rule table, which is 3 in the example of Fig. 13.

[0093] In S1403, the processor 10a sets a bit string representing the "evaluation frame" in the "frame control signal" of the evaluation frame. Here, unlike S903 in Fig. 9, the processor 10a does not need to set a bit string representing the evaluation signal ID in the "frame control signal".

[0094] In S1407, the processor 10a sets a bit string (e.g., "10011001") representing the evaluation signal to the "evaluation signal" of the evaluation frame. Unlike S907 in Fig. 9, the same bit pattern can be used as the evaluation signal regardless of the current value of index N here.

[0095] In S1409, the processor 10a transmits an evaluation frame to the semiconductor chip 1b. Specifically, the processor 10a applies Txdata and Txdata(bar) to the transmission coil 30a by inputting a pulse sequence corresponding to the bit sequence of the evaluation frame to the transmission side conversion circuit 50. At this time, the processor 10a applies an inversion rule corresponding to the current index N to the voltage of the evaluation signal in the evaluation frame by referring to the inversion rule table stored in the memory 20a. For example, in the example of FIG. 13, when N=1, the voltage pattern shown in FIG. 12(a) is input to the transmission coil 30a as Txdata, and when N=2, the voltage pattern shown in FIG. 12(b) is input to the transmission coil 30a as Txdata. This makes it possible to change the frequency characteristic of the voltage pattern for each evaluation frame without changing the bit pattern of the evaluation signal.

[0096] In the example of FIG. 12(b), the period in which the voltage is inverted is fixed to the latter half (last 50%) of one bit period, but as shown in FIG. 12(c), a configuration in which the period in which the voltage is inverted varies for each bit may be adopted. In the example of FIG. 12(c), the bits to be inverted are "1" in the bit pattern of "10" and "0" in the bit pattern of "01", as in FIG. 12(b). However, the part to be inverted in each bit period corresponding to the bit to be inverted is randomly determined for each bit (this determination is performed so that the part to be inverted does not include the sampling timing). When such a configuration is adopted, it becomes unnecessary to store an inversion rule table in the memory 20 of each semiconductor chip 1.

[0097] Next, with reference to FIG. 15, an evaluation value acquisition process of the sensing process in the case of using a method in which a part of a voltage pattern is inverted will be described.

[0098] In S1502, the processor 10b decodes the frame control signal following the preamble signal, and determines whether the type of the frame is an evaluation frame, similarly to S1002 in Fig. 10. If the type of the frame is an evaluation frame, the process proceeds to S1004, and if not, the process proceeds to S1003. Note that, unlike S1002 in Fig. 10, even if the type of the frame is an evaluation frame, the evaluation signal ID is not acquired.

[0099] In S1507, the processor 10b decodes the evaluation signal and obtains the decoded evaluation signal (the received bit string). Sampling for decoding the evaluation signal is performed at a predetermined sampling timing so as not to be included in the period in which the voltage is inverted. Therefore, the processor 10b can decode the evaluation signal without knowing the inversion rule used on the transmitting side.

[0100] In S1508, the processor 10b detects (counts) the number of bit errors by comparing a predetermined known correct bit sequence with the decoded evaluation signal (the received bit sequence), and obtains an evaluation value based on the number of bit errors. The processor 10b records the obtained evaluation value in the memory 20b. At that time, the processor 10b records the reception time of the evaluation frame from which the evaluation value was obtained, and the transmission source ID of the evaluation frame, in association with the evaluation value. As a result, information indicating the time series change of the evaluation value corresponding to a specific transmission source is accumulated in the memory 20b.

[0101] As for the positional relationship determination process in the sensing process, the processor 10b executes the process shown in FIG. 11 in the same manner as in the case of using the method of changing the bit pattern of the evaluation signal.

[0102] Method of changing the transmission line code of the evaluation signal In the above description, Non Return to Zero (NRZ) is used as the transmission line code (encoding method) for wireless communication between the semiconductor chips 1. Examples of transmission line codes that can be used other than NRZ include Return to Zero (RZ), Non Return to Zero Inversion (NRZI), and Manchester code.

[0103] Fig. 16 is a diagram for explaining Return to Zero (RZ), Non Return to Zero Inversion (NRZI), and Manchester code. As can be seen from Fig. 16, even if the bit pattern is the same, if the transmission line code is different, the voltage pattern is different, and therefore the frequency characteristics are also different. Therefore, by changing the transmission line code of the evaluation signal, it is possible to change the frequency characteristics of the voltage pattern representing the evaluation signal without changing the bit pattern.

[0104] Fig. 17 is a diagram showing an example of a transmission channel code table that manages a plurality of transmission channel codes. The transmission channel code table includes an index N, an evaluation signal ID, and a transmission channel code. In the example of Fig. 17, four types of transmission channel codes are included in the transmission channel code table. A common transmission channel code table is stored in advance in the memory 20 of each semiconductor chip 1 in the communication system. That is, information on a plurality of transmission channel codes to be used is shared in advance among the plurality of semiconductor chips 1 included in the communication system.

[0105] Fig. 18 is a flowchart of the evaluation frame transmission process in the sensing process when using a method of changing the transmission line code of the evaluation signal. In Fig. 18, Nmax is the number of transmission line codes stored in the transmission line code table, and is 4 in the example of Fig. 17.

[0106] In S1803, the processor 10a sets a bit string representing the "evaluation frame" to the "frame control signal" of the evaluation frame. The processor 10a also refers to the transmission line code table stored in the memory 20a and sets a bit string representing the evaluation signal ID corresponding to the current index N (for example, "1100" when N=1) to the "frame control signal."

[0107] In S1807, the processor 10a sets a bit string (e.g., "101100") representing the evaluation signal to the "evaluation signal" of the evaluation frame. Here, unlike S907 in Fig. 9, the same bit pattern can be used as the evaluation signal regardless of the current value of index N.

[0108] In S1809, the processor 10a transmits an evaluation frame to the semiconductor chip 1b. Specifically, the processor 10a applies Txdata and Txdata(bar) to the transmission coil 30a by inputting a pulse sequence corresponding to the bit sequence of the evaluation frame to the transmission side conversion circuit 50. At this time, the processor 10a refers to the transmission line code table stored in the memory 20a and performs encoding on the bit sequence of the evaluation signal in the evaluation frame using the transmission line code corresponding to the current index N. This makes it possible to change the frequency characteristic of the voltage pattern in which the evaluation signal is encoded for each evaluation frame without changing the bit pattern of the evaluation signal. Note that a predetermined transmission line code (e.g., NRZ) is used for the portion other than the evaluation signal.

[0109] Next, with reference to FIG. 19, an evaluation value acquisition process, which is part of the sensing process, will be described in the case where a method of changing the transmission line code of an evaluation signal is used.

[0110] In S1902, the processor 10b decodes the frame control signal following the preamble signal and determines whether the type of the frame is an evaluation frame. If the type of the frame is an evaluation frame, the process proceeds to S1004, and if not, the process proceeds to S1003. Note that if the type of the frame is an evaluation frame, the frame control signal also includes a bit string representing the evaluation signal ID, and therefore the evaluation signal ID is also obtained by decoding the frame control signal.

[0111] In S1907, the processor 10b decodes the evaluation signal based on the evaluation signal ID acquired in S1902, and acquires the decoded evaluation signal (received bit string). Specifically, the processor 10b refers to a transmission channel code table stored in the memory 20b to identify a transmission channel code corresponding to the evaluation signal ID. The processor 10b then decodes the evaluation signal according to the identified transmission channel code. Note that the processor 10b decodes the parts other than the evaluation signal according to a predetermined transmission channel code (for example, NRZ).

[0112] In S1908, the processor 10b detects (counts) the number of bit errors by comparing a predetermined known correct bit sequence with the decoded evaluation signal (the received bit sequence), and obtains an evaluation value based on the number of bit errors. The processor 10b records the obtained evaluation value in the memory 20b. At that time, the processor 10b records the reception time of the evaluation frame from which the evaluation value was obtained, and the transmission source ID of the evaluation frame, in association with the evaluation value. As a result, information indicating the time series change of the evaluation value corresponding to a specific transmission source is accumulated in the memory 20b.

[0113] As for the positional relationship determination process in the sensing process, the processor 10b executes the process shown in FIG. 11 in the same manner as in the case of using the method of changing the bit pattern of the evaluation signal.

[0114] <Modification regarding the method of notifying evaluation signal ID> In the above description, the processor 10a of the semiconductor chip 1a notifies the semiconductor chip 1b of the evaluation signal ID by setting the evaluation signal ID in the frame control signal of the evaluation frame. However, the method of notifying the evaluation signal ID is not limited to the method described above.

[0115] As an example, a configuration can be adopted in which the evaluation signal ID also serves as a signal indicating the frame type. For example, if the signal indicating the frame type is 4 bits, the signal indicating the frame type is defined as follows: "0001" indicates "information frame," "0010" indicates "control frame," and "0011" indicates "management frame." Also, the signal indicating the frame type is defined as follows: all of "1100," "1101," and "1110," which are exemplified as evaluation signal IDs in FIG. 8, indicate "evaluation frame." In this case, setting the evaluation signal ID in the frame control signal means simultaneously setting a signal indicating "evaluation frame" as the frame type in the frame control signal.

[0116] As another example, as shown in Fig. 20(a), a region for the evaluation signal ID (second signal portion) may be provided between the sender ID signal and the evaluation signal of the evaluation frame. In this case, for frames other than the evaluation frame, the region for the evaluation signal ID may be deleted or used for other purposes. For example, for information frames, the region for the evaluation signal ID may be used as part of the region for the data signal.

[0117] By adopting either of the two configurations illustrated above, there is no need to provide additional bits for the evaluation frame in the frame control signal, so the number of bits in the frame control signal can be reduced, thereby reducing wireless communication overhead.

[0118] Also, a configuration may be adopted in which the semiconductor chip 1a and the semiconductor chip 1b share information indicating the change pattern of the evaluation signal in advance, thereby making it unnecessary to notify the evaluation signal ID. For example, the processor 10a of the semiconductor chip 1a transmits information indicating the change pattern of the evaluation signal to the semiconductor chip 1b using an information frame. This allows the processor 10b of the semiconductor chip 1b to know in advance that the evaluation signals corresponding to the three types of evaluation signal IDs, such as evaluation signal IDs "1100" → "1101" → "1110" → "1100" → "1101" → "1110" → ..., will be used repeatedly in sequence. After that, the processor 10b identifies the correct evaluation signal (bit sequence) according to the change pattern of the evaluation signal every time it receives an evaluation frame, and obtains an evaluation value by comparing the received bit sequence with the correct bit sequence. Even when such a configuration is adopted, the number of bits of the frame control signal can be reduced, thereby reducing the overhead of wireless communication.

[0119] In a configuration that does not require the notification of the evaluation signal ID, if the semiconductor chip 1a and the semiconductor chip 1b continue to be far apart, many bit errors occur for a long period of time, and the semiconductor chip 1b may lose track of the timing of changing the evaluation signal. Therefore, a configuration may be adopted in which information indicating a change pattern of the evaluation signal is shared in advance between the semiconductor chip 1a and the semiconductor chip 1b, and the semiconductor chip 1a explicitly notifies the semiconductor chip 1b of the evaluation signal ID. In this configuration, if the semiconductor chip 1b is unable to correctly acquire the evaluation signal ID due to a temporary bit error, it can identify the correct evaluation signal according to the change pattern shared in advance and acquire the evaluation value. Even if the semiconductor chip 1b loses track of the timing of changing the evaluation signal, it can recognize the timing of changing the evaluation signal when it subsequently correctly receives the evaluation signal ID.

[0120] <Modifications regarding the format of the evaluation frame> In the above description, the evaluation frame has a format such as that shown in Fig. 7 or Fig. 20(a). However, the format of the evaluation frame is not limited to the format such as that shown in Fig. 7 or Fig. 20(a).

[0121] For example, when the transmission timing of the evaluation frame is shared in advance between the semiconductor chips 1a and 1b, the evaluation frame shown in Fig. 20(b) can be used. In this case, when a pulse train (Rxdata) is supplied from the receiving conversion circuit 60b at a known timing, the processor 10b of the semiconductor chip 1b determines that the pulse train is an evaluation frame, and can obtain the evaluation signal ID and the evaluation signal by decoding the pulse train.

[0122] An example of a method for sharing the transmission timing of the evaluation frame between the semiconductor chips 1a and 1b in advance is a method using an information frame (FIG. 6). For example, the processor 10a of the semiconductor chip 1a transmits to the semiconductor chip 1b an information frame in which information indicating the transmission timing is set in the "data signal", such as "after transmitting the information frame, transmit an evaluation frame every 0.2 seconds". By receiving this information frame, the processor 10b of the semiconductor chip 1b can recognize that the evaluation frame is transmitted every 0.2 seconds, such as 0.2 seconds, 0.4 seconds, 0.6 seconds, ..., starting from the transmission time of the information frame.

[0123] <Modifications on Method of Generating Multiple Evaluation Signals> The above describes a configuration that uses an evaluation signal table (FIG. 8) that manages multiple evaluation signals (bit patterns) in order to generate multiple evaluation signals with different bit patterns. However, the method of generating multiple evaluation signals with different bit patterns is not limited to the method described above. Other examples include a method that uses a pseudo random bit sequence (PRBS) generator and a method that changes the number of bit repetitions. Each method will be described in turn below.

[0124] ● Using a PRBS generator In this method, each semiconductor chip 1 includes a PRBS generator. The PRBS generator can be implemented according to any known technology (for example, the technology disclosed in Non-Patent Document 1). The PRBS generator may be implemented as a dedicated hardware circuit included in the semiconductor chip 1, or may be implemented as a software function executed by the processor 10 of the semiconductor chip 1. In the following description, it is assumed that the PRBS generator is implemented as a software function executed by the processor 10 of the semiconductor chip 1.

[0125] The PRBS generator of the semiconductor chip 1a and the PRBS generator of the semiconductor chip 1b are configured to generate a bit string (PRBS) using a common algorithm. A common initial value is set in the PRBS generator of the semiconductor chip 1a and the PRBS generator of the semiconductor chip 1b. In this case, the multiple bit strings sequentially generated by the PRBS generator of the semiconductor chip 1a match the multiple bit strings sequentially generated by the PRBS generator of the semiconductor chip 1b. The multiple bit strings sequentially generated in this manner can be used as multiple evaluation signals.

[0126] For example, the processor 10a of the semiconductor chip 1a sets a predetermined initial value in its own PRBS generator, and transmits information indicating this initial value to the semiconductor chip 1b using an information frame. The processor 10b of the semiconductor chip 1b sets the received initial value in its own PRBS generator. Thereafter, when the processor 10a of the semiconductor chip 1a transmits a plurality of evaluation frames in sequence, it uses each bit sequence sequentially generated by the PRBS generator as an evaluation signal for each evaluation frame. The processor 10b of the semiconductor chip 1b generates a bit sequence using the PRBS generator every time it receives an evaluation frame, and obtains an evaluation value by comparing the decoded evaluation signal (the received bit sequence) with the generated bit sequence (i.e., the correct bit sequence).

[0127] When generating multiple evaluation signals using a PRBS generator in this way, there is no need to store an evaluation signal table (FIG. 8) in the memory 20 of each semiconductor chip 1. This makes it possible to reduce the amount of memory 20 used. Also, since there is no need to include an evaluation signal ID in the evaluation frame, the number of bits in the evaluation frame can be reduced, thereby reducing wireless communication overhead.

[0128] Alternatively, a configuration may be adopted in which multiple initial values ​​are shared in advance between the semiconductor chip 1a and the semiconductor chip 1b, and multiple evaluation signals are generated for each of the multiple initial values ​​by a PRBS generator. For example, the processor 10a of the semiconductor chip 1a transmits information indicating the initial value X and the initial value Y to the semiconductor chip 1b using an information frame. After that, when the processor 10a transmits multiple evaluation frames sequentially, it uses a different bit string for each frame as the evaluation signal, such as a bit string generated from the initial value X for the first time, a bit string generated from the initial value Y for the first time, a bit string generated from the initial value X for the second time, a bit string generated from the initial value Y for the second time, a bit string generated from the initial value X for the third time, and so on. This can further reduce the bias in the frequency characteristics of the evaluation signal.

[0129] How to change the number of times a bit is repeated By varying the number of times each bit in a particular bit pattern is repeated, it is possible to generate multiple bit patterns that can be used as multiple evaluation signals from one bit pattern.

[0130] For example, for an 8-bit bit pattern "11001010," if each bit is repeated twice, a 16-bit bit pattern "1111000011001100" is obtained. The original bit pattern "11001010" (repetition count = 1) and the bit pattern "1111000011001100" obtained by repeating the bits (repetition count = 2) can be used as multiple evaluation signals.

[0131] When this method is used, the original bit pattern is shared in advance between the semiconductor chip 1a and the semiconductor chip 1b. For example, the processor 10a of the semiconductor chip 1a uses an information frame to transmit information indicating the original bit pattern to the semiconductor chip 1b. The processor 10a of the semiconductor chip 1a can transmit a plurality of evaluation signals with different frequency characteristics by changing the number of repetitions to 1, 2, 1, 2, . . . each time it transmits an evaluation frame. The processor 10b of the semiconductor chip 1b can generate a correct bit string to be compared with the received bit string from the original bit pattern by changing the number of repetitions to 1, 2, 1, 2, . . . each time it receives an evaluation frame.

[0132] In order to unify the number of bits among multiple evaluation signals, a part of a bit pattern obtained by repeating bits may be extracted and used as an evaluation signal. For example, "11110000" extracted from the first 8 bits of the bit pattern "1111000011001100" (repetition count = 2) may be used as the bit pattern corresponding to "repetition count = 2".

[0133] When generating a plurality of evaluation signals by changing the number of times each bit in a specific bit pattern is repeated in this manner, there is no need to store an evaluation signal table (FIG. 8) in the memory 20 of each semiconductor chip 1. This makes it possible to reduce the amount of memory 20 used. Also, since there is no need to include an evaluation signal ID in an evaluation frame, the number of bits in the evaluation frame can be reduced, thereby reducing wireless communication overhead.

[0134] The processor 10a may include information indicating the number of times the bits are repeated in the evaluation frame, which makes it possible to change the number of times the bits are repeated in an arbitrary pattern.

[0135] <Modifications regarding the length (number of bits) of the evaluation signal> Generally, the more bits of the evaluation signal, the more accurate the evaluation value that can be obtained. However, when the distance between the semiconductor chips 1 is long and the BER is large (for example, about 0.5), the accuracy of the evaluation value (BER) does not improve much even if the number of bits of the evaluation signal is increased. Therefore, a configuration may be adopted in which the number of bits of the evaluation signal is changed according to the evaluation value.

[0136] In this case, the processor 10b of the semiconductor chip 1b acquires the evaluation value and then transmits the acquired evaluation value to the semiconductor chip 1a. For example, the processor 10b can include the evaluation value in an ACK signal or a NACK signal (see S1009 in FIG. 10, FIG. 15, and FIG. 19) to be transmitted to the semiconductor chip 1a.

[0137] If the processor 10a fails to receive an ACK signal or a NACK signal corresponding to the transmitted evaluation frame, the quality of the wireless communication is likely to be extremely poor, and therefore the evaluation value (BER) may be determined to be 0.5.

[0138] The processor 10a of the semiconductor chip 1a compares the received evaluation value with one or more thresholds to determine the number of bits of the evaluation signal of the evaluation frame to be transmitted next. For example, the processor 10a determines the number of bits of the evaluation signal of the evaluation frame to be transmitted next when the evaluation value (BER) is 10 -10 If it is less than 10, the number of bits is determined to be 16. -10 If the BER is greater than or equal to 0.1 and less than 0.1, the number of bits is determined to be 8, and if the BER is greater than or equal to 0.1, the number of bits is determined to be 4. This prevents the transmission of long evaluation signals in situations where little improvement in the accuracy of the evaluation value is expected, thereby achieving efficient wireless communication.

[0139] The processors 10a and 10b are configured to be able to acquire an evaluation signal with the longest number of bits that may be determined. For example, when a PRBS generator is used, if the longest number of bits is 16, the PRBS generators of the processors 10a and 10b are configured to generate a 16-bit bit string. For example, if the number of bits actually determined is 8 bits, the processors 10a and 10b can use the first 8 bits of the 16-bit bit string generated by the PRBS generator as the evaluation signal. The processor 10b can know the number of bits of the evaluation signal in the received evaluation frame by subtracting the length of the area other than the evaluation signal from the frame length acquired from the "frame length signal" of the evaluation frame.

[0140] <Various concrete examples of positional relationships> Here, a specific example of the determination regarding the positional relationship performed in S1103 of Fig. 11 will be described. Note that the following describes the case where the semiconductor chip 1b transmits an evaluation frame to the semiconductor chip 1a (hence, the case where the semiconductor chip 1a executes the positional relationship determination process of Fig. 11).

[0141] For example, as shown in FIG. 21, consider a case where semiconductor chips 1a and 1b are arranged on a measurement target 4 at a distance Dx apart in the horizontal direction (X-axis direction). The measurement target 4 is a material that expands and contracts in the X-axis direction, such as an iron rail or a steel frame. In this case, when the measurement target 4 expands and contracts in the X-axis direction due to factors such as temperature change, the distance Dx changes accordingly. As described above, when the distance Dx changes, the coupling coefficient between the semiconductor chip 1a and the semiconductor chip 1b changes, and the number of bit errors in the evaluation signal changes. Therefore, the evaluation value based on the number of bit errors (e.g., BER) and the composite evaluation value (e.g., average BER) also change.

[0142] FIG. 22 is a diagram showing an example of the relationship between the distance Dx between the semiconductor chips 1a and 1b and the BER in the form of a graph and a table. Information showing the relationship between the distance Dx and the BER can be obtained, for example, by conducting an experiment in advance to measure the BER at multiple distances. The BER obtained here may be a BER based on one evaluation signal, or an average BER based on multiple evaluation signals. Therefore, the "BER" in FIG. 22 may be an average BER. This also applies to FIG. 23 and subsequent figures.

[0143] As can be seen from Fig. 22, the BER changes significantly at distances of around 450 μm. Therefore, the BER (1×10 -4 ) as a threshold value and stored in advance in the memory 20 of each semiconductor chip 1. In this case, in S1103 of FIG. 11, the processor 10a of the semiconductor chip 1a calculates the average BER (composite evaluation value) acquired in S1102 and the threshold value (1×10 -4 ), it is possible to determine whether or not the distance Dx is greater than 450 μm. That is, as a determination regarding the positional relationship, it is possible to determine whether or not the distance Dx is greater than a specific distance (here, 450 μm).

[0144] Also, for example, it is assumed that Dx is less than 450 μm in the original desirable positional relationship. In this case, the processor 10a determines whether the average BER (composite evaluation value) acquired in S1102 is greater than or equal to a threshold value (1×10 -4 ), it can be determined that the positional relationship between the semiconductor chips 1a and 1b has shifted from the original desirable positional relationship.

[0145] In the example of FIG. 22, the change in distance Dx occurs in response to expansion and contraction of the measurement target 4, so that the communication system including the semiconductor chips 1a and 1b can function as a sensor that detects expansion and contraction of the measurement target 4.

[0146] In the example of FIG. 22, the number of thresholds for BER is 1, but it may be 2 or more. In other words, the number of thresholds L may be any number as long as it is an integer equal to or greater than 1. FIG. 23 is a diagram showing an example in which four thresholds are set for BER. In this example, four BERs (1×10) corresponding to Dx=Dth1 (440 μm), Dth2 (445 μm), Dth3 (450 μm), and Dth4 (460 μm) are set as the four thresholds. -8 , 1×10 -5 , 1×10 -4 , 1×10 -3 ) is stored in advance in the memory 20 of each semiconductor chip 1. In this case, by determining where the average BER acquired in S1102 is located in the five sections divided by the four thresholds, it is possible to determine the positional relationship more accurately.

[0147] 23, information showing the relationship between the distance Dx and the BER in detail may be stored in the memory 20 of each semiconductor chip 1. In this case, it becomes possible to determine the positional relationship in more detail.

[0148] In the above description, the determination of the positional relationship is performed with respect to the distance Dx in the horizontal direction (X-axis direction) between the semiconductor chips 1a and 1b. However, the positional relationship that can be determined in this embodiment is not limited to the distance Dx in the horizontal direction (X-axis direction).

[0149] For example, as shown in Fig. 24(a), consider a case where the semiconductor chips 1a and 1b are displaced in the Y-axis direction due to the properties of the measurement target 4. In this case, as shown in Fig. 24(b), by acquiring information indicating the relationship between the displacement amount Dy in the Y-axis direction and the BER by a prior measurement, a BER threshold value for the displacement amount Dy can be determined and stored in the memory 20 of each semiconductor chip 1. This makes it possible to make a judgment regarding the displacement amount Dy as a judgment regarding the positional relationship.

[0150] As another example, consider the case where the semiconductor chip 1a is placed on the measurement target 4a, and the semiconductor chip 1b is placed on the measurement target 4b, as shown in Figs. 25(a) and (b). The contact point between the measurement target 4a and the measurement target 4b corresponds to the middle point between the semiconductor chip 1a and the semiconductor chip 1b, and the measurement target 4a is configured to rotate around this contact point as an axis. When the measurement target 4a and the measurement target 4b are horizontally aligned, the distance in the X-axis direction between the semiconductor chips 1a and 1b is Dx. In this case, as shown in Fig. 25(c), by acquiring information indicating the relationship between the angle Da of the measurement target 4a with respect to the X-axis and the BER by a prior measurement, the BER threshold value for the angle Da can be determined and stored in the memory 20 of each semiconductor chip 1. This makes it possible to perform a judgment regarding the angle Da as a judgment regarding the positional relationship.

[0151] As yet another example, consider a case where semiconductor chips 1a and 1b are arranged as shown in Figures 26(a) and (b). Unlike the cases of Figures 25(a) and (b), in Figures 26(a) and (b), the measurement target 4a rotates around the left side as the axis. In this case, as shown in Figure 26(c), by acquiring information indicating the relationship between the angle Da of the measurement target 4a with respect to the X-axis and the BER by a prior measurement, it is possible to determine the BER threshold value for the angle Da and store it in the memory 20 of each semiconductor chip 1. This makes it possible to make a judgment regarding the angle Da as a judgment regarding the positional relationship.

[0152] As another example, consider the case where the semiconductor chips 1a and 1b are arranged as shown in Figs. 27(a) and (b). Unlike the case of Figs. 26(a) and (b), in Figs. 27(a) and (b), the measurement target 4a rotates about the axis in the Y-axis direction passing through the center of the semiconductor chip 1a in the X-axis direction. In this case, as shown in Fig. 27(c), by acquiring information indicating the relationship between the rotation angle Dr of the measurement target 4a with respect to the X-axis and the BER by a prior measurement, a threshold value of the BER for the rotation angle Dr can be determined and stored in the memory 20 of each semiconductor chip 1. This makes it possible to make a judgment regarding the rotation angle Dr as a judgment regarding the positional relationship. In this case, when the rotation angle Dr exceeds 90 degrees, the direction of the magnetic flux penetrating the transmission coil 30a of the semiconductor chip 1a is reversed compared to when the rotation angle Dr is 90 degrees or less. Therefore, the polarity of the voltage induced in the transmission coil 30a is reversed, and as a result, the polarity of Rxdata is also reversed. Therefore, the processor 10a of the semiconductor chip 1a calculates the BER taking into account the pulse inversion.

[0153] As yet another example, consider a case where the semiconductor chips 1a and 1b are arranged as shown in FIG. 28(a). In FIG. 28(a), the measurement target 4b rotates about the axis in the X-axis direction passing through the center of the Y-axis direction of the semiconductor chip 1b. In this case, as shown in FIG. 28(b), by acquiring information indicating the relationship between the rotation angle Dr of the measurement target 4b with respect to the Y-axis and the BER by a prior measurement, a threshold value of the BER for the rotation angle Dr can be determined and stored in the memory 20 of each semiconductor chip 1. This makes it possible to perform a determination regarding the rotation angle Dr as a determination regarding the positional relationship. In this case, when the rotation angle Dr exceeds 90 degrees, the direction of the magnetic flux penetrating the transmission coil 30a of the semiconductor chip 1a is reversed compared to when the rotation angle Dr is 90 degrees or less. Therefore, the polarity of the voltage induced in the transmission coil 30a is reversed, and as a result, the polarity of Rxdata is also reversed. Therefore, the processor 10a of the semiconductor chip 1a calculates the BER taking into account the pulse inversion.

[0154] In the examples so far, the semiconductor chips 1a and 1b are arranged in the X-axis direction on the measurement target 4 (or on the measurement targets 4a and 4b). However, this embodiment is also applicable to the case where the semiconductor chips 1a and 1b are arranged (stacked) in the vertical direction (Z-axis direction).

[0155] For example, consider a case where semiconductor chips 1a and 1b are arranged as shown in Fig. 29(a). In this example, the distance Dz in the Z-axis direction between the semiconductor chips 1a and 1b changes. In this case, as shown in Fig. 29(b), by acquiring information indicating the relationship between the distance Dz in the Z-axis direction and the BER by a prior measurement, a BER threshold value for the distance Dz can be determined and stored in the memory 20 of each semiconductor chip 1. This makes it possible to make a judgment regarding the distance Dz as a judgment regarding the positional relationship.

[0156] As another example, consider a case where semiconductor chips 1a and 1b are arranged as shown in Fig. 30(a) and (b). Unlike the case of Fig. 29(a), the distance Dz in the Z-axis direction does not change in Fig. 30(a) and (b). In this situation, the positional relationship of measurement targets 4a and 4b in the X-axis direction changes. In this case, as shown in Fig. 30(c), by acquiring information indicating the relationship between the displacement amount Dx in the X-axis direction and the BER by a prior measurement, the BER threshold value for the displacement amount Dx can be determined and stored in the memory 20 of each semiconductor chip 1. This makes it possible to perform a judgment regarding the displacement amount Dx as a judgment regarding the positional relationship.

[0157] As yet another example, consider a case where semiconductor chips 1a and 1b are arranged as shown in Fig. 31(a) and (b). Unlike the case of Fig. 29(a), the distance Dz in the Z-axis direction does not change in Fig. 31(a) and (b). In this situation, the positional relationship of measurement targets 4a and 4b in the Y-axis direction changes. In this case, as shown in Fig. 31(c), by acquiring information indicating the relationship between the displacement amount Dy in the Y-axis direction and the BER by a prior measurement, a BER threshold value for the displacement amount Dy can be determined and stored in the memory 20 of each semiconductor chip 1. This makes it possible to perform a judgment regarding the displacement amount Dy as a judgment regarding the positional relationship.

[0158] As another example, consider the case where the semiconductor chips 1a and 1b are arranged as shown in Figs. 32(a) and (b). Unlike the case of Fig. 29(a), in Figs. 32(a) and (b), the distance Dz in the Z-axis direction does not change. In this situation, the positional relationship of the measurement targets 4a and 4b changes in both the X-axis and Y-axis directions. In this case, it is not possible to distinguish between the change in BER caused by the change in the positional relationship in the X-axis direction and the change in BER caused by the change in the positional relationship in the Y-axis direction. Therefore, attention is paid to the distance Dr between the centers of the semiconductor chips 1a and 1b. In this case, as shown in Fig. 32(c), by acquiring information indicating the relationship between the distance Dr between the centers of the semiconductor chips 1a and 1b and the BER, a BER threshold value for the distance Dr can be determined and stored in the memory 20 of each semiconductor chip 1. This makes it possible to perform a judgment regarding the distance Dr as a judgment regarding the positional relationship.

[0159] As yet another example, consider the case where the semiconductor chips 1a and 1b are arranged as shown in FIG. 33(a). In this example, the measurement target 4a rotates around a line parallel to the X-axis as the axis of rotation. In this case, as shown in FIG. 33(b), by acquiring information indicating the relationship between the rotation angle Da with respect to the X-axis and the BER by a prior measurement, a threshold value for the BER regarding the rotation angle Da can be determined and stored in the memory 20 of each semiconductor chip 1. This makes it possible to perform a determination regarding the rotation angle Da as a determination regarding the positional relationship. In this case, when the rotation angle Da exceeds 90 degrees, the direction of the magnetic flux penetrating the transmission coil 30a of the semiconductor chip 1a is reversed compared to when the rotation angle Da is 90 degrees or less. Therefore, the polarity of the voltage induced in the transmission coil 30a is reversed, and as a result, the polarity of Rxdata is also reversed. Therefore, the processor 10a of the semiconductor chip 1a calculates the BER taking into account the pulse inversion.

[0160] <Functional configuration of semiconductor chip 1> 34 is a block diagram showing the functional configuration of the semiconductor chip 1. In FIG. 34, a control unit 3401 is realized by the processor 10 executing a program stored in the memory 20.

[0161] The control unit 3401 performs overall control of the semiconductor chip 1. The control unit 3401 also has a function of performing various controls related to wireless communication of the semiconductor chip 1. The functions of performing various controls here include, for example, the following functions, but are not limited to these. A function of receiving an evaluation value based on the number of bit errors via the communication circuit 3423 and controlling the length of the evaluation signal (see "Modifications Related to the Length (Number of Bits) of the Evaluation Signal") A function of applying (inputting) a voltage pattern (Txdata and Txdata(bar)) to the transmitting coil 30 via the communication circuit 3423 A function for acquiring a voltage pattern (Rxdata) via the communication circuit 3423 A function for decoding the voltage pattern (Rxdata) acquired via the communication circuit 3423 - Function to detect the number of bit errors in the evaluation signal A function to obtain (calculate) an evaluation value based on the number of bit errors detected in an evaluation signal, and a composite evaluation value based on the number of bit errors detected in multiple evaluation signals A function for determining the positional relationship between semiconductor chips 1 based on the evaluation value or the composite evaluation value.

[0162] The generating unit 3402 has the function of the PRBS generator described in “Modification regarding the method of generating a plurality of evaluation signals.” The generating unit 3402 may be implemented as a dedicated hardware circuit included in the semiconductor chip 1, or may be implemented as a software function executed by the processor 10 of the semiconductor chip 1.

[0163] The storage unit 3411 is realized by a part of the storage area of ​​the memory 20. The storage unit 3411 stores various information required for the various processes described above, such as an evaluation signal table (FIG. 8).

[0164] The transmission circuit 3421 is realized by the transmission coil 30 and the transmission side conversion circuit 50. The transmission circuit 3421 performs wireless transmission to the other semiconductor chip 1 via inductive coupling between the transmission coil 30 and the reception coil 40 of the other semiconductor chip 1.

[0165] The receiving circuit 3422 is realized by the receiving coil 40 and the receiving side conversion circuit 60. The receiving circuit 3422 performs wireless reception from the other semiconductor chip 1 via inductive coupling between the receiving coil 40 and the transmitting coil 30 of the other semiconductor chip 1.

[0166] 2, the communication circuit 3423 is realized by the coil 35 and the conversion circuit 55, and the communication circuit 3423 plays the roles of the transmission circuit 3421 and the reception circuit 3422.

[0167] <Summary of the embodiment> The above-described embodiment makes it possible to assist in determining the positional relationship between communication devices such as semiconductor chips.

[0168] The specific configuration of the software (program) and hardware that implements the various functions described in the above-mentioned embodiments is not particularly limited. As long as it is technically possible, any software, any hardware, and any combination of any software and any hardware are included in the scope of the above-mentioned embodiments.

[0169] The above-described embodiments disclose at least the following communication device, control method, and program. [Item 1] A first communication device, a communication circuit including a first coil, the communication circuit performing wireless communication with a second communication device via inductive coupling between the first coil and a second coil of the second communication device; an application means for applying a plurality of voltage patterns to the first coil via the communication circuit, each voltage pattern including a first signal portion used for detecting a number of bit errors in the second communication device, the first signal portion of each voltage pattern having a different frequency characteristic; A first communication device comprising: [Item 2] A first communication device according to item 1, a different bit pattern is encoded in the first signal portion of each voltage pattern; A first communication device. [Item 3] A first communication device according to item 2, Each voltage pattern includes a second signal portion; the second signal portion includes identification information that identifies a bit pattern encoded in the first signal portion of a voltage pattern that includes the second signal portion. A first communication device. [Item 4] A first communication device according to item 1, generating means for pseudo-randomly generating a plurality of bit patterns based on a predetermined initial value; a first signal portion of each voltage pattern encoding a different one of the plurality of bit patterns; the predetermined initial value is shared between the first communication device and the second communication device; A first communication device. [Item 5] A first communication device according to any one of items 1 to 4, the first signal portion includes a pulse train corresponding to a line code; For at least one of the plurality of pulse trains corresponding to the plurality of voltage patterns, a partial period not including a sampling timing in the second communication device has a voltage inverted from a voltage corresponding to the line code. A first communication device. [Item 6] A first communication device according to any one of items 1 to 5, the first signal portion of each voltage pattern corresponds to a different line code; A first communication device. [Item 7] Item 6. A first communication device according to item 6, Each voltage pattern includes a second signal portion; the second signal portion includes identification information for identifying a line code corresponding to the first signal portion of a voltage pattern including the second signal portion; A first communication device. [Item 8] A first communication device according to any one of items 1 to 7, a receiving means for receiving, via the communication circuit, an evaluation value based on the number of bit errors detected in the second communication device, the evaluation value corresponding to the first signal portion of a first voltage pattern among the plurality of voltage patterns; a control means for controlling a length of the first signal portion of a second voltage pattern applied to the first coil after the first voltage pattern based on the evaluation value; The first communication device further comprises: [Item 9] a second communication device, a communication circuit including a second coil, the communication circuit performing wireless communication with the first communication device via inductive coupling between the second coil and a first coil of the first communication device; an acquisition means for acquiring, via the communication circuit, a plurality of reception voltage patterns corresponding to the plurality of transmission voltage patterns applied to the first coil, each transmission voltage pattern including a first transmission signal portion used for detecting a number of bit errors in the second communication device, and the first transmission signal portion of each transmission voltage pattern having a different frequency characteristic; detection means for detecting, for each received voltage pattern, a number of bit errors in a first received signal portion corresponding to said first transmitted signal portion; a determination means for making a determination regarding a positional relationship between the first communication device and the second communication device based on a number of bit errors detected in a plurality of first reception signal portions corresponding to the plurality of reception voltage patterns; A second communication device comprising: [Item 10] Item 9. A second communication device according to item 9, a different bit pattern is encoded in the first transmit signal portion of each transmit voltage pattern; Each transmit voltage pattern includes a second transmit signal portion; the second transmission signal portion includes identification information that identifies a bit pattern encoded in the first transmission signal portion of a transmission voltage pattern that includes the second transmission signal portion; the detection means detects the number of bit errors by comparing, for each received voltage pattern, a bit pattern obtained from the first received signal portion corresponding to the first transmitted signal portion with a bit pattern identified by identification information obtained from the second received signal portion corresponding to the second transmitted signal portion; A second communication device. [Item 11] The second communication device according to item 9 or 10, the first transmit signal portions of each transmit voltage pattern correspond to different line codes; Each transmit voltage pattern includes a second transmit signal portion; the second transmission signal portion includes identification information for identifying a line code corresponding to the first transmission signal portion of a transmission voltage pattern including the second transmission signal portion; the detection means decodes, for each received voltage pattern, the first received signal portion corresponding to the first transmission signal portion based on a transmission line code identified by identification information obtained from the second received signal portion corresponding to the second transmission signal portion; A second communication device. [Item 12] A second communication device according to any one of items 9 to 11, the determining means performs a determination regarding the positional relationship by comparing a composite evaluation value based on a number of bit errors detected in the plurality of first received signal portions with L threshold values; L is an integer equal to or greater than 1. A second communication device. [Item 13] Item 13. A second communication device according to item 12, L is an integer equal to or greater than 2. A second communication device. [Item 14] Item 14. The second communication device according to item 12 or 13, Each of the L thresholds is associated with a respective positional relationship between the first communication device and the second communication device. A second communication device. [Item 15] A control method executed by a first communication device, comprising: the first communication device comprises a communication circuit including a first coil, the communication circuit performing wireless communication with the second communication device via inductive coupling between the first coil and a second coil of a second communication device; The control method includes an application step of applying a plurality of voltage patterns to the first coil via the communication circuit, each voltage pattern including a first signal portion used for detecting a number of bit errors in the second communication device, and the first signal portion of each voltage pattern having a different frequency characteristic. Control methods. [Item 16] A control method executed by a second communication device, the second communication device comprises a communication circuit including a second coil, the communication circuit performing wireless communication with the first communication device via inductive coupling between the second coil and a first coil of the first communication device; The control method includes: an acquiring step of acquiring, via the communication circuit, a plurality of received voltage patterns corresponding to the plurality of transmitted voltage patterns applied to the first coil, each transmitted voltage pattern including a first transmitted signal portion used for detecting a number of bit errors in the second communication device, the first transmitted signal portion of each transmitted voltage pattern having a different frequency characteristic; a detection step of detecting, for each received voltage pattern, a number of bit errors in a first received signal portion corresponding to the first transmitted signal portion; a determination step of determining a positional relationship between the first communication device and the second communication device based on a number of bit errors detected in a plurality of first received signal portions corresponding to the plurality of received voltage patterns; A control method comprising: [Item 17] A program for execution by a processor of a first communication device, the first communication device comprises a communication circuit including a first coil, the communication circuit performing wireless communication with the second communication device via inductive coupling between the first coil and a second coil of a second communication device; When the program is executed by the processor, the program causes the processor to execute an application step of applying a plurality of voltage patterns to the first coil via the communication circuit, each voltage pattern including a first signal portion used for detecting a number of bit errors in the second communication device, the first signal portion of each voltage pattern having a different frequency characteristic. program. [Item 18] A program for execution by a processor of a second communication device, the second communication device comprises a communication circuit including a second coil, the communication circuit performing wireless communication with the first communication device via inductive coupling between the second coil and a first coil of the first communication device; The program, when executed by the processor, causes the processor to: an acquiring step of acquiring, via the communication circuit, a plurality of received voltage patterns corresponding to the plurality of transmitted voltage patterns applied to the first coil, each transmitted voltage pattern including a first transmitted signal portion used for detecting a number of bit errors in the second communication device, the first transmitted signal portion of each transmitted voltage pattern having a different frequency characteristic; a detection step of detecting, for each received voltage pattern, a number of bit errors in a first received signal portion corresponding to the first transmitted signal portion; a determination step of determining a positional relationship between the first communication device and the second communication device based on a number of bit errors detected in a plurality of first received signal portions corresponding to the plurality of received voltage patterns; A program to execute.

[0170] The invention is not limited to the above-described embodiment, and various modifications and variations are possible within the scope of the gist of the invention. [Explanation of symbols]

[0171] 1...semiconductor chip, 10...processor, 20...memory, 30...transmitting coil, 40...receiving coil, 50...transmitting side conversion circuit, 60...receiving side conversion circuit

Claims

1. A first communication device, a communication circuit including a first coil, the communication circuit performing wireless communication with a second communication device via inductive coupling between the first coil and a second coil of the second communication device; an application means for applying a plurality of voltage patterns to the first coil via the communication circuit, each voltage pattern including a first signal portion used for detecting a number of bit errors in the second communication device, the first signal portion of each voltage pattern having a different frequency characteristic; A first communication device comprising:

2. 2. A first communication device according to claim 1, a different bit pattern is encoded in the first signal portion of each voltage pattern; A first communication device.

3. A first communication device according to claim 2, Each voltage pattern includes a second signal portion; the second signal portion includes identification information that identifies a bit pattern encoded in the first signal portion of a voltage pattern that includes the second signal portion; A first communication device.

4. 2. A first communication device according to claim 1, generating means for pseudo-randomly generating a plurality of bit patterns based on a predetermined initial value; a first signal portion of each voltage pattern encoding a different one of the plurality of bit patterns; the predetermined initial value is shared between the first communication device and the second communication device; A first communication device.

5. A first communication device according to any one of claims 1 to 4, the first signal portion includes a pulse train corresponding to a line code; For at least one of the plurality of pulse trains corresponding to the plurality of voltage patterns, a partial period not including a sampling timing in the second communication device has a voltage inverted from a voltage corresponding to the transmission line code. A first communication device.

6. A first communication device according to any one of claims 1 to 4, the first signal portion of each voltage pattern corresponds to a different line code. A first communication device.

7. A first communication device according to claim 6, Each voltage pattern includes a second signal portion; the second signal portion includes identification information for identifying a line code corresponding to the first signal portion of a voltage pattern including the second signal portion; A first communication device.

8. A first communication device according to any one of claims 1 to 4, a receiving means for receiving, via the communication circuit, an evaluation value based on a number of bit errors detected in the second communication device, the evaluation value corresponding to the first signal portion of a first voltage pattern among the plurality of voltage patterns; a control means for controlling a length of the first signal portion of a second voltage pattern applied to the first coil after the first voltage pattern based on the evaluation value; The first communication device further comprises:

9. A first communication device according to any one of claims 1 to 4, Each voltage pattern includes a plurality of signal portions that form a frame having a predetermined format; the first signal portion of each voltage pattern is one of the plurality of signal portions. A first communication device.

10. a second communication device, a communication circuit including a second coil, the communication circuit performing wireless communication with the first communication device via inductive coupling between the second coil and a first coil of the first communication device; an acquisition means for acquiring, via the communication circuit, a plurality of reception voltage patterns corresponding to the plurality of transmission voltage patterns applied to the first coil, each transmission voltage pattern including a first transmission signal portion used for detecting a number of bit errors in the second communication device, the first transmission signal portion of each transmission voltage pattern having a different frequency characteristic; detection means for detecting, for each received voltage pattern, a number of bit errors in a first received signal portion corresponding to said first transmitted signal portion; a determination means for making a determination regarding a positional relationship between the first communication device and the second communication device based on a number of bit errors detected in a plurality of first reception signal portions corresponding to the plurality of reception voltage patterns; A second communication device comprising:

11. A second communication device according to claim 10, a different bit pattern is encoded in the first transmit signal portion of each transmit voltage pattern; Each transmit voltage pattern includes a second transmit signal portion; the second transmission signal portion includes identification information that identifies a bit pattern encoded in the first transmission signal portion of a transmission voltage pattern that includes the second transmission signal portion; the detection means detects the number of bit errors by comparing, for each received voltage pattern, a bit pattern obtained from the first received signal portion corresponding to the first transmitted signal portion with a bit pattern identified by identification information obtained from the second received signal portion corresponding to the second transmitted signal portion; A second communication device.

12. A second communication device according to claim 10 or 11, the first transmit signal portions of each transmit voltage pattern correspond to different line codes; Each transmit voltage pattern includes a second transmit signal portion; the second transmission signal portion includes identification information for identifying a line code corresponding to the first transmission signal portion of a transmission voltage pattern including the second transmission signal portion, the detection means decodes, for each received voltage pattern, the first received signal portion corresponding to the first transmission signal portion based on a transmission line code identified by identification information obtained from the second received signal portion corresponding to the second transmission signal portion; A second communication device.

13. A second communication device according to claim 10 or 11, the determining means performs a determination regarding the positional relationship by comparing a composite evaluation value based on a number of bit errors detected in the plurality of first received signal portions with L threshold values; L is an integer of 1 or more; A second communication device.

14. A second communication device according to claim 13, L is an integer of 2 or more; A second communication device.

15. A second communication device according to claim 13, Each of the L thresholds is associated with a respective positional relationship between the first communication device and the second communication device. A second communication device.

16. A second communication device as claimed in claim 13, comprising: Each transmit voltage pattern includes a plurality of transmit signal portions forming a frame having a predetermined format; the first transmit signal portion of each transmit voltage pattern is one of the plurality of transmit signal portions. A second communication device.

17. A control method executed by a first communication device, comprising: the first communication device comprises a communication circuit including a first coil, the communication circuit performing wireless communication with the second communication device via inductive coupling between the first coil and a second coil of a second communication device; The control method includes an application step of applying a plurality of voltage patterns to the first coil via the communication circuit, each voltage pattern including a first signal portion used for detecting a number of bit errors in the second communication device, and the first signal portion of each voltage pattern having a different frequency characteristic. Control methods.

18. A control method executed by a second communication device, comprising: the second communication device comprises a communication circuit including a second coil, the communication circuit performing wireless communication with the first communication device via inductive coupling between the second coil and a first coil of the first communication device; The control method includes: an acquiring step of acquiring, via the communication circuit, a plurality of received voltage patterns corresponding to the plurality of transmitted voltage patterns applied to the first coil, each transmitted voltage pattern including a first transmitted signal portion used for detecting a number of bit errors in the second communication device, the first transmitted signal portion of each transmitted voltage pattern having a different frequency characteristic; a detection step of detecting, for each received voltage pattern, a number of bit errors in a first received signal portion corresponding to said first transmitted signal portion; a determination step of making a determination regarding a positional relationship between the first communication device and the second communication device based on a number of bit errors detected in a plurality of first received signal portions corresponding to the plurality of received voltage patterns; A control method comprising:

19. A program for execution by a processor of a first communication device, the first communication device comprises a communication circuit including a first coil, the communication circuit performing wireless communication with the second communication device via inductive coupling between the first coil and a second coil of a second communication device; When the program is executed by the processor, the program causes the processor to execute an application step of applying a plurality of voltage patterns to the first coil via the communication circuit, each voltage pattern including a first signal portion used for detecting a number of bit errors in the second communication device, the first signal portion of each voltage pattern having a different frequency characteristic. program.

20. A program for execution by a processor of a second communication device, the second communication device comprises a communication circuit including a second coil, the communication circuit performing wireless communication with the first communication device via inductive coupling between the second coil and a first coil of the first communication device; The program, when executed by the processor, causes the processor to: an acquiring step of acquiring, via the communication circuit, a plurality of received voltage patterns corresponding to the plurality of transmitted voltage patterns applied to the first coil, each transmitted voltage pattern including a first transmitted signal portion used for detecting a number of bit errors in the second communication device, the first transmitted signal portion of each transmitted voltage pattern having a different frequency characteristic; a detection step of detecting, for each received voltage pattern, a number of bit errors in a first received signal portion corresponding to said first transmitted signal portion; a determination step of making a determination regarding a positional relationship between the first communication device and the second communication device based on a number of bit errors detected in a plurality of first received signal portions corresponding to the plurality of received voltage patterns; A program to execute.

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