Amorphous silicon-based film resistant to crystallization

Abstract

The deposition method may prevent or reduce crystallization of silicon in the deposited amorphous silicon film, which may occur after annealing at high temperatures. Silicon crystallization can be prevented by doping the silicon with an element. The element may be boron, carbon, or phosphorus. Doping above a certain concentration of the element prevents substantial crystallization at high temperatures and for durations of 30 minutes or more. Methods and devices are described.

Description

[Technical field]

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This application claims the benefit of priority to U.S. patent application Ser. No. 62 / 929,365, filed Nov. 1, 2019, the contents of which are incorporated by reference in their entirety for all purposes. Technical Field

[0002] The present technology relates to semiconductor deposition processes, and more particularly, to methods for preventing silicon crystallization in deposited amorphous silicon layers. [Background technology]

[0002] background

[0003] Integrated circuits are made possible by processes that produce intricately patterned layers of material on substrate surfaces. Fabricating patterned materials on substrates requires controlled methods of formation and removal of exposed material. As device sizes continue to shrink, material uniformity can affect subsequent operations. For example, surface uniformity of masking materials can affect subsequent etch uniformity.

[0003]

[0004] Thus, there is a need for improved systems and methods that can be used to manufacture high quality devices and structures. These and other needs are addressed by the present technology. Summary of the Invention

[0004]

[0005] An example of a deposition method can prevent or reduce crystallization of silicon in a deposited amorphous silicon film that may occur after annealing at high temperatures. Silicon can be prevented from crystallizing by doping it with an element. The element can be boron, carbon, or phosphorus. Doping beyond a certain concentration of the element prevents substantial crystallization at high temperatures and for durations of 30 minutes or more.

[0005]

[0006] An embodiment may include a deposition method. The method may include delivering a silicon-containing precursor and a dopant-containing precursor to a processing region of a semiconductor processing chamber. The dopant may include boron, carbon, or phosphorus. The atomic percentage of the dopant atoms in the dopant-containing precursor relative to the sum of the dopant atoms in the dopant-containing precursor and the silicon atoms in the silicon-containing precursor may range from 5% to 40%. The method may further include forming a plasma of the silicon-containing precursor and the dopant-containing precursor in the processing region of the semiconductor processing chamber. The method may also include depositing the silicon-dopant material on a substrate disposed in the processing region of the semiconductor processing chamber. Additionally, the method may include performing a thermal annealing of the silicon-dopant material to form an annealed silicon-dopant material on the substrate. The annealed silicon-dopant material may be substantially free of crystalline silicon.

[0006]

[0007] The embodiment may also include a method including delivering a silicon-containing precursor and a boron-containing precursor to a processing region of a semiconductor processing chamber. The atomic percentage of the dopant atoms in the dopant-containing precursor relative to the sum of the dopant atoms in the dopant-containing precursor and the silicon atoms in the silicon-containing precursor may range from 5% to 40%. The method may also include forming a plasma of the silicon-containing precursor and the boron-containing precursor in the processing region of the semiconductor processing chamber. The method may further include depositing the silicon-boron material on a substrate disposed in the processing region of the semiconductor processing chamber. Additionally, the method may include patterning the silicon-boron material to form a patterned silicon-boron material. The method may further include depositing a silicon nitride material by atomic layer deposition on the patterned silicon-boron material. Additionally, the method may include performing a thermal annealing of the patterned silicon-boron material at a temperature in the range of 650° C. to 850° C. to form an annealed silicon-boron material. The annealed silicon-boron material can be substantially free of crystalline silicon.

[0007]

[0008] The embodiment may include a semiconductor device. The device may include a substrate. The device may also include a silicon-dopant material on the substrate. The dopant may include boron, carbon, or phosphorus. The atomic percentage of the dopant atoms relative to the sum of the dopant atoms and silicon atoms in the silicon-dopant material may range from 5% to 40%. The silicon-dopant material may be substantially free of crystalline silicon. Additionally, the silicon-dopant material may be patterned. Additionally, the device may include a silicon nitride material on the silicon-dopant layer. The silicon nitride material and the silicon-dopant material may be annealed at a temperature of 650° C. to 850° C. for at least 2 hours.

[0008]

[0009] Such techniques may provide many advantages over conventional systems and techniques. For example, the process may produce films characterized by improved uniformity. Additionally, operation of embodiments of the present techniques may produce improved mask materials that may facilitate processing operations. These and other embodiments, along with many of their advantages and features, are described in more detail in conjunction with the following description and accompanying figures.

[0009]

[0010] A further understanding of the nature and advantages of the disclosed technology may be realized by reference to the remaining portions of the specification and drawings. [Brief description of the drawings]

[0010] [Figure 1]

[0011] 1 shows a schematic cross-sectional view of an exemplary processing chamber in accordance with some embodiments of the present technique. [Diagram 2]

[0012] 1 illustrates exemplary operations in a deposition method according to some embodiments of the present technique. [Figure 3A-3C]

[0013] 3A-3C illustrate the processing of a semiconductor layer according to some embodiments of the present technique. [Figure 4]

[0014] 1 shows Raman spectroscopy results of deposited materials according to some embodiments of the present technique. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0011]

[0015] Some of the figures are included as schematic diagrams. It is understood that these figures are for illustrative purposes and should not be considered to be to scale unless specifically stated to be to scale. Furthermore, as schematic diagrams, the figures are provided to aid in understanding and may not include all aspects or information compared to realistic representations and may include exaggerated material for illustrative purposes.

[0012]

[0016] In the accompanying figures, similar components or features may have the same reference label. Additionally, various components of the same type may be distinguished by tracing the reference numbers with a letter that distinguishes the similar components. When only a first reference number is used in this specification, the description is applicable to any one of the similar components having the same first reference number, regardless of the letter.

[0013]

[0017] Processing of semiconductor devices may include annealing at high temperatures for several hours. This high temperature annealing may cause further reactions in the deposited semiconductor layers. For example, an amorphous silicon layer may be deposited. After annealing at a temperature of about 650° C., some of the silicon may crystallize. The crystallization of silicon in the amorphous layer may present processing challenges. Crystalline silicon may etch at a different rate than amorphous silicon, which may cause non-uniformities that affect subsequent processing. Layers adjacent to the silicon may adhere or interact differently with amorphous silicon than with crystalline silicon. The problem of amorphous silicon crystallizing becomes more significant as feature dimensions shrink.

[0014]

[0018] The addition of dopants such as boron, carbon, or phosphorus has been found to prevent substantial crystallization of silicon and keep it amorphous. The doping concentration of silicon can be significantly higher than the doping of silicon into the source and drain regions of a semiconductor transistor. Without intending to be bound by theory, it is believed that the dopant atoms may form a stable system within the silicon. For example, the SiB3 phase may be stable under high temperatures. This stable phase may prevent the formation of crystalline silicon.

[0015]

[0019] FIG. 1 illustrates a cross-sectional view of an exemplary processing chamber 100 according to some embodiments of the present technique. The diagram may provide an overview of a system incorporating one or more aspects of the present technique and / or may provide an overview of a system capable of performing one or more operations according to embodiments of the present technique. Additional details of the chamber 100 or the method performed may be further described below. Although the chamber 100 may be utilized to form a film layer according to some embodiments of the present technique, it should be understood that the method may similarly be performed in any chamber in which film formation may occur. The processing chamber 100 may include a chamber body 102, a substrate support 104 disposed within the chamber body 102, and a lid assembly 106 coupled with the chamber body 102 and enclosing the substrate support 104 within a processing volume 120. The substrate 103 may be provided in the processing volume 120 via an opening 126, which may be sealed in a conventional manner for processing using a slit valve or door. The substrate 103 may be seated on a surface 105 of the substrate support during processing. The substrate support 104 may be rotatable along an axis 147 about which the shaft 144 of the substrate support 104 may be disposed, as indicated by arrow 145. Alternatively, the substrate support 104 may be elevated to rotate as needed during the deposition process.

[0016]

[0020] The plasma profile modulator 111 may be disposed within the processing chamber 100 to control the plasma distribution across the substrate 103 disposed on the substrate support 104. The plasma profile modulator 111 may include a first electrode 108 that may be disposed adjacent to the chamber body 102 and may separate the chamber body 102 from other components of the lid assembly 106. The first electrode 108 may be part of the lid assembly 106 or may be a separate sidewall electrode. The first electrode 108 may be an annular or ring-shaped member and may be a ring electrode. The first electrode 108 may be a continuous loop around the circumference of the processing chamber 100 surrounding the processing volume 120 or may be discontinuous at selected locations as required. The first electrode 108 may also be a perforated electrode, such as a perforated ring or mesh electrode, or may be a plate electrode, such as a secondary gas distributor, for example.

[0017]

[0021] One or more isolators 110a, 110b, which may be a dielectric material such as ceramic or metal oxide, e.g., aluminum oxide and / or aluminum nitride, may contact the first electrode 108 and electrically and thermally isolate the first electrode 108 from the gas distributor 112 and the chamber body 102. The gas distributor 112 may define an aperture 118 for distributing the process precursors to the processing volume 120. The gas distributor 112 may be coupled to a first power source 142, such as an RF generator, an RF power source, a DC power source, a pulsed DC power source, a pulsed RF power source, or any other power source capable of being coupled to a processing chamber. In some embodiments, the first power source 142 may be an RF power source.

[0018]

[0022] The gas distributor 112 may be a conductive gas distributor or a non-conductive gas distributor. The gas distributor 112 may also be formed of conductive and non-conductive components. For example, the body of the gas distributor 112 may be conductive, while the faceplate of the gas distributor 112 may be non-conductive. The gas distributor 112 may be powered, for example, by a first power source 142 as shown in FIG. 1, or the gas distributor 112 may be coupled to ground in some embodiments.

[0019]

[0023] The first electrode 108 can be coupled to a first conditioning circuit 128 that can control the ground path of the processing chamber 100. The first conditioning circuit 128 can include a first electronic sensor 130 and a first electronic controller 134. The first electronic controller 134 can be or include a variable capacitor or other circuit element. The first conditioning circuit 128 can be or include one or more inductors 132. The first conditioning circuit 128 can be any circuit that allows for a variable or controllable impedance under the plasma conditions present in the processing volume 120 during processing. In some illustrated embodiments, the first conditioning circuit 128 can include a first circuit leg and a second circuit leg coupled in parallel between ground and the first electronic sensor 130. The first circuit leg can include a first inductor 132A. The second circuit leg can include a second inductor 132B coupled in series with the first electronic controller 134. The second inductor 132B can be disposed between the first electronic controller 134 and a node connecting both the first and second circuit legs to the first electronic sensor 130. The first electronic sensor 130 can be a voltage or current sensor and can be coupled to the first electronic controller 134, which can allow for some closed-loop control of the plasma conditions within the process volume 120.

[0020]

[0024] The second electrode 122 may be coupled to the substrate support 104. The second electrode 122 may be embedded in the substrate support 104 or coupled to a surface of the substrate support 104. The second electrode 122 may be a plate, a perforated plate, a mesh, a wire screen, or any other distributed arrangement of conductive elements. The second electrode 122 may be a conditioning electrode and may be coupled to a second conditioning circuit 136 by a conduit 146, such as a cable having a selected resistance, such as, for example, 50 ohms, disposed on a shaft 144 of the substrate support 104. The second conditioning circuit 136 may have a second electronic sensor 138 and a second electronic controller 140, which may be a second variable capacitor. The second electronic sensor 138 may be a voltage or current sensor and may be coupled to the second electronic controller 140 to further control the plasma conditions in the process volume 120.

[0021]

[0025] A third electrode 124, which may be a bias electrode and / or an electrostatic chucking electrode, may be coupled to the substrate support 104. The third electrode may be coupled to a second power source 150 through a filter 148, which may be an impedance matching circuit. The second power source 150 may be DC power, pulsed DC power, RF bias power, pulsed RF source or bias power, or a combination of these or other power sources. In some embodiments, the second power source 150 may be RF bias power.

[0022]

[0026] The lid assembly 106 and substrate support 104 of FIG. 1 can be used with any processing chamber for plasma or thermal processing. During operation, the processing chamber 100 can provide real-time control of plasma conditions within the processing volume 120. The substrate 103 can be placed on the substrate support 104, and process gases can flow through the lid assembly 106 using the inlet 114 according to any desired flow plan. The gases can exit the processing chamber 100 through the outlet 152. Power can be coupled with the gas distributor 112 to establish a plasma within the processing volume 120. In some embodiments, the substrate can be subjected to an electrical bias using the third electrode 124.

[0023]

[0027] Upon energizing the plasma in the process volume 120, a potential difference may be established between the plasma and the first electrode 108. A potential difference may also be established between the plasma and the second electrode 122. The electronic controllers 134, 140 may then be used to adjust the flow characteristics of the ground paths represented by the two adjustment circuits 128 and 136. Set points may be provided to the first adjustment circuit 128 and the second adjustment circuit 136 to provide independent control of the deposition rate and center-to-edge plasma density uniformity. In an embodiment where the electronic controllers may both be variable capacitors, the electronic sensor may adjust the variable capacitors to maximize the deposition rate and independently minimize the thickness non-uniformity.

[0024]

[0028] Each of the conditioning circuits 128, 136 may have a variable impedance that can be adjusted using the respective electronic controller 134, 140. If the electronic controller 134, 140 is a variable capacitor, the capacitance range of each variable capacitor and the inductance of the first inductor 132A and the second inductor 132B may be selected to provide an impedance range. This range may depend on the frequency and voltage characteristics of the plasma, and the capacitance range of each variable capacitor may be minimum. Thus, when the capacitance of the first electronic controller 134 is minimum or maximum, the impedance of the first conditioning circuit 128 may be high, resulting in a plasma shape with minimum aerial or lateral reach on the substrate support. When the capacitance of the first electronic controller 134 approaches a value that minimizes the impedance of the first conditioning circuit 128, the aerial reach of the plasma is maximized, effectively covering the entire working area of ​​the substrate support 104. As the capacitance of the first electronic controller 134 deviates from the minimum impedance setting, the plasma shape may shrink from the chamber walls and the aerial coverage of the substrate support may decrease. The second electronic controller 140 may have a similar effect, increasing and decreasing the aerial coverage of the plasma above the substrate support as the capacitance of the second electronic controller 140 may change.

[0025]

[0029] The electronic sensors 130, 138 may be used to regulate the respective circuits 128, 136 in a closed loop. Depending on the sensor type used, a current or voltage set point may be attached to each sensor, which may be equipped with control software that determines adjustments to the respective electronic controllers 134, 140 to minimize deviations from the set point. As a result, the plasma shape may be selected and dynamically controlled during processing. Although the above discussion is based on the electronic controllers 134, 140 being variable capacitors, it should be understood that any electronic component with adjustable characteristics may be used to provide adjustable impedance to the regulation circuits 128 and 136.

[0026]

[0030] 2 illustrates a method 200 for depositing a silicon-dopant material on a substrate. The substrate may include a semiconductor wafer. The semiconductor wafer may include a silicon wafer or a silicon-on-insulator (SOI) wafer. The substrate may include layers on top of the semiconductor wafer. These layers may include silicon layers, dielectric (SiO2, SiN) layers, metal layers, metal nitride (e.g., TiN) layers, and combinations thereof. The layers may be patterned.

[0027]

[0031] In block 202, silicon-containing precursors and dopant-containing precursors can be delivered to a processing region of a semiconductor processing chamber. The processing chamber can be configured for PECVD (plasma enhanced chemical vapor deposition). In PECVD, the percentage of dopant can be lower to avoid crystallization than in other deposition processes, including LPCVD. The dopant can include boron, carbon, or phosphorus. The dopant can be an atom. The dopant can be an atom in the boron column ("Group III"), the carbon column ("Group IV") excluding silicon, the nitrogen column ("Group V"), the oxygen column ("Group VI"), or the fluorine column ("Group VII") (e.g., fluorine) of the periodic table. The dopant can also exclude any column or any atom in any column described herein. Additionally, the dopant can be a combination of atoms described herein. By way of example, the dopant can be a combination of boron and fluorine, boron and phosphorus, or boron and carbon. The atomic percentage of the dopant in the dopant-containing precursor relative to the sum of the silicon in the silicon-containing precursor and the dopant in the dopant-containing precursor can be in the range of 5% to 10%, 6% to 8%, 10% to 20%, 20% to 30%, 20% to 25%, 25% to 30%, 30% to 35%, 35% to 40%, 45% to 45%, 45% to 50%, or greater than 50%.

[0028]

[0032] Other gases may be delivered along with the silicon-containing precursor and the dopant-containing precursor. The other gases may include argon, helium, nitrogen, ammonia, diatomic hydrogen, or a hydrogen-containing gas.

[0029]

[0033] In block 204, a plasma of the silicon-containing precursor and the dopant-containing precursor may be formed. The plasma may include other gases delivered to the process chamber. The plasma may be a capacitively coupled plasma or an inductively coupled plasma.

[0030]

[0034] In block 206, a silicon-dopant material can be deposited on the substrate. The silicon-dopant material can be formed by a plasma reaction of a silicon-containing precursor and a dopant-containing precursor. The atomic percentage of dopant atoms relative to the sum of dopant atoms and silicon atoms in the silicon-dopant material can be in the range of 5% to 40%, 5% to 10%, 6% to 8%, 10% to 20%, 20% to 30%, 20% to 25%, 25% to 30%, 30% to 35%, or 35% to 40%, 40% to 45%, 45% to 50%, or more than 50%.

[0031]

[0035] The dopant may be boron. The atomic percentage of boron in the silicon-dopant material may range from 5% to 10%, 6% to 8%, 10% to 20%, 20% to 30%, 20% to 25%, 25% to 30%, 30% to 35%, or 35% to 40%. Below a threshold percentage of boron, silicon may crystallize, and above the threshold percentage, silicon may remain amorphous. The threshold percentage may vary depending on the annealing temperature and time. Higher annealing temperatures may result in higher threshold percentages. The threshold percentage may be any percentage disclosed herein. At higher percentages, the silicon-boron material may be more difficult to process in downstream operations (e.g., etching) because boron may not be removed when the silicon is etched away. Etching difficulties may be seen at percentages of about 30%, 35%, or 40% or more. Using PECVD instead of LPCVD offers advantages in tunability and deposition rate. Furthermore, with LPCVD, materials containing 45% dopant may show some crystallization at annealing temperatures of 700° C. or higher, while PECVD materials with lower dopant concentrations may not show crystallization at the same temperatures.

[0032]

[0036] In some embodiments, the dopant may be carbon. The carbon-containing precursor may be propylene (i.e., C3H6) or any suitable alkane, alkene, alkyne, or hydrocarbon. The atomic percentage of carbon in the silicon-dopant material may range from 5% to 10%, 6% to 8%, 10% to 20%, 20% to 30%, 20% to 25%, 25% to 30%, 30% to 35%, 35% to 40%, 45% to 50%, or greater than 50%. Below a threshold percentage of carbon, silicon may crystallize, and above the threshold percentage, silicon may remain amorphous. The threshold percentage may vary depending on the annealing temperature and time. Higher annealing temperatures may result in higher threshold percentages. The threshold percentage may be any percentage disclosed herein. The threshold percentage of carbon that remains amorphous for a given annealing temperature and time may be higher than the threshold percentage of boron. At high carbon percentages (e.g., 35% or higher), silicon-carbon materials may resemble silicon carbide. Boron may be preferred as a dopant for carbon because silicon may remain amorphous at lower doping rates.

[0033]

[0037] In additional embodiments, the dopant may be phosphorus. The phosphorus-containing precursor may include phosphine (i.e., PH3). The atomic percentage of phosphorus in the silicon-dopant material may range from 5% to 10%, 6% to 8%, 10% to 20%, 20% to 30%, 20% to 25%, 25% to 30%, 30% to 35%, 35% to 40%, 40% to 45%, 45% to 50%, or greater than 50%. Below a threshold percentage of phosphorus, silicon may crystallize, and above a threshold percentage, silicon may remain amorphous. The threshold percentage may vary depending on the annealing temperature and time. Higher annealing temperatures may result in higher threshold percentages. The threshold percentage may be any percentage disclosed herein. The threshold percentage of carbon that remains amorphous for a given annealing temperature and time can be higher than the threshold percentage of boron. Boron may be preferred as a dopant over carbon because silicon can remain amorphous at lower doping rates. Higher dopant levels can introduce additional difficulties in downstream processing (e.g., defects, line-end roughness, particles).

[0034]

[0038] The substrate and silicon-dopant material can be removed from the processing chamber and transferred to an apparatus for another operation (e.g., lithography, etching, deposition, annealing).

[0035]

[0039] In block 208, the silicon-dopant material may be patterned to form a patterned silicon-dopant material. The dashed box in block 208 indicates that the block is optional in method 200. The patterning may include etching to form trenches and / or vias. The patterning may include appropriate lithography and etching operations.

[0036]

[0040] In block 210, a silicon nitride material may be deposited on the silicon-dopant material. The dashed box in block 210 indicates that the block is optional in method 200. The deposition may be by atomic layer deposition. The deposition of the silicon nitride may be prior to performing a thermal anneal in block 212. The deposition of the silicon nitride material may be performed on the patterned silicon-dopant material. The silicon nitride material may be deposited conformally or substantially conformally.

[0037]

[0041] At block 212, thermal annealing of the silicon-dopant material can be performed to form an annealed silicon-dopant material that is substantially free of crystalline silicon. In embodiments, substantially free of crystalline silicon can mean less than 3%, less than 2%, less than 1%, less than 0.5%, or 0% crystalline silicon. A silicon-dopant material that is substantially free of crystalline silicon refers to any material in the continuous silicon-dopant layer that is formed when depositing the silicon-dopant material. A silicon-dopant material that is substantially free of crystalline silicon does not refer to a portion of a silicon layer, which may include some amorphous sections within the crystalline portion of silicon.

[0038]

[0042] The annealing can be carried out at a temperature of at least 635° C. In some embodiments, the annealing can be at a temperature between 635° C. and 650° C., between 650° C. and 700° C., between 700° C. and 750° C., between 750° C. and 800° C., between 800° C. and 850° C., or greater than 850° C. The duration of the annealing can be at least 30 minutes. The duration of the annealing can be between 30 minutes and 1 hour, between 1 hour and 2 hours, between 2 hours and 3 hours, between 3 hours and 4 hours, or greater than 4 hours.

[0039]

[0043] The annealed silicon-dopant material has a peak at 520 cm -1 Or 520cm -1 There may be cases where no Raman spectroscopy peak is observed within 5% of 520 cm. -1The peak at 480 cm may indicate the presence of crystalline silicon. The annealed silicon-dopant material exhibits a peak at 480 cm -1 Or 480cm -1 A peak may be observed within 5% of the -1 The broad peak at 520 cm may indicate the presence of amorphous silicon. -1 The peak at 480 cm indicates amorphous silicon. -1 It is a sharper (higher and narrower) peak than the broad peak of

[0040]

[0044] The method illustrated in FIG. 2 may include boron as a dopant. For example, the method may include delivering a silicon-containing precursor and a boron-containing precursor to a processing region of a semiconductor processing chamber. The method may further include forming a plasma of the silicon-containing precursor and the boron-containing precursor in the processing region of the semiconductor processing chamber. The silicon-containing precursor may include silane. The boron-containing precursor may include diborane. The method may further include depositing a silicon-boron material on a substrate disposed in the processing region of the semiconductor processing chamber. The atomic percentage of the boron atoms relative to the sum of the boron atoms and silicon atoms in the silicon-boron material may range from 5% to 40%. The silicon-boron material may be patterned to form a patterned silicon-boron material. Additionally, the method may include depositing a silicon nitride material by atomic layer deposition on the patterned silicon-boron material.

[0041]

[0045] An embodiment of the present technology may include a semiconductor device. The device may include a substrate. The device may further include a silicon-dopant material on the substrate. The dopant may include boron, carbon, or phosphorus. The atomic percentage of the dopant atoms relative to the sum of the dopant atoms and silicon atoms in the silicon-dopant material may range from 5% to 40%, or any range described herein. The silicon-dopant material may be free of crystalline silicon. The silicon-dopant material may be patterned. A silicon nitride material may be on the silicon-dopant layer. The silicon nitride material and the silicon-dopant material may be annealed at a temperature of 650° C. to 750° C., or any temperature described herein. The silicon nitride material and the silicon-dopant material may be annealed for at least 2 hours, or any period described herein.

[0042]

[0046] Any material below the silicon nitride material and above the substrate may be free of crystalline silicon. The silicon above the substrate and below the silicon nitride material may be amorphous.

[0043]

[0047] In some embodiments, the semiconductor device may include multiple layers of silicon-dopant material.The semiconductor device may include multiple layers of silicon nitride material.

[0044]

[0048] 3A, 3B, and 3C show an example of a process flow using multiple layers of silicon-dopant material. In FIG. 3A, the layers can be on a substrate 302. The substrate 302 can be any substrate described herein. A first silicon oxide layer 306 can be on top of the substrate 302. A first silicon-dopant layer 310 can be on top of the first silicon oxide layer 306. A second silicon oxide layer 314 can be on top of the first silicon-dopant layer 310. A second silicon-dopant layer 318 can be on top of the second silicon oxide layer 314. A carbon hardmask layer 322 can be patterned on top of the second silicon-dopant layer 318.

[0045]

[0049] The first silicon-dopant layer 310 and the second silicon-dopant layer 318 can include amorphous silicon, but can exclude crystalline silicon. The first silicon-dopant layer 310 and the second silicon-dopant layer 318 can be formed by any method disclosed herein, including method 200. The layers in FIG. 3A are shown as being in direct contact with adjacent layers. In some embodiments, intermediate layers can be between the layers shown in FIG. 3A.

[0046]

[0050] 3B, a silicon nitride layer 326 is deposited. The silicon nitride layer 326 may be deposited by atomic layer deposition. The silicon nitride layer 326 may be conformally or substantially conformally deposited on the carbon hard mask layer 322.

[0047]

[0051] FIG. 3C shows the carbon hard mask layer 322, the second silicon-dopant layer 318, the silicon nitride layer 326, and the second silicon oxide layer 314 after further etching. The second silicon-dopant layer 318 acts as a mask for the second silicon oxide layer 314. If the second silicon-dopant layer 318 contains crystalline silicon or too high a dopant concentration, the second silicon-dopant layer 318 may not be etched uniformly. For example, crystalline silicon may result in more line edge roughness, and too high a dopant concentration may result in dopant particles that cause roughness at the edges of the etched structures. The second silicon oxide layer 314 is patterned to form a structure 330. The first silicon oxide layer 306 and the first silicon-dopant layer 310 may be further patterned. The structure 330 may be used as a mask for further processing of the underlying layers.

[0048]

[0052] Figure 4 shows the Raman spectroscopy results for various boron doping levels. Intensity in arbitrary units is plotted on the y-axis versus wavenumber (cm -1) is shown on the x-axis. Spectra of various counts in kcps (kilo counts per second) of boron are shown. A higher number of boron counts measured by X-ray fluorescence (XRF) indicates a higher percentage of boron in the layer. Spectra of 54, 40, 28, 13, and 11 kcps are shown. Using the XRF setup, the counts at 54 kcps are approximately 53% boron. The counts at 43 kcps are approximately 43% boron. The counts at 28 kcps are approximately 35% boron. Additionally, results are included for amorphous silicon without boron doping and deposited at 550°C. All amorphous silicon and silicon-boron layers are annealed at 650°C for 30 minutes. The layer thicknesses were 3 kA or 3.5 kA.

[0049]

[0053] The amorphous silicon, 11 kcps boron, and 13 kcps boron samples have a 520 cm -1 This wavelength is associated with crystalline silicon. In contrast, the 28 kcps boron, 40 kcps boron, and 54 kcps boron samples showed a sharp peak at 520 cm -1 Instead, the 28 kcps boron, 40 kcps boron, and 54 kcps boron samples showed a peak at 520 cm -1 The 28 kcps boron, 40 kcps boron, and 54 kcps boron do not show a peak at 480 cm associated with amorphous silicon. -1 shows a broader peak at

[0050]

[0054] Figure 4 shows that the percentage of boron in silicon is low, and that boron-free amorphous silicon crystallizes after annealing at 650° C. for 30 minutes. Figure 4 also shows that higher percentages of boron do not crystallize after annealing at 650° C. for 30 minutes.

[0051]

[0055] Boron-doped silicon was also tested by annealing at 650°C for 4 hours. Again, the higher the boron count, the more substantial the crystallization, while maintaining an amorphous silicon layer. Samples with boron counts below 7.5 kcps (4.2 atomic % boron in the gas [with respect to boron and silicon combined]) crystallized. Samples with boron counts above 8.6 kcps (5.6% in the gas) remained amorphous.

[0052]

[0056] The boron doped silicon was further tested by annealing at 750°C for two hours. Samples with boron numbers below 11 kcps (8.3% in gas) crystallized. Samples with boron numbers above 12.9 kcps (10.9% in gas) remained amorphous. Additional annealing temperatures and durations, such as 750°C for six hours, will also be tested.

[0053]

[0057] In the foregoing description, for purposes of explanation, numerous details are set forth in order to provide an understanding of various embodiments of the present technology. However, it will be apparent to one skilled in the art that particular embodiments may be practiced without some of these details, or with additional details.

[0054]

[0058] Although several embodiments have been disclosed, those skilled in the art will recognize that various modifications, alternative constructions, and equivalents may be used without departing from the spirit of the embodiments. Moreover, some well-known processes and elements have not been described to avoid unnecessarily obscuring the present technology. Thus, the above description should not be interpreted as limiting the scope of the present technology. Furthermore, although a method or process may be described sequentially or stepwise, it should be understood that the operations may be performed simultaneously or in a different order than that described.

[0055]

[0059] Where a range of values ​​is presented, unless the context clearly dictates otherwise, it is understood that each intervening value between the upper and lower limits of that range is also specifically disclosed to the smallest unit of the unit of the lower limit. Any narrower range between any stated or unstated intervening value in a stated range, as well as any other stated or intervening value in that stated range, are also encompassed. The upper and lower limits of these smaller ranges may be individually included or excluded in the range, and each range in which either, neither, or both limits are included in the narrower range is also encompassed within the technology, subject to the specifically excluded limit in the stated range. Where a stated range includes one or both of the limits, ranges excluding either or both of the included limits are also included.

[0056]

[0060] As used in this specification and the appended claims, the singular forms "a," "an," and "the" include plural referents unless the context clearly indicates otherwise. Thus, for example, reference to "a precursor" includes a reference to a plurality of such precursors, reference to "a layer" includes a reference to one or more layers and equivalents thereof known to those skilled in the art, and so forth.

[0057]

[0061] Additionally, the terms "comprise(s)", "comprising", "contain(s)", "containing", "include(s)", and "including", when used in this specification and claims, are intended to specify the presence of stated features, integers, components, or steps, but do not exclude the presence or addition of one or more other features, integers, components, steps, operations, or groups.

Claims

1. delivering a silicon-containing precursor and a dopant-containing precursor to a processing region of a semiconductor processing chamber, comprising: the dopant comprises boron, carbon, or phosphorus; delivering the silicon-containing precursor and the dopant-containing precursor to a processing region of a semiconductor processing chamber, wherein an atomic percentage of dopant atoms in the dopant-containing precursor relative to the sum of dopant atoms in the dopant-containing precursor and silicon atoms in the silicon-containing precursor is in the range of 5% to 40%; forming a plasma of the silicon-containing precursor and the dopant-containing precursor in the processing region of the semiconductor processing chamber; depositing a silicon-dopant material onto a substrate disposed within the processing region of the semiconductor processing chamber; and performing a thermal annealing of the silicon-dopant material to form an annealed silicon-dopant material on the substrate, the annealed silicon-dopant material being free of crystalline silicon or containing less than 3% crystalline silicon; The deposition method comprising:

2. the dopant is boron; The deposition method of claim 1, wherein said atomic percentage is in the range of 6% to 30%.

3. The deposition method of claim 1 , wherein the dopant is carbon.

4. The deposition method of claim 1 wherein said dopant is phosphorus.

5. The deposition method of any one of claims 1 to 4, wherein performing the thermal annealing of the silicon-dopant material comprises performing the thermal annealing at a temperature of at least 635°C for at least 30 minutes.

6. The deposition method of claim 5, wherein performing the thermal annealing of the silicon-dopant material comprises performing the thermal annealing at a temperature in the range of 650°C to 750°C.

7. 7. The deposition method of claim 5 or 6, wherein said thermal annealing is performed for at least 2 hours.

8. The annealed silicon-dopant material has a 520 cm －１ The deposition method according to claim 1 , wherein the deposition method exhibits no Raman spectroscopy peak at

9. The annealed silicon-dopant material has a 480 cm －１ The deposition method according to claim 1 , wherein the deposition method exhibits a Raman spectroscopy peak at

10. The deposition method of any one of claims 1 to 9, further comprising depositing a silicon nitride material on the silicon-dopant material by atomic layer deposition before performing the thermal annealing.

11. The deposition method of claim 10, further comprising patterning the silicon-dopant material prior to depositing the silicon nitride material.

12. 11. The deposition method of claim 10, wherein the material beneath the silicon nitride material and above the substrate is free of crystalline silicon or contains less than 3% crystalline silicon.

13. delivering a silicon-containing precursor and a boron-containing precursor to a processing region of a semiconductor processing chamber, wherein an atomic percentage of dopant atoms in the dopant-containing precursor relative to the sum of dopant atoms in the dopant-containing precursor and silicon atoms in the silicon-containing precursor is in the range of 5% to 40%; forming a plasma of the silicon-containing precursor and the boron-containing precursor in the processing region of the semiconductor processing chamber; depositing a silicon-boron material onto a substrate disposed in the processing region of the semiconductor processing chamber; patterning the silicon-boron material to form a patterned silicon-boron material; depositing a silicon nitride material on the patterned silicon-boron material by atomic layer deposition; and performing a thermal annealing of the patterned silicon-boron material at a temperature in the range of 650° C. to 750° C. to form an annealed silicon-boron material, the annealed silicon-boron material being free of crystalline silicon or containing less than 3% crystalline silicon. The method includes:

14. the silicon-containing precursor comprises a silane; and the boron-containing precursor comprises diborane.

15. substrate; a silicon-dopant material on the substrate, the dopant in the silicon-dopant material comprises boron, carbon, or phosphorus; the atomic percentage of dopant atoms relative to the sum of dopant atoms and silicon atoms in the silicon-dopant material is in the range of 5% to 40%; the silicon-dopant material is free of crystalline silicon or contains less than 3% crystalline silicon; and the silicon-dopant material is patterned; and Silicon nitride material on silicon-dopant layer 13. A semiconductor device comprising:

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