Fault diagnosis for PWM controller I / O terminals

Abstract

To solve the problem in which: it is desirable to have a simple fault diagnosis apparatus through which a system controller can reliably determine a fault status of an LED system.SOLUTION: An apparatus includes: a clamping circuit configured to supply a predetermined voltage at an output of the clamping circuit; a clamping switch coupled to the output of the clamping circuit; and a pass device connected between the clamping switch and an input / output terminal of a controller.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001]

[0001] An embodiment of the present invention relates to a fault diagnosis apparatus, and more particularly, to a fault diagnosis apparatus in a light emitting diode system. [Background technology]

[0002]

[0002] A light emitting diode (LED) is a semiconductor light source. When a voltage is applied to an LED, a current flows through it. In response to the current flowing through the LED, electrons and holes recombine at the PN junction of the diode. In the recombination process, energy is released in the form of photons.

[0003]

[0003] A typical LED system includes multiple LED strings. Each LED string includes multiple light emitting diodes, a power switch, and a current sensing resistor connected in series between a power supply and ground. The LED system further includes a PWM controller. In operation, the PWM controller is configured to receive a PWM signal generated by a system controller (e.g., a microcontroller) and a voltage across the current sensing resistor. Based on the received signal, the PWM controller is configured to generate a gate drive signal that is applied to a gate of the power switch. The gate drive signal is controlled such that an average current flowing through the multiple light emitting diodes is adjustable based on different operating requirements. The process of controlling the LED average current is often referred to as dimming.

[0004]

[0004] Pulse width modulation (PWM) is a commonly used control technique to generate analog signals from digital devices such as microcontrollers. In a typical PWM controller system, the microcontroller communicates and / or interfaces with a semiconductor integrated circuit (e.g., a PWM controller) with one or more protocols. LED systems also typically include hardware fault detection mechanisms. When a fault is detected, the PWM controller reports the fault to the microcontroller through various communication methods. The simplest communication method is one-wire communication, where the microcontroller and the PWM controller exchange information through a single wire. Single-wire communication can be classified as a one-way communication system, where the microcontroller sends instructions to the PWM controller and the PWM controller executes the instructions. Other communication methods are based on a two-way communication system where both the microcontroller and the PWM controller can send and receive instructions. A two-way communication system can be obtained by using an appropriate protocol such as I2C, SPI, UART, or any combination thereof. In some applications, a fault flag pin is another common alternative. The fault flag pin is used to indicate a fault condition of the PWM controller. By reading the fault status provided by the fault flag pin, the microcontroller can determine if a fault has occurred in the LED system.

[0005]

[0005] The above mentioned communication methods are effective. However, the implementation of these communication methods results in complex and expensive systems. Such complex and expensive systems have many drawbacks such as lack of design flexibility, low reliability, etc. It is desirable to have a simple fault diagnosis device that allows a system controller to reliably determine the fault condition of an LED system. This disclosure describes a simple and cost-effective device for determining the fault condition of an LED system. Summary of the Invention

[0006]

[0006] These and other problems are generally solved or avoided, and technical advantages generally achieved, by preferred embodiments of the present disclosure which provide an apparatus and method for diagnosing faults in an LED system.

[0007]

[0007] According to one embodiment, the apparatus includes a clamp circuit configured to supply a predetermined voltage at an output of the clamp circuit, a clamp switch coupled to the output of the clamp circuit, and a pass device connected between the clamp switch and an input / output terminal of a controller.

[0008]

[0008] According to another embodiment, a method includes configuring a microcontroller to generate a PWM signal that is supplied to a PWM terminal of a controller of a light emitting diode (LED) system, detecting a fault event in the LED system, and clamping a logic high voltage of the PWM signal to a predetermined level via a clamp device in response to the fault event in the LED system.

[0009]

[0009] According to yet another embodiment, a system includes a plurality of light emitting diodes connected in series between an input voltage bus and a power switch, a PWM controller configured to generate a gate drive signal provided to a gate of the power switch, a fault diagnosis circuit coupled to a PWM terminal of the PWM controller, the fault diagnosis circuit including a clamp circuit configured to provide a predetermined voltage at an output of the clamp circuit, a clamp switch coupled to the output of the clamp circuit, and a pass device connected between the clamp switch and an input / output terminal of the PWM controller.

[0010]

[0010] The foregoing has outlined rather broadly the features and technical advantages of the present disclosure in order that the detailed description of the disclosure that follows may be better understood. Additional features and advantages of the present disclosure which form the subject of the claims of the present disclosure will be described below. Those skilled in the art will appreciate that the conception and specific embodiments disclosed may be readily utilized as a basis for modifying or designing other structures or processes for carrying out the same purposes of the present disclosure. Those skilled in the art will also appreciate that such equivalent constructions do not depart from the spirit and scope of the present disclosure as set forth in the appended claims.

[0011] For a more complete understanding of the present disclosure, and the advantages thereof, reference is now made to the following descriptions taken in conjunction with the accompanying drawings, in which: [Brief description of the drawings]

[0012] [Figure 1] FIG. 1 illustrates a block diagram of a light emitting diode system according to various embodiments of the present disclosure. [Diagram 2] 2 shows a schematic diagram of a first embodiment of the fault diagnosis device shown in FIG. 1 according to various embodiments of the present disclosure; [Diagram 3] 3 illustrates two signals associated with the fault diagnosis apparatus shown in FIG. 2 when the fault diagnosis apparatus is configured to operate under a first control mechanism according to various embodiments of the present disclosure. [Figure 4] 3 illustrates two signals associated with the fault diagnosis apparatus shown in FIG. 2 when the fault diagnosis apparatus is configured to operate under a second control mechanism according to various embodiments of the present disclosure. [Diagram 5] 3 illustrates a first implementation of the pass device shown in FIG. 2 according to various embodiments of the present disclosure. [Figure 6] 3 illustrates a second implementation of the pass device shown in FIG. 2 according to various embodiments of the present disclosure. [Figure 7] 3 illustrates a third implementation of the pass device shown in FIG. 2 according to various embodiments of the present disclosure. [Figure 8] 3 illustrates a fourth embodiment of the pass device shown in FIG. 2 according to various embodiments of the present disclosure. [Figure 9] 2 shows a schematic diagram of a second embodiment of the fault diagnosis device shown in FIG. 1 according to various embodiments of the present disclosure. [Figure 10] 1 illustrates a schematic diagram of a control circuit for adjusting a reference voltage according to various embodiments of the present disclosure. [Figure 11] FIG. 2 shows a schematic diagram of a control circuit for adjusting a gate drive voltage according to various embodiments of the present disclosure. [Figure 12] FIG. 2 illustrates a schematic diagram of a control circuit for adjusting both the reference voltage and the gate drive voltage according to various embodiments of the present disclosure. [Figure 13] 2 shows a flow chart for controlling the light emitting diode system shown in FIG. 1 according to various embodiments of the present disclosure. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0013]

[0025] Corresponding numerals and symbols in the different figures generally refer to corresponding parts unless otherwise indicated. The figures are drawn to clearly illustrate relevant aspects of the various embodiments and are not necessarily drawn to scale.

[0014]

[0026] The making and use of the presently preferred embodiments are described in detail below. It should be understood, however, that the present disclosure provides many applicable inventive concepts that can be embodied in a wide variety of specific contexts. The specific embodiments described are merely illustrative of specific ways to make and use the present disclosure and do not limit the scope of the present disclosure.

[0015]

[0027] The present disclosure is described with respect to preferred embodiments in a particular context, namely, a fault diagnosis apparatus for an LED system. However, the present disclosure may also be applied to a variety of electronic systems. Various embodiments are described in detail below with reference to the accompanying drawings.

[0016]

[0028] 1 shows a block diagram of a light emitting diode system according to various embodiments of the present disclosure. A plurality of light emitting diodes D1-DN, a power switch Q1, and a current sensing resistor R are connected between an input voltage bus VIN and ground. S 1, the PWM controller 100 includes a bias voltage terminal VCC connected to an input voltage bus VIN, a PWM terminal configured to receive a PWM signal generated by the system controller 150, a ground terminal GND connected to ground, and a R S and Q1 has a feedback terminal FB connected to the common node thereof, and an output terminal OUT connected to the gate of Q1.

[0017]

[0029] In operation, the PWM controller 100 is configured to generate gate drive signals for controlling the turn-on and turn-off of Q1 to control the average current through the plurality of light emitting diodes D1-DN.

[0018]

[0030] As shown in FIG. 1, the light-emitting diode system further includes a fault diagnosis device 200 coupled between the PWM terminal and ground. In operation, the fault diagnosis device 200 functions as a fault condition reporting device. More specifically, when a fault (e.g., open load fault, short-to-ground fault, VIN short-circuit fault, thermal shutdown, etc.) occurs, the fault diagnosis device 200 can change the logic high voltage of the PWM signal, so that the system controller 150 can determine the fault condition of the LED system based on the logic high voltage change. In some embodiments, when a fault occurs, the fault diagnosis device 200 can reduce the logic high voltage of the PWM signal from a first logic high voltage (e.g., 4V) to a second logic high voltage (e.g., 3V). In response to this logic high voltage change, the system controller 150 can find that a fault has occurred in the LED system. The detailed structure and operation principle of the fault diagnosis device 200 will be described below with reference to FIGS. 2 to 12.

[0019]

[0031] In some embodiments, the system controller 150, the fault diagnosis device 200, and the PWM controller 100 are integrated into one integrated circuit. In alternative embodiments, the system controller 150, the fault diagnosis device 200, and the PWM controller 100 may be implemented on three separate integrated circuits.

[0020]

[0032] It should be noted that the light-emitting diode system shown in FIG. 1 is just an example. According to different applications and design needs, the system configuration may be changed accordingly. For example, the current sensing resistor R S may be disposed between the plurality of light emitting diodes and the power switch Q1. Additionally, although FIG. 1 illustrates a light emitting diode with one LED string, the light emitting diode may accommodate any number of LED strings.

[0021]

[0033] In some embodiments, system controller 150 is implemented as a microcontroller. In alternative embodiments, system controller 150 may be implemented as any suitable processor, such as a digital signal processing (DSP) controller, a field programmable gate array (FPGA) processor, or the like.

[0022]

[0034] FIG. 2 shows a schematic diagram of a first embodiment of the fault diagnosis apparatus shown in FIG. 1 according to various embodiments of the present disclosure. The fault diagnosis apparatus 200 includes a fault logic unit 202, a pass device 204, a clamp switch Q2, and a clamp circuit 206. As shown in FIG. 2, the pass device 204, the clamp switch Q2, and the clamp circuit 206 are connected in series. More specifically, the pass device 204 is connected between an input / output terminal (e.g., a PWM terminal shown in FIG. 1) of an integrated circuit (e.g., the PWM controller 100 shown in FIG. 1) and the clamp switch Q2. The clamp switch Q2 is coupled between the pass device 204 and the output of the clamp circuit 206. The clamp circuit 206 is configured to provide a predetermined voltage at the output of the clamp circuit 206.

[0023]

[0035] As shown in FIG. 2, the clamp circuit 206 includes an operational amplifier A1, a first resistor R1, and a second resistor R2. The non-inverting input of the operational amplifier A1 is connected to a predetermined reference VREF. The inverting input of the operational amplifier A1 is connected to a common node of the first resistor R1 and the second resistor R2. The first resistor R1 and the second resistor R2 are connected in series between the output of the operational amplifier A1 and ground. As shown in FIG. 2, the output of the operational amplifier A1 is the output of the clamp circuit 206.

[0024]

[0036] The fault logic unit 202 has an output connected to the gate of the clamp switch Q2. In operation, the fault logic unit 202 is configured to detect faults such as an open load fault, a short to ground fault, a VIN short fault, a thermal shutdown, etc. Based on the detected fault, the fault logic unit 202 can generate a signal to turn on the clamp switch Q2. In some embodiments, the signal from the fault logic unit 202 may also be used to enable the operational amplifier A1.

[0025]

[0037] In operation, when operational amplifier A1 is enabled, the voltage at the inverting input of operational amplifier A1 is equal to VREF. According to the working principle of the voltage divider, the voltage at the output of operational amplifier A1 (V1) can be expressed as:

number

[0026]

[0038] In some embodiments, the clamp switch Q2 is fully turned on when a fault occurs. After the clamp switch Q2 is fully turned on, V2 shown in FIG. 2 is equal to V1.

[0027]

[0039] In normal operation, the PWM signal provided to the PWM terminal is a logic high voltage (e.g., 4V) and a logic low voltage (e.g., 0V). When a fault occurs, operational amplifier A1 is enabled and clamp switch Q2 is turned on. The voltage at node V2 is equal to voltage V1 in equation (1). Pass device 204 may be implemented as a diode (e.g., D1 shown in FIG. 6). When a logic high voltage is on the PWM terminal, clamp circuit 206, clamp switch Q2, and pass device 204 are configured to clamp the logic high voltage on the PWM terminal to a predetermined set point. In some embodiments, the predetermined set point is equal to the voltage on node V2 plus the forward voltage drop of the diode in pass device 204. The clamped logic high voltage is lower than the logic high voltage in normal operation. On the other hand, when a logic low voltage is on the PWM terminal, the logic low voltage is lower than the voltage on node V2. This causes the diode in pass device 204 to be reverse biased. The reverse biased diode prevents the voltage on node V2 from affecting the logic low voltage.

[0028]

[0040] In normal operation, the clamp switch Q2 is turned off by a low gate voltage generated by the fault logic unit 202. Because the clamp switch Q2 is off, the clamp switch Q2 and the pass device 204 form a high impedance circuit coupled to the PWM terminal. When a fault occurs, the fault logic unit 202 generates a gate drive signal to turn on the clamp switch Q2. The clamp circuit 206 provides a predetermined voltage to the node V1. In addition, the clamp circuit 206 provides a sink current to clamp the logic high voltage of the PWM signal to a lower voltage (e.g., 3V). During the clamping process, the pass device 204 acts as a buffer. This buffer can provide isolation to prevent the clamp switch Q2 from facing a harsh environment on the input / output terminal. Furthermore, when the PWM signal is in a logic low state, the clamp switch Q2 and / or the pass device 204 can prevent the clamping action from affecting the PWM signal. This ensures that the logic low state of the PWM signal can be detected by the PWM controller 100. In other words, the PWM controller 100 can receive the PWM signal correctly even if the fault clamp is triggered.

[0029]

[0041] During operation, operating conditions change for different applications. Different operating conditions may cause large voltage drop differences across pass devices 204. Such large voltage drop differences make it difficult for system controller 150 to determine whether a fault has occurred. In some embodiments, three different fault diagnosis methods are employed to help system controller 150 correctly determine whether a fault has occurred.

[0030]

[0042] In the first method, the logic high voltage of the PWM signal is detected after a fault event occurs. The detected logic high voltage of the PWM signal is compared with a predetermined level (e.g., 3V). Based on the comparison result, the predetermined reference VREF is adjusted. For example, if the detected logic high voltage of the PWM signal is less than the predetermined level, the predetermined reference VREF is increased until the detected logic high voltage of the PWM signal is equal to the predetermined level. On the other hand, if the detected logic high voltage of the PWM signal is higher than the predetermined level, the predetermined reference VREF is decreased until the detected logic high voltage of the PWM signal is equal to the predetermined level. By using the first method, the logic high voltage of the PWM signal is equal to the predetermined level under various operating conditions. A control circuit for adjusting the predetermined reference VREF is described below with reference to FIG. 10.

[0031]

[0043] In the second method, the logic high voltage of the PWM signal is detected after a fault event occurs. The detected logic high voltage of the PWM signal is compared with a predetermined level (e.g., 3V). The gate drive voltage of the clamp switch Q2 is adjusted based on the comparison result. For example, if the detected logic high voltage of the PWM signal is less than the predetermined level, the gate drive voltage of the clamp switch Q2 is reduced. The reduction in the gate drive voltage results in a significant voltage drop across the clamp switch Q2. This significant voltage drop across the clamp switch Q2 helps the detected logic high voltage of the PWM signal to be equal to the predetermined level. By using the second method, the logic high voltage of the PWM signal is equal to the predetermined level under various operating conditions. A control circuit for adjusting the gate drive voltage will be described below with reference to FIG. 11.

[0032]

[0044] In the third method, the logic high voltage of the PWM signal is detected after the fault event occurs. The detected logic high voltage of the PWM signal is compared with a predetermined level (e.g., 3V). If the logic high voltage of the PWM signal is less than the predetermined level, the gate drive voltage of the clamp switch Q2 is reduced so that the logic high voltage of the PWM signal is equal to the predetermined level. On the other hand, if the logic high voltage of the PWM signal is greater than the predetermined level, the predetermined reference VREF is decreased so that the logic high voltage of the PWM signal is equal to the predetermined level. By using the third method, the logic high voltage of the PWM signal is equal to the predetermined level under various operating conditions. A control circuit for adjusting both the predetermined reference VREF and the gate drive voltage is described below with reference to FIG. 12.

[0033]

[0045] In some embodiments, depending on different applications and design needs, the clamp switch Q2 may be replaced by an isolation switch. The isolation switch is formed by two transistors connected back to back, namely a first transistor and a second transistor. In some embodiments, when the logic high voltage of the PWM signal is below a predetermined level, the gate drive voltage of the first transistor of the isolation switch is reduced so that the logic high voltage of the PWM signal is equal to the predetermined level. In an alternative embodiment, when the logic high voltage of the PWM signal is below a predetermined level, the gate drive voltage of the second transistor of the isolation switch is reduced so that the logic high voltage of the PWM signal is equal to the predetermined level. Also, when the logic high voltage of the PWM signal is below a predetermined level, the gate drive voltage of the first transistor and the gate drive voltage of the second transistor are alternately adjusted so that the logic high voltage of the PWM signal is equal to the predetermined level.

[0034]

[0046] One advantageous feature of alternatingly adjusting the gate drive voltages of the first and second transistors is that power dissipation can be evenly distributed between these two transistors.

[0035]

[0047] 3 illustrates two signals associated with the fault diagnosis apparatus shown in FIG. 2 when the fault diagnosis apparatus is configured to operate under a first control mechanism according to various embodiments of the present disclosure. The horizontal axis illustrates time intervals. There are two rows. The first row represents the PWM signal. The second row represents the fault signal that is generated when a fault occurs.

[0036]

[0048] Under the first control mechanism, when a fault is detected, the fault diagnostic device is enabled. As shown in FIG. 3, at t1, the PWM signal changes from a logic low state to a logic high state (e.g., 4V). At t2, a fault occurs. In response to the fault, a fault signal is generated by an appropriate fault detection device. At t2, the fault logic unit enables the operational amplifier A1 and turns on the clamp switch Q2. As described above with respect to FIG. 2, the clamp circuit 206, the clamp switch Q2, and the pass device 204 are configured such that the logic high voltage on the PWM terminal is clamped to a predetermined set point (e.g., 3V). As shown in FIG. 3, the PWM pulse during the duration from t1 to t3 has two logic high levels (e.g., 4V and 3V).

[0037]

[0049] At t3, the PWM signal changes from a logic high state to a logic low state. At t4, the PWM signal changes from a logic low state to a logic high state. From t4 to t5, the logic high voltage remains at a predetermined set point (e.g., 3V). From t6 to t7, the logic high voltage remains at a predetermined set point (e.g., 3V). At t8, the fault disappears. The fault signal changes from a logic high state to a logic low state as shown in Figure 3. At t9, the PWM signal returns to normal.

[0038]

[0050] FIG. 4 shows two signals related to the fault diagnosis apparatus shown in FIG. 2 when the fault diagnosis apparatus is configured to operate under a second control mechanism according to various embodiments of the present disclosure. Under the second control mechanism, the operation principle of the fault diagnosis apparatus is similar to that shown in FIG. 3, except that there is a predetermined delay (t4 to t41 shown in FIG. 4). From t2 to t8, in each PWM pulse, due to the predetermined delay, the PWM pulse normally remains at a logic high voltage (e.g., 4V) at the beginning of the PWM pulse. After the predetermined delay, the clamp circuit 206, the clamp switch Q2, and the pass device 204 are configured so that the logic high voltage on the PWM terminal is clamped to a predetermined set point (e.g., 3V). As shown in FIG. 4, the PWM pulse in the duration from t1 to t9 has two different logic high levels (e.g., 4V and 3V).

[0039]

[0051] 5 illustrates a first implementation of the pass device shown in FIG 2 according to various embodiments of the present disclosure. The pass device 204 includes a p-type transistor Q3, a first clamp diode D1, a second clamp diode D2, and a bias resistor R3.

[0040]

[0052] As shown in Figure 5, the body terminal and the source terminal of the p-type transistor Q3 are connected together. A first clamp diode D1 is connected between the gate terminal and the drain terminal of the p-type transistor Q3. A second clamp diode D2 is connected between the gate terminal and the source terminal of the p-type transistor Q3. A bias resistor R3 is connected between the gate terminal of the p-type transistor Q3 and ground.

[0041]

[0053] In operation, when a logic high voltage is present on the PWM terminal, the channel of p-type transistor Q3 is turned on since the gate terminal of Q3 is connected to ground through bias resistor R3. When a logic low voltage is present on the PWM terminal, the channel of p-type transistor Q3 is turned off. The first clamp diode D1 and the second clamp diode D2 act as protection elements to prevent damage to p-type transistor Q3.

[0042]

[0054] One advantageous feature of having a p-type transistor Q3 is that a p-type transistor (e.g., Q3) is more robust than an n-type transistor (e.g., Q2), so the p-type transistor Q3 can protect the clamp switch Q2 from harsh operating conditions on the input / output lines (e.g., ESD, latch-up, etc.).

[0043]

[0055] Another advantageous feature of having p-type transistor Q3 is that when p-type transistor Q3 is turned on, Q3 provides zero voltage drop, thereby achieving accurate clamping.

[0044]

[0056] 6 illustrates a second implementation of the pass device shown in FIG. 2 according to various embodiments of the present disclosure. The pass device 204 includes a diode D1. As shown in FIG. 6, the anode of the diode D1 is connected to an input / output terminal (e.g., a PWM terminal) of the PWM controller 100. The cathode of the diode D1 is connected to a clamp switch Q2.

[0045]

[0057] In operation, when a logic high voltage is on the PWM terminal, forward biased D1 provides a conductive path to pull down the logic high voltage from a first voltage level (e.g., 4V) to a second voltage level (e.g., 3V). When a logic low voltage is on the PWM terminal, reverse biased D1 prevents the clamp circuit from affecting the logic low voltage. Additionally, diode D1 provides isolation, thereby preventing the clamp switch Q2 from being damaged when there is a large negative voltage on the input / output line (e.g., the line between the microcontroller and the PWM terminal of the PWM controller).

[0046]

[0058] 7 illustrates a third implementation of the pass device shown in FIG 2 according to various embodiments of the present disclosure. The pass device 204 includes a resistor R3 connected between an input / output terminal (e.g., a PWM terminal) of the PWM controller 100 and a clamp switch Q2.

[0047]

[0059] In operation, the pass device is implemented as a resistor so that the voltage clamp is active throughout the PWM cycle. A low resistance value of R3 may provide a strong clamping action. However, such a low resistance value may result in false logic high voltage detection when the system controller 150 sends a logic low voltage to the PWM controller 100. The resistance value of R3 may be selected based on various factors including the value of the logic high voltage, the value of the logic low voltage, the sink current capability under the logic high voltage, and the source current capability under the logic low voltage. In some embodiments, R3 may be implemented as an adjustable resistor. When a logic low voltage is on the PWM terminal, R3 is a high resistance value. When a logic high voltage is on the PWM terminal, R3 is a low resistance value.

[0048]

[0060] 8 illustrates a fourth implementation of the pass device shown in FIG. 2 according to various embodiments of the present disclosure. The pass device 204 comprises an ESD device, including but not limited to common ESD circuits such as a diode, an NMOS transistor, a PMOS transistor, a bipolar junction transistor, or any combination thereof.

[0049]

[0061] In some embodiments, the ESD device in pass device 204 is implemented as a Zener diode D2 as shown in Figure 8. The cathode of Zener diode D2 is connected to the input / output terminal of PWM controller 100. The anode of the Zener diode is connected to clamp switch Q2.

[0050]

[0062] 9 shows a schematic diagram of a second embodiment of the fault diagnosis apparatus shown in FIG. 1 according to various embodiments of the present disclosure. The second embodiment of the fault diagnosis apparatus shown in FIG. 9 is similar to the first embodiment of the fault diagnosis apparatus shown in FIG. 2, except that the clamp switch is merged into the NMOS ESD cell. The pass device can be replaced by the NMOS ESD cell. Thus, the pass device can be omitted as shown in FIG. 9.

[0051]

[0063] FIG. 10 shows a schematic diagram of a control circuit for adjusting a reference voltage according to various embodiments of the present disclosure. The control circuit for adjusting a reference voltage includes a peak voltage detector 220, a buffer formed by an amplifier A3, and a summer 240. The peak voltage detector 220 detects the variation of the voltage of the PWM terminal. As shown in FIG. 10, the peak voltage detector 220 includes a voltage divider formed by resistors R3 and R4, an amplifier A4, a diode D1, a first capacitor C1, a power-up reset switch Q4, and a second capacitor C2.

[0052]

[0064] The voltage at the PWM terminal is provided to the non-inverting input of amplifier A4 via a voltage divider. A first capacitor C1 and the voltage divider form a low pass filter for attenuating undesired signals. A power-up reset switch Q4 is controlled by a power-up reset signal POR. The power-up reset signal POR is configured to reset the peak voltage detector so that new peaks can be detected. As shown in FIG. 10, the peak voltage detector is configured to provide a signal VPEAK representing a sampled version of the voltage on the PWM terminal.

[0053]

[0065] The sampled signal VPEAK is buffered in an amplifier A3 to generate a signal Vsns that represents a sampled version of the voltage on the PWM terminal. A bandgap reference circuit (not shown) is configured to generate a reference voltage Vbg.

[0054]

[0066] The adder 240 includes a differential amplifier A2 and two summing resistors R11 and R12. According to the operation principle of the differential amplifier, the output voltage Vadj of the differential amplifier A2 can be expressed by the following equation:

number

[0055]

[0067] The difference between Vbg and Vsns is fed to the non-inverting input of amplifier A1 via two summing resistors R11 and R12. The difference between Vbg and Vsns serves as the input of a negative feedback loop. This negative feedback loop precisely regulates the voltage of the PWM terminal to a predetermined value (e.g., 3V). In some embodiments, in FIG. 10, Rin is equal to 10KΩ; Rfb is equal to 200KΩ; Vbg is equal to 1.2V; Vsns is equal to 1.26V; R11 is equal to 10KΩ; R12 is equal to 5KΩ; R1 is equal to 100Ω; and R2 is equal to 83.3Ω. The voltage of the PWM terminal is regulated to 3.01V, which is close to the predetermined value of 3.0V. In contrast, without the control circuit for regulating the reference voltage shown in FIG. 10, the voltage of the PWM terminal is regulated to 3.15V. The control circuit for adjusting the reference voltage shown in FIG. 10 can improve the voltage adjustment accuracy.

[0056]

[0068] 11 shows a schematic diagram of a control circuit for adjusting the gate drive voltage according to various embodiments of the present disclosure. The control circuit shown in FIG. 11 is similar to the control circuit shown in FIG. 10, except that the sampled signal (i.e., Vsns) is fed to the non-inverting input of amplifier A2, and the output voltage of amplifier A2 (i.e., Vadj) is added to the gate drive voltage of Q2. The output voltage of amplifier A2 can be expressed as:

number

[0057]

[0069] Through the circuit shown in FIG. 11, when the logic high voltage on the PWM terminal is less than a predetermined level (e.g., 3V), the output voltage Vadj of the amplifier A2 is reduced according to equation (3). The reduced Vadj is added to the gate drive voltage of the clamp switch Q2. This reduces the gate drive voltage of the clamp switch Q2. The reduction in the gate drive voltage results in a significant voltage drop across the clamp switch Q2. This significant voltage drop across the clamp switch Q2 helps the logic high voltage on the PWM terminal to increase until the logic high voltage on the PWM terminal reaches the predetermined level (e.g., 3V). On the other hand, when the logic high voltage on the PWM terminal is greater than the predetermined level (e.g., 3V), the circuit shown in FIG. 11 can also help the logic high voltage on the PWM terminal reach the predetermined level (e.g., 3V). In some embodiments, in FIG. 11, Rin is equal to 10KΩ; Rfb is equal to 200KΩ; Vbg is equal to 1.2V; and Vsns is equal to 1.239V. R11 is equal to 10KΩ. R12 is equal to 5KΩ. R1 is equal to 100Ω. R2 is equal to 110Ω. V1 is equal to 2.29V. V2 is equal to 2.485V. The voltage of the PWM terminal is regulated to 3.01V, which is close to the predetermined value of 3.0V. In contrast, without the control circuit for adjusting the gate drive voltage shown in FIG. 11, the voltage of the PWM terminal is regulated to 2.828V. The control circuit for adjusting the gate drive voltage shown in FIG. 11 can improve the voltage regulation accuracy.

[0058]

[0070] FIG. 12 shows a schematic diagram of a control circuit for adjusting both the reference voltage and the gate drive voltage according to various embodiments of the present disclosure. The control circuit shown in FIG. 12 is a combination of the control circuit shown in FIG. 10 and the control circuit shown in FIG. 11. The first circuit block 270 includes an amplifier A2, resistors Rin1, Rfb1, R12, and a first switch S1. The first circuit block 270 is used to generate a signal for adjusting the gate drive voltage of the clamp switch Q2. The output voltage of the amplifier A2 can be expressed as the following equation:

number

[0059]

[0071] As shown in Figure 12, the output voltage Vadj_gate of amplifier A2 is added to the gate drive voltage of clamp switch Q2 via resistor R12 and first switch S1. The operating principle of amplifier A2 was previously described with reference to Figure 11 and will not be repeated here.

[0060]

[0072] The second circuit block 280 includes an amplifier A5, resistors Rin2, Rfb2, R14, and a second switch S2. The second circuit block 280 is used to generate a signal for adjusting the reference voltage supplied to the non-inverting input of the amplifier A1. The output voltage of the amplifier A5 can be expressed by the following equation:

number

[0061]

[0073] As shown in Fig. 12, the output voltage Vadj_ref of the amplifier A5 is applied to the non-inverting input of the amplifier A1 via a resistor R14 and a second switch S2. The operation principle of the amplifier A5 was previously described with reference to Fig. 10 and will not be repeated here.

[0062]

[0074] The third circuit block 290 is used to control the on and off of the switches S1 and S2. As shown in FIG. 12, Vbg is provided to the non-inverting input of the comparator CH1. Vsns is provided to the inverting input of the comparator CH1. The output of the comparator CH1 is connected to the input of the inverter INV1. The output signal S1C of the comparator CH1 is used to control the first switch S1. The output signal S2C of the inverter INV1 is used to control the second switch S2. The comparator CH1 and the inverter INV1 are configured to achieve the following control objectives. First, if the logic high voltage of the PWM terminal is less than a predetermined level (e.g., 3V), the first switch S1 is turned on and the second switch S2 is turned off. The gate drive voltage of the clamp switch Q2 is reduced by the first circuit block 270. In operation, the first circuit block 270 continues to reduce the gate drive voltage of Q2 until the logic high voltage on the PWM terminal is equal to a predetermined level (e.g., 3V). Secondly, when the logic high voltage on the PWM terminal is greater than the predetermined level (e.g., 3V), the first switch S1 is turned off and the second switch S2 is turned on. The reference supplied to the non-inverting input of the amplifier A1 is reduced by the second circuit block 280. In operation, the second circuit block 280 continues to reduce the reference supplied to the non-inverting input of the amplifier A1 until the logic high voltage on the PWM terminal is equal to a predetermined level (e.g., 3V). If the two input signals of the comparator CH1 are swapped (i.e., Vbg is coupled to the inverting input terminal and Vsns is coupled to the non-inverting input terminal), the circuit shown in FIG. 12 can similarly help the logic high voltage on the PWM terminal reach a predetermined level (e.g., 3V).

[0063]

[0075] 13 shows a flow chart for controlling the light-emitting diode system shown in FIG. 1 according to various embodiments of the present disclosure. This flow chart shown in FIG. 13 is merely an example and should not unduly limit the scope of the claims. Those skilled in the art may recognize many variations, substitutions, and modifications. For example, various steps shown in FIG. 13 may be added, deleted, substituted, rearranged, and repeated.

[0064]

[0076] 1 and 2, a number of light emitting diodes (e.g., D1-DN shown in FIG. 1) are connected in series between an input voltage bus (e.g., VIN shown in FIG. 1) and a power switch (e.g., Q1 shown in FIG. 1). A PWM controller (e.g., PWM controller 100 shown in FIG. 1) is configured to generate a gate drive signal that is provided to a gate of the power switch. A fault diagnosis device (e.g., fault diagnosis device 200 shown in FIG. 1) is connected to a PWM terminal of the PWM controller. The fault diagnosis circuit includes a clamp circuit (e.g., clamp circuit 206 shown in FIG. 2) configured to provide a predetermined voltage at an output of the clamp circuit, a clamp switch (e.g., clamp switch Q2 shown in FIG. 2) coupled to the output of the clamp circuit, and a pass device (e.g., pass device 204 shown in FIG. 2) connected between the clamp switch and an input / output terminal of the PWM controller.

[0065]

[0077] The clamp circuit includes an operational amplifier (e.g., operational amplifier A1 shown in FIG. 2), a first resistor (e.g., R1 shown in FIG. 2), and a second resistor (e.g., R2 shown in FIG. 2). A non-inverting input of the operational amplifier is connected to a predetermined reference. An inverting input of the operational amplifier is connected to a common node of the first resistor and the second resistor. The first resistor and the second resistor are connected in series between an output of the operational amplifier and ground. An output of the operational amplifier is an output of the clamp circuit. The clamp switch has a gate connected to a fault logic unit (e.g., fault logic unit 202 shown in FIG. 2). The fault logic unit is configured such that in response to a fault event, the fault logic unit generates a signal that causes the fault logic unit to turn on the clamp switch.

[0066]

[0078] The following method is adopted to generate a fault diagnostic signal under fault conditions so that a system controller (eg, a microcontroller) can determine whether a fault has occurred in the light emitting diode system.

[0067]

[0079] In step 1302, the microcontroller is configured to generate a PWM signal that is provided to a PWM terminal of a controller of a light emitting diode (LED) system.

[0068]

[0080] In step 1304, a fault event is detected in the LED system.

[0069]

[0081] In step 1306, in response to a fault event in the LED system, the logic high voltage of the PWM signal is clamped to a predetermined level via a clamp device.

[0070]

[0082] In some embodiments, the clamp apparatus comprises a clamp circuit configured to provide a predetermined voltage at an output of the clamp circuit, a clamp switch coupled to the output of the clamp circuit, and a pass device connected between the clamp switch and a PWM terminal of the controller.

[0071]

[0083] In some embodiments, the clamp circuit comprises an operational amplifier, a first resistor, and a second resistor. A non-inverting input of the operational amplifier is connected to a predetermined reference. An inverting input of the operational amplifier is connected to a common node of the first resistor and the second resistor. The first resistor and the second resistor are connected in series between an output of the operational amplifier and ground, and the output of the operational amplifier is an output of the clamp circuit. The clamp switch has a gate connected to a fault logic unit, the fault logic unit configured to generate a signal in response to a fault event that causes the fault logic unit to turn on the clamp switch. The pass device comprises a diode. An anode of the diode is connected to the input / output terminal of the integrated circuit. A cathode of the diode is connected to the clamp switch.

[0072]

[0084] The method further includes the steps of sensing a logic high voltage of the PWM signal after a fault event occurs, comparing the logic high voltage of the PWM signal with a predetermined level, and adjusting the predetermined criterion based on a comparison result obtained in the step of comparing the logic high voltage of the PWM signal with the predetermined level, where as a result of adjusting the predetermined criterion, the logic high voltage of the PWM signal is equal to the predetermined level under various operating conditions.

[0073]

[0085] The method further includes the steps of sensing a logic high voltage of the PWM signal after a fault event occurs, comparing the logic high voltage of the PWM signal with a predetermined level, and adjusting a gate drive voltage of the clamp switch based on a comparison result obtained in the step of comparing the logic high voltage of the PWM signal with the predetermined level, where adjusting the gate drive voltage of the clamp switch results in the logic high voltage of the PWM signal being equal to the predetermined level under various operating conditions.

[0074]

[0086] The method further includes sensing a logic high voltage of the PWM signal after the fault event occurs and comparing the logic high voltage of the PWM signal to a predetermined level. If the logic high voltage of the PWM signal is less than the predetermined level, reducing the gate drive voltage of the clamp switch such that the logic high voltage of the PWM signal equals the predetermined level. If the logic high voltage of the PWM signal is greater than the predetermined level, reducing the predetermined criteria such that the logic high voltage of the PWM signal equals the predetermined level.

[0075]

[0087] The method further includes configuring the fault logic unit such that at least one PWM pulse of the PWM signal has two logic high levels.

[0076]

[0088] Although the embodiments of the present disclosure and its advantages have been described in detail, it should be understood that various changes, substitutions and alterations can be made therein without departing from the spirit and scope of the present disclosure as defined by the appended claims.

[0077]

[0089] Moreover, the scope of the present application is not intended to be limited to the particular embodiments of the processes, machines, manufacture, compositions of matter, means, methods, and steps described herein. As one skilled in the art will readily appreciate from the disclosure herein, any currently existing or hereafter developed processes, machines, manufacture, compositions of matter, means, methods, or steps that perform substantially the same function or achieve substantially the same result as the corresponding embodiments described herein may be utilized in accordance with the present disclosure. Accordingly, it is intended that the appended claims include within their scope such processes, machines, manufacture, compositions of matter, means, methods, or steps. [Explanation of symbols]

[0078] 100 PWM Controllers 150 System Controller 200 Fault diagnosis device 202 Faulty Logical Unit 204 Path Device 206 Clamp Circuit 220 Peak Voltage Detector 240 Adder 270 First Circuit Block 280 Second Circuit Block 290 Third Circuit Block 1302 Steps 1304 Steps 1306 Steps A1 Operational Amplifier A2 Differential amplifier A3 Amplifier A4 Amplifier A5 Amplifier C1 First capacitor C2 Second capacitor CH1 Comparator D1 First clamp diode D1-DN Light Emitting Diode D2 Second clamp diode ESD Common FB Feedback terminal GND Ground terminal INV1 Inverter OUT Output terminal POR Power-up reset signal Q1 Power switch Q2 Clamp switch Q3 p-type transistor Q4 Power-up reset switch R1 First resistor R11 Adding resistor R12 resistor R14 resistor R2 Second resistor R3 resistor RS Current Sensing Resistor Rin1 resistor Rin2 resistor S1 Switch S1 First switch S1C Output Signal S2 Second switch S2C Output Signal V1 Voltage V1 Node V2 Node VCC Bias voltage terminal VIN Input voltage bus VPEAK signal Vadj Output voltage Vadj_gate output voltage Vadj_ref Output voltage Vbg Reference voltage Vsns signal

Claims

1. A clamp circuit comprising an operational amplifier, a first resistor, and a second resistor, the clamp circuit configured to provide a predetermined voltage at an output of the clamp circuit; the non-inverting input of said operational amplifier is connected to a predetermined reference; an inverting input of the operational amplifier is connected to a common node of the first resistor and the second resistor; a clamp circuit, the first resistor and the second resistor being connected in series between an output of the operational amplifier and ground, the output of the operational amplifier being the output of the clamp circuit; a clamp switch coupled to the output of the clamp circuit; a pass device connected between the clamp switch and an input / output terminal of a controller; An apparatus comprising:

2. the clamp circuit, the clamp switch, and the pass device are configured such that in response to a fault event, a logic high voltage at the input / output terminal of the controller is clamped to a predetermined set point.

2. The apparatus of claim 1.

3. a fault logic unit having an output connected to a gate of the clamp switch, the fault logic unit configured such that in response to a fault event, the fault logic unit generates a signal that causes the clamp switch to be turned on.

2. The apparatus of claim 1.

4. the pass device comprises a p-type transistor, a first clamp diode, a second clamp diode, and a bias resistor; a body terminal is connected to a source terminal of the p-type transistor; the first clamp diode is connected between the gate terminal and the drain terminal of the p-type transistor; the second clamp diode is connected between the gate terminal and the source terminal of the p-type transistor; the bias resistor is connected between the gate terminal and ground; 2. The apparatus of claim 1.

5. the pass device comprises a diode; the anode of the diode is connected to the input / output terminal of the controller; The cathode of the diode is connected to the clamp switch.

2. The apparatus of claim 1.

6. the pass device comprises a resistor connected between the input / output terminal of the controller and the clamp switch; 2. The apparatus of claim 1.

7. the pass device comprises an electrostatic discharge (ESD) device; 2. The apparatus of claim 1.

8. the ESD device is a Zener diode; a cathode of the Zener diode is connected to the input / output terminal of the controller; The anode of the Zener diode is connected to the clamp switch.

8. The apparatus of claim 7.

9. the pass device comprises a conductive line connected between the clamp switch and the input / output terminal of the controller; the clamp switch comprises an n-type metal oxide semiconductor (NMOS) ESD cell; 2. The apparatus of claim 1.

10. the input / output terminal of the controller is a pulse width modulation (PWM) terminal of the controller, the PWM terminal configured to receive a PWM signal from a system controller; 2. The apparatus of claim 1.

11. the controller being a PWM controller configured to generate gate drive signals for controlling an average current through a plurality of light emitting diodes connected in series; 2. The apparatus of claim 1.

12. configuring a microcontroller to generate a PWM signal that is provided to a PWM terminal of a controller of a light emitting diode (LED) system; detecting a fault event in the LED system; in response to the fault event in the LED system, clamping a logic high voltage of the PWM signal via a clamping device to a predetermined level; Including, The clamping device comprises: a clamp circuit comprising an operational amplifier, a first resistor, and a second resistor, the clamp circuit configured to provide a predetermined voltage at an output of the clamp circuit; a clamp switch coupled to the output of the clamp circuit; a pass device connected between the clamp switch and the PWM terminal of the controller; Equipped with the non-inverting input of said operational amplifier is connected to a predetermined reference; an inverting input of the operational amplifier is connected to a common node of the first resistor and the second resistor; the first resistor and the second resistor are connected in series between the output of the operational amplifier and ground; the output of the operational amplifier is the output of the clamp circuit; method.

13. the clamp switch has a gate connected to a fault logic unit, the fault logic unit being configured to generate a signal in response to the fault event that causes the fault logic unit to turn on the clamp switch; the pass device comprises a diode; The anode of the diode is connected to the PWM terminal of the controller, and the cathode of the diode is connected to the clamp switch. The method of claim 12.

14. sensing the logic high voltage of the PWM signal after the fault event occurs; comparing the logic high voltage of the PWM signal to the predetermined level; adjusting the predetermined criterion based on a comparison result obtained in the step of comparing the logic high voltage of the PWM signal to the predetermined level, whereby as a result of adjusting the predetermined criterion, the logic high voltage of the PWM signal is equal to the predetermined level under various operating conditions; The method of claim 13 further comprising:

15. sensing the logic high voltage of the PWM signal after the fault event occurs; comparing the logic high voltage of the PWM signal to the predetermined level; adjusting a gate drive voltage of the clamp switch based on a comparison result from the step of comparing the logic high voltage of the PWM signal to the predetermined level, where adjusting the gate drive voltage of the clamp switch results in the logic high voltage of the PWM signal being equal to the predetermined level under various operating conditions; The method of claim 13 further comprising:

16. sensing the logic high voltage of the PWM signal after the fault event occurs; comparing the logic high voltage of the PWM signal to the predetermined level; Further comprising: if the logic high voltage of the PWM signal is less than the predetermined level, reducing a gate drive voltage of the clamp switch such that the logic high voltage of the PWM signal is equal to the predetermined level; if the logic high voltage of the PWM signal is greater than the predetermined level, reducing the predetermined reference such that the logic high voltage of the PWM signal is equal to the predetermined level; The method of claim 13.

17. configuring the fault logic unit such that at least one PWM pulse of the PWM signal has two logic high levels. The method of claim 13.

18. a plurality of light emitting diodes connected in series between the input voltage bus and the power switch; a PWM controller configured to generate a gate drive signal provided to a gate of the power switch; a fault diagnostic circuit coupled to a PWM terminal of the PWM controller; Equipped with The fault diagnosis circuit includes: a clamp circuit configured to provide a predetermined voltage at an output of the clamp circuit; a clamp switch coupled to the output of the clamp circuit; a pass device connected between the clamp switch and an input / output terminal of the PWM controller; A system comprising:

19. the clamp circuit comprises an operational amplifier, a first resistor, and a second resistor; the non-inverting input of said operational amplifier is connected to a predetermined reference; an inverting input of the operational amplifier is connected to a common node of the first resistor and the second resistor; the first resistor and the second resistor are connected in series between an output of the operational amplifier and ground, the output of the operational amplifier being the output of the clamp circuit; the clamp switch has a gate connected to a fault logic unit, the fault logic unit being configured to generate a signal that causes the clamp switch to be turned on in response to a fault event; the pass device comprises a diode; the anode of the diode is connected to the input / output terminal of the PWM controller; The cathode of the diode is connected to the clamp switch.

20. The system of claim 18.

Images