Processing device, method and program

Abstract

To provide an arithmetic processing device, a method, and a program capable of suppressing a sudden increase or decrease in current in a device that uses a large number of digital filters.SOLUTION: An arithmetic processing device 1 includes a digital filter 2, a dummy data input unit 3, which allows dummy data to be input to the digital filter 2 when there is no input data to the digital filter 2, and a cancellation processing unit 4, which performs arithmetic processing to cancel an output component caused by the dummy data for output data from the digital filter 2.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present disclosure relates to a processor, a method, and a program. [Background technology]

[0002] In communications such as mobile phones, a time division multiplexing (TDM) method is sometimes used to divide and multiplex digital signals over time. In the case of TDM, for example, in downstream communications, a high voltage current may momentarily flow through the power line at the moment when the input to the filter in upstream communications stops.

[0003] In recent years, semiconductor chips such as FPGAs (Field Programmable Gate Arrays) that have come to be used in mobile devices such as mobile phones have a large circuit scale and use a large number of digital filters such as FIR (Finite Impulse Response) filters. In this case, problems such as a sudden increase and decrease in power consumption occur when switching between using and not using a filter circuit. To solve this problem, it is necessary to operate the arithmetic unit inside the filter, which consumes a large amount of power, even when it is not in use, to smooth out the power consumption. Patent Document 1 discloses a technology related to a dummy data generation circuit that outputs dummy data from a dummy data table when no data is input for a certain period of time. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] JP 2008-072164 A Summary of the Invention [Problem to be solved by the invention]

[0005] However, in the case of a hard macro in which a filter circuit is built in as hardware, the internal circuit cannot be changed according to the purpose. For example, even if a computing unit is operated, only its output is cut off, and measures such as eliminating the influence on the filter output cannot be taken in many cases. In addition, when dummy data is input from the outside as in Patent Document 1, it is necessary to provide a separate computing circuit to cancel the influence on the output. In this case, a design that takes into account the current consumption of the separately provided computing circuit is required. In addition, it is possible to smooth the current consumption by providing a dummy circuit according to the power consumption of this computing circuit, but this is difficult when the scale of the dummy circuit is large. Therefore, in a device that uses many digital filters, it is difficult to suppress a sudden increase or decrease in current without using a separate computing circuit.

[0006] An object of the present disclosure is to provide a processor, a method, and a program for solving such problems. [Means for solving the problem]

[0007] The arithmetic processing device according to the present disclosure includes a digital filter, a dummy data input unit that inputs dummy data to the digital filter when there is no input data to the digital filter, and a cancellation processing unit that performs arithmetic processing on output data from the digital filter to cancel output components caused by the dummy data.

[0008] The arithmetic processing method according to the present disclosure includes a step of inputting dummy data to a digital filter when there is no input data to the digital filter, and a step of performing arithmetic processing on output data from the digital filter to cancel output components caused by the dummy data.

[0009] The program disclosed herein causes a calculation processing device to execute a process of inputting dummy data to a digital filter when there is no input data to the digital filter, and a process of performing a calculation process on output data from the digital filter to cancel output components caused by the dummy data. Effect of the Invention

[0010] The present disclosure makes it possible to provide a processing device, method, and program capable of suppressing abrupt increases and decreases in current in a device that uses multiple digital filters. [Brief description of the drawings]

[0011] [Figure 1] FIG. 1 is a configuration diagram of a processor according to a first embodiment of the present disclosure. [Diagram 2] FIG. 11 is a configuration diagram of a processor according to a second embodiment of the present disclosure. [Diagram 3] FIG. 11 is a diagram illustrating the operation of a processor according to a second embodiment of the present disclosure. [Figure 4] FIG. 11 is a diagram illustrating the operation of a processor according to a second embodiment of the present disclosure. [Diagram 5] FIG. 11 is a diagram illustrating the operation of a processor according to a second embodiment of the present disclosure. [Figure 6] FIG. 11 is a diagram illustrating the operation of a processor according to a second embodiment of the present disclosure. [Figure 7] FIG. 11 is a configuration diagram of a control circuit according to a second embodiment of the present disclosure. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0012] Hereinafter, the embodiments will be described with reference to the drawings. Note that the drawings are simplified, and the technical scope of the embodiments should not be interpreted narrowly based on the description in the drawings. Also, the same elements are given the same reference numerals, and duplicated explanations will be omitted.

[0013] In the following embodiments, when necessary for convenience, the description will be divided into multiple sections or embodiments. However, unless otherwise specified, they are not unrelated to each other, and one is a partial or complete modification, application example, detailed explanation, supplementary explanation, etc. of the other. Furthermore, in the following embodiments, when the number of elements, etc. (including the number, numerical value, amount, range, etc.) is mentioned, it is not limited to the specific number, and may be more or less than the specific number, unless otherwise specified or when it is clearly limited to a specific number in principle.

[0014] Furthermore, in the following embodiments, the components (including operation steps, etc.) are not necessarily essential unless otherwise specified or considered to be clearly essential in principle. Similarly, in the following embodiments, when referring to the shape, positional relationship, etc. of components, etc., it is intended to include those that are substantially similar or similar to the shape, etc., unless otherwise specified or considered to be clearly not essential in principle. The same applies to the above numbers, etc. (including numbers, values, amounts, ranges, etc.).

[0015] <Embodiment 1> The configuration of a processor 1 in this embodiment will be described with reference to Fig. 1. Fig. 1 is a configuration diagram of the processor 1 in this embodiment.

[0016] The arithmetic processing device 1 in this embodiment includes a digital filter 2, a dummy data input unit 3, and a cancellation processing unit 4. The digital filter 2 can use various digital filters such as an FIR (Finite Impulse Response) filter or an IIR (Infinite Impulse Response) filter.

[0017] The dummy data input unit 3 inputs dummy data to the digital filter 2 when there is no input data to the digital filter 2 .

[0018] The cancellation processing unit 4 performs a calculation process on the output data from the digital filter 2 to cancel the output component caused by the dummy data input by the dummy data input unit 3 .

[0019] According to the arithmetic processing device 1 of the present embodiment, it is possible to suppress abrupt increases and decreases in current in a device that uses many digital filters.

[0020] <Embodiment 2> The configuration of the arithmetic processing device 1 in this embodiment will be described with reference to Fig. 2. Fig. 2 is a configuration diagram of the arithmetic processing device 1 in this embodiment.

[0021] 2 shows an example of the configuration of the arithmetic processing device 1 according to this embodiment. In this embodiment, the arithmetic processing device 1 includes an FIR filter 10.

[0022] When there is no data to be input to the FIR filter 10, the dummy data d stored in the dummy data table 11 is m is input to the FIR filter 10. Also, the input data X n and dummy data d to be entered from dummy data table 11 m An input / dummy data switching circuit 12 for selecting either one of the above is provided at the input portion of the FIR filter 10.

[0023] The cancellation data table 13 stores cancellation data used in the calculation process for canceling the output components from the FIR filter 10 that are caused by the dummy data. Also, a cancellation data switching circuit 14 is provided for selecting either data “0” or cancellation data input from the cancellation data table 13.

[0024] A canceling adder 15 that adds the data output from the canceling data switching circuit 14 and the data output from the FIR filter 10 is provided at the output section of the FIR filter 10. In addition, an output data switching circuit 16 is provided that selects either the data input from the canceling adder 15 or "0".

[0025] In this embodiment, the digital filter is described as being an FIR filter 10, but the digital filter is not limited to this and various other digital filters such as an IIR filter can be used.

[0026] Here, an example of the configuration of the FIR filter 10 in this embodiment is shown. As shown in Fig. 2, in this embodiment, the number of taps of the FIR filter 10 is 5. However, the number of taps of the FIR filter 10 is not limited to 5. The FIR filter 10 also includes delay elements R0 to R4, multipliers A0 to A4, and an in-filter adder 17. The multipliers A0 to A4 are connected to the delay elements R0 to R4, respectively. The delay elements R0 to R4 use logic circuits such as D-type flip-flops, for example.

[0027] Data X output from the input / dummy data switching circuit 12 n ~X n-4 is stored in delay elements R0 to R4. The input data is delayed by one unit time in the order of delay elements R4, R3, R2, R1, and R0, and then input to multipliers A0, A1, A2, A3, and A4, respectively.

[0028] The multiplier A0 multiplies the data X stored in the delay element R4 by n The multiplier A1 multiplies the data X by a tap coefficient a0 and outputs the data after the coefficient multiplication to the adder 17 in the filter. n-1 The multiplier A2 multiplies the data X by a tap coefficient a1 and outputs the data after the coefficient multiplication to the adder 17 in the filter. n-2 The multiplier A3 multiplies the data X by a tap coefficient a2 and outputs the data after the coefficient multiplication to the adder 17 in the filter. n-3 The multiplier A4 multiplies the data X by a tap coefficient a3 and outputs the data after the coefficient multiplication to the adder 17 in the filter. n-4 is multiplied by a tap coefficient a4, and the data after the coefficient multiplication is output to the adder 17 in the filter.

[0029] The adder 17 obtains output data from the FIR filter 10 by adding all the coefficient-multiplied data output from each of the multipliers A0 to A4.

[0030] As shown in FIG. 2, an input / dummy data switching circuit 12 is provided at the input section of the FIR filter 10. The input data X n If there is no dummy data, dummy data d from dummy data table 11 m Enter.

[0031] As shown in Fig. 2, the output section of the FIR filter 10 is provided with a cancellation adder 15 that cancels output components caused by dummy data generated by using the dummy data in calculations inside the FIR filter 10. A cancellation data table 13 has data for canceling output components caused by the dummy data. When it is necessary to cancel output components caused by the dummy data, a cancellation data switching circuit 14 selects data from the dummy data table 11 and outputs it to the cancellation adder 15. At this time, the cancellation adder 15 subtracts the output from the FIR filter 10 using the data input from the cancellation data switching circuit 14.

[0032] When dummy data dm is stored in all delay elements of the FIR filter 10, the output data switching circuit 16 selects 0 as the output data.

[0033] Here, dummy data d is input to the FIR filter 10. m The configuration of the OFDM (Orthogonal Frequency Division Multiplexing) signal generator 20 that determines whether to input or not will be described with reference to Fig. 7. Fig. 7 is a diagram showing the configuration of the OFDM signal generator 20 in this embodiment.

[0034] The input / dummy data switching circuit 12 receives the input data X n If it is possible to clearly determine the timing when becomes 0, the dummy data d mHowever, the input / dummy data switching circuit 12 selects and outputs the input data X n When it is not possible to determine the timing at which the input signal becomes 0, the power calculation unit 21 of the OFDM signal generation unit 20 calculates the power of the input signal.

[0035] 7, the OFDM signal generating unit 20 includes a power calculating unit 21, an IFFT (Inverse Fast Fourier Transform) unit 22, a buffer unit, and a threshold comparing unit 24. The OFDM signal generating unit 20 is provided on the input side of the FIR filter 10.

[0036] As shown in FIG. 7, the OFDM signal generating unit 20 includes a buffer unit 23 on the input side of the IFFT unit 22, and transmits an input signal. The IFFT unit 22 performs inverse Fourier transform processing on a certain number of signal samples (for example, one OFDM symbol). At this time, a power calculation unit 21 calculates the signal power of the input signal that passes through the buffer unit 23. A threshold is set for the signal power of the input signal calculated by the power calculation unit 21, and a threshold comparison unit 24 judges whether the signal power is equal to or lower than the threshold. If the threshold comparison unit 24 judges that the power is equal to or lower than the threshold, the input / dummy data switching circuit 12 switches the dummy data d m Select and output.

[0037] <Description of the Operation of the Arithmetic Processing Unit in the Present Embodiment> The operation of the arithmetic processing device 1 in this embodiment according to the data states of the delay elements R0 to R4 of the FIR filter 10 will be explained in chronological order with reference to FIGS.

[0038] In Figure 2, the input data X n At this time, the input / dummy data switching circuit 12 switches the data X n The cancel data switching circuit 14 selects and outputs 0.

[0039] Here, the output y(n) of the N-tap FIR filter 10 is expressed by the following formula (1). In this embodiment, N=5.k is the tap coefficient, x n-k represents the input data.

Number

[0040] Figure 3 shows the case where the input data becomes 0. At this time, since there is no input data, the input / dummy data switching circuit 12 selects and outputs the dummy data d0. At this time, the dummy data d0 is stored in the delay element R4 of the FIR filter 10. At this time, the cancellation data switching circuit 14 outputs the cancellation data d0×a0 from the cancellation data table 13 to the cancellation adder 15, and subtraction is performed from the output of the FIR filter 10 to cancel the output component caused by the dummy data.

[0041] The cancellation data table(n) stored in the cancellation data table 13 for cancellation is as shown in the following formula (2). Note that n = 0 to (N×2 - 1). d n―k is the data used as a dummy. However, d n―k is not 0 when (n - k) < N, and is 0 otherwise.

Number

[0042] Next, Figure 4 shows the state where the dummy data d0 to d4 are stored in all the delay elements R0 to R4 of the FIR filter 10. It is preferable that the output of the FIR filter becomes 0 when the 5-tap dummy data d0 to d4 are stored in the delay elements R0 to R4. Therefore, the output data switching circuit 16 selects and outputs 0.

[0043] At this time, while the input data is 0, the values in the dummy data table 11 are repeatedly input. That is, in formula (2), it is repeated until n = (n + 1) mod (N - 1).

[0044] At this time, by inputting the dummy data in the dummy data table 11 to the FIR filter 10 sequentially for each unit time, the adder 17 in the filter of the FIR filter 10 operates, and the current can be continued to be consumed as it is.

[0045] Furthermore, from the input 0 state, the input data X n The state when the input data X starts to be input again is shown in FIG. n and outputs it to the FIR filter 10. The cancellation data switching circuit 14 also selects cancellation data in the cancellation data table 13 and outputs it to the cancellation adder 15. The cancellation adder 15 subtracts the output from the FIR filter 10 using the cancellation data output from the cancellation data switching circuit 14, thereby canceling the output component caused by the dummy data remaining in the FIR filter 10. At this time, the output data switching circuit 16 selects the output from the cancellation adder 15 and outputs it.

[0046] Finally, all the dummy data is removed from the delay elements R0 to R4 inside the FIR filter 10, and the input data X n+1 ~X n+5 The state when is entered is shown in Figure 6. At this time, there is no need to cancel the output component caused by the dummy data. Therefore, the cancellation data switching circuit 14 selects and outputs 0. In other words, when n=N-1 in equation (1), the cancellation data switching circuit 14 selects and outputs 0.

[0047] According to the arithmetic processing device 1 of the present embodiment, the time when there is no input to the FIR filter 10 can be suppressed, so that the arithmetic circuit and the delay elements R0 to R4 continue to perform switching operations, and the power consumption becomes equivalent to that during normal operation. Therefore, the power consumption in the FIR filter 10 is smoothed.

[0048] The currents of the input / dummy data switching circuit 12 and the cancellation data switching circuit 14, which are used to select and output data from the dummy data table 11 and the cancellation data table 13, are smaller than the current consumption of the FIR filter 10 itself. Therefore, by providing a circuit for inputting dummy data and a circuit for canceling the output component caused by the dummy data, the power consumption of the circuit can be smoothed.

[0049] As described above, by providing a circuit that inputs dummy data while there is no input to the digital filter and a circuit that cancels the effect on the digital filter output due to the input of dummy data, the power consumption of the arithmetic processing device 1 can be smoothed.

[0050] <Other embodiments> In the above embodiment, the present disclosure has been described as a hardware configuration, but the present disclosure is not limited thereto. The arithmetic processing device 1 in the present disclosure has an embodiment as an arithmetic processing method, for example. That is, the arithmetic processing method has a step of inputting dummy data to a digital filter when there is no input data to the digital filter, and a step of performing an arithmetic processing for canceling an output component caused by the dummy data for output data from the digital filter.

[0051] Furthermore, in the present disclosure, the processing in the arithmetic processing device 1 can also be realized by causing a CPU (Central Processing Unit) to execute a computer program.

[0052] In the above example, the program can be stored and provided to the computer using various types of non-transitory computer readable media. The non-transitory computer readable media includes various types of tangible storage media. Examples of the non-transitory computer readable media include magnetic recording media (e.g., flexible disks, magnetic tapes, hard disk drives), magneto-optical recording media (e.g., magneto-optical disks), CD-ROM (Read Only Memory), CD-R, CD-R / W, and semiconductor memory (e.g., mask ROM, PROM (Programmable ROM), EPROM (Erasable PROM), flash ROM, RAM (Random Access Memory)). The program may also be provided to the computer by various types of transitory computer readable media. Examples of the transitory computer readable media include electrical signals, optical signals, and electromagnetic waves. The temporary computer-readable medium can supply the program to the computer via a wired communication path such as an electric wire or an optical fiber, or via a wireless communication path.

[0053] The above-mentioned program is a calculation processing program that causes the information processing device 1 to execute a process of inputting dummy data to a digital filter when there is no input data to the digital filter, and a process of performing a calculation process on the output data from the digital filter to cancel the output component caused by the dummy data.

[0054] The above describes in detail the embodiments of the present disclosure with reference to the drawings. However, the specific configuration is not limited to the above, and various design changes and the like are possible within the scope that does not deviate from the gist of the present disclosure. [Explanation of symbols]

[0055] 1 Processing Unit 2 Digital Filter 3 Dummy data input section 4 Cancellation processing section 10. FIR Filters 11 Dummy Data Table 12 Input / dummy data switching circuit 13 Cancellation Data Table 14 Cancel data switching circuit 15 Cancellation adder 16 Output data switching circuit 17 Adder in Filter 20 OFDM signal generation section 21 Power Calculation Section 22 IFFT section 23 Buffer section 24 Threshold comparison unit

Claims

1. A digital filter whose impulse response completes within a finite time; a dummy data input unit for inputting dummy data to the digital filter when there is no input data to the digital filter; a cancellation processing unit that performs a calculation process for canceling an output component caused by the dummy data with respect to the output data from the digital filter; A processing unit comprising:

2. The dummy data input unit determines whether or not there is no input data. The processor according to claim 1 .

3. when it is not possible to determine whether the input data is present, the dummy data input unit calculates a signal power of an input signal corresponding to the input data, and when the signal power is equal to or less than a threshold, inputs the dummy data to the digital filter. The processor according to claim 2 .

4. The input data is generated by performing an inverse Fourier transform on the input signal. The processor according to claim 3 .

5. The dummy data input unit includes an inverse Fourier transform unit that performs an inverse Fourier transform on the input signal to generate the input data. The processor according to claim 3 .

6. The dummy data input unit includes a buffer unit through which the input signal passes. The processor according to any one of claims 3 to 5.

7. The dummy data input unit includes a dummy data table for storing the dummy data. The processor according to any one of claims 1 to 5.

8. The cancellation processing unit includes a cancellation data table for storing cancellation data used in a calculation process for canceling an output component caused by the dummy data. The processor according to any one of claims 1 to 5.

9. The digital filter is a Finite Impulse Response (FIR) filter. The processor according to any one of claims 1 to 5.

10. When dummy data is stored in all of the delay elements of the FIR filter, 0 is output as output data. The processor according to claim 9.

11. A step of inputting dummy data to a digital filter when there is no input data to the digital filter whose impulse response ends within a finite time; performing a calculation process on the output data from the digital filter to cancel an output component caused by the dummy data; A computation method comprising:

12. A process of inputting dummy data to a digital filter when there is no input data to the digital filter whose impulse response ends within a finite time; a process of performing a calculation process on the output data from the digital filter to cancel an output component caused by the dummy data; A program that causes a processor to execute the above.

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