Electronic Control Unit

Abstract

To appropriately shorten an execution time of secure boot.SOLUTION: An electronic control device 1 includes a hardware security module 4 for generating a verification value on the basis of an encryption key, and capable of executing verification processing of an area by collating the generated verification value with a collation value, and an arithmetic part 5 capable of executing arithmetic processing. A target area of secure boot is divided so as to include at least a first division area and a second division area. A portion of verification processing of the first division area is executed by the hardware security module, the entire verification processing of the second division area is executed by the arithmetic part, and the portion of the verification processing of the first division area and the entire verification processing of the second division area are executed in parallel.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to an electronic control device. [Background technology]

[0002] For example, electronic control devices mounted on vehicles are equipped with a function to rewrite applications (hereinafter referred to as apps) in order to add functions to the apps or repair defects, and also with a function to detect app tampering by malicious third parties. An app means software that realizes a specific function. There is a mechanism called secure boot as a method for detecting app tampering before starting the launch of the app. For example, Patent Document 1 discloses a method of executing secure boot using a hardware security module (hereinafter referred to as HSM (Hardware Security Module)). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2017-33248 A Summary of the Invention [Problem to be solved by the invention]

[0004] The target area of ​​secure boot is proportional to the verification time required to verify the target area, and the verification time increases as the target area of ​​secure boot increases. In a configuration in which an electronic control device that executes secure boot cooperates with other electronic control devices to execute applications, the electronic control device that executes secure boot needs to complete secure boot before starting data communication with the other electronic control devices. However, since the verification time increases as the target area of ​​secure boot increases as described above, if the entire target area of ​​secure boot is executed by the HSM, there are cases in which verification of the entire target area cannot be completed before starting data communication.

[0005] The present invention has been made in consideration of the above-mentioned circumstances, and has an object to provide an electronic control device that can appropriately reduce the execution time of secure boot. [Means for solving the problem]

[0006] According to the invention described in claim 1, a hardware security module (4) capable of generating a verification value based on an encryption key and verifying an area by verifying the generated verification value against a verification value; and a calculation unit (5) capable of performing calculation processing; A data flash (6) that can be accessed securely by activating a dedicated security program; A target area for secure boot is divided to include at least a first divided area and a second divided area. A part of the verification process for the first divided area is executed by the hardware security module, and the whole of the verification process for the second divided area is executed by the arithmetic unit, and the part of the verification process for the first divided area and the whole of the verification process for the second divided area are executed in parallel. The data flash stores an encryption key required for the calculation unit to generate a verification value.

[0007] Unlike conventional methods in which all of the areas subject to secure boot are executed by the hardware security module, by executing part of the verification process of the first divided area in the hardware security module and the entire verification process of the second divided area in the calculation unit in parallel, the execution time of secure boot can be appropriately shortened. [Brief description of the drawings]

[0008] [Figure 1] Functional block diagram showing one embodiment. [Diagram 2] Flowchart showing processing for the entire area subject to secure boot [Diagram 3] Flowchart showing the CPU side processing in the verification processing of area A [Figure 4] Flowchart showing the process on the HSM side in the verification process of area A [Diagram 5] A diagram explaining the verification process for area A [Figure 6] Flowchart showing the CPU side processing in the verification processing of area B [Figure 7] Flowchart showing the process on the HSM side in the verification process of area B [Figure 8] A diagram explaining the verification process for area B [Figure 9] Flowchart showing the CPU side processing in the verification processing of area C [Figure 10] A diagram explaining the verification process for area C [Figure 11] Timing Chart DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0009] An embodiment will be described below with reference to the drawings. As shown in FIG. 1, an electronic control unit (ECU) 1 is, for example, an in-vehicle electronic control unit mounted on a vehicle, and is a device having a function of managing a plurality of ECUs. The electronic control unit 1 may be, for example, a device that controls a drive system, a device that controls an ADAS (Advanced Driving Assistant System), a device that controls a multimedia system, etc. The electronic control unit 1 is equipped with a secure boot function that detects tampering of an app by a malicious third party before starting the startup of the app.

[0010] The electronic control device 1 includes an MPU 2. The MPU 2 includes a ROM 3, an HSM 4, a CPU 5 as a calculation unit, and a data flash 6. The MPU 2 executes a computer program stored in a non-transient substantial storage medium to perform processing corresponding to the computer program, and controls the operation of the electronic control device 1. The CPU 5 is capable of executing calculation processing.

[0011] The ROM 3 includes a secure boot target area 7 as an area for storing data, and a boot program area 8 for storing a boot program and a security program area 9 for storing a security program for security authentication as areas for storing programs. The secure boot target area 7 is divided into an area A as a third divided area, an area B as a first divided area, and an area C as a second divided area. The area A includes area division information of the areas B and C, a MAC value of the area B, and a MAC value of the area C. The area division information of the area B is address information indicating a storage range of data specified by a start address and an end address of the area B, and the area division information of the area C is address information indicating a storage range of data specified by a start address and an end address of the area C. The MAC value corresponds to a collation value. The boot program area 8 includes area division information of the area A. The area division information of the area A is address information indicating a storage range of data specified by a start address and an end address of the area A. The area division information of the area A is information that can be written only once, and cannot be updated after being written.

[0012] The HSM 4 stores an encryption key required to generate a verification value when verifying areas A and B, and a MAC value for area A. The data flash 6 is security accessible when a dedicated security program stored in a security program area 9 is started, and stores an encryption key required to generate a verification value when verifying area C.

[0013] Next, the operation of the above-mentioned configuration will be described with reference to FIGS. In the electronic control device 1, the HSM 4 and the CPU 5 cooperate to execute the verification process for areas A and B, and the CPU 5 executes the verification process for area C alone. As shown in Fig. 2, the electronic control device 1 executes the verification process for area A (S1), and when the verification process for area A is completed, executes the verification process for area B and the verification process for area C in parallel (S2, S3). The verification processes for areas A to C will be described below.

[0014] (1) Verification process for area A The verification process for area A will be described with reference to FIGS. When the CPU 5 starts CPU-side processing for the verification process of area A, it acquires area division information of area A stored in the boot program area 8 of ROM 3 (A1), and acquires the data of area A stored in the secure boot target area 7 of ROM 3 (A2). The CPU 5 transmits permission to execute verification of area A to the HSM 4 (A3), transmits the area division information of area A to the HSM 4 (A4), transmits the data of area A to the HSM 4 (A5), and waits to receive the verification result of area A from the HSM 4.

[0015] When the HSM4 starts the HSM-side processing for the verification process of the area A, it receives the verification execution permission for the area A sent from the CPU5 (B1). When the HSM4 receives the area division information for the area A sent from the CPU5 (B2) and receives the data for the area A sent from the CPU5 (B3), it generates a verification value for the area A using the encryption key it holds (B4). The HSM4 compares the generated verification value for the area A with the MAC value for the area A it holds (B5), verifies the area A (B6), sends the verification result for the area A to the CPU5 (B7), and ends the processing on the HSM side. That is, if the verification value and the MAC value match, the HSM4 sends the verification result indicating the match between the verification value and the MAC value to the CPU5, and if the verification value and the MAC value do not match, it sends the verification result indicating the mismatch between the verification value and the MAC value to the CPU5.

[0016] When the CPU 5 receives the verification result of area A sent from the HSM 4 (A6), it determines whether or not the verification value and the MAC value match based on the received verification result (A7). If the CPU 5 determines that the verification value and the MAC value match (A7: YES), it proceeds to verification of areas B and C (A8) and ends the CPU-side processing. If the CPU 5 determines that the verification value and the MAC value do not match (A7: NO), it interrupts startup without proceeding to verification of areas B and C (A9) and ends the CPU-side processing. Figure 5 shows how various information is transmitted and received in the verification processing of area A.

[0017] (2) Verification process for area B The verification process for area B will be described with reference to FIGS. When the CPU 5 starts CPU-side processing for the verification process of area B by determining that the verification result of area A matches, it acquires area division information of area B stored in the secure boot target area 7 of ROM 3 (A11), specifies a data storage range based on the acquired area division information of area B, and acquires the data of area B (A12). The CPU 5 transmits permission to execute verification of area B to the HSM 4 (A13), transmits the area division information of area B to the HSM 4 (A14), transmits the data of area B to the HSM 4 (A15), and waits to receive the verification value of area B from the HSM 4.

[0018] When the HSM 4 starts the HSM-side processing for the verification process of area B, it receives the verification execution permission for area B sent from the CPU 5 (B11). The HSM 4 receives the area division information for area B sent from the CPU 5 (B12), and when it receives the data for area B sent from the CPU 5 (B13), it generates a verification value for area B using the encryption key it holds (B14). The HSM 4 sends the generated verification value for area B to the CPU 5 (B15), and ends the HSM-side processing.

[0019] When the CPU 5 receives the verification value for area B transmitted from the HSM 4 (A16), it acquires the MAC value for area B stored in the secure boot target area 7 of the ROM 3 (A17), compares the received verification value for area B with the acquired MAC value for area B (A18), and verifies area B (A19). When the CPU 5 determines that the verification value and the MAC value match (A20: YES), it ends the CPU-side processing. When the CPU 5 determines that the verification value and the MAC value do not match (A20: NO), it interrupts the startup (A21) and ends the CPU-side processing. FIG. 8 shows how various information is transmitted and received in the verification processing for area B.

[0020] (3) Verification process for area C The verification process for area C will be described with reference to FIGS. When the CPU 5 starts CPU-side processing for the verification process of area C by determining that the verification results of area A match, it acquires area division information of area C stored in the secure boot target area 7 of the ROM 3 (A31), specifies a data storage range based on the acquired area division information of area C, and acquires the data of area C (A32). The CPU 5 transmits an instruction to read the encryption key to the security program (A33), and acquires the encryption key stored in the data flash 6 by activating the security program (A34), and generates a verification value for area C using the acquired encryption key (A35).

[0021] The CPU 5 acquires the MAC value of area C stored in the secure boot target area 7 of the ROM 3 (A36), compares the generated verification value of area C with the acquired MAC value of area C (A37), and verifies area C (A38). If the CPU 5 determines that the verification value and the MAC value match (A39: YES), it ends the CPU-side processing. If the CPU 5 determines that the verification value and the MAC value do not match (A39: NO), it interrupts the startup (A40) and ends the CPU-side processing. FIG. 10 shows how various information is transmitted and received in the verification processing of area C. That is, the HSM 4 is not involved at all in the verification processing of area C.

[0022] 11, the generation of the verification value for area B is executed by HSM4, and the generation of the verification value for area C and the comparison between the verification value and the MAC value are executed by CPU5, so that the generation of the verification value for area B and the generation of the verification value for area C and the comparison between the verification value and the MAC value are executed in parallel. The allocation of the data amount of area B where the verification process is executed by HSM4 and the data amount of area C where the verification process is executed by CPU5 can be determined according to the following formula. Specifically, when the capacity of the application area to be the target area of ​​secure boot is determined, the data amounts to be allocated to areas B and C are determined based on the start-up time of HSM4, the boot loader time of CPU5, and the processing speeds of HSM4 and CPU5.

[0023] HSM verification speed: Time calculated from the number of verifications per second of HSM4 CPU verification speed: Time calculated from the amount of verifications per second of CPU5 HSM Startup Time: The time it takes for the HSM4 to start up Bootloader Time: CPU5 bootloader time Total verification area: Sum of area B and area C HSM verification volume: Amount of data to be allocated to area B CPU verification volume: Amount of data to be allocated to area C In this case, HSM startup time + (HSM verification volume / HSM verification speed) = Boot loader time + (CPU verification amount / CPU verification speed)…(A) HSM verification volume + CPU verification volume = total verification area…(a) Since the above formulas (A) and (B) are used to calculate the HSM verification volume and the CPU verification volume, respectively, the following formulas can be used: HSM verification volume = ((total verification area + (HSM startup time - boot loader time) x HSM verification speed) x CPU verification speed) / (HSM verification speed + CPU verification speed) CPU verification volume = ((total verification area + (boot loader time - HSM startup time) x CPU verification speed) x HSM verification speed) / (HSM verification speed + CPU verification speed)

[0024] As described above, according to the embodiment, the following advantageous effects can be obtained. In the electronic control device 1, the generation of the verification value for area B is executed by the HSM 4, the generation of the verification value for area C and the comparison of the verification value with the MAC value are executed by the CPU 5, and the generation of the verification value for area B, the generation of the verification value for area C and the comparison of the verification value with the MAC value are executed in parallel. Unlike the conventional method in which all areas subject to secure boot are executed by the HSM 4, the generation of the verification value for area B in the HSM 4, and the generation of the verification value for area C in the CPU 5 and the comparison of the verification value with the MAC value are executed in parallel, thereby making it possible to appropriately shorten the execution time of the secure boot.

[0025] The encryption key required for the CPU 5 to generate the verification value for the area C is stored in the data flash 6, which is security-accessible by activating a dedicated security program. The security of the encryption key can be appropriately ensured.

[0026] After completing the verification process for area A, the generation of a verification value for area B, the generation of a verification value for area C, and the comparison of the verification value with the MAC value are executed in parallel. When executing the verification process for areas B and C, if the MAC values ​​of areas B and C have been tampered with, the verification results will become meaningless. Therefore, the verification process for area A, in which the MAC values ​​of areas B and C are stored, is executed first, and then the verification process for areas B and C is executed on the condition that the verification value of area A matches the MAC value, thereby making it possible to properly guarantee the verification results of areas B and C.

[0027] Although the present disclosure has been described based on the embodiment, it is understood that the present disclosure is not limited to the embodiment or structure. The present disclosure also includes various modifications and modifications within the equivalent range. In addition, various combinations and forms, as well as other combinations and forms including only one element, more than one element, or less than one element, are also within the scope and concept of the present disclosure.

[0028] Although the example has been given with one CPU, two or more CPUs may be used. In the case of a first CPU and a second CPU as two CPUs, the area may be divided into areas A, B, C, and D, and a verification process for area A in which each MAC value for areas B, C, and D is stored is first executed, and verification processes for areas B, C, and D are executed on the condition that the verification value for area A matches the MAC value, and the generation of the verification value for area B in the HSM 4, the generation of the verification value for area C and the comparison of the verification value with the MAC value in the first CPU, and the generation of the verification value for area D and the comparison of the verification value with the MAC value in the second CPU may be executed in parallel.

[0029] The control unit and the method described in the present disclosure may be realized by a special-purpose computer provided by configuring a processor and a memory programmed to execute one or more functions embodied in a computer program. Alternatively, the control unit and the method described in the present disclosure may be realized by a special-purpose computer provided by configuring a processor with one or more dedicated hardware logic circuits. Alternatively, the control unit and the method described in the present disclosure may be realized by one or more special-purpose computers configured by a combination of a processor and a memory programmed to execute one or more functions and a processor configured with one or more hardware logic circuits. Also, the computer program may be stored in a computer-readable non-transitory tangible recording medium as instructions executed by a computer. [Explanation of symbols]

[0030] In the drawing, 1 is an electronic control device, 2 is an MPU, 3 is a ROM, 4 is an HSM, 5 is a CPU (calculating unit), and 6 is a data flash.

Claims

1. a hardware security module (4) capable of generating a verification value based on an encryption key and verifying an area by verifying the generated verification value against a verification value; A calculation unit (5) capable of executing calculation processing; A data flash (6) that can be securely accessed by starting a dedicated security program; Dividing a target area for secure boot to include at least a first divided area and a second divided area, executing a part of a verification process for the first divided area in the hardware security module, and executing an entirety of the verification process for the second divided area in the arithmetic unit, A part of the verification process for the first divided region and an entirety of the verification process for the second divided region are executed in parallel; The electronic control device, wherein the data flash stores an encryption key required for the calculation unit to generate a verification value.

2. generating a verification value based on a cryptographic key in the hardware security module as part of the verification process of the first divided region; 2. The electronic control device according to claim 1, wherein the calculation unit executes a comparison between a verification value and a comparison value as the remaining part of the verification process for the first divided region.

3. Dividing the target area of ​​the secure boot to include at least the first divided area and the second divided area, and further including a third divided area; The third divided region stores divided region information indicating each region of the first divided region and the second divided region, a matching value of the first divided region, and a matching value of the second divided region, 3. The electronic control device according to claim 1, further comprising: a step of executing a part of the verification process for the first divided region and the verification process for the second divided region in parallel after completing the verification process for the third divided region.

4. The calculation unit is multiple, The electronic control device according to claim 1 , wherein the second divided region is a plurality of regions.

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