Display device

Abstract

To provide a display device in which it is made possible to shrink the peripheral area of a display panel.SOLUTION: A pixel circuit board 41 includes: a plurality of first wirings 31 arranged on one surface side of a substrate 12 and electrically connected to a plurality of pixel circuits 3, respectively; a plurality of contact plugs 32 arranged in the thickness direction of the substrate 12 and electrically connected to the plurality of first wirings 31, respectively; and a plurality of second wirings 33 arrange on the other surface side of the substrate 12 and electrically connected to the plurality of contact plugs 32, respectively. A drive circuit board 42 includes a plurality of third wirings 46 arranged on one or other surface side of a substrate 44 and electrically connected to a drive circuit 36. The second wirings 33 and the third wirings 46 are electrically connected together in a state in which the other surface of the pixel circuit board 41 and the one or other surface of the drive circuit board 42 face each other, and the drive circuit board 42 is provided in a region that overlaps a display region E in a plan view.SELECTED DRAWING: Figure 18

Description

[Technical field]

[0001] The present invention relates to a display device. Place Regarding. [Background technology]

[0002] For example, organic electroluminescence (EL) display devices (organic EL displays) using organic EL elements have high brightness and self-luminance, can be driven at a low DC voltage, have high response speed, and emit light from a solid organic film, so that they have excellent display performance and can be made thin, lightweight, and consume less power. For these reasons, they are expected to replace liquid crystal display devices in the future (for example, see Patent Document 1 below).

[0003] Specifically, an organic EL display device includes a display panel including a display area in which a plurality of pixels are arranged in a matrix on a surface of the display panel. The display panel includes a plurality of scanning lines (gate lines), a plurality of signal lines (data lines), and a plurality of power lines (power lines) arranged in the horizontal and vertical directions on the surface of the display area, and a pixel circuit constituting the above-mentioned pixels is provided in each of the areas partitioned by the plurality of scanning lines and the plurality of signal lines.

[0004] The display panel includes, as pixel circuits, an organic EL element which is a light-emitting element, a capacitor which is a storage capacitance, and two thin film transistor (TFT) elements which are switching elements. In the display panel, the potential (image data) of the signal line is stored in the storage capacitance which is connected to the signal line via the selection TFT element by the switching operation of the selection TFT element which is connected to the scan line. Also, depending on the potential of the storage capacitance, a drive current flows through the organic EL element which is connected to the power supply line via the drive TFT element. This makes it possible to cause the organic EL element to emit light (light up).

[0005] The display panel is also provided with a peripheral area called a bezel (frame) surrounding the periphery of the display area. In the peripheral area, a plurality of connection parts corresponding to a plurality of scanning lines and a plurality of signal lines drawn out to the outside of the display area are arranged in the horizontal and vertical directions of the peripheral area. The plurality of scanning lines and the plurality of signal lines are electrically connected to an external driving circuit (driver) via a flexible printed circuit board (FPC) connected to the plurality of connection parts. [Prior art documents] [Patent documents]

[0006] [Patent Document 1] JP 2013-105148 A Summary of the Invention [Problem to be solved by the invention]

[0007] However, in the above-mentioned conventional display devices, the provision of a peripheral area outside the display area not only increases the panel size but also increases the panel weight, which is a problem. In addition, when multiple display panels are arranged in a plane as a multi-display to display one screen, the peripheral area of ​​the display panel becomes an obstacle.

[0008] The present invention has been proposed in view of the above-mentioned conventional circumstances, and provides a display device that makes it possible to reduce the peripheral area of ​​a display panel. Place The purpose is to provide. [Means for solving the problem]

[0009] In order to achieve the above object, the present invention provides the following means. [1] A display panel including a display area in which a plurality of pixels are arranged in a plane, The display panel includes a pixel circuit substrate on which pixel circuits constituting the pixels are provided; A drive circuit board on which a drive circuit for driving the pixel circuit is provided. and, The pixel circuit board Board a plurality of first wirings arranged on one surface side and electrically connected to each of the plurality of pixel circuits; The pixel circuit a plurality of contact plugs arranged in a thickness direction of the substrate and electrically connected to the plurality of first wirings, The pixel circuit a plurality of second wirings disposed on the other surface side of the substrate and electrically connected to each of the plurality of contact plugs; and, The driving circuit Board A plurality of third wirings are arranged on one surface side or the other surface side and are electrically connected to the drive circuit. and having The second wiring and the third wiring are electrically connected in a state in which the other surface of the pixel circuit substrate faces one surface or the other surface of the drive circuit substrate, and The drive circuit board is provided in a region overlapping with the display region in a plan view. 、 the pixel circuit substrate includes a plurality of scanning lines arranged in one direction intersecting within a plane of the display area, and a plurality of signal lines arranged in another direction intersecting within the plane of the display area, the pixel circuit is provided for each area partitioned by the plurality of scanning lines and the plurality of signal lines; the first wiring, the contact plug, and the second wiring are provided corresponding to the scanning lines and the signal lines, respectively; the third wirings are arranged in line in the one direction and the other direction for each line row corresponding to the scanning lines and the signal lines, respectively; the driving circuit is a scanning line driving circuit electrically connected to the plurality of scanning lines, the display panel includes a flexible printed wiring board provided with a signal line drive circuit electrically connected to the plurality of signal lines; The second wiring provided corresponding to the signal line is electrically connected to the flexible printed wiring board, The flexible printed circuit board is provided in a region that overlaps with the display region in a plan view. A display device characterized by: 。 Effect of the Invention

[0010] As described above, according to the present invention, a display device capable of reducing the peripheral area of ​​a display panel is provided. Place It is possible to provide. [Brief description of the drawings]

[0011] [Figure 1]1 is a circuit diagram showing a configuration of a display device according to a first embodiment of the present invention. [Diagram 2] FIG. 2 is a circuit diagram showing a configuration of a pixel circuit. [Diagram 3] 2 is a cross-sectional view showing a configuration of a main part of a display panel. FIG. [Figure 4] FIG. 2 is a cross-sectional view showing a configuration of a pixel circuit substrate. [Diagram 5] FIG. 2 is a perspective plan view showing a configuration of a pixel circuit substrate. [Figure 6] FIG. 13 is a perspective plan view showing another configuration of a pixel circuit substrate. [Figure 7] FIG. 13 is a perspective plan view showing another configuration of a pixel circuit substrate. [Figure 8] FIG. 13 is a perspective plan view showing another configuration of a pixel circuit substrate. [Figure 9] FIG. 2 is a plan view of the display panel as viewed from the rear surface side. [Figure 10] 1A to 1C are cross-sectional views illustrating a process for manufacturing a pixel circuit substrate. [Figure 11] 1A to 1C are cross-sectional views illustrating a process for manufacturing a pixel circuit substrate. [Figure 12] 1A to 1C are cross-sectional views illustrating a process for manufacturing a pixel circuit substrate. [Figure 13] 1A to 1C are cross-sectional views illustrating a process for manufacturing a pixel circuit substrate. [Figure 14] 1A to 1C are cross-sectional views illustrating a process for manufacturing a pixel circuit substrate. [Figure 15] 1A to 1C are cross-sectional views illustrating a process for manufacturing a pixel circuit substrate. [Figure 16] 1A to 1C are cross-sectional views illustrating a process for manufacturing a pixel circuit substrate. [Figure 17] 1A to 1C are cross-sectional views illustrating a process for manufacturing a pixel circuit substrate. [Figure 18] 10 is a cross-sectional view showing a configuration of a main part of a display panel included in a display device according to a second embodiment of the present invention. FIG. [Figure 19] FIG. 2 is a perspective plan view of the display panel as seen from the rear surface side. [Figure 20] FIG. 2 is a cross-sectional view showing a configuration of a drive circuit board. [Figure 21] FIG. 11 is a cross-sectional view of a main part showing another configuration of the display panel. [Figure 22] 10A to 10C are cross-sectional views for explaining a process for manufacturing a pixel circuit substrate and a driving circuit substrate by using the same mother substrate. [Figure 23] 10A to 10C are cross-sectional views illustrating a step of cutting the mother substrate into pixel circuit substrates and driving circuit substrates. [Figure 24] 11 is a cross-sectional view showing a configuration of a main part of a pixel circuit substrate in a display panel included in a display device according to a third embodiment of the present invention. FIG. [Diagram 25] FIG. 2 is a perspective plan view of the display panel as seen from the rear surface side. [Figure 26] FIG. 11 is a perspective plan view showing another configuration of the display panel. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0012] Hereinafter, an embodiment of the present invention will be described in detail with reference to the drawings. In addition, the drawings used in the following description may show characteristic parts in a schematic manner for the sake of convenience in order to make the characteristics easier to understand, and the number of components and dimensional ratios are not necessarily the same as in reality. Furthermore, the materials, dimensions, etc. exemplified in the following description are merely examples, and the present invention is not necessarily limited to them, and can be appropriately changed and implemented within the scope of the present invention.

[0013] (First embodiment) [Display device] First, as a first embodiment of the present invention, a display device 1A shown in, for example, FIGS. 1 to 9 will be described.

[0014] FIG. 1 is a circuit diagram showing the configuration of a display device 1A. FIG. 2 is a circuit diagram showing the configuration of a pixel circuit 3. FIG. 3 is a cross-sectional view of a main part showing the configuration of a display panel 2A. FIG. 4 is a cross-sectional view showing the configuration of a pixel circuit substrate 4. FIG. 5 is a perspective plan view showing the configuration of a pixel circuit substrate 4. FIG. 6 is a perspective plan view showing another configuration of a pixel circuit substrate 4. FIG. 7 is a perspective plan view showing another configuration of a pixel circuit substrate 4. FIG. 8 is a perspective plan view showing another configuration of a pixel circuit substrate 4. FIG. 9 is a plan view of the display panel 2A as viewed from the back surface side.

[0015] A display device 1A of this embodiment, as shown in FIGS. 1, 2 and 3, is an organic EL display device (organic EL display) in which the present invention is applied to perform color display using organic EL elements.

[0016] Specifically, this display device 1A includes a display panel 2A including a display area E in which a plurality of pixels P are arranged side by side within a plane. The display panel 2A includes a pixel circuit substrate 4 on which pixel circuits 3 that constitute the pixels P are provided.

[0017] The pixel circuit substrate 4 includes a plurality of scanning lines 5 arranged in one direction (vertical direction in FIGS. 1 and 2) intersecting within the plane of the display region E, and a plurality of signal lines 6 and a plurality of power supply lines 7 arranged in another direction (horizontal direction in FIGS. 1 and 2) intersecting within the plane of the display region E. The pixel circuit substrate 4 has a structure in which a pixel circuit 3 is provided for each area partitioned by the plurality of scanning lines 5, the plurality of signal lines 6, and the plurality of power supply lines 7.

[0018] Furthermore, the display panel 2A has a structure in which a plurality of pixels (called "sub-pixels") P corresponding to at least the three primary colors of red (R), green (G), and blue (B) are treated as one pixel unit (called a "pixel") Pu, and these pixel units Pu are periodically arranged within the plane.

[0019] In this embodiment, one pixel unit Pu is configured by periodically arranging a pixel P corresponding to red (R), a pixel P corresponding to green (G), and a pixel P corresponding to blue (B) in another direction. Also, in this embodiment, the pixel units Pu, each rectangular in plan view, are arranged in a matrix on the surface of a display region E, each rectangular in plan view, to configure a display panel 2A, each rectangular in plan view.

[0020] The pixel unit Pu is not necessarily limited to the above-mentioned configuration, and may be configured, for example, by four pixels P, including the pixel P corresponding to red (R), green (G), and blue (B) and a pixel P corresponding to white (W). The configuration is not limited to the above-mentioned configuration in which a plurality of pixels P corresponding to color display is arranged, and a configuration in which a plurality of pixels P corresponding to monochrome display is arranged is also possible. The display area E and the display panel 2A are not necessarily limited to the above-mentioned rectangular shapes, and their planar shapes can be changed as appropriate.

[0021] As shown in Figures 2 and 4, the pixel circuit 3 includes an organic EL element 8 which is a light-emitting element, a capacitor 9 which is a storage capacitance C, and two TFT elements (a selection TFT element 10 and a driving TFT element 11) which are switching elements.

[0022] The organic EL element 8 has a structure in which a pixel electrode 13, an organic functional layer 14, and a common electrode 15 are sequentially laminated on one surface (front surface in FIG. 4) of a substrate 12 constituting the pixel circuit board 4. That is, the organic EL element 8 has a structure in which the organic functional layer 14 is sandwiched between the pixel electrode 13, which is a positive electrode (+), and the common electrode 15, which is a negative electrode (-).

[0023] The substrate 12 is made of a flexible substrate such as a plastic substrate. In this embodiment, a film-like plastic substrate having a thickness of, for example, 10 μm or less is used as the substrate 12. The plastic substrate is made of a resin material such as polyimide.

[0024] The substrate 12 is not necessarily limited to the above-mentioned flexible substrate, but may be a rigid substrate such as a glass substrate.

[0025] The pixel electrodes 13 are provided corresponding to each of the multiple pixels P. The pixel electrodes 13 are made of a metal electrode material such as aluminum (Al). The pixel electrodes 13 are formed on an interlayer insulating layer 16 that covers a surface on which two TFT elements 10 and 11 (described later) are formed. The interlayer insulating layer 16 is made of a material such as silicon oxide (SiO x The pixel electrode 13 is electrically connected to the source electrode 11s side of the driving TFT element 11.

[0026] The organic functional layer 14 has a structure (called a "heterostructure") in which, for example, a hole injection layer, a hole transport layer, a light emitting layer, an electron transport layer, and an electron injection layer are laminated in this order. A bank layer 17 is provided on the interlayer insulating layer 16, except on the surface of the pixel electrode 13. The bank layer 17 is made of, for example, a coating type organic insulating material. The organic functional layer 14 is embedded inside the bank layer 17.

[0027] The common electrode 15 constitutes one solid electrode common to a plurality of pixels P. The common electrode 15 is made of a transparent electrode material such as indium tin oxide (ITO). The common electrode 15 is formed so as to cover the surface on which the organic functional layer 14 and the bank layer 17 are formed. In addition, a protective layer 18 is formed on the common electrode 15 so as to cover the entire surface of the substrate 12. The protective layer 18 is made of, for example, a coating-type organic insulating material.

[0028] The common electrode 15 is electrically connected to a GND line 19. The GND line 19 is provided on a surface of a gate insulating layer 20 constituting two TFT elements 10 and 11 described later. The GND line 19 is electrically connected to the common electrode 15 via a contact plug 21a penetrating the interlayer insulating layer 16, a contact electrode 21b formed on the interlayer insulating layer 16, and a contact plug 21c penetrating the bank layer 17.

[0029] In the organic EL element 8, holes injected and transported from the pixel electrode 13 side through the hole injection layer and the hole transport layer, and electrons injected and transported from the common electrode side through the electron injection layer and the electron transport layer recombine in the light-emitting layer, thereby enabling the element to emit light.

[0030] The organic EL element 8 has a top emission structure in which light is extracted from one surface side of the substrate 12 (hereinafter, one surface of the substrate 12 is referred to as the "front surface" and the other surface of the substrate 12 is referred to as the "rear surface").

[0031] When a color display is performed using the organic EL element 8, a configuration is used in which an organic EL element that emits white light is combined with color filters corresponding to red (R), green (G), and blue (B). Alternatively, a configuration in which organic EL elements that emit red light, green light, and blue light are combined may be used.

[0032] The storage capacitance C is arranged such that one end of the capacitor 9 is electrically connected to the source electrode 10s of the selection TFT element 10 and the gate electrode 11g of the driving TFT element 11, and the other end of the capacitor 9 is electrically connected to the source electrode 11s of the driving TFT element 11.

[0033] The two TFT elements 10 and 11 are provided side by side on a substrate 12. The two TFT elements 10 and 11 are made of an oxide semiconductor, such as an oxide of indium (In)-tin (Sn)-zinc (Zn) (InSnZnO). The oxide semiconductor may be an oxide containing at least one metal element, such as In, gallium (Ga), Zn, Sn, or Al, or may be polycrystalline silicon, amorphous silicon, or an organic semiconductor. The gate insulating layer 20 is made of, for example, silicon oxide (SiO x ) are used.

[0034] The selection TFT element 10 is arranged with its gate electrode 10g electrically connected to the scanning line 5, its drain electrode 10d electrically connected to the signal line 6, and its source electrode 10s electrically connected to the gate electrode 11g of the driving TFT element 11 and one end of the storage capacitance C (capacitor 9).

[0035] The driving TFT element 11 is provided with a gate electrode 10g electrically connected to the source electrode 10s of the selection TFT element 10 and the storage capacitance C (one end side of the capacitor 9), a drain electrode 11d electrically connected to the power line 7, and a source electrode 11s electrically connected to the pixel electrode 13 and the other end side of the storage capacitance C (capacitor 9).

[0036] In the display panel 2A, the switching operation of the selection TFT element 10 causes the potential (image data) of the signal line 6 to be held in the storage capacitor C via the selection TFT element 10. Furthermore, a drive current flows from the power line 7 to the organic EL element 8 via the drive TFT element 11 in accordance with the potential of the storage capacitor C. This makes it possible to cause the organic EL element 8 to emit light (light up).

[0037] As shown in Figures 3, 4 and 5, the pixel circuit substrate 4 of this embodiment has a plurality of first wirings 31 arranged on the front side of the substrate 12, a plurality of contact plugs 32 arranged in the thickness direction of the substrate 12, a plurality of second wirings 33 arranged on the rear side of the substrate 12, and a plurality of connection portions 34 arranged on the rear side of the substrate 12.

[0038] The multiple first wirings 31 are electrically connected to each of the multiple pixel circuits 3. The multiple contact plugs 32 are electrically connected to each of the multiple first wirings 31. The multiple second wirings 33 are electrically connected to each of the multiple contact plugs 32. That is, the first wirings 31 and the second wirings 33 are electrically connected via the contact plugs 32.

[0039] The first wiring 31 and the second wiring 33 are formed in a linear pattern using a conductive material such as copper, aluminum, molybdenum, chromium, etc. The contact plug 32 is formed by embedding in a contact hole penetrating the substrate 12 using a conductive material such as copper, aluminum, molybdenum, chromium, etc.

[0040] The first wiring 31, the contact plug 32, and the second wiring 33 are provided corresponding to each of the multiple scanning lines 5. That is, each scanning line 5 is routed from the front surface side to the back surface side of the substrate 12 by the first wiring 31, the contact plug 32, and the second wiring 33.

[0041] The first wiring 31, the contact plug 32, and the second wiring 33 are provided corresponding to each of the multiple signal lines 6. That is, each signal line 6 is routed from the front surface side to the back surface side of the substrate 12 by the first wiring 31, the contact plug 32, and the second wiring 33.

[0042] The multiple connection portions 34 electrically connect each of the multiple second wirings 33 to each of the multiple terminals provided on one end side of a flexible printed circuit board (FPC) 35.

[0043] The connection portion 34 is formed by using a connection material such as an anisotropic conductive film (ACF) or anisotropic conductive paste (ACP) to cross between the multiple second wirings 33, and while maintaining insulation between each of the second wirings 33, the connection portion 34 is made conductive at positions where it overlaps with each of the second wirings 33, thereby electrically connecting each of the second wirings 33 to each terminal of the FPC 35 and bonding the FPC 35 to the pixel circuit board 4.

[0044] The multiple scanning lines 5 are electrically connected to an FPC 35 (hereinafter, referred to as "first flexible printed circuit board (FPC) 35A" as necessary) via multiple connection portions 34 (hereinafter, referred to as "first connection portions 34A" as necessary).

[0045] The first connection parts 34A are arranged in one direction (vertical direction in FIG. 5) for each line row corresponding to each of the plurality of scanning lines 5. The first FPC 35A is provided with a scanning line driving circuit (gate driver) 36 including, for example, a shift register and a level shifter. The plurality of scanning lines 5 are electrically connected to the gate driver 36 via the first FPC 35A. The gate driver 36 sequentially supplies scanning signals to the plurality of scanning lines 5, and switches the driving of the selection TFT elements 10 in response to the scanning signals.

[0046] The multiple signal lines 6 are electrically connected to an FPC 35 (hereinafter, referred to as a "second flexible printed circuit board (FPC) 35B" as necessary) via multiple connection portions 34 (hereinafter, referred to as "second connection portions 34B" as necessary).

[0047] The second connection parts 34B are arranged in the other direction (horizontal direction in FIG. 5) for each line row corresponding to each of the multiple signal lines 6. The second FPC 35B is provided with a signal line driving circuit (data driver) 37 including, for example, a shift register, a level shifter, a video line, an analog switch, etc. The multiple signal lines 6 are electrically connected to the data driver 37 via this second FPC 35B. The data driver 37 supplies image data to the multiple signal lines 6.

[0048] Within the area that overlaps with the display area E of the pixel circuit substrate 4 in a planar view, a plurality of contact plugs 32 (hereinafter, distinguished as "first contact plugs 32A" as necessary) are arranged in one direction (the vertical direction in Figure 5) for each line row corresponding to each of the plurality of scanning lines 5.

[0049] The first contact plugs 32A are located inside the first connection parts 34A in the region, and are electrically connected to one end of each of the second wirings 33 (hereinafter, distinguished as "first back surface wirings 33A" as necessary). On the other hand, the first connection parts 34A are located on one end side (right end side in FIG. 5) in the other direction (horizontal direction in FIG. 5) in the region, and are electrically connected to the other end of each of the first back surface wirings 33A.

[0050] In addition, within the region that overlaps with the display region E of the pixel circuit substrate 4 in a planar view, a plurality of contact plugs 32 (hereinafter, distinguished as "second contact plugs 32B" as necessary) are arranged side by side in another direction (the horizontal direction in Figure 5) for each line row corresponding to each of the plurality of signal lines 6.

[0051] The second contact plugs 32B are located inside the second connection parts 34B in the region, and are electrically connected to one end of each of the second wirings 33 (hereinafter, distinguished as "second back surface wirings 33B" as necessary). On the other hand, the second connection parts 34B are located at one end (upper end in FIG. 5) in one direction (vertical direction in FIG. 5) in the region, and are electrically connected to the other end of each of the second back surface wirings 33B.

[0052] Moreover, the first wiring 31, the contact plug 32, and the second wiring 33 are provided corresponding to each of the multiple power supply lines 7. That is, each power supply line 7 is routed from the front surface side to the back surface side of the substrate 12 by the first wiring 31, the contact plug 32, and the second wiring 33.

[0053] The multiple first wirings 31 provided corresponding to each of the multiple power supply lines 7 are electrically connected to a single common second wiring 33 (hereinafter, distinguished as a "third back surface wiring 33C" as necessary) via multiple contact plugs 32 (hereinafter, distinguished as a "third contact plug 32C" as necessary) provided corresponding to each of the multiple power supply lines 7.

[0054] A plurality of third contact plugs 32C are arranged in one direction (vertical direction in FIG. 5) in a region overlapping with the display region E of the pixel circuit substrate 4 in a plan view. The plurality of third contact plugs 32C are located on the other end side (left end side in FIG. 5) in the other direction (horizontal direction in FIG. 5) in the region, and are electrically connected to a third back surface wiring 33C extending in the one direction (vertical direction in FIG. 5).

[0055] Moreover, the first wiring 31, the contact plug 32, and the second wiring 33 are provided corresponding to the GND line 19. That is, the GND line 19 is routed from the front surface side to the back surface side of the substrate 12 by the first wiring 31, the contact plug 32, and the second wiring 33.

[0056] The first wiring 31 provided corresponding to the GND line 19 is electrically connected to a single common second wiring 33 (hereinafter, distinguished as the "fourth back surface wiring 33D" as necessary) via a plurality of contact plugs 32 (hereinafter, distinguished as the "fourth contact plugs 32D" as necessary) provided corresponding to the GND line 19.

[0057] A plurality of fourth contact plugs 32D are arranged in one direction (vertical direction in FIG. 5) in a region overlapping with the display region E of the pixel circuit substrate 4 in a plan view. The plurality of fourth contact plugs 32D are located on the other end side (left end side in FIG. 5) in the other direction (horizontal direction in FIG. 5) in the region, and are electrically connected to a fourth back surface wiring 33D extending in the one direction (vertical direction in FIG. 5).

[0058] The pixel circuit substrate 4 is provided with an interlayer insulating layer 38 that covers the back surface of the substrate 12. The first back surface wiring 33A and the third back surface wiring 33C are electrically connected to the first contact plug 32A and the third contact plug 32C that penetrate the substrate 12 and the interlayer insulating layer 38. On the other hand, the second back surface wiring 33B and the fourth back surface wiring 33D are electrically connected to the second contact plug 32B and the fourth contact plug 32D that penetrate the substrate 12.

[0059] As a result, a part of the first back surface wiring 33A and a part of the second back surface wiring 33B are arranged in a crossing state, and the third back surface wiring 33C and a part of the second back surface wiring 33B are arranged in a crossing state.

[0060] In the display device 1A of the embodiment having the above-mentioned configuration, a plurality of connection parts 34 (first connection part 34A and second connection part 34B) are provided in a region overlapping with the display region E of the display panel 2A in a planar view. This makes it possible to connect the first FPC 35A and the second FPC 35B via the plurality of connection parts 34 in the region overlapping with the display region E of the display panel 2A in a planar view, and to arrange the gate driver 36 and the data driver 37 provided on the first FPC 35A and the second FPC 35B on the back side of the pixel circuit substrate 4.

[0061] Moreover, the area that overlaps with the display area E of the pixel circuit substrate 4 in a plan view almost coincides with the outline of the substrate 12. This eliminates the need to provide a peripheral area for arranging the gate driver 36 and the data driver 37 outside the display area E, making it possible to reduce the peripheral area of ​​the display panel 2A. Therefore, when multiple display panels 2A are arranged in a plane as a multi-display and displayed as a single screen, it is possible to achieve a seamless (unnoticeable) screen display.

[0062] In the display device 1A, the pixel circuit substrate 4 has a configuration as shown in FIG. 5, but is not necessarily limited to such a configuration. For example, the display device 1A may have a configuration as shown in FIGS. 6 to 8.

[0063] Specifically, in the pixel circuit substrate 4 shown in FIG. 6, within a region overlapping with the display region E in a planar view, multiple first contact plugs 32A are located at one end side (left end side in FIG. 6) of the other direction (horizontal direction in FIG. 6), arranged in a row in one direction (vertical direction in FIG. 6), and electrically connected to one end side of each first back surface wiring 33A.

[0064] On the other hand, the multiple first connection portions 34A are located inside the multiple first contact plugs 32A in the region, arranged side by side in one direction (the vertical direction in FIG. 6), and are electrically connected to the other end side of each first back surface wiring 33A.

[0065] In addition, in the region overlapping with the display region E in a planar view, multiple second contact plugs 32B are located at one end side (top end side in FIG. 6) of one direction (vertical direction in FIG. 6) and arranged in a row in the other direction (horizontal direction in FIG. 6) and are electrically connected to one end side of each second back surface wiring 33B.

[0066] On the other hand, the multiple second connection portions 34B are located more inward than the multiple second contact plugs 32B in the region, are arranged side by side in the other direction (the horizontal direction in FIG. 6), and are electrically connected to the other end side of each second back surface wiring 33B.

[0067] In this manner, in the pixel circuit substrate 4 shown in FIG. 6, the first contact plug 32A and the second contact plug 32B can be arranged side by side at the end of the region overlapping with the display region E in a plan view.

[0068] On the other hand, in the pixel circuit substrate 4 shown in Figure 7, within the region overlapping with the display region E in a planar view, multiple first contact plugs 32A are located at the center of the other direction (the horizontal direction in Figure 7), arranged in a row in one direction (the vertical direction in Figure 7), and are electrically connected to one end side of each first back surface wiring 33A.

[0069] On the other hand, the multiple first connection portions 34A are located outside the multiple first contact plugs 32A in the region, are arranged side by side in one direction (the vertical direction in FIG. 7), and are electrically connected to the other end side of each first back surface wiring 33A.

[0070] In addition, in the region overlapping with the display region E in a planar view, multiple second contact plugs 32B are positioned at the center in one direction (the vertical direction in Figure 7) and arranged side by side in the other direction (the horizontal direction in Figure 7), and are electrically connected to one end side of each second back surface wiring 33B.

[0071] On the other hand, the multiple second connection portions 34B are located outside the multiple second contact plugs 32B in the region, are arranged side by side in the other direction (the horizontal direction in FIG. 7), and are electrically connected to the other end side of each second back surface wiring 33B.

[0072] In this manner, in the pixel circuit substrate 4 shown in FIG. 7, the first contact plug 32A and the second contact plug 32B can be arranged side by side in the center of the region overlapping with the display region E in a plan view.

[0073] On the other hand, in the pixel circuit substrate 4 shown in FIG. 8, within a region overlapping with the display region E in a planar view, multiple first contact plugs 32A are arranged in a row in one diagonal direction (diagonal right direction in FIG. 8) and are electrically connected to one end side of each first back surface wiring 33A.

[0074] On the other hand, the multiple first connection portions 34A are located outside the multiple first contact plugs 32A in the region, arranged in a line in one diagonal direction (diagonal right direction in FIG. 8), and are electrically connected to the other end side of each first back surface wiring 33A.

[0075] In addition, in the region overlapping with the display region E in a planar view, multiple second contact plugs 32B are arranged in the other diagonal direction (the left diagonal direction in Figure 8) and are electrically connected to one end side of each second back surface wiring 33B.

[0076] On the other hand, the multiple second connection portions 34B are located outside the multiple second contact plugs 32B in the region, are arranged side by side in the other diagonal direction (the left diagonal direction in Figure 8), and are electrically connected to the other end side of each second back surface wiring 33B.

[0077] In this manner, in the pixel circuit substrate 4 shown in FIG. 8, the first contact plug 32A and the second contact plug 32B can be arranged diagonally (obliquely) in a region that overlaps with the display region E in a planar view.

[0078] In addition, in the above-mentioned display device 1A, as shown in FIG. 9, on the rear side of the display panel 2A, a plurality of first FPCs 35A each having a gate driver 36 for each of the plurality of scanning lines 5 may be arranged side by side in one direction (the vertical direction in FIG. 9), and a plurality of second FPCs 35B each having a data driver 37 for each of the plurality of signal lines 6 may be arranged side by side in the other direction (the horizontal direction in FIG. 9).

[0079] [Display Device Manufacturing Method] Next, a method for manufacturing the display device 1A will be described with reference to FIGS. 10 to 17 are cross-sectional views illustrating the steps of manufacturing the pixel circuit substrate 4. As shown in FIG.

[0080] The method for manufacturing the display device 1A of this embodiment includes a step of fabricating the pixel circuit substrate 4 when manufacturing the display panel 2A.

[0081] In the process of fabricating the pixel circuit substrate 4, first, a substrate 12 formed in a film shape on the surface of a first glass substrate 101 is prepared as shown in Fig. 10. Then, on one surface (front surface) of the substrate 12, the first wiring 31 including the above-mentioned scanning line 5, signal line 6, power supply line 7, and GND line 19, contact plug 21a, contact electrode 21b, contact plug 21c, organic EL element 8 (pixel electrode 13, organic functional layer 14, and common electrode 15) constituting the pixel circuit 3, capacitor 9, selection TFT element 10 including a gate insulating layer 20, and driving TFT element 11, interlayer insulating layer 16, bank layer 17, and protective layer 18 are formed.

[0082] In addition, these forming steps can use a conventionally known film forming process, photolithography process, or the like, and there is no particular limitation on the forming method.

[0083] Next, as shown in FIG. 11, a second glass substrate 103 is attached to the top layer of the substrate 12 via an adhesive layer 102.

[0084] Next, as shown in Fig. 12, laser light L is irradiated from the first glass substrate 101 side toward substrate 12. At this time, the laser light L passes through the first glass substrate 101 and is absorbed by the substrate 12, whereby a part of the plastic film near the interface with the first glass substrate 101 is evaporated by heat. This makes it possible to peel off the first glass substrate 101 from the other surface (rear surface) of the substrate 12, as shown in Fig. 13.

[0085] Next, as shown in FIG. 14, contact holes 104 penetrating the substrate 12 and the gate insulating layer 20 are formed at positions of the substrate 12 where the second contact plugs 32B and the fourth contact plugs 32D are to be formed.

[0086] Next, as shown in FIG. 15, a second contact plug 32B and a fourth contact plug 32D are formed by embedding them in the contact holes 104, and then a second back surface wiring 33B and a fourth back surface wiring 33D are patterned on the back surface of the substrate 12.

[0087] Next, as shown in FIG. 16, an interlayer insulating layer 38 is formed on the rear surface of the substrate 12, and then contact holes 105 penetrating the substrate 12 and the interlayer insulating layer 38 are formed at the positions where the first contact plug 32A and the third contact plug 32C of the substrate 12 are to be formed.

[0088] Next, as shown in FIG. 17, a first contact plug 32A and a third contact plug 32C are embedded in the contact hole 105, and then a first back surface wiring 33A and a third back surface wiring 33C are patterned on the back surface of the substrate 12.

[0089] Next, after forming the ACP that becomes the first connection portion 34A and the second connection portion 34B, the first FPC 35A and the second FPC 35B are connected via the first connection portion 34A and the second connection portion 34B. Finally, the second glass substrate 103 is removed together with the adhesive layer 102. This makes it possible to manufacture the display panel 2A.

[0090] In the manufacturing method of the display device 1A of the present embodiment, by providing a plurality of connection parts 34 (first connection part 34A and second connection part 34B) in an area overlapping with the display area E of the above-mentioned display panel 2A in a planar view, it is possible to arrange the gate driver 36 and the data driver 37 provided on the first FPC 35A and the second FPC 35B on the back surface side of the pixel circuit substrate 4. This makes it unnecessary to provide a peripheral area for arranging the gate driver 36 and the data driver 37 outside the display area E, and it is possible to manufacture a display panel 2A with a reduced peripheral area.

[0091] Furthermore, by using a film-like plastic substrate having a thickness of 10 μm or less as the substrate 12, it is possible to reduce the size (opening diameter) of the above-mentioned contact holes 104 and 105. This makes it possible to reduce the size of the pixels P and achieve high definition of the display panel 2A.

[0092] Second embodiment [Display device] Next, as a second embodiment of the present invention, a display device 1B shown in, for example, FIGS. 18 to 21 will be described.

[0093] Fig. 18 is a cross-sectional view of a main part showing the configuration of a display panel 2B included in the display device 1B. Fig. 19 is a see-through plan view of the display panel 2B seen from the back side. Fig. 20 is a cross-sectional view showing the configuration of a drive circuit board 42. Fig. 21 is a cross-sectional view of a main part showing another configuration of the display panel 2B. In the following explanation, the same parts as those in the display device 1A will not be explained and will be denoted by the same reference numerals in the drawings.

[0094] 18 and 19, the display device 1B of this embodiment includes a display panel 2B including a display area E in which a plurality of pixels P are arranged side by side within a plane. The display panel 2B includes a pixel circuit board 41 on which pixel circuits 3 constituting the pixels P are provided, a drive circuit board 42 on which a gate driver 36 is provided, and an FPC 43 on which a data driver 37 is provided.

[0095] The pixel circuit substrate 41 has basically the same configuration as the pixel circuit substrate 4. That is, the pixel circuit substrate 41 has a configuration in which, on one surface (front surface) of the substrate 12, the scanning lines 5, the signal lines 6, the power supply lines 7, the GND lines 19, the contact plugs 21a, the contact electrodes 21b, the contact plugs 21c, the organic EL elements 8 (pixel electrodes 13, organic functional layers 14, and common electrodes 15) constituting the pixel circuits 3, the capacitors 9, the selection TFT elements 10 including the gate insulating layer 20, and the driving TFT elements 11, the interlayer insulating layer 16, the bank layer 17, and the protective layer 18 are provided.

[0096] In addition, the pixel circuit substrate 41 has a configuration in which the first contact plug 32A and the second contact plug 32B are arranged side by side at the ends of a region that overlaps with the display region E in a planar view, like the pixel circuit substrate 4 shown in FIG. 6 above.

[0097] As shown in FIGS. 18 and 20, the drive circuit board 42 has a configuration in which a plurality of gate driver TFT elements 45 that constitute the gate driver 36 are arranged side by side on one surface (the front surface in this embodiment) of a substrate 44.

[0098] The substrate 44 is the same as the substrate 12. The gate driver TFT element 45 is the same as the two TFT elements 10 and 11. In addition, on the front surface side of the substrate 44, a gate insulating layer 20 and an interlayer insulating layer 16 are laminated in this order.

[0099] 18 to 20, the drive circuit board 42 of this embodiment has a plurality of third wirings 46 arranged on the front side of the board 44. The third wirings 46 are the same as the first wirings 31 and the second wirings 33.

[0100] A plurality of third wirings 46 are arranged in one direction (the vertical direction in FIG. 19) on the surface of the drive circuit board 42 for each line row corresponding to each of the plurality of scanning lines 5. The plurality of third wirings 46 are electrically connected to the gate driver 36 (a plurality of gate driver TFT elements 45).

[0101] The display panel 2B has a structure in which the first rear surface wiring 33A and the third wiring 46 are electrically connected via the first connection portion 34A with the rear surface of the pixel circuit substrate 41 facing the front surface of the drive circuit substrate 42. As a result, the multiple scanning lines 5 are electrically connected to the gate driver 36 (multiple gate driver TFT elements 45) of the drive circuit substrate 42.

[0102] The display panel 2B has a structure in which a plurality of second rear wirings 33B and the FPC 43 are connected via second connection portions 34B. As a result, the plurality of signal lines 6 are electrically connected to the data driver 37 via the FPC 43.

[0103] In the display device 1B of the embodiment having the above-mentioned configuration, the drive circuit board 42 and the FPC 43 are provided in a region overlapping with the display region E of the above-mentioned display panel 2B in a planar view. This makes it possible to arrange the gate driver 36 provided on the drive circuit board 42 and the data driver 37 provided on the FPC 43 on the back side of the pixel circuit board 41 in the region overlapping with the display region E of the display panel 2B in a planar view.

[0104] Moreover, the area of ​​the pixel circuit substrate 41 that overlaps with the display region E in a plan view almost coincides with the outline of the substrate 44. This eliminates the need to provide a peripheral area for arranging the gate driver 36 and the data driver 37 outside the display region E, making it possible to reduce the peripheral area of ​​the display panel 2B. Therefore, when a plurality of display panels 2B are arranged in a plane as a multi-display and displayed as a single screen, it is possible to perform a seamless (unnoticeable) screen display.

[0105] The display device 1B is not necessarily limited to the configuration of the display panel 2B as shown in FIG. 18, and may be configured as shown in FIG. 21, for example.

[0106] 21 has a plurality of third wirings 46 arranged on the other surface (rear surface) of a substrate 44, and a plurality of contact plugs 47 arranged in the thickness direction of the substrate 44. The contact plugs 47 are the same as the contact plugs 32 and are formed by being embedded in contact holes penetrating the substrate 44.

[0107] The multiple third wirings 46 are electrically connected to the multiple contact plugs 47. The multiple contact plugs 47 are electrically connected to the gate driver 36 (the multiple gate driver TFT elements 45). That is, the multiple third wirings 46 and the gate driver 36 (the multiple gate driver TFT elements 45) are electrically connected via the contact plugs 47.

[0108] As a result, the display panel 2B shown in Figure 21 has a structure in which the back surface of the pixel circuit substrate 41 and the back surface of the drive circuit substrate 42 are opposed to each other, and the first back surface wiring 33A and the third wiring 46 are electrically connected via the first connection portion 34A (not shown).

[0109] In this case, too, by providing a drive circuit board 42 within an area that overlaps with the display area E of the display panel 2B in a planar view, it is possible to arrange the gate driver 36 provided on this drive circuit board 42 on the back side of the pixel circuit board 41.

[0110] [Display Device Manufacturing Method] Next, a method for manufacturing the display device 1B will be described with reference to FIGS. 22 is a cross-sectional view for explaining the process of manufacturing the pixel circuit substrate 41 and the drive circuit substrate 42 using the same mother substrate 200. Fig. 23 is a cross-sectional view for explaining the process of cutting the mother substrate 200 into the pixel circuit substrate 41 and the drive circuit substrate 42. In the following explanation, steps similar to those in the manufacturing method of the display device 1A will be explained using the same reference numerals, although the drawings will be omitted.

[0111] In the method of manufacturing the display device 1A of this embodiment, when manufacturing the display panel 2, first, as shown in FIG. 22, a pixel circuit substrate 41 and a drive circuit substrate 42 are manufactured using the same mother substrate 200.

[0112] Specifically, a mother substrate 200 that will become the substrate 12 and the substrate 44 formed in a film shape on the surface of the first glass substrate 101 is prepared. Then, in the process of producing the pixel circuit substrate 41, the front surface side of the pixel circuit substrate 41 is formed on one surface (front surface) of the mother substrate 200 using a method similar to the process of producing the pixel circuit substrate 4 shown in FIG.

[0113] That is, the first wiring 31 including the above-mentioned scanning line 5, signal line 6, power supply line 7 and GND line 19, the contact plug 21a, the contact electrode 21b and the contact plug 21c, the organic EL element 8 (pixel electrode 13, organic functional layer 14 and common electrode 15) constituting the pixel circuit 3, the capacitor 9, the selection TFT element 10 including the gate insulation layer 20 and the driving TFT element 11, the interlayer insulation layer 16, the bank layer 17 and the protective layer 18 are formed.

[0114] On the other hand, in the process of producing the drive circuit substrate 42, a gate driver TFT element 45 is formed simultaneously with the selection TFT element 10 and the drive TFT element 11 including the gate insulating layer 20 of the pixel circuit substrate 41. A third wiring 46 is formed simultaneously with the first wiring 31. An interlayer insulating layer 16 is formed to cover the selection TFT element 10, the drive TFT element 11, and the gate driver TFT element 45. In this way, the front surface side of the drive circuit substrate 42 is formed on the front surface of the mother substrate 200.

[0115] Next, a second glass substrate 103 is attached to the top layer of the mother substrate 200 via an adhesive layer 102 .

[0116] Next, laser light L is irradiated from the first glass substrate 101 side toward the mother substrate 200. At this time, the laser light L passes through the first glass substrate 101 and is absorbed by the mother substrate 200, and a part of the plastic film near the interface with the first glass substrate 101 is evaporated by heat. This makes it possible to peel off the first glass substrate 101 from the other surface (rear surface) of the mother substrate 200.

[0117] Next, contact holes 104 penetrating the substrate 12 and the gate insulating layer 20 are formed at positions of the mother substrate 200 where the second contact plugs 32B and the fourth contact plugs 32D are to be formed.

[0118] Next, the second contact plug 32B and the fourth contact plug 32D are formed by embedding them in the contact holes 104, and then the second back surface wiring 33B and the fourth back surface wiring 33D are patterned on the back surface of the mother substrate 200.

[0119] Next, after forming an interlayer insulating layer 38 on the rear surface of the mother substrate 200, contact holes 105 penetrating the mother substrate 200 and the interlayer insulating layer 38 are formed at the positions of the mother substrate 200 where the first contact plugs 32A and the third contact plugs 32C are to be formed.

[0120] Next, the first contact plug 32A and the third contact plug 32C are embedded in the contact hole 105, and then the first back surface wiring 33A and the third back surface wiring 33C are patterned on the back surface of the mother substrate 200.

[0121] Next, as shown in FIG. 23, the second glass substrate 103 is removed together with the adhesive layer 102 from the mother substrate 200, and then the mother substrate 200 is cut into the pixel circuit substrate 41 and the drive circuit substrate 42.

[0122] Next, after forming the ACP that becomes the first connection portion 34A and the second connection portion 34B, the first back surface wiring 33A and the third wiring 46 are electrically connected via the first connection portion 34A, and the second back surface wiring 33B and the FPC 43 are electrically connected via the second connection portion 34B, with the back surface of the pixel circuit substrate 41 and the front surface of the drive circuit substrate 42 facing each other. This makes it possible to manufacture the display panel 2B.

[0123] In the manufacturing method of the display device 1B of the present embodiment, by providing the drive circuit board 42 and the FPC 43 in an area overlapping with the display area E of the above-mentioned display panel 2B in a planar view, it is possible to arrange the gate driver 36 provided on the drive circuit board 42 and the data driver 37 provided on the FPC 43 on the back side of the pixel circuit board 41. This makes it unnecessary to provide a peripheral area for arranging the gate driver 36 and the data driver 37 outside the display area E, and it is possible to manufacture a display panel 2B with a reduced peripheral area.

[0124] In addition, in the manufacturing method of the display device 1B of the present embodiment, it is possible to simultaneously manufacture the pixel circuit substrate 41 and the drive circuit substrate 42 using the above-mentioned mother substrate 200. This makes it possible to reduce the manufacturing cost of the display panel 2B.

[0125] Furthermore, by using a film-like plastic substrate having a thickness of 10 μm or less as the mother substrate 200, it is possible to reduce the size (opening diameter) of the above-mentioned contact holes 104, 105. This makes it possible to reduce the size of the pixels P and achieve high definition of the display panel 2A.

[0126] In this embodiment, the pixel circuit substrate 41 and the drive circuit substrate 42 are simultaneously manufactured using the mother substrate 200. However, it is also possible to manufacture multiple pixel circuit substrates 41 and drive circuit substrates 42 at the same time using different mother substrates.

[0127] (Third embodiment) [Display device] Next, as a third embodiment of the present invention, a display device 1C shown in, for example, FIGS. 24 to 26 will be described.

[0128] Fig. 24 is a cross-sectional view of a main part showing the configuration of a pixel circuit substrate 51 of a display panel 2C included in a display device 1C. Fig. 25 is a perspective plan view of the display panel 2C seen from the back side. Fig. 26 is a perspective cross-sectional view showing another configuration of a display panel 2B. In the following explanation, the same parts as those in the display device 1A will not be described and will be denoted by the same reference numerals in the drawings.

[0129] 24 and 25, a display device 1C of this embodiment includes a display panel 2C including a display area E in which a plurality of pixels P are arranged side by side within a plane. The display panel 2C has a pixel circuit substrate 51 on which pixel circuits 3 constituting the pixels P are provided.

[0130] The pixel circuit substrate 51 has basically the same configuration as the pixel circuit substrate 4. That is, the pixel circuit substrate 41 has a configuration in which, on one surface (front surface) of the substrate 12, the scanning lines 5, the signal lines 6, the power supply lines 7, the GND lines 19, the contact plugs 21a, the contact electrodes 21b, the contact plugs 21c, the organic EL elements 8 (pixel electrodes 13, organic functional layers 14, and common electrodes 15) constituting the pixel circuits 3, the capacitors 9, the selection TFT elements 10 including the gate insulating layer 20, and the driving TFT elements 11, the interlayer insulating layer 16, the bank layer 17, and the protective layer 18 are provided.

[0131] In the pixel circuit substrate 51 of this embodiment, the multiple scanning lines 5 have multiple first wirings 52 arranged on the front side of the substrate 12, multiple first contact plugs 53 arranged in the thickness direction of the substrate 12, and multiple second wirings 54 arranged on the rear side of the substrate 12.

[0132] Among these, the first wiring 52 corresponds to the first wiring 31 corresponding to the scanning line 5. The first contact plug 53 corresponds to the first contact plug 32A. The second wiring 54 corresponds to the first back surface wiring 33A.

[0133] On the other hand, the multiple signal lines 6 have multiple third wirings 55 arranged on the front side of the substrate 12, multiple second contact plugs 56 arranged in the thickness direction of the substrate 12, and multiple fourth wirings 57 arranged on the back side of the substrate 12.

[0134] Among these, the third wiring 55 corresponds to the first wiring 31 corresponding to the signal line 6. The second contact plug 56 corresponds to the second contact plug 32B. The fourth wiring 57 corresponds to the second back surface wiring 33B.

[0135] The multiple first contact plugs 53 and the multiple second contact plugs 56 are arranged side by side in one direction (vertical direction in Figure 25) and another direction (horizontal direction in Figure 25) within a region that overlaps with the display region E in a planar view so that the second wiring 54 and the fourth wiring 57 do not intersect.

[0136] Specifically, the multiple first contact plugs 53 are located at one and the other horizontal ends within a region that overlaps with the display region E in a planar view, and are arranged side by side on one side (the upper side in Figure 25) and the other side (the lower side in Figure 25) in the vertical direction, sandwiching the vertical center.

[0137] On the other hand, the multiple second contact plugs 56 are located at one and the other vertical ends within the region that overlaps with the display region E in a planar view, and are arranged side by side on one side (left side in Figure 25) and the other side (right side in Figure 25) of the horizontal center.

[0138] As a result, the multiple second wirings 54 (first back surface wirings 33A) and the multiple fourth wirings 57 (second back surface wirings 33B) are arranged without intersecting each other on the back surface of the substrate 12 from which the interlayer insulating layer 38 is omitted. Similarly, the third back surface wiring 33C and the fourth back surface wiring 33D are arranged on the back surface of the substrate 12 from which the interlayer insulating layer 38 is omitted. That is, the first to fourth back surface wirings 33A to 33D are arranged in the same plane in the thickness direction of the pixel circuit substrate 51.

[0139] As a result, in the display panel 2C of this embodiment, the overall length of the scanning lines 5 and the signal lines 6 can be made shorter than those in the display panels 2A and 2B.

[0140] The display panel 2C of the present embodiment can be configured such that the pixel circuit substrate 4 of the display panels 2A and 2B is replaced with a pixel circuit substrate 51. When the pixel circuit substrate 4 of the display panel 2B is replaced with a pixel circuit substrate 51 in the display panel 2C, the third wiring 46 provided on the drive circuit substrate 42 is referred to as a “fifth wiring” to be distinguished from the third wiring 55.

[0141] This allows the display device 1C of this embodiment to reduce the peripheral area of ​​the display panel 2C. Also, when multiple display panels 2C are arranged in a plane as a multi-display to display one screen, it is possible to perform a seamless (unnoticeable) screen display.

[0142] Furthermore, in the display device 1C of this embodiment, by shortening the overall length of the scanning lines 5 and the signal lines 6, it is possible to suppress signal delays caused by the high-speed response of each pixel P.

[0143] In addition, in the above-mentioned display device 1C, the configuration of the pixel circuit substrate 51 as shown in FIG. 25 is exemplified, but the present invention is not necessarily limited to such a configuration, and it is also possible to use, for example, a configuration as shown in FIG. 26.

[0144] 26, the first contact plugs 53 are arranged side by side in the vertical direction, positioned at the center in the horizontal direction in the region overlapping with the display region E in a plan view. On the other hand, the second contact plugs 56 are arranged side by side in the horizontal direction, positioned at the center in the vertical direction in the region overlapping with the display region E in a plan view.

[0145] In this case too, it is possible to shorten the overall length of the scanning lines 5 and the signal lines 6 while arranging the multiple second wirings 54 (first back surface wirings 33A) and the multiple fourth wirings 57 (second back surface wirings 33B) on the back surface of the substrate 12 without intersecting with each other.

[0146] In addition, in the pixel circuit substrate 51, in a region overlapping with the display region E in a planar view, a configuration may be adopted in which a plurality of first contact plugs 53 are arranged in a row in one diagonal direction (diagonal direction) and a plurality of second contact plugs 56 are arranged in a row in the other diagonal direction (diagonal direction).

[0147] In this case too, it is possible to shorten the overall length of the scanning lines 5 and the signal lines 6 while arranging the multiple second wirings 54 (first back surface wirings 33A) and the multiple fourth wirings 57 (second back surface wirings 33B) on the back surface of the substrate 12 without intersecting with each other.

[0148] The present invention is not necessarily limited to the above-described embodiment, and various modifications can be made without departing from the spirit of the present invention. For example, in the above embodiment, the present invention is applied to the above-mentioned organic EL display, but the light-emitting element is not necessarily limited to an organic EL element, and may be an LED element such as a micro LED, or a light-emitting element such as a quantum dot. The present invention can also be applied to a liquid crystal display or the like. [Explanation of symbols]

[0149] 1A, 1B, 1C... Display device 2A, 2B, 2C... Display panel 3... Pixel circuit 4... Pixel circuit board 5... Scanning line 6... Signal line 7... Power supply line 8... Organic EL element 9... Capacitor 10... Selection TFT element 11... Driving TFT element 12... Substrate 13... Pixel electrode 14... Organic functional layer 15... Common electrode 16... Interlayer insulating layer 17... Bank layer 18... Protective layer 19... GND line 20... Gate insulating layer 31... First wiring 32... Contact plug 32A... First contact plug 32B... Second contact plug 32C... Third contact plug 32D... Fourth contact plug 33... Second wiring 33A... First back wiring 33B... Second back wiring 33C... Third back wiring 33D... Fourth back wiring 34... Connection portion 34A...first connection portion 34B...second connection portion 35...flexible printed circuit board (FPC) 35A...first FPC 35B...second FPC 36...scanning line driving circuit (gate driver) 37...signal line driving circuit (data driver) 38...interlayer insulating layer 41...pixel circuit board 42...driving circuit board 43...FPC 44...substrate 45...TFT element for gate driver 46...third wiring (fifth wiring) 47...contact plug 51...pixel circuit board 52...first wiring 53...first contact plug 54...second wiring 55...third wiring 56...second contact plug 57...fourth wiring 200...mother substrate C...storage capacitance P...pixel Pu...pixel unit E...display area

Claims

[Claim 1] A display panel including a display area in which a plurality of pixels are arranged in a plane, The display panel includes a pixel circuit substrate on which pixel circuits constituting the pixels are provided; a drive circuit board provided with a drive circuit for driving the pixel circuit; a plurality of first wirings arranged on one surface side of the pixel circuit substrate and electrically connected to each of the plurality of pixel circuits; a plurality of contact plugs arranged in a thickness direction of the pixel circuit substrate and electrically connected to the plurality of first wirings, a plurality of second wirings arranged on the other surface side of the pixel circuit substrate and electrically connected to each of the plurality of contact plugs; a plurality of third wirings arranged on one surface side or the other surface side of the drive circuit board and electrically connected to the drive circuit; The second wiring and the third wiring are electrically connected in a state in which the other surface of the pixel circuit substrate faces one surface or the other surface of the drive circuit substrate, and the drive circuit board is provided in a region overlapping with the display region in a plan view, the pixel circuit substrate includes a plurality of scanning lines arranged in one direction intersecting within a plane of the display area, and a plurality of signal lines arranged in another direction intersecting within the plane of the display area, the pixel circuit is provided for each area partitioned by the plurality of scanning lines and the plurality of signal lines; the first wiring, the contact plug, and the second wiring are provided corresponding to the scanning lines and the signal lines, respectively; the third wirings are arranged in line in each of the first direction and the second direction for each of the scanning lines and the signal lines; the driving circuit is a scanning line driving circuit electrically connected to the plurality of scanning lines, the display panel includes a flexible printed wiring board provided with a signal line drive circuit electrically connected to the plurality of signal lines; The second wiring provided corresponding to the signal line is electrically connected to the flexible printed wiring board, A display device, comprising: a flexible printed wiring board provided in a region that overlaps with the display region in a plan view.

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