Semiconductor Device

Abstract

To provide a semiconductor device capable of enhancing heat dissipation characteristics.SOLUTION: A first member having a first face includes a plurality of circuit blocks disposed in an interior region of the first face when the first face is viewed in plan view. A second member is joined to the first face of the first member in plane contact. The second member includes a plurality of first transistors that are connected in parallel with each other to form a first amplifier circuit. A conductor projection protrudes from the second member on a side opposite to the side of the first member. The plurality of first transistors are arranged in an area that does not overlap any of the plurality of circuit blocks of the first member in plan view.SELECTED DRAWING: Figure 5

Description

[Technical field]

[0001] The present invention relates to a semiconductor device. [Background technology]

[0002] RF front-end modules that integrate the transmission and reception functions of high-frequency signals are built into electronic devices used in mobile communications, satellite communications, etc. RF front-end modules include a monolithic microwave integrated circuit (MMIC) with high-frequency amplification functions, a control IC that controls the high-frequency amplification circuit, a switch IC, a duplexer, etc.

[0003] A high-frequency module that is miniaturized by stacking a control IC on an MMIC is disclosed in the following Patent Document 1. The high-frequency module disclosed in Patent Document 1 includes an MMIC mounted on a module substrate and a control IC stacked on top of the MMIC. Electrodes of the MMIC, electrodes of the control IC, and electrodes on the module substrate are electrically connected by wire bonding. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] US Patent Application Publication No. 2015 / 0303971 Summary of the Invention [Problem to be solved by the invention]

[0005] For example, heterojunction bipolar transistors (HBTs) are used in high-frequency amplifier circuits. HBTs generate heat due to collector loss during operation. The increase in temperature of the HBT due to heat generation acts to further increase the collector current. When this positive feedback condition is met, the HBT goes into thermal runaway. To prevent thermal runaway, an upper limit is set on the output power of the HBT.

[0006] In order to increase the output power of a high-frequency amplifier circuit, it is desirable to improve the heat dissipation characteristics of semiconductor devices including HBTs, etc. With the high-frequency module disclosed in Patent Document 1, it is difficult to satisfy the recent demand for high-frequency amplifier circuits with high output power.

[0007] An object of the present invention is to provide a semiconductor device capable of improving heat dissipation characteristics. [Means for solving the problem]

[0008] According to one aspect of the present invention, a first member having a first surface, the first surface being viewed in plan, the first member including a plurality of circuit blocks disposed in an internal region of the first surface; a second member including a plurality of first transistors joined in surface contact with the first surface of the first member and connected in parallel to each other to form a first amplifier circuit; a conductor projection protruding from the second member toward a side opposite to the first member; Equipped with The first transistors are arranged in a region that does not overlap any of the circuit blocks of the first member in a plan view. and overlapping the first member. A semiconductor device is provided. Effect of the Invention

[0009] The heat generated in the first transistor is conducted through two heat transfer paths: one from the first transistor to the first member, and the other via the conductor protrusion, thereby improving the heat dissipation characteristics of the first transistor. [Brief description of the drawings]

[0010] [Figure 1] FIG. 1 is a block diagram of a high-frequency module including a semiconductor device according to a first embodiment. [Diagram 2] FIG. 2 is a diagram showing the positional relationship of circuit components of the high-frequency module according to the first preferred embodiment in a plan view. [Diagram 3]FIG. 3 is a schematic cross-sectional view of the semiconductor device according to the first embodiment. [Figure 4] FIG. 4A is an equivalent circuit diagram of each of a plurality of cells constituting a first amplifier circuit of a semiconductor device according to a first embodiment, and FIG. 4B is a schematic cross-sectional view of one cell constituting the first amplifier circuit formed in a second member. [Diagram 5] FIG. 5A is a schematic diagram showing the in-plane arrangement of each circuit block when the first surface of the semiconductor device according to the first embodiment is viewed in a plane, and FIG. 5B is a diagram showing the arrangement, in a plane view, of multiple transistors constituting a first amplifier circuit. [Figure 6] 6A to 6F are cross-sectional views of a semiconductor device during its manufacturing process. [Figure 7] 7A to 7C are cross-sectional views of a semiconductor device during its manufacturing process, and FIG. 7D is a cross-sectional view of the completed semiconductor device. [Figure 8] FIG. 8 is a schematic diagram showing the in-plane arrangement of each circuit block of a semiconductor device according to the second embodiment. [Figure 9] FIG. 9 is a schematic diagram showing the in-plane arrangement of each circuit block of a semiconductor device according to a third embodiment. [Figure 10] FIG. 10 is a schematic diagram showing the in-plane arrangement of each circuit block of a semiconductor device according to a fourth embodiment. [Figure 11] FIG. 11 is a schematic diagram showing the in-plane arrangement of each circuit block of a semiconductor device according to a fifth embodiment. [Figure 12] FIG. 12 is a schematic diagram showing the in-plane arrangement of each circuit block of a semiconductor device according to a sixth embodiment. [Figure 13] FIG. 13 is a schematic diagram showing the in-plane arrangement of each circuit block of a semiconductor device according to the seventh embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0011] [First Example] A semiconductor device according to a first embodiment will be described with reference to Figures 1 to 7D. The semiconductor device according to the first embodiment described below is a high-frequency power amplifier.

[0012] 1 is a block diagram of a high-frequency module 20 including a semiconductor device according to a first embodiment. The high-frequency module 20 includes the semiconductor device 30 according to the first embodiment, an output matching circuit 76, a plurality of duplexers 70, an antenna switch 72, two receiving band selection switches 73, two low-noise amplifiers 71, a receiving output terminal selection switch 74, and a second control circuit 75. These circuit components are flip-chip mounted on a module substrate. The high-frequency module 20 has a function of transmitting and receiving signals in a frequency division duplex (FDD) system.

[0013] The semiconductor device 30 includes a first member 31 and a second member 32 joined to the first member 31. The first member 31 is provided with an input switch 43, a first control circuit 42, and a band selection switch 41. The second member 32 is provided with a two-stage high-frequency amplifier circuit 50 including a first amplifier circuit 51 and a second amplifier circuit 52, and a bias circuit 53. The second amplifier circuit 52 is the first stage amplifier circuit, and the first amplifier circuit 51 is the last stage amplifier circuit. In FIG. 1, the circuit blocks provided in the first member 31 are relatively lightly hatched, and the circuit blocks provided in the second member 32 are relatively darkly hatched. The bias circuit 53 supplies a bias current to the first amplifier circuit 51 and the second amplifier circuit 52 in response to a control signal from the first control circuit 42.

[0014] The two input contacts of the input switch 43 are connected to radio frequency signal input terminals IN1 and IN2 provided on the module substrate. Radio frequency signals are input from the two radio frequency signal input terminals IN1 and IN2. The input switch 43 selects one of the two input contacts, and inputs the radio frequency signal input to the selected contact to the radio frequency amplifier circuit 50.

[0015] The high frequency signal amplified by the high frequency amplifier circuit 50 is input to one input contact of the band selection switch 41 through the output matching circuit 76. The band selection switch 41 selects one contact from among a plurality of output contacts, and outputs the high frequency signal amplified by the high frequency amplifier circuit 50 from the selected output contact.

[0016] Two of the multiple output contacts of the band selection switch 41 are connected to auxiliary output terminals PAAUX1 and PAAUX2 provided on the module board. The other six contacts are connected to the transmission input ports of the multiple duplexers 70 provided for each band. The band selection switch 41 has the function of selecting one duplexer 70 from the multiple duplexers 70 provided for each band.

[0017] The antenna switch 72 has a plurality of contacts on the circuit side and two contacts on the antenna side. Two of the plurality of contacts on the circuit side of the antenna switch 72 are connected to transmission signal input terminals TRX1 and TRX2, respectively. The other six contacts on the circuit side are connected to input / output ports of the plurality of duplexers 70, respectively. The two contacts on the antenna side are connected to antenna terminals ANT1 and ANT2, respectively. An antenna is connected to each of the antenna terminals ANT1 and ANT2.

[0018] The antenna switch 72 connects the two antenna-side contacts to two contacts selected from the multiple circuit-side contacts. When communication is performed using one band, the antenna switch 72 connects one circuit-side contact to one antenna-side contact. The high-frequency signal amplified by the high-frequency amplifier circuit 50 and passed through the duplexer 70 for the corresponding band is transmitted from the antenna connected to the selected antenna-side contact.

[0019] Each of the two receive band selection switches 73 has four input contacts and one output contact. Three of the four input contacts of each of the two band selection switches 73 are connected to the receive output ports of the duplexer 70. The remaining one contact of each of the two band selection switches 73 is connected to the auxiliary input terminals LNAAUX1 and LNAAUX2, respectively.

[0020] The output contacts of the two receiving band selection switches 73 are respectively connected to the two low-noise amplifiers 71. The two receiving band selection switches 73 input the received signals that have passed through the duplexer 70 to the low-noise amplifiers 71.

[0021] The two circuit side contacts of the output terminal selection switch 74 are respectively connected to the output ports of the two low-noise amplifiers 71. The three terminal side contacts of the output terminal selection switch 74 are respectively connected to received signal output terminals LNAOUT1, LNAOUT2, and LNAOUT3. The received signal amplified by the low-noise amplifier 71 is output from the received signal output terminal selected by the output terminal selection switch 74.

[0022] Power supply voltages are applied to the first amplifier circuit 51 and the second amplifier circuit 52 from power supply terminals VCC1 and VCC2 provided on the module substrate, respectively.

[0023] The first control circuit 42 is connected to the power supply terminal VIO1, the control signal terminal SDATA1, and the clock terminal SCLK1. The first control circuit 42 controls the bias circuit 53, the input switch 43, and the band selection switch 41 based on a control signal provided to the control signal terminal SDATA1.

[0024] The second control circuit 75 is connected to the power supply terminal VIO2, the control signal terminal SDATA2, and the clock terminal SCLK2. The second control circuit 75 controls the low-noise amplifier 71, the receiving band selection switch 73, and the output terminal selection switch 74 based on a control signal provided to the control signal terminal SDATA2.

[0025] The module substrate is further provided with a power supply terminal VBAT and a drain voltage terminal VDD2. Power is supplied from the power supply terminal VBAT to the bias circuit of the high frequency amplifier circuit 50 and the first control circuit 42. A power supply voltage is applied to the low noise amplifier 71 from the drain voltage terminal VDD2.

[0026] 2 is a diagram showing the positional relationship in a plan view of circuit components of a high-frequency module 20 according to a first embodiment. A semiconductor device 30, a plurality of duplexers 70, a low-noise amplifier 71, an antenna switch 72, and a plurality of other surface-mount type passive components are mounted on a module substrate 21. A first member 31 of the semiconductor device 30 is larger than a second member 32 in a plan view and includes the second member 32.

[0027] A band selection switch 41, a first control circuit 42, and an input switch 43 are formed on the first member 31. In Fig. 2, an area in which circuit blocks such as the band selection switch 41, the first control circuit 42, and the input switch 43 are arranged is surrounded by a dashed line. Here, a circuit block refers to an assembly of a plurality of circuit elements, such as semiconductor elements and passive elements, configured to realize a certain function, and wiring that connects these circuit elements to each other. In general, a circuit is designed for each circuit block, and each circuit block is laid out on a semiconductor substrate.

[0028] The output matching circuit 76 is composed of passive elements such as inductors arranged in the module substrate, and capacitors and the like surface-mounted on the module substrate. The inductors constituting the output matching circuit 76 are arranged at positions overlapping with the semiconductor device 30 in a plan view. In this specification, a state in which "two members overlap in a plan view" includes a state in which one member contains the other member, a state in which a part of one member overlaps a part of the other member, and a state in which the outer peripheries of the two members coincide.

[0029] FIG. 3 is a schematic cross-sectional view of a semiconductor device 30 according to a first embodiment. The first member 31 includes a substrate 311, a multilayer wiring structure 312 disposed thereon, and a first member protective film 317 covering the surface of the multilayer wiring structure 312. The substrate 311 includes a semiconductor portion of a single semiconductor system. For example, a silicon substrate or a silicon-on-insulator (SOI) substrate is used as the substrate 311. A band selection switch 41 (FIG. 1), a first control circuit 42 (FIG. 1), and an input switch 43 (FIG. 1) are configured by semiconductor elements formed on the surface layer of the substrate 311 and wiring in the multilayer wiring structure 312. In FIG. 3, the region in which the input switch 43 is formed is shown surrounded by a dashed line. The outermost surface of the first member 31 is referred to as a first surface 31A. An opening is provided in a part of the first member protective film 317, and the opening is filled with a metal film 318. The upper surfaces of the first member protective film 317 and the metal film 318 correspond to the first surface 31A.

[0030] The second member 32 is joined to the first surface 31A of the first member 31 in surface contact. In addition, in a plan view, at least a portion of the second member 32 overlaps at least a portion of the metal film 318, and the second member 32 is in surface contact with the metal film 318. An interlayer insulating film 67 is disposed on the first surface 31A so as to cover the second member 32. A plurality of openings are provided at predetermined positions in the interlayer insulating film 67. Pads 62, 63, and wiring 61 are disposed on the interlayer insulating film 67. The wiring layer in which the pads 62, 63, and wiring 61 are disposed may be referred to as a rewiring layer. The wiring 61 in the rewiring layer may be referred to as a rewiring.

[0031] The wiring 61 passes through an opening provided in the interlayer insulating film 67, and connects the circuit formed in the second member 32 to the circuit formed in the first member 31. For example, the wiring 61 is connected to the input switch 43 via a wiring 315 in the multilayer wiring structure 312. For example, the wiring 61 is used to connect the input switch 43 and the second amplifier circuit 52 shown in FIG. 1, to connect the first control circuit 42 and the second amplifier circuit 52, to connect the first control circuit 42 and the first amplifier circuit 51, etc.

[0032] The pad 62 is included in the second member 32 in a plan view, and is connected to a circuit formed in the second member 32. The other pad 63 is disposed outside the second member 32 in a plan view, and is connected to an input switch 43 formed in the first member 31 via a wiring 316 in the multilayer wiring structure 312.

[0033] A protective film 68 is disposed on the interlayer insulating film 67 so as to cover the redistribution layer. Openings are provided in the protective film 68 to expose partial regions of the upper surfaces of the pads 62 and 63. Conductor protrusions 82 and 83 are disposed on the pads 62 and 63, respectively. The conductor protrusion 82 includes a Cu pillar 82A connected to the pad 62 and a solder layer 82B disposed on the upper surface of the Cu pillar 82A. The conductor protrusion 82 having such a structure is called a Cu pillar bump.

[0034] An under-bump metal layer may be disposed on the bottom surface of the Cu pillar 82A in order to improve adhesion. The other conductor protrusions 83 have the same layered structure as the conductor protrusion 82. Instead of the Cu pillar bump, an Au bump, a solder ball bump, a conductor post erected on a pad, or the like may be used for the conductor protrusions 82, 83, etc. A bump without a solder layer, such as an Au bump, is also called a pillar. A conductor post erected on a pad is also called a post.

[0035] 1, for example, to connect the power supply terminal VCC1 and the first amplifier circuit 51, to connect the power supply terminal VCC2 and the second amplifier circuit 52, and to connect the first amplifier circuit 51 and the output matching circuit 76. Furthermore, the conductor protrusion 82 is used to connect the ground conductor in the second member 32 and the ground conductor of the module substrate.

[0036] The conductor protrusion 83 is used, for example, to connect the input switch 43 shown in FIG. 1 to the high-frequency signal input terminals IN1 and IN2, to connect the first control circuit 42 to the power supply terminal VIO1, the control signal terminal SDATA1, and the clock terminal SCLK1, and to connect the band selection switch 41 to the output matching circuit 76, the multiple duplexers 70, etc.

[0037] In the multilayer wiring structure 312, at least one layer of metal pattern 313 and a plurality of vias 314 that connect the metal patterns 313 to each other or connect the metal film 318 and the metal pattern 313 in the thickness direction are arranged. The plurality of metal patterns 313 overlap a part of the second member 32 in a plan view. The metal pattern 313 arranged in the lowest wiring layer is connected to the substrate 311 through a plurality of vias 314. The metal pattern 313 is not electrically connected to any circuit block of the first member 31. The metal film 318, the metal pattern 313, and the vias 314 function as a heat transfer path from the second member 32 to the substrate 311. In addition to functioning as a current path, the conductor protrusion 82 also functions as a heat transfer path from the second member 32 to the module substrate.

[0038] 4A is an equivalent circuit diagram of each of a plurality of cells constituting a first amplifier circuit 51 (FIG. 1) of a semiconductor device according to a first embodiment. The first amplifier circuit 51 is composed of a plurality of cells connected in parallel to each other. The second amplifier circuit 52 (FIG. 1) also has a circuit configuration similar to that of the first amplifier circuit 51. However, the number of cells constituting the second amplifier circuit 52 is smaller than the number of cells constituting the first amplifier circuit 51.

[0039] Each cell includes a transistor Q, an input capacitor Cin, and a ballast resistor Rb. The base of the transistor Q is connected to a high-frequency signal input wiring 105RF via the input capacitor Cin. Furthermore, the base of the transistor Q is connected to a base bias wiring 104BB via a ballast resistor Rb. The emitter of the transistor Q is grounded. The collector of the transistor Q is connected to a collector wiring 104C. A power supply voltage is applied to the collector of the transistor Q via the collector wiring 104C, and an amplified high-frequency signal is output from the collector.

[0040] 4B is a schematic cross-sectional view of one cell constituting the first amplifier circuit 51 (FIG. 1) formed on the second member 32. The second member 32 includes an underlying semiconductor layer 101. The underlying semiconductor layer 101 is in surface contact with the first member 31, thereby bonding the second member 32 to the first member 31. The underlying semiconductor layer 101 is divided into a conductive region 101A and an element isolation region 101B. The underlying semiconductor layer 101 is made of, for example, GaAs. The conductive region 101A is made of n-type GaAs, and the element isolation region 101B is formed by ion-implanting an insulating impurity into the n-type GaAs layer.

[0041] A transistor Q is disposed on the conductive region 101A. The transistor Q includes a collector layer 102C, a base layer 102B, and an emitter layer 102E, which are stacked in this order on the conductive region 101A. The emitter layer 102E is disposed on a portion of the base layer 102B. As an example, the collector layer 102C is made of n-type GaAs, the base layer 102B is made of p-type GaAs, and the emitter layer 102E is made of n-type InGaP. That is, the transistor Q is a heterojunction bipolar transistor.

[0042] A base electrode 103B is disposed on the base layer 102B and is electrically connected to the base layer 102B. An emitter electrode 103E is disposed on the emitter layer 102E and is electrically connected to the emitter layer 102E. A collector electrode 103C is disposed on the conductive region 101A. The collector electrode 103C is electrically connected to the collector layer 102C via the conductive region 101A.

[0043] A first interlayer insulating film 111 is disposed on the underlying semiconductor layer 101 so as to cover the transistor Q, the collector electrode 103C, the base electrode 103B, and the emitter electrode 103E. The first interlayer insulating film 111 is formed of an inorganic insulating material such as SiN. A plurality of openings are provided at predetermined positions in the interlayer insulating film 111.

[0044] An emitter wiring 104E, a base wiring 104B, a collector wiring 104C, and a base bias wiring 104BB of the first layer are disposed on the interlayer insulating film 111. Furthermore, a ballast resistor element Rb is disposed on the interlayer insulating film 111. The emitter wiring 104E is connected to the emitter electrode 103E through an opening provided in the interlayer insulating film 111. The base wiring 104B is connected to the base electrode 103B through another opening provided in the interlayer insulating film 111. The collector wiring 104C is connected to the collector electrode 103C through another opening provided in the interlayer insulating film 111.

[0045] The base wiring 104B extends to an area where the transistor Q is not arranged, and its tip overlaps one end of the ballast resistance element Rb. At the overlapping portion, the base wiring 104B and the ballast resistance element Rb are electrically connected. The other end of the ballast resistance element Rb overlaps the base bias wiring 104BB. At the overlapping portion, the ballast resistance element Rb and the base bias wiring 104BB are electrically connected.

[0046] A second interlayer insulating film 112 is disposed on the interlayer insulating film 111 so as to cover the first emitter wiring 104E, the base wiring 104B, the base bias wiring 104BB, and the ballast resistor element Rb. The second interlayer insulating film 112 is also formed of an inorganic insulating material such as SiN.

[0047] A second-layer emitter wiring 105E and a high-frequency signal input wiring 105RF are disposed on the interlayer insulating film 112. The second-layer emitter wiring 105E is connected to the first-layer emitter wiring 104E through an opening provided in the interlayer insulating film 112. A portion of the high-frequency signal input wiring 105RF overlaps with the first-layer base wiring 104B in a plan view. An input capacitor Cin is formed in the overlapping region between the two.

[0048] A third interlayer insulating film 67 is disposed so as to cover the second-layer emitter wiring 105E and the high-frequency signal input wiring 105RF. The third interlayer insulating film 67 is formed of an organic insulating material such as polyimide. The third interlayer insulating film 67 extends up to above the first member 31 as shown in FIG.

[0049] A pad 62 is disposed on the third interlayer insulating film 67. The pad 62 passes through an opening provided in the interlayer insulating film 67 and is connected to the second emitter wiring 105E.

[0050] 5A is a schematic diagram showing the in-plane arrangement of each circuit block when the first surface 31A of the semiconductor device 30 according to the first embodiment is viewed in plan. The multiple circuit blocks formed in the first member 31 include a band selection switch 41, a first control circuit 42, and an input switch 43. These circuit blocks are arranged in an internal region of the first surface 31A when the first surface 31A is viewed in plan.

[0051] The multiple circuit blocks formed in the second member 32 include a first amplifier circuit 51 in the final stage, a second amplifier circuit 52 in the initial stage, and a bias circuit 53. In Fig. 5A, the circuit blocks formed in the first member 31 are hatched downward to the right. The region in which the second amplifier circuit 52 and the bias circuit 53 formed in the second member 32 are disposed is hatched upward to the right. Similar hatching is used in Figs. 8 to 13.

[0052] FIG. 5B is a diagram showing the arrangement of the multiple transistors Q (FIGS. 4A and 4B) constituting the first amplifier circuit 51 in a plan view. Each of the multiple transistors Q includes a collector layer 102C and a base layer 102B. In a plan view, the outer periphery of the collector layer 102C and the outer periphery of the base layer 102B are substantially aligned. In a plan view, the emitter layer 102E (FIG. 4B) is included in the base layer 102B. Each of the transistors Q has a shape that is long in one direction (the up-down direction in FIG. 5B) in a plan view. The longitudinal directions of the multiple transistors Q are parallel to each other, and the multiple transistors Q are arranged side by side in a direction perpendicular to the longitudinal direction (the left-right direction in FIG. 5B).

[0053] A plurality of transistors Q are distributed within a region 55. The region 55 in which the plurality of transistors Q are distributed is defined as, for example, the smallest convex polygon that contains the plurality of transistors Q in a plan view.

[0054] A plurality of transistor arrays each consisting of a plurality of transistors Q may be arranged in a direction perpendicular to the direction in which the transistors Q are arranged. In this case, the smallest convex polygon that includes all the transistors Q included in the plurality of transistor arrays may be defined as the region 55 in which the plurality of transistors Q are distributed.

[0055] As shown in Fig. 5A, a region 55 in which a plurality of transistors Q are distributed is disposed in a circuit block constituting the first amplifier circuit 51. Conductor protrusions 82E and 82C are connected to the emitters and collectors of the plurality of transistors Q, respectively. In a plan view, the emitter conductor protrusion 82E encompasses the region 55 in which the plurality of transistors Q are distributed. In addition, the input capacitor Cin and ballast resistor element Rb shown in Figs. 4A and 4B are disposed in the circuit block constituting the first amplifier circuit 51.

[0056] The first amplifier circuit 51 does not overlap any of the circuit blocks formed in the first member 31. Therefore, an area 55 in which the multiple transistors Q are distributed also does not overlap any of the circuit blocks formed in the first member 31. Furthermore, each of the multiple transistors Q does not overlap any of the circuit blocks formed in the first member 31. A metal pattern 313, a via 314, and a metal film 318 (FIG. 3) in a multilayer wiring structure 312 (FIG. 3) are arranged in an area overlapping with the circuit blocks constituting the first amplifier circuit 51 in a plan view.

[0057] The circuit blocks constituting the second amplifier circuit 52 and the bias circuit 53 overlap any of the circuit blocks formed in the first member 31. For example, the circuit block constituting the second amplifier circuit 52 overlaps with the circuit block constituting the input switch 43 and the first control circuit 42 formed in the first member 31, and the circuit block constituting the bias circuit 53 overlaps with the circuit block constituting the first control circuit 42 and the band selection switch 41 formed in the first member 31. In this manner, one of the circuit blocks in the second member 32 that is not the circuit block constituting the first amplifier circuit 51 may overlap across multiple circuit blocks in the first member 31, or as another configuration, may overlap with one circuit block in the first member 31.

[0058] Next, a method for manufacturing the semiconductor device 30 according to the first embodiment will be described with reference to Figures 6A to 7D. Figures 6A to 7C are cross-sectional views of the semiconductor device 30 during the manufacturing process, and Figure 7D is a cross-sectional view of the completed semiconductor device 30.

[0059] As shown in Fig. 6A, a release layer 201 is epitaxially grown on a mother substrate 200 of a single crystal of a compound semiconductor such as GaAs, and an element formation layer 202 is formed on the release layer 201. In the element formation layer 202, the transistor Q of the second member 32 shown in Fig. 4B, the first wiring layer, the second wiring layer, and the like are formed. These circuit elements and wiring layers are formed by a general semiconductor process. In Fig. 6A, the element structure formed in the element formation layer 202 is omitted. At this stage, the element formation layer 202 is not separated into individual second members 32.

[0060] 6B, a resist pattern (not shown) is used as an etching mask to pattern the element formation layer 202 (FIG. 5A) and the release layer 201. At this stage, the element formation layer 202 (FIG. 5A) is separated into each second member 32.

[0061] Next, as shown in Fig. 6C, a connecting support 204 is attached onto the separated second member 32. As a result, the multiple second members 32 are connected to each other via the connecting support 204. Note that the resist pattern used as an etching mask in the patterning step of Fig. 6B may be left to interpose a resist pattern between the second member 32 and the connecting support 204.

[0062] 6D, the release layer 201 is selectively etched with respect to the mother substrate 200 and the second member 32. As a result, the second member 32 and the connecting support 204 are peeled off from the mother substrate 200. In order to selectively etch the release layer 201, a compound semiconductor having an etching resistance different from that of both the mother substrate 200 and the second member 32 is used as the release layer 201.

[0063] 6E, a substrate 210 on which an input switch 43 and a multilayer wiring structure 312 (FIG. 3) to be provided on a first member 31 (FIG. 3) are formed is prepared. At this stage, the substrate 210 is not separated into individual first members 31.

[0064] As shown in Fig. 6F, the second member 32 is bonded to the substrate 210. The second member 32 and the substrate 210 are bonded by van der Waals bonds or hydrogen bonds. Alternatively, the second member 32 may be bonded to the substrate 210 by electrostatic forces, covalent bonds, eutectic alloy bonds, or the like. For example, when a portion of the surface of the substrate 210 is formed of Au, the second member 32 may be bonded to the substrate 210 by closely contacting the Au region and applying pressure thereto.

[0065] Next, as shown in Fig. 7A, the connecting support 204 is peeled off from the second member 32. After the connecting support 204 is peeled off, as shown in Fig. 7B, an interlayer insulating film 67 and a rewiring layer are formed on the substrate 210 and the second member 32. The rewiring layer includes the wiring 61, the pads 62 and 63 (Fig. 3), and the like.

[0066] 7C, a protective film 68 is formed on the redistribution layer, and openings are formed at predetermined positions in the protective film 68. Thereafter, a conductor protrusion 82 is formed in the opening and on the protective film 68. At the same time as the conductor protrusion 82 is formed, other conductor protrusions 83 (FIG. 3) and the like are also formed.

[0067] 7D, the substrate 210 is diced, thereby obtaining the semiconductor device 30.

[0068] Next, the excellent effects of the first embodiment will be described. In the first embodiment, as shown in FIG. 3, a heat transfer path from the second member 32 to the first member 31 is formed. Since the second member 32 is in surface contact with the first member 31, the second member 32 and the first member 31 are thermally coupled with low thermal resistance. Furthermore, since the metal pattern 313 and the via 314 are arranged in the multilayer wiring structure 312 directly below the second member 32, the thermal resistance of the heat transfer path from the second member 32 to the substrate 311 is lower than that of a configuration in which the entire multilayer wiring structure 312 directly below the second member 32 is formed of an insulating material. Note that the metal pattern 313 is not electrically connected to any of the circuit blocks of the first member 31, so the metal pattern 313 functioning as a heat transfer path does not affect the operation of the circuit blocks of the first member 31. Note that the metal pattern 313 may be electrically connected to a ground conductor in the first member 31.

[0069] The heat conducted from the second member 32 to the first member 31 is diffused within the first member 31. The heat diffused within the first member 31 is radiated to the outside from the surface of the first member 31. When the semiconductor device 30 is mounted on a module substrate and covered with a molded resin, the heat is conducted from the first member 31 to the molded resin.

[0070] Furthermore, the conductor protrusion 82 functions as a heat transfer path from the second member 32 to the module substrate. In this way, heat is dissipated through two paths, the heat transfer path from the second member 32 toward the module substrate and the heat transfer path toward the first member 31. This improves the heat dissipation characteristics from the second member 32. In order to obtain a sufficient effect of improving the heat dissipation characteristics, it is preferable to use a semiconductor having a higher thermal conductivity than the compound semiconductor forming the semiconductor element formed in the second member 32, such as an elemental semiconductor such as Si or Ge, in the semiconductor portion of the substrate 311 of the first member 31. In addition, it is preferable to use a compound semiconductor-based semiconductor element having a higher electron mobility than the semiconductor portion of the substrate 311 of the first member 31 as the semiconductor element formed in the second member 32 in order to amplify a high-frequency signal.

[0071] Heat is particularly likely to be generated in a region 55 (FIG. 5A) of the second member 32 where a plurality of transistors Q constituting the first amplifier circuit 51 are distributed. In order to reduce the thermal resistance of the heat transfer path from the region 55 where the plurality of transistors Q are distributed to the substrate 311 (FIG. 3) of the first member 31, it is preferable to arrange the metal pattern 313 (FIG. 3) so that the region 55 where the plurality of transistors Q are distributed is included in the metal pattern 313 in a planar view. Furthermore, it is preferable to arrange the metal film 318 (FIG. 3) so that the region 55 where the plurality of transistors Q are distributed is included in the metal film 318 in a planar view.

[0072] A larger high-frequency current flows through the first amplifier circuit 51 than through the second amplifier circuit 52 and the bias circuit 53, and therefore the first amplifier circuit 51 is likely to become a noise source. In the first embodiment, the first amplifier circuit 51 (FIG. 5A) does not overlap with any circuit block of the first member 31 in a plan view, and therefore, an excellent effect is obtained in that each circuit block of the first member 31 is less susceptible to the effects of noise generated in the first amplifier circuit 51.

[0073] In the first embodiment, the second amplifier circuit 52 and the bias circuit 53 (FIG. 5A) of the second member 32 overlap with any of the circuit blocks of the first member 31 in a plan view. This makes it possible to reduce the size of the semiconductor device 30 in a plan view.

[0074] Next, a modification of the first embodiment will be described. In the first embodiment, the heat transfer path consisting of the metal film 318 (FIG. 3), the multiple metal patterns 313 in the multilayer wiring structure 312 of the first member 31, and the multiple vias 314 (FIG. 3) contacts the second member 32 and the substrate 311, but the heat transfer path consisting of the metal film 318, the metal pattern 313, and the multiple vias 314 does not necessarily need to contact the second member 32 and the substrate 311. For example, the heat transfer path consisting of the multiple metal patterns 313 and the multiple vias 314 may be thermally coupled to the second member 32 and the substrate 311 via an insulating film. In this case, the insulating film functions as a part of the heat transfer path from the second member 32 to the substrate 311. Also, the metal film 318 may not be disposed, and the entire area of ​​the first surface 31A may be the first member protective film 317. In this case, the part of the first member protective film 317 that contacts the second member 32 mainly functions as the heat transfer path.

[0075] Furthermore, if the metal pattern 313 and the via 314 are not arranged, the thermal resistance of the heat transfer path from the second member 32 to the substrate 311 becomes high, but if sufficient heat dissipation characteristics can be obtained from the first amplifier circuit 51, it is not necessary to arrange the metal pattern 313 and the via 314. In this case, the insulating film included in the multilayer wiring structure 312 functions as the heat transfer path.

[0076] Although the high-frequency amplifier circuit 50 (FIG. 1) of the semiconductor device 30 according to the first embodiment has a two-stage configuration consisting of a second amplifier circuit 52 in the first stage and a first amplifier circuit 51 in the final stage, the high-frequency amplifier circuit 50 may have a multi-stage configuration of three or more stages. In this case as well, it is preferable that a region 55 (FIG. 5A) in which a plurality of transistors Q constituting the first amplifier circuit 51 in the final stage are distributed does not overlap any of the circuit blocks of the first member 31.

[0077] In the first embodiment, the semiconductor device 30 is mounted on the high-frequency module 20 (FIG. 1) of the frequency division duplex (FDD) system, but it is also possible to mount it on a high-frequency module of the time division duplex (TDD) system.

[0078] When the semiconductor device 30 is mounted on a high-frequency module of the TDD system, the band selection switch 41 may be replaced with a transmission / reception changeover switch. The transmission / reception changeover switch has two contacts and one common terminal. One of the two contacts is connected to the first amplifier circuit 51 in the final stage via an output matching circuit 76 (FIG. 1), and the other contact is connected to a low-noise amplifier 71 (FIG. 1) for amplifying a reception signal, or is connected to the low-noise amplifier 71 via a reception band selection switch 73 (FIG. 1). The common terminal is connected to an antenna terminal via a filter. For example, the transmission / reception changeover switch overlaps with the bias circuit 53 of the second member 32 in a plan view, similar to the band selection switch 41 (FIG. 5A) of the first embodiment.

[0079] [Second Example] Next, a semiconductor device according to a second embodiment will be described with reference to Fig. 8. Below, a description of the configuration common to the semiconductor device according to the first embodiment described with reference to Figs. 1 to 7D will be omitted.

[0080] 8 is a schematic diagram showing the in-plane arrangement of each circuit block of a semiconductor device 30 according to the second embodiment. In the first embodiment (FIG. 5A), a part of the circuit block constituting the band selection switch 41 of the first member 31 overlaps with the second member 32. In contrast, in the second embodiment, the circuit block constituting the band selection switch 41 does not overlap with the second member 32 in a plan view, and is arranged outside the second member 32.

[0081] A circuit block constituting the bias circuit 53 of the second member 32 overlaps with a circuit block constituting the input switch 43 of the first member 31 and a circuit block constituting the first control circuit 42. A circuit block constituting the second amplifier circuit 52 of the second member 32 overlaps with a circuit block constituting the first control circuit 42 of the first member 31.

[0082] Next, the advantageous effects of the second embodiment will be described. In the second embodiment, as in the first embodiment, the heat dissipation characteristics from the transistor Q of the first amplifier circuit 51 can be improved. Furthermore, in the second embodiment, the circuit block constituting the band selection switch 41 does not overlap with the second member 32 in a plan view, which provides the excellent effect of easily ensuring input / output isolation. Specifically, the high-frequency signal transmitted through the band selection switch 41 is less likely to couple with the input side of the high-frequency amplifier circuit 50 (FIG. 1) through the second member 32. This provides the excellent effect of making it less likely for oscillation to occur in the high-frequency amplifier circuit 50.

[0083] Next, a modified example of the second embodiment will be described. In the second embodiment, the semiconductor device 30 is mounted on an FDD-type high-frequency module, but it is also possible to mount it on a TDD-type high-frequency module. When mounting the semiconductor device 30 on a TDD-type high-frequency module, the band selection switch 41 can be replaced with a transmission / reception changeover switch. In this case, it is preferable that the circuit block constituting the transmission / reception changeover switch does not overlap the second member 32 in a plan view, but is arranged outside the second member 32.

[0084] [Third Example] Next, a semiconductor device according to a third embodiment will be described with reference to Fig. 9. Below, a description of the configuration common to the semiconductor device according to the second embodiment described with reference to Fig. 8 will be omitted.

[0085] 9 is a schematic diagram showing the in-plane arrangement of each circuit block of the semiconductor device 30 according to the third embodiment. In the second embodiment (FIG. 8), the circuit block constituting the input switch 43 of the first member 31 overlaps with the second member 32 in a plan view. In contrast, in the third embodiment, the circuit block constituting the input switch 43 does not overlap with the second member 32 in a plan view.

[0086] Next, the excellent effects of the third embodiment will be described. In the third embodiment, as in the second embodiment, the heat dissipation characteristics from the transistor Q of the first amplifier circuit 51 can be improved. Furthermore, in the third embodiment, neither of the circuit blocks constituting the input switch 43 connected to the input side of the high frequency amplifier circuit 50 nor the band selection switch 41 connected to the output side of the high frequency amplifier circuit 50 overlaps with the second member 32. This makes it possible to further improve the isolation between the input and output of the high frequency amplifier circuit 50.

[0087] [Fourth Example] Next, a semiconductor device according to a fourth embodiment will be described with reference to Fig. 10. Below, a description of the configuration common to the semiconductor device according to the third embodiment described with reference to Fig. 9 will be omitted.

[0088] 10 is a schematic diagram showing the in-plane arrangement of each circuit block of a semiconductor device 30 according to the fourth embodiment. In the third embodiment, the circuit block constituting the second amplifier circuit 52 of the second member 32 overlaps with the circuit block constituting the first control circuit 42 of the first member 31. In contrast, in the fourth embodiment, the circuit block constituting the second amplifier circuit 52 of the second member 32 does not overlap with any circuit block of the first member 31.

[0089] Next, the excellent effects of the fourth embodiment will be described. In the fourth embodiment, as in the third embodiment, it is possible to improve the heat dissipation characteristics from the transistor Q of the first amplifier circuit 51. Furthermore, in the fourth embodiment, the circuit block constituting the second amplifier circuit 52 in the second member 32 does not overlap any of the circuit blocks in the first member 31, so that it is possible to reduce the effect of noise generated in the second amplifier circuit 52 on the circuit formed in the first member 31.

[0090] Note that the region in which the multiple transistors constituting the second amplifier circuit 52 are distributed may be arranged so as not to overlap any of the circuit blocks of the first member 31, and other regions of the second amplifier circuit 52 may be arranged so as to overlap any of the circuit blocks of the first member 31. Even in this case, the effect of improving the heat dissipation characteristics from the multiple transistors constituting the second amplifier circuit 52 can be obtained.

[0091] [Fifth Example] Next, a semiconductor device according to a fifth embodiment will be described with reference to Fig. 11. Below, a description of the configuration common to the semiconductor device according to the fourth embodiment described with reference to Fig. 10 will be omitted.

[0092] 11 is a schematic diagram showing the in-plane arrangement of each circuit block of the semiconductor device 30 according to the fifth embodiment. In the fourth embodiment (FIG. 10), in a plan view, the circuit blocks constituting the first amplifier circuit 51 and the second amplifier circuit 52 of the second member 32 do not overlap any circuit block of the first member 31, and the circuit block constituting the bias circuit 53 of the second member 32 overlaps with the circuit block constituting the first control circuit 42 of the first member 31. In contrast, in the fifth embodiment, none of the circuit blocks of the second member 32 overlaps with the circuit block of the first member 31 in a plan view. In other words, none of the circuit blocks of the first member 31 overlap with the second member 32 in a plan view.

[0093] Next, the excellent effects of the fifth embodiment will be described. In the fifth embodiment, as in the fourth embodiment, the heat dissipation characteristics from the transistor Q of the first amplifier circuit 51 can be improved. Furthermore, in the fifth embodiment, an excellent effect is obtained that the circuit formed in the first member 31 is less susceptible to the effects of heat and noise from the second member 32. The first control circuit 42 in the first member 31 includes, for example, a charge pump that obtains a predetermined voltage. The charge pump and digital circuit of the first control circuit 42 are likely to become a noise source for the analog circuit. In the fifth embodiment, since the second member 32 does not overlap any circuit block in the first member 31, an excellent effect is obtained that the circuit in the second member 32 is less susceptible to the effects of noise sources in the first member 31.

[0094] In the fifth embodiment, the second member 32 does not overlap any of the circuit blocks of the first member 31, and therefore the dimensions of the semiconductor device 30 in a plan view are greater than the dimensions of any of the semiconductor devices 30 in the first to fourth embodiments. The configuration of any one of the embodiments to be adopted for the semiconductor device 30 may be determined according to the level of noise countermeasures required.

[0095] [Sixth Example] Next, a semiconductor device according to a sixth embodiment will be described with reference to Fig. 12. Below, a description of the configuration common to the semiconductor device according to the first embodiment described with reference to Figs. 1 to 7D will be omitted.

[0096] 12 is a schematic diagram showing the in-plane arrangement of each circuit block of a semiconductor device 30 according to the sixth embodiment. In the first embodiment (FIGS. 1, 5, etc.), the second amplifier circuit 52 in the first stage of the high-frequency amplifier circuit 50 is formed in the second member 32. In contrast, in the sixth embodiment, the second amplifier circuit 52 is formed in the first member 31. The first amplifier circuit 51 and a bias circuit 53 are formed in the second member 32.

[0097] The circuit block constituting the bias circuit 53 of the second member 32 overlaps with the circuit block constituting the input switch 43 of the first member 31 in a plan view. The circuit block constituting the first amplifier circuit 51 of the second member 32 does not overlap with any of the circuit blocks of the first member 31 in a plan view.

[0098] Next, the excellent effects of the sixth embodiment will be described. In the sixth embodiment, as in the first embodiment, the heat dissipation characteristics from the transistor Q of the first amplifier circuit 51 can be improved. Moreover, in the sixth embodiment, since the second amplifier circuit 52 is formed in the first member 31, the second member 32 can be made smaller. In general, substrates based on elemental semiconductors such as silicon are less expensive than substrates based on compound semiconductors such as GaAs. Furthermore, the manufacturing process for elemental semiconductors is easier to reduce costs than the manufacturing process for compound semiconductors. In the sixth embodiment, the second member 32 including the semiconductor element based on compound semiconductors can be made smaller, thereby reducing the cost of the semiconductor device 30.

[0099] [Seventh Example] Next, a semiconductor device according to a seventh embodiment will be described with reference to Fig. 13. Below, a description of the configuration common to the semiconductor device according to the sixth embodiment described with reference to Fig. 12 will be omitted.

[0100] 13 is a schematic diagram showing the in-plane arrangement of each circuit block of a semiconductor device 30 according to the seventh embodiment. In the sixth embodiment, the second amplifier circuit 52 is formed on the first member 31, but the bias circuit 53 remains on the second member 32. In contrast, in the seventh embodiment, the bias circuit 53 is also formed on the first member 31.

[0101] Next, the excellent effects of the seventh embodiment will be described. In the seventh embodiment, both the second amplifier circuit 52 and the bias circuit 53 are formed in the first member 31. Only the first amplifier circuit 51 in the final stage remains in the second member 32. Therefore, in the seventh embodiment, it is possible to make the second member 32 smaller than in the sixth embodiment. This allows the cost of the semiconductor device 30 to be further reduced.

[0102] The above-mentioned embodiments are merely examples, and it goes without saying that partial replacement or combination of the configurations shown in different embodiments is possible. Similar effects due to similar configurations of multiple embodiments are not mentioned in each embodiment. Furthermore, the present invention is not limited to the above-mentioned embodiments. For example, it will be obvious to those skilled in the art that various modifications, improvements, combinations, etc. are possible. [Explanation of symbols]

[0103] 20 High Frequency Module 21 Module Board 30 Semiconductor Devices 31 First member 31A 1st page 32 Second member 41 Transmit band selection switch 42 First control circuit 43 Input Switch 50 High frequency amplifier circuit 51 Final stage first amplifier circuit 52 First stage second amplifier circuit 53 Bias Circuit 55 Region in which multiple transistors of the first amplifier circuit are distributed 61 Wiring 62, 63 Pad 67 Interlayer insulating film 68 Protective film 70 Duplexer 71 Low noise amplifier 72 Antenna Switch 73 Receiving band selection switch 74 Output terminal selection switch 75 Second control circuit 76 Output matching circuit 82 Conductor protrusion 82A Cu pillar 82B solder layer 82C Collector conductor projection 82E Emitter conductor projection 83 Conductor protrusion 101 Underlying semiconductor layer 101A conductive area 101B Element isolation area 102B Base layer 102B Base layer 102C Collector layer 102E Emitter layer 103B Base electrode 103C Collector electrode 103E Emitter electrode 104B Base wiring 104BB Base bias wiring 104C Collector wiring 104E Emitter wiring 105E Emitter wiring 105RF High frequency signal input wiring 111 Interlayer insulating film 112 Interlayer insulating film 200 Motherboard 201 Peeling layer 202 Device formation layer 204 Connecting support 210 Substrate 311 Substrate 312 Multilayer wiring structure 313 Metal Pattern 314 Beer 315, 316 Wiring 317 First component protective film

Claims

1. a first member having a first surface, the first surface being viewed in a plan view and including a plurality of circuit blocks disposed in an internal region of the first surface; a second member including a plurality of first transistors joined in surface contact with the first surface of the first member and connected in parallel to each other to form a first amplifier circuit; a conductor projection protruding from the second member toward a side opposite to the first member; Equipped with The semiconductor device, wherein the first transistors are arranged in a region that does not overlap any of the circuit blocks of the first member in a plan view and overlap the first member.

2. The semiconductor device according to claim 1 , wherein the second member overlaps at least one of the plurality of circuit blocks of the first member in a plan view.

3. A first member having a first surface, the first surface being viewed in a plan view and including a plurality of circuit blocks arranged in an internal region of the first surface; a second member including a plurality of first transistors joined in surface contact with the first surface of the first member and connected in parallel to each other to form a first amplifier circuit; a conductor projection protruding from the second member toward a side opposite to the first member; Equipped with the first transistors are arranged in a region that does not overlap any of the circuit blocks of the first member in a plan view, one of the plurality of circuit blocks of the first member constitutes a band selection switch that outputs a high-frequency signal input to one input contact to which the high-frequency signal output from the first amplifier circuit is input, to one output contact selected from a plurality of output contacts; A semiconductor device in which a circuit block constituting the band selection switch is disposed outside the second member in a plan view.

4. A first member having a first surface, the first surface being viewed in a plan view and including a plurality of circuit blocks arranged in an internal region of the first surface; a second member including a plurality of first transistors joined in surface contact with the first surface of the first member and connected in parallel to each other to form a first amplifier circuit; a conductor projection protruding from the second member toward a side opposite to the first member; Equipped with the first transistors are arranged in a region that does not overlap any of the circuit blocks of the first member in a plan view, one of the plurality of circuit blocks of the first member constitutes an input switch that inputs a high-frequency signal input to one input contact selected from a plurality of input contacts to the first amplifier circuit; A semiconductor device in which a circuit block constituting the input switch is disposed outside the second member in a plan view.

5. the second member further includes at least one second transistor constituting a second amplifier circuit connected in a preceding stage of the first amplifier circuit; The semiconductor device according to claim 1 , wherein the at least one second transistor is disposed in a region of the first member that does not overlap any of the plurality of circuit blocks in a plan view.

6. A first member having a first surface, the first surface being viewed in a plan view and including a plurality of circuit blocks arranged in an internal region of the first surface; a second member including a plurality of first transistors joined in surface contact with the first surface of the first member and connected in parallel to each other to form a first amplifier circuit; a conductor projection protruding from the second member toward a side opposite to the first member; Equipped with the first transistors are arranged in a region that does not overlap any of the circuit blocks of the first member in a plan view, one of the plurality of circuit blocks of the first member constitutes a second amplifier circuit connected to a front stage of the first amplifier circuit; The second member includes a bias circuit that supplies a bias current to the first amplifier circuit, and the bias circuit overlaps with at least one of the multiple circuit blocks of the first member.

7. A first member having a first surface, the first surface being viewed in a plan view and including a plurality of circuit blocks disposed in an internal region of the first surface; a second member including a plurality of first transistors joined in surface contact with the first surface of the first member and connected in parallel to each other to form a first amplifier circuit; a conductor projection protruding from the second member toward a side opposite to the first member; Equipped with the first transistors are arranged in a region that does not overlap any of the circuit blocks of the first member in a plan view, One of the plurality of circuit blocks of the first member constitutes a bias circuit that supplies a bias current to the first amplifier circuit.

8. A first member having a first surface, the first surface being viewed in a plan view and including a plurality of circuit blocks arranged in an internal region of the first surface; a second member including a plurality of first transistors joined in surface contact with the first surface of the first member and connected in parallel to each other to form a first amplifier circuit; a conductor projection protruding from the second member toward a side opposite to the first member; Equipped with the first transistors are arranged in a region that does not overlap any of the circuit blocks of the first member in a plan view, The second member does not overlap any of the multiple circuit blocks of the first member in a plan view.

9. A first member having a first surface, the first surface being viewed in a plan view and including a plurality of circuit blocks arranged in an internal region of the first surface; a second member including a plurality of first transistors joined in surface contact with the first surface of the first member and connected in parallel to each other to form a first amplifier circuit; a conductor projection protruding from the second member toward a side opposite to the first member; Equipped with the first transistors are arranged in a region that does not overlap any of the circuit blocks of the first member in a plan view, the first member includes a semiconductor substrate and a multilayer wiring structure disposed on one surface of the semiconductor substrate; the first surface is a surface on the side of the multilayer wiring structure, The multilayer wiring structure of the semiconductor device includes a metal pattern that overlaps the second member in a plan view and is not electrically connected to any of the plurality of circuit blocks.

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