COMMUNICATION SYSTEM, PROCESSING METHOD, AND PROGRAM

Abstract

To provide a communication system, a processing method, and a program that reduce the occurrence of communication errors even when a communication connection destination (that is, communication path) is changed and load capacity is changed.SOLUTION: In a communication system, a resistance generation instruction circuit 307 includes: first identifying means for identifying resistance values of pull-up resistors 306a1, 306a2, ..., 306a(n-1), and 306an according to load capacitance in a communication path for bus communication; second identifying means for identifying resistors that provides the resistance values from among a plurality of resistors; and a select signal generation unit 307a1 as configuration means for causing the resistors identified by the second identifying means to configure resistance of the resistance values.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present disclosure relates to a communication system, a processing method, and a program. [Background technology]

[0002] Among communication systems, there are those that use a switch to switch between connection destinations (communication paths) to perform communication. Patent Document 1 discloses, as a related technique, a technique related to a bus system that performs communication via a bus line. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2003-242048 A Summary of the Invention [Problem to be solved by the invention]

[0004] In a communication system that uses a switch to switch between connection destinations (communication paths), the pull-up resistor that holds the communication path at a high potential is generally a fixed value. When using a switch to switch between connection destinations (communication paths), the load capacity differs for each communication path, and the margin for communication errors also differs. As a result, communication errors are more likely to occur depending on the communication path.

[0005] Therefore, in a communication system, there is a demand for a technique that can reduce the occurrence of communication errors even when a communication connection destination (that is, a communication path) is changed and the load capacity is changed.

[0006] An object of each aspect of the present disclosure is to provide a communication system, a processing method, and a program that can solve the above-mentioned problems. [Means for solving the problem]

[0007] In order to achieve the above object, according to one aspect of the present disclosure, a communication system includes: The present invention is provided with a first specifying means for specifying a resistance value of a pull-up resistor according to a load capacitance in a communication path for bus communication, a second specifying means for specifying a resistor that realizes the resistance value by combining a plurality of resistors from among the plurality of resistors, and a configuring means for configuring a resistor with the resistance value using a control signal for combining the resistors specified by the second specifying means. .

[0008] In order to achieve the above object, according to another aspect of the present disclosure, A processing method executed by a communication system, the method including: identifying a resistance value of a pull-up resistor according to a load capacity in a communication path for bus communication; identifying a resistor that realizes the resistance value by combining a plurality of resistors from among the plurality of resistors; and configuring a resistor with the resistance value using a control signal for combining the identified resistors. .

[0009] In order to achieve the above object, according to another aspect of the present disclosure, a program includes: The present invention allows a computer to execute the following: specifying a resistance value of a pull-up resistor according to a load capacitance in a communication path for bus communication; specifying a resistor from among a plurality of resistors that realizes the resistance value by combining the plurality of resistors; and configuring a resistor with the resistance value using a control signal for combining the specified resistors. . Effect of the Invention

[0010] According to each aspect of the present disclosure, even when a communication connection destination (that is, a communication path) is changed and the load capacity is changed, the occurrence of communication errors can be reduced. [Brief description of the drawings]

[0011] [Figure 1] FIG. 1 is a diagram illustrating an example of a configuration of a communication system according to an embodiment of the present disclosure. [Diagram 2] FIG. 2 is a diagram illustrating an example of a table TBL0 according to an embodiment of the present disclosure. [Diagram 3] FIG. 2 is a diagram illustrating an example of a table TBL1 according to an embodiment of the present disclosure. [Figure 4] FIG. 2 is a diagram illustrating an example of a processing flow of a communication system according to an embodiment of the present disclosure. [Diagram 5] FIG. 1 is a diagram illustrating a minimum configuration of a communication system according to an embodiment of the present disclosure. [Figure 6] FIG. 11 is a diagram illustrating an example of a processing flow of a communication system having a minimum configuration according to an embodiment of the present disclosure. [Figure 7] FIG. 1 is a schematic block diagram illustrating a configuration of a computer according to at least one embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0012] Hereinafter, the embodiments will be described in detail with reference to the drawings. <Embodiment> Fig. 1 is a diagram illustrating an example of a configuration of a communication system 1 according to an embodiment of the present disclosure. As shown in Fig. 1, the communication system 1 includes boards 10a, 10b, 10c, and 10d, cables 20a, 20b, 20c, and 20d, and a board 30. The boards 10a, 10b, 10c, and 10d are collectively referred to as boards 10. The cables 20a, 20b, 20c, and 20d are collectively referred to as cables 20.

[0013] As shown in FIG. 1, the board 10a includes devices 101a1 and 101a2, a terminal 102a, and a pull-up resistor 103a. Each of the devices 101a1 and 101a2 is a slave device that performs I2C communication with the board 30 via an Inter-Integrated Circuit (I2C) bus. The terminal 102a is connected to the devices 101a1 and 101a2, and the pull-up resistor 103a. The terminal 102a is also connected to the board 30 via a cable 20a. The pull-up resistor 103a holds the potential of the terminal 102a at a high potential. The location of the board 10a is A0.

[0014] As shown in FIG. 1, the board 10b includes devices 101b1 and 101b2, a terminal 102b, and a pull-up resistor 103b. Each of the devices 101b1 and 101b2 is a slave device that performs I2C communication with the board 30 via the I2C bus. The terminal 102b is connected to the devices 101b1 and 101b2, and the pull-up resistor 103b. The terminal 102b is also connected to the board 30 via a cable 20b. The pull-up resistor 103b holds the potential of the terminal 102b at a high potential. The location of the board 10b is A1.

[0015] As shown in FIG. 1, the board 10c includes devices 101c1 and 101c2, a terminal 102c, and a pull-up resistor 103c. Each of the devices 101c1 and 101c2 is a slave device that performs I2C communication with the board 30 via the I2C bus. The terminal 102c is connected to the devices 101c1 and 101c2, and the pull-up resistor 103c. The terminal 102c is also connected to the board 30 via a cable 20c. The pull-up resistor 103c holds the potential of the terminal 102c at a high potential. The location of the board 10c is A2.

[0016] As shown in FIG. 1, the board 10d includes devices 101d1, 101d2, 101d3, and 101d4, a terminal 102d, and a pull-up resistor 103d. Each of the devices 101d1, 101d2, 101d3, and 101d4 is a slave device that performs I2C communication with the board 30 via the I2C bus. The terminal 102d is connected to the devices 101d1, 101d2, 101d3, and 101d4, and the pull-up resistor 103d. The terminal 102d is also connected to the board 30 via a cable 20d. The pull-up resistor 103d holds the potential of the terminal 102d at a high potential. The location of the board 10d is B.

[0017] The cable 20a connects the board 10a to the board 30. Specifically, the cable 20a connects the terminal 102a to a terminal 301a of the board 30, which will be described later.

[0018] The cable 20b connects the board 10b to the board 30. Specifically, the cable 20b connects the terminal 102b to a terminal 301b of the board 30, which will be described later.

[0019] The cable 20c connects the board 10c to the board 30. Specifically, the cable 20c connects the terminal 102c to a terminal 301c of the board 30, which will be described later.

[0020] The cable 20d connects the board 10d to the board 30. Specifically, the cable 20d connects the terminal 102d to a terminal 301d of the board 30, which will be described later.

[0021] 1, the board 30 includes terminals 301a, 301b, 301c, 301d, bus selectors 302a, 302b, 302c, bus switches 303a, 303b, an inverter circuit 304, a resistor combiner 305, pull-up resistors 306a1, 306a2, . . . , 306a(n-1), 306an, a resistor generation instruction circuit 307, a device configuration unit 308, and a bus master 309. The bus selectors 302a, 302b, 302c are collectively referred to as bus selector 302. The bus switches 303a, 303b are collectively referred to as bus switch 303.

[0022] The terminal 301a is connected to a P0 terminal (to be described later) of the bus selector 302b and a P0 terminal (to be described later) of the bus selector 302c via a wire A. The terminal 301a is also connected to a terminal 102a of the board 10a via a cable 20a.

[0023] The terminal 301b is connected to a P1 terminal (to be described later) of the bus selector 302b and a P1 terminal (to be described later) of the bus selector 302c via a wire B. The terminal 301b is also connected to a terminal 102b of the board 10b via a cable 20b.

[0024] The terminal 301c is connected to a P2 terminal (to be described later) of the bus selector 302b and a P2 terminal (to be described later) of the bus selector 302c via a wire C. The terminal 301c is also connected to a terminal 102c of the board 10c via a cable 20c.

[0025] The terminal 301d is connected to a P3 terminal (to be described later) of the bus selector 302b and a P3 terminal (to be described later) of the bus selector 302c via a wire D. The terminal 301d is also connected to a terminal 102d of the board 10d via a cable 20d.

[0026] Each of the bus selectors 302 outputs a signal from one of the terminals P0, P1, P2, and P3 in response to an input signal, thereby selecting a bus for propagating the signal.

[0027] Specifically, the bus selector 302a receives a signal from the bus master 309 and outputs a signal from one of terminals P0, P1, P2, and P3 of the bus selector 302a. The terminal P0 of the bus selector 302a is connected to the bus switches 303a and 303b, the resistor combiner 305, and a bus state determination unit 307a3 (described later) of the resistor generation instruction circuit 307.

[0028] Specifically, the bus selector 302b receives a signal from the bus switch 303a and outputs the signal from one of the terminals P0, P1, P2, and P3 of the bus selector 302b. Specifically, the bus selector 302c receives a signal from the bus switch 303b and outputs the signal from one of the terminals P0, P1, P2, and P3 of the bus selector 302c.

[0029] Each of the bus switches 303 receives an input of a signal corresponding to a bus enable signal output by a bus switch switching circuit 307a2 (described later) of the resistance generation instruction circuit 307. Then, each of the bus switches 303 connects or disconnects the bus in response to the input signal.

[0030] Specifically, the bus switch 303a directly inputs the bus enable signal output by the bus switch switching circuit 307a2, and connects or disconnects the bus according to the input bus enable signal. Also, specifically, the bus switch 303b inputs the bus enable signal output by the bus switch switching circuit 307a2 via the inversion circuit 304, and connects or disconnects the bus according to the input signal. That is, the bus switches 303a and 303b receive mutually inverted signals as signals according to the bus enable signal. Therefore, when the bus switch 303a connects the bus, the bus switch 303b disconnects the bus. Also, when the bus switch 303b connects the bus, the bus switch 303a disconnects the bus. As a result, when the bus switch 303a connects the bus, the signal propagating through the bus is input to the bus selector 302b, but is not input to the bus selector 302c. Furthermore, when the bus switch 303b connects the buses, a signal propagating through the bus is input to the bus selector 302c but is not input to the bus selector 302b.

[0031] The inversion circuit 304 inverts the input signal and outputs the inversion signal. The inversion circuit 304 is provided between the bus switch changeover circuit 307a2 and the bus switch 303b, as shown in FIG.

[0032] 1, the resistance combiner 305 includes bus switches 305a1, 305a2, . . . , 305a(n-1), and 305an. The bus switches 305a1, 305a2, . . . , 305a(n-1), and 305an are collectively referred to as bus switches 305a.

[0033] Each of the bus switches 305a receives a select signal output by a select signal generating unit 307a1 (described later) of the resistor generation instruction circuit 307. Each of the bus switches 305a connects or disconnects the bus in response to the received select signal. Note that the select signal is a signal corresponding to the resistor to be generated, and an individual signal corresponding to each of the bus switches 305a is input to each of the bus switches 305a.

[0034] An input of each of the bus switches 305a is connected to a terminal P0 of the bus selector 302a. A pull-up resistor 306a1 is connected to the output of the bus switch 305a1, a pull-up resistor 306a2 is connected to the output of the bus switch 305a2, a pull-up resistor 306a(n-1) is connected to the output of the bus switch 305a(n-1), and a pull-up resistor 306an is connected to the output of the bus switch 305an.

[0035] A select signal corresponding to the resistance to be generated is input to each of the bus switches 305a, and each of the bus switches 305a connects or disconnects the bus in response to the select signal, so that the resistance generated by the pull-up resistors 306a1 to 306an becomes a resistance having a desired resistance value.

[0036] The pull-up resistors 306a1, 306a2, . . . , 306a(n-1), and 306an are connected or disconnected to each other in response to the bus connection or bus disconnection by the bus switch 305a, respectively, to become resistors having a desired resistance value. The pull-up resistors 306a1, 306a2, . . . , 306a(n-1), and 306an are collectively referred to as pull-up resistors 306a. Each of the pull-up resistors 306a has a resistance value that is an element of a resistor having a desired resistance value, and the resistance value of each of the pull-up resistors 306a is determined to generate a resistor having the desired resistance value. Note that the resistance values ​​of each of the pull-up resistors 306a may be the same or different as long as a resistor having the desired resistance value can be generated.

[0037] As shown in FIG. 1, the resistance generation instruction circuit 307 includes a select signal generating unit 307a1 (an example of a first determination means, an example of a second determination means, and an example of a configuration means), a bus switch switching circuit 307a2 (an example of a switching means), a bus state determination unit 307a3 (an example of a determination means), and a memory unit 307a4.

[0038] The select signal generating unit 307a1 generates a select signal that causes the resistance generated by the pull-up resistors 306a1 to 306an to have a desired resistance value. The select signal generating unit 307a1 then outputs the generated select signal to the resistor combiner 305.

[0039] The bus switch switching circuit 307a2 receives the determination result of whether or not a bus has stalled from the bus state determination unit 307a3. Then, the bus switch switching circuit 307a2 generates a bus valid signal for switching between the bus selector 302b and the bus selector 302c based on the received determination result. The bus switch switching circuit 307a2 outputs the generated bus valid signal to the bus switch 303a and the inverter circuit 304.

[0040] The bus state determination unit 307a3 constantly monitors the state of the bus. In addition, the bus state determination unit 307a3 recognizes whether the bus selector 302b or 302c is selected. The bus state determination unit 307a3 determines whether a bus selector constituting a part of the current path (i.e., either one of the bus selectors 302b and 302c) has stalled. If the bus state determination unit 307a3 determines that a bus selector has stalled, it outputs an instruction to the bus switch switching circuit 307a2 to switch to a bus selector (i.e., the bus selector 302b or 302c) other than the bus selector constituting a part of the current path.

[0041] The storage unit 307a4 stores various information necessary for the processing performed by the resistance generation instruction circuit 307. For example, the storage unit 307a4 stores a table TBL0 and a table TBL1. The table TBL0 is a table that defines the correspondence between all connection destinations (paths) and the optimum resistance value for each connection destination. FIG. 2 is a diagram showing an example of the table TBL0 in an embodiment of the present disclosure. As shown in FIG. 2, in the table TBL0, for example, as connection 1, the connection destinations are stored in the order of the bus master 309 (described as [bus master] in FIG. 2), the bus selector 302a (described as [bus SEL(A)] in FIG. 2), the bus switch 303a (described as [bus SW(A)] in FIG. 2), the bus selector 302b (described as [bus SEL(B)] in FIG. 2), and the board 10a (described as [board A (location: A0)] in FIG. 2), and 2.4 kΩ is associated with and stored as the optimum resistance value for the connection destination.

[0042] Table TBL1 is a table that defines the correspondence between each connection destination, an optimum resistance value for each connection destination, and a combination of resistors for realizing the optimum resistance value (i.e., a combination of pull-up resistors 306a1-306an). Fig. 3 is a diagram showing an example of table TBL1 in an embodiment of the present disclosure. As shown in Fig. 3, table TBL1 contains, for example, connection 1, an optimum resistance value of 2.4 kΩ for connection 1, and a combination of resistors for realizing the resistance value, 4 kΩ+6 kΩ (parallel connection of 4 kΩ and 6 kΩ).

[0043] The device configuration unit 308 recognizes all current connection states of the I2C bus in the communication system 1. Then, the device configuration unit 308 outputs all current connection states of the I2C bus in the communication system 1 to the resistor generation instruction circuit 307. The device configuration unit 308 also instructs the resistor generation instruction circuit 307 to update tables TBL0 and TBL1. The device configuration unit 308 is a control unit that instructs the generation of resistors having optimal pull-up resistance values.

[0044] The bus master 309 is an I2C bus master controller and communicates with the devices 101a1, 101a2, 101b1, 101b2, 101c1, 101c2, 101d1, 101d2, 101d3, and 101d4, which are slave devices provided on the board 10.

[0045] The above-described processing performed by each processing unit in the communication system 1 is merely an example and is not limited to the above-described processing. For example, the processing unit may perform processing shown in the processing of the communication system 1 described below.

[0046] Next, a process performed by the communication system 1 according to an embodiment of the present disclosure will be described. FIG. 4 is a diagram showing an example of a process flow of the communication system 1 according to an embodiment of the present disclosure. Here, the process performed by the communication system 1 will be described with reference to FIG. 4. It is assumed that the load capacities of the cables 20a, 20b, 20c, and 20d are all different. That is, it is assumed that the load capacities for the output terminals of the bus selectors 302b and 302c are different. In addition, the process of the communication system 1 will be described here by taking as an example a case where the bus master 309 of the board 30 communicates with the device 101a1 of the board 10a. Specifically, in the communication system 1, when the bus master 309 of the board 30 communicates with the device 101a1 of the board 10a via the bus selector 302c, the bus selector 302c stalls, and the path is changed to the path of the bus master 309-bus selector 302a-bus switch 303a-bus selector 302b-board 10a (path 1 in the table TBL0 of FIG. 2) that communicates via the bus selector 302b. In this case, the bus selector 302a outputs a signal from the terminal P0 of the bus selector 302a. Also, the bus selector 302b outputs a signal from the terminal P0 of the bus selector 302b. Also, the bus switch changeover circuit 307a2 outputs a bus enable signal to the bus switch 303a and the inversion circuit 304, which causes the bus switch 303a to connect the bus and the bus switch 303b to disconnect the bus.

[0047] When the bus master 309 of the board 30 communicates with the device 101a1 of the board 10a, the device configuration unit 308 recognizes all current connection states of the I2C bus in the communication system 1 (step S1). Then, the device configuration unit 308 outputs all current connection states of the I2C bus in the communication system 1 to the resistor generation instruction circuit 307. The bus state determination unit 307a3 determines whether the bus selector 302c has stalled (step S2). When the bus state determination unit 307a3 determines that the bus selector 302c has not stalled (NO in step S2), the process returns to step S2. When the bus state determination unit 307a3 determines that the bus selector 302c has stalled (YES in step S2), the bus state determination unit 307a3 outputs an instruction to switch the bus selector (i.e., switch from the bus selector 302c to the bus selector 302b) to the bus switch switching circuit 307a2.

[0048] The bus switch switching circuit 307a2 receives the determination result of whether or not a stall has occurred from the bus state determination unit 307a3. Then, the bus switch switching circuit 307a2 generates a bus enable signal for switching the bus selector 302c to the bus selector 302b based on the received determination result (step S3). The bus switch switching circuit 307a2 outputs the generated bus enable signal to the bus switch 303a and the inversion circuit 304. As a result, the communication path in the communication system 1 becomes the path of the bus master 309-bus selector 302a-bus switch 303a-bus selector 302b-board 10a (path 1 in table TBL0 in FIG. 2).

[0049] The device configuration unit 308 recognizes all current connection states of the I2C bus in the communication system 1, including the new path (step S4). The device configuration unit 308 outputs the current connection states, including the new path, to the resistance generation instruction circuit 307.

[0050] The select signal generating unit 307a1 generates a select signal that causes the resistance generated by the pull-up resistors 306a1-306an to have a desired resistance value based on the current path including the new path output by the device configuration unit 308. For example, the select signal generating unit 307a1 specifies an optimal resistance value corresponding to the current path including the new path in the table TBL0 (step S5). In the example shown here, the select signal generating unit 307a1 specifies the path 1 that matches the current path including the new path in the table TBL0 of FIG. 2, and specifies a resistance value of 2.4 kΩ associated with the path 1. The select signal generating unit 307a1 specifies a combination of the pull-up resistors 306a1-306an associated with the specified resistance value in the table TBL1 (step S6). In the example shown here, the select signal generating unit 307a1 specifies a combination of resistance values ​​that realizes a resistance value of 2.4 kΩ associated with the path 1 in the table TBL1 of FIG. 2, that is, a combination of the pull-up resistors 306a1-306an. Then, the select signal generating unit 307a1 generates a select signal that realizes the identified combination of the pull-up resistors 306a1 to 306an (step S7).

[0051] Each of the bus switches 305a receives the select signal output by the select signal generating unit 307a1, and connects or disconnects the bus in response to the received select signal (step S8).

[0052] As described above, a select signal corresponding to the resistance to be generated is input to each of the bus switches 305a, and each of the bus switches 305a connects or disconnects the bus in response to the select signal, so that the resistance generated by the pull-up resistors 306a1 to 306an becomes a resistance having a desired resistance value.

[0053] (advantage) As described above, in the communication system 1, the select signal generating unit 307a1 (an example of a first specifying means) specifies a resistance value of a pull-up resistor according to a load capacitance in a communication path for bus communication. Furthermore, the select signal generating unit 307a1 (an example of a second specifying means) specifies a resistor that realizes the resistance value from among a plurality of resistors. Furthermore, the select signal generating unit 307a1 (an example of a configuring means) configures a resistor with the resistance value in the specified resistor. In this way, even if the communication connection destination (i.e., the communication path) is changed and the load capacitance is changed, the occurrence of communication errors can be reduced.

[0054] In addition, in the communication system 1, the bus state determination unit 307a3 (an example of a determination means) determines whether or not the bus in the communication path has stalled based on the connection state of the communication path. In response to this, as described above, the select signal generation unit 307a1 configures a resistor with the resistance value. In this way, the communication system 1 can restore the bus by switching the switch bus without performing processes such as resetting the bus or various reconfigurations, and it becomes possible to shorten the time until restoration.

[0055] 5 is a diagram illustrating a minimum configuration of a communication system 1 according to an embodiment of the present disclosure. As shown in FIG. 5, the communication system 1 includes a select signal generating unit 307a1 (an example of a first specifying means, an example of a second specifying means, and an example of a configuring means). The select signal generating unit 307a1 specifies a resistance value of a pull-up resistor according to a load capacitance in a communication path for bus communication. The select signal generating unit 307a1 specifies a resistor that realizes the resistance value from among a plurality of resistors. The select signal generating unit 307a1 causes the specified resistor to configure a resistor with the resistance value.

[0056] 6 is a diagram showing an example of a processing flow of the communication system 1 having a minimum configuration according to the embodiment of the present disclosure. Next, the processing of the communication system 1 having a minimum configuration according to the embodiment of the present disclosure will be described with reference to FIG.

[0057] The select signal generating unit 307a1 specifies a resistance value of a pull-up resistor according to a load capacitance in a communication path for bus communication (step S101). The select signal generating unit 307a1 specifies a resistor that realizes the resistance value from among a plurality of resistors (step S102). The select signal generating unit 307a1 causes the specified resistor to configure a resistor with the resistance value (step S103).

[0058] The above describes the communication system 1 with a minimum configuration according to an embodiment of the present disclosure. With this communication system 1, even if the communication connection destination (i.e., the communication path) is changed and the load capacity is changed, the occurrence of communication errors can be reduced.

[0059] It should be noted that the order of the processes in the embodiments of the present disclosure may be changed as long as appropriate processes are performed.

[0060] Although the embodiment of the present disclosure has been described, the above-mentioned communication system 1, boards 10, 30, and other control devices may have a computer system inside. The above-mentioned process steps are stored in a computer-readable recording medium in the form of a program, and the above-mentioned process is performed by the computer reading and executing the program. Specific examples of computers are shown below.

[0061] 7 is a schematic block diagram showing the configuration of a computer according to at least one embodiment. As shown in FIG. 7, the computer 5 includes a CPU 6, a main memory 7, a storage 8, and an interface 9.

[0062] For example, the above-mentioned communication system 1, boards 10, 30, and other control devices are each implemented in a computer 5. The operations of the above-mentioned processing units are stored in the storage 8 in the form of a program. The CPU 6 reads the program from the storage 8, loads it in the main memory 7, and executes the above-mentioned processes according to the program. The CPU 6 also secures storage areas in the main memory 7 corresponding to the above-mentioned storage units according to the program.

[0063] Examples of the storage 8 include a hard disk drive (HDD), a solid state drive (SSD), a magnetic disk, a magneto-optical disk, a compact disc read only memory (CD-ROM), a digital versatile disc read only memory (DVD-ROM), and a semiconductor memory. The storage 8 may be an internal medium directly connected to the bus of the computer 5, or an external medium connected to the computer 5 via an interface 9 or a communication line. In addition, when the program is distributed to the computer 5 via a communication line, the computer 5 that receives the program may load the program into the main memory 7 and execute the above-mentioned process. In at least one embodiment, the storage 8 is a non-transitory tangible storage medium.

[0064] The program may also realize some of the functions described above. Furthermore, the program may be a file that can realize the functions described above in combination with a program already recorded in the computer system, that is, a so-called differential file (differential program).

[0065] Although some embodiments of the present disclosure have been described, these embodiments are merely examples and do not limit the scope of the disclosure. Various additions, omissions, substitutions, and modifications may be made to these embodiments without departing from the spirit of the disclosure.

[0066] Note that some or all of the above-described embodiments can be described as, but are not limited to, the following supplementary notes.

[0067] (Appendix 1) a first specifying means for specifying a resistance value of a pull-up resistor according to a load capacitance in a communication path for performing bus communication; A second specifying means for specifying a resistor that realizes the resistance value from among a plurality of resistors; A configuration means for configuring a resistor having the resistance value in the resistor specified by the second specification means; A communication system comprising:

[0068] (Appendix 2) a determination means for determining whether or not a bus in the communication path has stalled based on a connection state in the communication path; 2. The communication system of claim 1, comprising:

[0069] (Appendix 3) a switching means for switching to a spare communication path when the determining means determines that the bus has stalled; 3. The communication system according to claim 2, comprising:

[0070] (Appendix 4) The spare communication path is A bus switch and a bus selector are provided. 4. A communication system as described in claim 3.

[0071] (Appendix 5) A processing method executed by a communication system, comprising: Specifying a resistance value of a pull-up resistor according to a load capacitance in a communication path for performing bus communication; Identifying a resistor that realizes the resistance value from among a plurality of resistors; configuring the identified resistor with a resistance of said resistance value; A processing method comprising:

[0072] (Appendix 6) On the computer, Specifying a resistance value of a pull-up resistor according to a load capacitance in a communication path for performing bus communication; Identifying a resistor that realizes the resistance value from among a plurality of resistors; configuring the identified resistor with a resistance of said resistance value; A program that executes the following. [Explanation of symbols]

[0073] 1. Communication systems 5. Computers 6. CPU 7. Main memory 8. Storage 9. Interface 10, 30... Board 20 Cable 101···Device 102, 301... Terminal 103, 306... Pull-up resistor 302 Bus selector 303, 305a Bus switch 304...Inverting circuit 305...Resistance combiner 307...Resistance generation instruction circuit 307a1···Select signal generator 307a2 Bus switch switching circuit 307a3 Bus status determination unit 308...Equipment component 309... Bus Master

Claims

1. a first specifying means for specifying a resistance value of a pull-up resistor according to a load capacitance in a communication path for performing bus communication; a second specifying means for specifying, from among the plurality of resistors, a resistor that realizes the resistance value by combining the plurality of resistors; a configuration means for configuring a resistor having the resistance value by using a control signal for combining the resistors specified by the second specification means; A communication system comprising:

2. a determination means for determining whether or not a bus in the communication path has stalled based on a connection state in the communication path; The communication system of claim 1 .

3. a switching means for switching to a spare communication path when the determining means determines that the bus has stalled; The communication system of claim 2 .

4. The spare communication path is A bus switch and a bus selector are provided. The communication system according to claim 3.

5. A processing method executed by a communication system, comprising: Specifying a resistance value of a pull-up resistor according to a load capacitance in a communication path for performing bus communication; identifying a resistor from among the plurality of resistors that achieves the resistance value by combining the plurality of resistors; configuring a resistor of said resistance value using a control signal for combining the identified resistors; A processing method comprising:

6. On the computer, Specifying a resistance value of a pull-up resistor according to a load capacitance in a communication path for performing bus communication; identifying a resistor from among the plurality of resistors that achieves the resistance value by combining the plurality of resistors; configuring a resistor of said resistance value using a control signal for combining the identified resistors; A program that executes the following.

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