Magnetic tunnel junction with all-around structure

Abstract

The magnetic tunnel junction (MTJ) device includes a cylindrical pillar structure and a first ferromagnetic layer disposed on at least a portion of the pillar structure. The first ferromagnetic layer exhibits a magnetization that is changeable in the presence of at least one of an applied bias and heat. The MTJ device further includes a dielectric barrier disposed on at least a portion of the first ferromagnetic layer and a second ferromagnetic layer disposed on at least a portion of the dielectric barrier. The second ferromagnetic layer exhibits a fixed magnetization. The MTJ device is configured such that the first and second ferromagnetic layers and the dielectric barrier concentrically surround the pillar structure.

Description

[Technical field]

[0001] The present invention relates generally to electrical, electronic and computer technologies, and more particularly to magnetic tunnel junction structures. [Background technology]

[0002] Magnetic tunnel junctions, or MTJs, are nanostructured devices in the field of magnetoelectronics or spinelectronics (hereafter referred to as spintronics), where the experimental observation of significant large and tunable magnetoresistance (change in material resistance with an external magnetic field) is closely related to the utilization of not only the charge of electrons but also their spin.

[0003] Magnetic tunnel junction (MTJ) devices, the primary storage element of magnetic random access memory (MRAM), are magnetic storage and switching devices in which two ferromagnetic layers are separated by a thin insulating barrier (e.g., aluminum oxide) to form a stack structure. One ferromagnetic layer has a fixed magnetization and is called the fixed or pinned layer, while the other ferromagnetic layer has a changeable magnetization and is called the free layer. When a bias is applied to the MTJ device, electrons spin-polarized by the ferromagnetic layer cross the insulating barrier through a process known as tunneling, generating a current whose magnitude depends on the orientation of the magnetization of the ferromagnetic layer. The MTJ element exhibits low resistance when the magnetic moment of the free layer is parallel to that of the pinned layer and high resistance when the magnetic moment of the free layer is oriented antiparallel to that of the pinned layer.

[0004] The materials and geometry used to build the stack of different layers that form an MTJ device are one of the most important parameters for defining the device's characteristics in terms of speed (i.e., switching time) and power consumption (e.g., voltage or current or both required to switch the device from one state to another). The typical structure of an MTJ is a cylindrical pillar (i.e., a stack of materials) where a current flows from the top layer to the bottom layer or vice versa to switch the magnetization of one ferromagnetic layer, which is called a Spin-Transfer Torque (STT) device. Another form of MTJ is called a Spin-Orbit Torque (SOT) device. In an SOT device, the pillar is cylindrical, but deposited on top of a heavy metal conductor. A current flows horizontally through this conductor, switching the magnetization of the ferromagnetic layers at the interface.

[0005] In both STT and SOT MTJ devices with cylindrical stacks, the surface area of ​​the interface is equal to the area of ​​a circle (A = πr 2 , where A is the area of ​​the interface and r is the radius of the cylindrical stack). Currently, the energy (power × time) required to switch the state of an MTJ device is still relatively large, which is undesirable. Summary of the Invention

[0006] The present invention, as manifested in one or more embodiments, advantageously provides a magnetic tunnel junction (MTJ) structure having an all-around configuration in which the ferromagnetic layer and the barrier layer surround each other rather than being in a stacked arrangement, and a method for fabricating the MTJ structure, which can be formed in a manner consistent with nanowires, advantageously increasing the interfacial area between the free layer and the spin-orbit torque (SOT) metal, thereby improving switching efficiency.

[0007] The present invention provides a structure according to claim 1 and a method according to claim 12.

[0008] The techniques of the present invention can provide substantial beneficial technical effects. By way of example only and not by way of limitation, an MTJ according to one or more embodiments of the present invention can provide one or more of the following advantages: Increased interface area between free layer and SOT metal Faster switching speed Improved power efficiency, and -Improved cell density due to vertical growth of SOT metal

[0009] These and other features and advantages of the present invention will become apparent from the following detailed description of illustrative embodiments thereof, which is to be read in connection with the accompanying drawings. [Brief description of the drawings]

[0010] The following drawings are presented by way of example only and not by way of limitation, and like reference numerals (where used) indicate corresponding elements throughout the several views.

[0011] [Figure 1A] FIG. 1 is a perspective view of at least a portion of a standard spin-orbit torque (SOT) magnetic tunnel junction (MTJ) device. [Figure 1B] FIG. 1 is a perspective view of at least a portion of a standard spin-transfer torque (STT) MTJ device. [Diagram 2] FIG. 2 is a perspective view illustrating at least a portion of an exemplary SOT MTJ device having an all-around structure according to an embodiment of the present invention. [Figure 3A] FIG. 3 is a perspective view of at least a portion of the example SOT MTJ device shown in FIG. 2 conceptually illustrating increased interface area, according to an embodiment of the present invention. [Figure 3B] FIG. 3 is a plan view of at least a portion of the example SOT MTJ device shown in FIG. 2 conceptually illustrating increased interface area in accordance with an embodiment of the present invention. [Figure 4]1A-1D are cross-sectional views illustrating exemplary processing steps / stages in the fabrication of an exemplary MTJ device having an all-around structure according to an embodiment of the present invention. [Diagram 5] 1A-1D are cross-sectional views illustrating exemplary processing steps / stages in the fabrication of an exemplary MTJ device having an all-around structure according to an embodiment of the present invention. [Figure 6] 1A-1D are cross-sectional views illustrating exemplary processing steps / stages in the fabrication of an exemplary MTJ device having an all-around structure according to an embodiment of the present invention. [Figure 7] 1A-1D are cross-sectional views illustrating exemplary processing steps / stages in the fabrication of an exemplary MTJ device having an all-around structure according to an embodiment of the present invention. [Figure 8] 1A-1D are cross-sectional views illustrating exemplary processing steps / stages in the fabrication of an exemplary MTJ device having an all-around structure according to an embodiment of the present invention. [Figure 9] 1A-1D are cross-sectional views illustrating exemplary processing steps / stages in the fabrication of an exemplary MTJ device having an all-around structure according to an embodiment of the present invention. [Figure 10] 1A-1D are cross-sectional views illustrating exemplary processing steps / stages in the fabrication of an exemplary MTJ device having an all-around structure according to an embodiment of the present invention. [Figure 11] 1A-1D are cross-sectional views illustrating exemplary processing steps / stages in the fabrication of an exemplary MTJ device having an all-around structure according to an embodiment of the present invention. [Figure 12] 1A-1D are cross-sectional views illustrating exemplary processing steps / stages in the fabrication of an exemplary MTJ device having an all-around structure according to an embodiment of the present invention. [Figure 13A] 1A-1D are cross-sectional views illustrating exemplary processing steps / stages in the fabrication of an exemplary MTJ device having an all-around structure according to an embodiment of the present invention. [Figure 13B] 1A-1D are cross-sectional views illustrating exemplary processing steps / stages in the fabrication of an exemplary MTJ device having an all-around structure according to an embodiment of the present invention. [Figure 14] 1A-1D are cross-sectional views illustrating exemplary processing steps / stages in the fabrication of an exemplary MTJ device having an all-around structure according to an embodiment of the present invention. [Figure 15] 1A-1D are cross-sectional views illustrating exemplary processing steps / stages in the fabrication of an exemplary MTJ device having an all-around structure according to an embodiment of the present invention. [Figure 16] 1A-1D are cross-sectional views illustrating exemplary processing steps / stages in the fabrication of an exemplary MTJ device having an all-around structure according to an embodiment of the present invention. [Figure 17] 1A-1D are cross-sectional views illustrating exemplary processing steps / stages in the fabrication of an exemplary MTJ device having an all-around structure according to an embodiment of the present invention. [Figure 18] 1A-1D are cross-sectional views illustrating exemplary processing steps / stages in the fabrication of an exemplary MTJ device having an all-around structure according to an embodiment of the present invention. [Figure 19] 1A-1D are cross-sectional views illustrating exemplary processing steps / stages in the fabrication of an exemplary MTJ device having an all-around structure according to an embodiment of the present invention.

[0012] It should be understood that elements in the figures are illustrated for simplicity and clarity. Common but well-understood elements that may be useful or necessary in a commercially viable embodiment may not be shown in the figures so as not to obstruct the view of the illustrated embodiments. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0013] The principles of the present invention are described herein in the context of an exemplary magnetic tunnel junction (MTJ) device, and a method for fabricating an MTJ device, having an all-around structure that beneficially increases the interfacial area between layers, thereby improving switching efficiency, as manifested in one or more embodiments.

[0014] 1A and 1B are perspective views of at least a portion of a standard spin-orbit torque (SOT) magnetic tunnel junction (MTJ) device 100 and a spin-transfer torque (STT) MTJ device 120, respectively. Referring to FIG. 1A, the SOT MTJ device 100 is shown sandwiched between a first conductor 102 and a second conductor 104. The MTJ device 100 is formed as a cylindrical pillar or stack structure including a first ferromagnetic material layer 106, which may be a free layer, in electrical contact with the first conductor 102, a dielectric barrier 108 formed on the first ferromagnetic material layer, and a second ferromagnetic material layer 110, which may be a fixed or pinned layer, formed on the dielectric barrier. As previously mentioned, the fixed layer 110 has a magnetization that is fixed and the free layer 106 has a magnetization that can change in the presence of an applied bias or heat or both. Similarly, as shown in FIG. 1B, the STT MTJ device 120 is formed as a cylindrical pillar / stack structure including a first ferroelectric material layer 126, a dielectric barrier 128 formed on the first ferroelectric material layer, and a second ferroelectric material layer 130 formed on the dielectric barrier.

[0015] Depending on the materials used to form the different layers of the MTJ device and the materials used for the conductors, the free layer can be switched by SOT or STT or both mechanisms. In either case, the switching mechanism is triggered at the interface between two material layers in the stack. Since the stacks forming the MTJ devices 100, 120 are cylindrical, the interface area between any two layers is πr 2 where r is the radius of the stack. The amount of energy required to switch the magnetization of an MTJ device is directly proportional to this interface area.

[0016] To increase the interface area and thereby improve the switching efficiency of the MTJ device, aspects of the present invention as manifested in one or more embodiments thereof beneficially provide an MTJ device having an all-around structure in which the ferromagnetic layer and the barrier layer are not arranged in a stacked arrangement but concentrically surround each other. Figure 2 is a perspective view illustrating at least a portion of an exemplary MTJ device 200 having an all-around structure according to one embodiment of the present invention. The MTJ device 200 uses a SOT-based switching mechanism. Although embodiments of the present invention are not limited to any particular number of material layers, the basic MTJ embodiment shown in FIG. 2 includes, for clarity of explanation, four main layers: a reference ferromagnetic layer 202 having an immutable magnetization (spin up or down), referred to herein as the fixed or pinned layer; a free ferromagnetic layer 204 having a reconfigurable magnetization (e.g., the spin can be flipped to up or down using an applied bias current or voltage or both), referred to herein as the free layer; a barrier 206 disposed between the fixed layer 202 and the free layer 204; and a conductor 208 disposed through the center of the MTJ device 200 such that the fixed and free layers and the barrier concentrically surround the conductor.

[0017] In one or more embodiments, the conductor 208 comprises a SOT metal, which is preferably a heavy metal such as, for example, tungsten (W), platinum (Pt), tantalum (Ta), etc. The conductor 208 may be formed as a thin shell (e.g., about 2-20 nanometers (nm) thick) of SOT metal disposed on an insulator core 210. The insulator core 210 may be a cylindrical central nanowire oriented along a substantially vertical (z-axis) long axis, preferably made of a suitable dielectric material (e.g., silicon dioxide, silicon nitride (SiN), silicon oxynitride (SiO x N y ) etc.), however, embodiments of the present invention are not limited to any particular material or dimensions for the insulator core.

[0018] In one or more embodiments, the free layer 204 may include a suitable magnetic material, such as, for example, cobalt, iron, boron, or combinations thereof, and is disposed on at least a portion of the surface of the conductor 208 and surrounds the conductor in a toroidal fashion. The barrier 206 may be, for example, magnesium oxide (MgO), aluminum oxide (AlO x ), magnesium aluminate or magnesium aluminum oxide (MgAlO x ), or a combination thereof, and is disposed on a surface of the free layer 204 and surrounds the free layer in a toroidal manner. The fixed layer 202, which may include a suitable magnetic material, such as cobalt, iron, boron, platinum, nickel, tungsten, iridium, or a combination thereof, is disposed on a surface of at least a portion of the barrier 206 and surrounds the barrier in a toroidal manner, with the fixed layer 202 being electrically insulated from the free layer 204 by the barrier 206.

[0019] The free layer 204 is a layer that is in direct contact with the SOT conductor 208, thereby forming an interface with the SOT conductor 208. By passing a current through the conductor 208 in one direction or the other, a physical phenomenon occurs at the interface with the free layer 204, which allows the orientation (i.e., direction) of the magnetization of the free layer to be switched depending on the direction of the current. This change in magnetization of the free layer 204 causes the entire MTJ device 200 to exhibit a change in resistance.

[0020] By forming an MTJ device according to an embodiment of the present invention in which the various layers of the MTJ device are arranged concentrically around the central nanowire conductor 208 in an all-around configuration, the interface between adjacent layers is substantially increased compared to the circular area of ​​a conventional MTJ stack. More specifically, referring to Figures 3A and 3B, the interface between the free layer 204 and the conductor 208 follows the circumference of the conductor, so that the area of ​​the interface is 2πr multiplied by the height h of the free layer, where r is the radius of the conductor (i.e., A = 2πrh). Thus, the surface area of ​​the interface between the free layer 204 and the conductor 208, and thus the switching efficiency of the MTJ device, can be controlled as a function of both the radius of the conductor and the height of the free layer, which represents a significantly larger area compared to a standard MTJ stack of comparable dimensions. In addition to providing a substantial increase in the interface area between the free layer 204 and the conductor 208, the circumferential magnetization of the free layer in the all-around structure of the MTJ device 200 advantageously provides improved stability.

[0021] By way of example only and not by way of limitation, FIGS. 4-19 are cross-sectional views illustrating exemplary process steps / stages in the fabrication of an exemplary MTJ device 400 having an all-around structure, according to an embodiment of the present invention. While the overall fabrication method and structures formed thereby are entirely novel, certain individual process steps required to carry out the method may utilize conventional semiconductor fabrication techniques and conventional semiconductor fabrication tools. These techniques and tools will be familiar to those of ordinary skill in the relevant art in view of the teachings herein. Furthermore, many of the process steps and tools used to fabricate semiconductor devices are described in many readily available publications, including, for example, PH Holloway et al., Handbook of Compound Semiconductors: Growth, Processing, Characterization, and Devices, Cambridge University Press, 2008, and RK Willardson et al., Processing and Properties of Compound Semiconductors, Academic Press, 2001, both of which are incorporated herein by reference in their entirety for all purposes. It is emphasized that while several individual process steps are described herein, they are merely exemplary, and that one of ordinary skill in the art would be familiar with several equally suitable alternatives that would also fall within the scope of the present invention.

[0022] It should be understood that the various layers and / or regions illustrated in the accompanying figures may not be drawn to scale. Additionally, one or more semiconductor layers of a type commonly used in such semiconductor devices may not be explicitly shown in a given figure to facilitate a clearer illustration. This does not imply that the semiconductor layers not explicitly shown are omitted in the actual device.

[0023] 4, fabrication of an exemplary all-around MTJ device 400 begins with a complementary metal oxide semiconductor (CMOS) wafer having an nth level of metallization, where n is an integer value representing a particular metallization level within the wafer. The nth level of metallization (Mn level) is formed by depositing a layer of dielectric material 402 (e.g., silicon dioxide (SiO x ), ceramic precursor polyborosilazane (SiBCN), silicon nitride (SiN), or combinations thereof) and Mn metal connections 404 (e.g., tantalum nitride (TaN), titanium nitride (TiN), tungsten (W), copper (Cu), ruthenium (Ru), cobalt (Co), tantalum (Ta), titanium (Ti), or any combinations thereof), which can be patterned using standard lithography and etching. Metal connections 404 can be formed, in one or more embodiments, by etching an opening through the dielectric material layer 402, depositing an optional liner 406 on the sidewalls and bottom of the opening, and filling the opening with metal 406.

[0024] 5 illustrates the formation of a dummy core 500 on the top surface of the metal connection 404. The dummy core 500 is formed, in one or more embodiments, by depositing a layer of dummy amorphous silicon 502, followed by depositing a hard mask layer 504 in a desired pattern over a portion of the top surface of the amorphous silicon layer. The hard mask layer 504 is preferably a silicon oxide compound (SiO x ), although other materials may be used as well (e.g., silicon nitride). The dummy core 500 is then patterned using lithography and anisotropic reactive ion etching (RIE) to form pillars that are preferably substantially cylindrical. In one or more embodiments, the height of the pillars is about 50-200 nm and the diameter of the pillars is about 20-100 nm, although embodiments of the present invention are not limited to any particular dimensions.

[0025] 6, the main layers of the MTJ device are deposited. Specifically, a thin layer of SOT metal 602 is deposited on at least a portion of the top surface of the dielectric material layer 402 and on the dummy core 500, including the sidewalls of the amorphous silicon 502 pillars and the sidewalls and top surface of the hard mask layer 504. A free layer 604 is then deposited on at least a portion of the top surface of the SOT metal layer 602, a tunnel barrier 606 is deposited on at least a portion of the top surface of the free layer 604, and a reference (i.e., fixed or pinned) layer 608 is deposited on at least a portion of the top surface of the tunnel barrier 606. In one or more embodiments, the SOT metal layer 602 comprises tungsten having a deposition thickness of about 2-20 nm, the free layer 604 comprises cobalt, iron, boron, or a combination thereof having a deposition thickness of about 2-10 nm, and the tunnel barrier 606 is deposited on at least a portion of the top surface of the tunnel barrier 606. x ), magnesium aluminate (MgAlO x ) or a combination thereof and having a deposition thickness of about 0.4-2 nm, and the reference layer 608 includes cobalt, iron, boron, platinum, nickel, tungsten, iridium, or a combination thereof and has a deposition thickness of about 5-50 nm. However, it should be understood that embodiments of the present invention are not limited to any particular material type or dimensions for the various MTJ device layers.

[0026] A metal hardmask layer 610 is then deposited on at least a portion of the top surface of the reference layer 608. The metal hardmask layer 610, in one or more embodiments, preferably comprises, for example, titanium nitride (TiN), tantalum nitride (TaN), ruthenium, or a combination thereof, and has a deposition thickness of about 5-30 nm. Each of the MTJ device layers 604, 606, 608, the SOT metal layer 602, and the hardmask layer 610 can be formed using known deposition techniques, including, but not limited to, sputtering, atomic layer deposition (ALD), plasma-enhanced ALD, or a combination thereof. The MTJ device layers 604, 606, 608, the SOT metal layer 602, and the hardmask layer 610 surrounding the amorphous silicon pillar 502 form the resulting MTJ stack.

[0027] 7, the portions of the hard mask layer 610 disposed on the horizontal surfaces of the MTJ structure are removed, for example, using a directional etch or chemical mechanical polishing or planarization (CMP), leaving the hard mask layer 610 on the vertical sidewalls of the MTJ stack. A dummy dielectric layer 702 is then formed on the horizontal surfaces of the MTJ structure, including at least a portion of the top surface of the dielectric material layer 402 and the top surface of the MTJ stack (i.e., capping the SOT metal layer 602, the MTJ device layers 604, 606, 608, and the hard mask layer 610). In one or more embodiments, the dummy dielectric layer 702 is formed, for example, using a directional deposition of a dielectric material (e.g., silicon nitride) followed by an isotropic etch to remove the dielectric material deposited on the vertical surfaces (e.g., sidewalls) of the MTJ stack. The final thickness of the structure is greater than the thickness of the MTJ stack (e.g., about 20-50 nm).

[0028] 8 illustrates the deposition of a conformal dielectric layer 802 covering the top surface of the MTJ structure, including the top surface of the dielectric material layer 402 and the top surface of the dummy dielectric layer 702 formed on the top surface of the MTJ stack, and the sidewalls 610 of the MTJ stack. The conformal dielectric layer 802 may be, for example, SiO x , SiBCN, etc., and serves primarily to protect the metal hardmask layer 610 in subsequent processing steps. The conformal dielectric layer 802 is preferably about 30-100 nm thick, although embodiments of the present invention are not limited to any particular dimensions for the conformal dielectric layer.

[0029] Next, as shown in FIG. 9, RIE is performed to remove portions of the conformal dielectric layer 802 on the horizontal surfaces of the MTJ structure, including the conformal dielectric layer disposed on the top surface of the MTJ stack and at least a portion of the conformal dielectric layer formed on the top surface of the dummy dielectric layer 702. The remaining portions of the conformal dielectric layer 802 disposed on the sidewalls of the MTJ stack are recessed, for example, using an anisotropic (i.e., directional) etch, thereby exposing the portion of the dummy dielectric layer 702 formed on the top surface of the MTJ stack and the top of the hard mask layer 610 disposed on the sidewalls of the MTJ stack. This RIE of the conformal dielectric layer 802 can be performed in a manner consistent with a CMOS spacer process. In one or more embodiments, the conformal dielectric layer 802 is recessed to approximately 30-100 nm, although embodiments of the present invention are not limited to any particular dimension of the conformal dielectric layer.

[0030] In Fig. 10, selective anisotropic RIE is performed to remove a portion of the dummy dielectric layer 702. Specifically, the dummy dielectric layer 702 capping the top surface of the MTJ stack and the portion of the dummy dielectric layer formed on the dielectric material layer 402 that is not covered by the conformal dielectric layer 802 are removed. Then, as shown in Fig. 11, selective isotropic RIE is performed to remove the remaining dummy dielectric layer 702 disposed under the conformal dielectric layer 802.

[0031] 12, an isotropic etch is performed to remove portions of the metal hardmask layer 610 that are not protected by the conformal dielectric layer 802. In one or more embodiments, the isotropic etch can be accomplished using, for example, RIE or a wet etch or a combination of RIE and wet etch.

[0032] As shown in Figures 13A and 13B, isotropic etching of the MTJ stack with cyclic oxidation / removal is performed, for example, using RIE only and RIE and organic wet etching to remove portions of the MTJ device layers 604, 606, and 608 that are not protected by the hard mask layer 610. Alternatively, highly-angled ion beam etching can be used to remove portions of the MTJ device layers to obtain a slightly different profile (not explicitly shown). In one or more embodiments, as shown in Figure 13A, the etching process can be terminated using the SOT metal layer 602 as an etch stop layer. In this embodiment, the SOT metal layer 602 remains essentially intact. In an alternative embodiment, the SOT metal layer 602 can be etched together with the MTJ device layers 604, 606, 608, leaving only the SOT metal layer protected by the hard mask layer 610, as shown in Figure 13B. The processing steps that follow are described with reference to the embodiment shown in FIG. 13B, although each of these processing steps also applies to the embodiment shown in FIG. 13A as well, as will be apparent to one of ordinary skill in the art.

[0033] 14, an encapsulating dielectric layer 1402 is formed over at least a portion of the dielectric material layer 402, completely surrounding the MTJ device structure. The encapsulating dielectric layer 1402 may include silicon nitride, although other dielectric materials may be used as well. Optionally, one or more interlayer dielectric (ILD) structures 1404 may be formed within the encapsulating dielectric layer 1402 to electrically isolate the MTJ device from adjacent conductive structures and / or devices. The ILD structures 1404 may be, for example, SiO x , SiBCN, SiN, or combinations thereof, although embodiments of the present invention are not limited to any particular dielectric material. In one or more embodiments, CMP is then performed to planarize the top surface of the MTJ structure. CMP can be performed until at least a portion of the top surface of the hard mask layer 504 is exposed.

[0034] 15, the dummy core (500), including the hard mask layer and the dummy amorphous silicon pillars (504 and 502, respectively, in FIG. 5), is removed leaving an opening 1502 through which the top surface of the underlying metal contact 404 and the vertical walls of the SOT metal 602 are exposed. In one or more embodiments, as known to those skilled in the art, the dummy core is removed using a known etching process, such as, but not limited to, RIE, wet etching, or a combination thereof, for example, using tetramethylammonium hydroxide (TMAH), dilute hydrofluoric acid (DHF), or similar etchants, thereby forming the opening 1502.

[0035] 16, a layer of SOT metal 1606 is deposited on the sidewalls and bottom of the opening 1502, thereby effectively lining the interior surface of the opening. With the SOT metal 602 and metal connection 404 exposed, the SOT metal layer 1602 is electrically connected to the SOT metal 602 and metal connection 404, thereby forming a SOT metal extension within the opening 1502. The SOT metal extension 1602 essentially forms a via that provides electrical contact with the underlying metal connection 404. In one or more embodiments, the SOT metal extension 1602 comprises tungsten having a thickness of about 2-5 nm, although embodiments of the invention are not limited to any particular metal type or dimensions. Once the SOT metal extension 1602 is formed, the opening 1502 is filled with a core dielectric material 1604 and planarized using CMP or a similar planarization / polishing process such that the SOT metal extension and core dielectric material are substantially flush with the top surface of the encapsulating dielectric layer 1402.

[0036] A photoresist layer 1702 is formed over the semiconductor wafer, including over at least a portion of the encapsulating dielectric layer 1402, the ILD structure 1404, the SOT metal extension 1602, and the top surface of the core dielectric material 1604. The photoresist layer 1702 is then patterned using standard lithography and etching to form at least one opening 1704 through the photoresist layer and at least partially through the encapsulating dielectric layer 1402. In the process of forming the opening 1704, which in one or more embodiments is accomplished using ILD RIE and oxide RIE or the like, the conformal dielectric layer 802 on at least one side of the MTJ device is removed, thereby exposing at least a portion of the adjacent metal hardmask layer 610 on which the conformal dielectric layer was formed through the sidewall of the opening 1704. The opening 1704 is then used to form the MTJ device contact. Although only one MTJ device contact is shown in this exemplary embodiment, it should be understood that in one or more embodiments, multiple MTJ device contacts can be formed. One advantage of forming multiple MTJ device contacts is that they can be shared or isolated.

[0037] 18 illustrates the fabrication of an MTJ device contact 1802, which in one or more embodiments is preferably formed using a contact metallization process. During the metallization process, a metal layer 1802 is deposited over at least a portion of the wafer, filling the opening 1704. The metal layer 1802 may include, for example, Ta, Ti, TaN, TiN, W, Ru, Co, Cu, or combinations thereof, although embodiments of the present invention are not limited to any particular metal forming the metal layer. The metal layer 1802 provides electrical contact with the metal hardmask layer 610, and is therefore referred to as an MTJ device contact.

[0038] Next, a CMP, or similar planarization process, is performed to remove any portions of metal layer 1802 that extend over the top surface of the wafer outside of the openings (1704 in FIG. 17) and to remove the photoresist layer (1702 in FIG. 17) from the top surface of the wafer. As a result of the CMP, the SOT metal extensions 1602 and the core dielectric material 1604 are exposed through the top surface of the structure.

[0039] 19, an ILD layer 1902 is formed on the top surface of the wafer, such as using standard deposition processes. The ILD layer 1902 may be made of the same dielectric material (e.g., SiO ) that is used to form the ILD structure 1404. x , SiBCN, SiN, or combinations thereof), but embodiments of the present invention are not limited to any particular material and / or process for forming ILD layer 1902.

[0040] 19, the ILD layer 1902 is patterned (e.g., using standard lithography and etching) to form openings through the ILD layer: a first opening exposing the SOT metal extension 1602 and the core dielectric material 1604, and a second opening exposing the MTJ device contact 1802. For example, using a sidewall metallization process, a first metal liner 1906 is formed on the sidewall of the first opening, and a second metal liner 1908 is formed on the sidewall of the second opening. The first and second openings are then filled with a metal, or alternative conductor, to form a first contact 1910 and a second contact 1912, respectively. The first contact 1910 provides electrical connection to the free layer 604 of the MTJ device through the SOT metal extension 1602 and the SOT layer 602, and the second contact 1912 provides electrical connection to the reference layer 608 of the MTJ device through the MTJ device contact 1802 and the metal hard mask 610. The first and second contacts 1910, 1912 and the first and second metal liners 1906, 1908, in one or more embodiments, can include Ta, Ti, TaN, TiN, W, Ru, Co, Cu, or combinations thereof, although embodiments of the present invention are not limited to any particular conductor material. Furthermore, the contacts and the metal liners need not be formed of the same material.

[0041] As mentioned above, the MTJ device formed according to one or more embodiments of the present invention is advantageously arranged such that the various layers of the MTJ device are arranged concentrically around the central core dielectric material 1604 (which functions as a nanowire conductor) in an all-around configuration. In this manner, the interface area between adjacent layers (e.g., between the free layer 604 and the SOT metal extension 1602) is substantially increased compared to the circular area of ​​a conventional MTJ stack. Furthermore, the circumferential magnetization of the free layer 604 in the all-around structure of the MTJ device advantageously achieves improved stability.

[0042] At least a portion of the techniques of the present invention may be implemented in an integrated circuit. In forming integrated circuits, identical dies are typically fabricated in a repeating pattern on the surface of a semiconductor wafer. Each die includes the devices described herein and may include other structures or circuits or both. The individual dies are cut or diced from the wafer and then packaged as integrated circuits. Those skilled in the art will know how to dice a wafer and package the dies to manufacture integrated circuits. Any of the exemplary circuits illustrated in the accompanying figures or portions thereof may be part of an integrated circuit. Integrated circuits so manufactured are considered part of the present invention.

[0043] Those skilled in the art will appreciate that the exemplary structures discussed above may be distributed in raw form (i.e., a single wafer having multiple unpackaged chips), as bare die, in packaged form, or incorporated as parts of intermediate or final products, such as magnetic random access memories (MRAMs), that would benefit from having MTJ devices formed in accordance with one or more embodiments of the present invention.

[0044] Integrated circuits according to aspects of the present disclosure can be used in essentially any memory storage application or electronic system, or both, such as, but not limited to, MRAM devices. Suitable systems for implementing embodiments of the present invention can include, but are not limited to, data storage systems, and the like. Systems incorporating such integrated circuits are considered part of the present invention. Given the teachings of the present disclosure provided herein, those skilled in the art will be able to contemplate other implementations and applications of embodiments of the present invention.

Claims

1. 1. A method for forming a magnetic tunnel junction device having an all-around structure, comprising: forming a cylindrical pillar structure; forming a first ferromagnetic layer over at least a portion of the pillar structure, the first ferromagnetic layer having a magnetization changeable in the presence of at least one of an applied bias and heat; forming a tunnel barrier over at least a portion of the first ferromagnetic layer; forming a second ferromagnetic layer having a fixed magnetization over at least a portion of the tunnel barrier; Including, the first and second ferromagnetic layers and the tunnel barrier concentrically surround the pillar structure; forming the pillar structure depositing an amorphous silicon layer over an upper surface of at least a portion of the metal connection formed in the layer of dielectric material; depositing a hard mask layer over a portion of an upper surface of the amorphous silicon layer, the hard mask layer and the amorphous silicon layer forming a dummy core; Etching the dummy core to form a cylindrical pillar structure; depositing a layer of spin-orbit torque (SOT) metal over a top surface of the dielectric material layer and over at least a portion of the sidewalls and top surface of the dummy core; A method comprising:

2. 2. The method of claim 1, wherein forming the first ferromagnetic layer comprises depositing a layer of at least one of cobalt, iron, and boron over at least a portion of a top surface of the SOT metal.

3. The formation of the tunnel barrier includes forming a layer of magnesium oxide (MgO), aluminum oxide (AlO ｘ ), and magnesium aluminate (MgAlO ｘ 3. The method of claim 2, further comprising depositing at least one of the layers:

4. The method of claim 3 , wherein forming the second ferromagnetic layer comprises depositing at least one of a layer of cobalt, iron, boron, platinum, nickel, tungsten, and iridium.

5. 1. A method for forming a magnetic tunnel junction device having an all-around structure, comprising: forming a cylindrical pillar structure; forming a first ferromagnetic layer over at least a portion of the pillar structure, the first ferromagnetic layer having a magnetization changeable in the presence of at least one of an applied bias and heat; forming a tunnel barrier over at least a portion of the first ferromagnetic layer; forming a second ferromagnetic layer having a fixed magnetization over at least a portion of the tunnel barrier; forming a metal hardmask layer over at least a portion of a top surface of the second ferromagnetic layer; removing portions of the metal hard mask layer formed on horizontal surfaces of the second ferromagnetic layer; forming a dummy dielectric layer on a horizontal surface of the magnetic tunnel junction device; forming a conformal dielectric layer over a top surface of the magnetic tunnel junction device; wherein the first and second ferromagnetic layers and the tunnel barrier concentrically surround the pillar structure.

6. performing a reactive ion etch to remove portions of the conformal dielectric layer formed on horizontal surfaces of the magnetic tunnel junction device; recessing the conformal dielectric layer remaining on sidewalls of the pillar structure, thereby exposing a portion of the dummy dielectric layer formed on a top surface of the pillar structure and exposing a top portion of the metal hardmask layer disposed on sidewalls of the pillar structure; removing a portion of the dummy dielectric layer formed on a top surface of the pillar structure and a portion not covered by the conformal dielectric layer; selectively etching to remove remaining portions of the dummy dielectric layer disposed beneath the conformal dielectric layer; The method of claim 5 further comprising:

7. removing portions of the metal hardmask layer that are not protected by the conformal dielectric layer; removing the portions of the first and second ferromagnetic layers and the tunnel barrier that are not protected by remaining portions of the metal hard mask layer; forming an encapsulation layer surrounding the magnetic tunnel junction device; forming electrical contacts to the second ferromagnetic layer and the pillar structure; The method of claim 6 further comprising:

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