Video Transmission Equipment

Abstract

To easily grasp the presence or absence of deviation in synthesis, when restoring signals output from an image transmission device to a 4K image and checking it.SOLUTION: An image transmission device receives image signals configured of four sub-images (2K images) obtained by horizontally and vertically dividing a 4K image to be transmitted, draws a test signal of a predetermined color along edges corresponding to boarder lines dividing the 4k image for each of the four sub-images configuring the image signal, and outputs the image signals configured of a plurality of divided images in which the test signals are drawn.SELECTED DRAWING: Figure 2

Description

[Technical field]

[0001] The present invention relates to a video transmission device that receives as input a video signal composed of a plurality of divided videos obtained by dividing a video to be transmitted in the horizontal and vertical directions. [Background technology]

[0002] In recent years, video transmission using 4K video signals in the form of serial signals in SDI (Serial Digital Interface) format has come into practical use. Fig. 18 shows an example of a processing flow of a video transmission device according to the prior art. In a 4K video signal in the form of a serial signal in SDI format, the Square Division division method (hereinafter, "SQD method") is a signal configuration in which a 4K video is divided into four 2K videos of 3G-SDI with a speed of 3 Gbps. Hereinafter, the SQD signals divided into four 2K videos are referred to as sub-images SDI(a) to SDI(d), respectively.

[0003] In the video transmission device, the signal level of each of the input sub-images SDI(a) to SDI(d) is corrected by the receiver (RCV) 100a of the SDI receiving circuit 100, and then the SDI decoding unit 100b converts (decodes) the serial signal into a parallel signal. In general, the four input signals of the video transmission device have non-uniform path lengths due to differences in wiring lengths inside and outside the device, and therefore phase differences occur between the signals. Therefore, the TRS detection unit 101 detects a characteristic signal (TRS: Timing Reference Signal) that indicates the start reference of the horizontal line of the video signal from the decoded signal, and the subsequent phase correction unit 103 matches the phase between the four input signals under the control of the phase control unit 102. This makes it possible to handle the four divided signals as a single 4K signal within the device. Hereinafter, the parallel signals that have undergone phase correction are referred to as sub-images (a) to (d), respectively. Each sub-image is composed of 10-bit parallel signals that are luminance and chrominance streams.

[0004] In the video processing within the video transmission device, the signal is first extracted to a video buffer, and after processing the video in various ways, it is remultiplexed onto the stream. At this time, the remultiplexing process is timed based on the TRS, so that the signal is multiplexed into the correct position on the SDI. To check that the remultiplexing process is normal, it is usually necessary to input a test signal with a simple pattern from outside, observe the signal output from the video transmission device with a measuring instrument, and make a judgment by analyzing the coded signal.

[0005] Here, the prior art in the technical field of the present invention includes the following. For example, Patent Document 1 discloses an invention in which a relay device receives video information transmitted from a source device and superimposes information on the reception state on the black screen area of ​​an SDTV signal when performing a relay operation in which the relay device receives video information transmitted from a source device and transmits it to a destination device. Patent Document 2 discloses an invention in which a first and second active video signal is extracted from a first and second video signal by removing horizontal and vertical blanking areas, and a predetermined video signal of the second active video signal is inserted into a block having an empty space area among a plurality of blocks obtained by dividing the first active video signal. [Prior art documents] [Patent documents]

[0006] [Patent Document 1] JP 2008-193518 A [Patent Document 2] JP 2008-244667 A Summary of the Invention [Problem to be solved by the invention]

[0007] As described above, when transmitting an SDI signal in which 4K video has been converted into serial data, the video transmission device divides the video into 2K videos, processes the images, and then synthesizes the 2K videos to output as a 4K video SDI signal. However, as a result of dividing and synthesizing the video signal and undergoing image processing, the display positions of the divided videos cannot be accurately restored, and there is a possibility that display misalignment may occur. When restoring the signal output from the video transmission device to 4K video and checking it, it is difficult to recognize the misalignment of the video at first glance, and it is not easy to determine whether there was a misalignment when combining the video from the restored video alone.

[0008] The present invention has been made in consideration of the above-described conventional circumstances, and aims to make it possible to easily determine whether or not there is a deviation during synthesis when restoring a signal output from a video transmission device to 4K video and checking it. [Means for solving the problem]

[0009] In order to achieve the above object, a video transmission device according to one aspect of the present invention is configured as follows. That is, in a video transmission device to which a video signal composed of a plurality of divided videos obtained by dividing a video to be transmitted in the horizontal and vertical directions is input, a test signal of a predetermined color is drawn along the side corresponding to the boundary line dividing the video to be transmitted for each of the plurality of divided videos constituting the input video signal, and the video signal composed of the plurality of divided videos on which the test signal is drawn is output.

[0010] Here, in the video transmission device according to the present invention, the test signal drawn on each of the plurality of divided videos may be a plurality of lines and the number of lines may be the same.

[0011] Furthermore, in the video transmission device according to the present invention, test signals of different colors can be drawn on two opposing sides of two divided videos that are adjacent to each other.

[0012] In addition, the video transmission device of the present invention can be configured to generate an enlarged test signal that enlarges the portion where the horizontal composite boundary and the vertical composite boundary intersect based on the multiple split images on which the test signal is drawn, and to further draw the enlarged test signal on one of the multiple split images. Effect of the Invention

[0013] According to the present invention, when a signal output from a video transmission device is restored to 4K video and checked, it becomes possible to easily grasp whether or not there is a deviation during synthesis. [Brief description of the drawings]

[0014] [Figure 1] FIG. 2 is a diagram illustrating an example of a processing flow of a video transmission device according to an embodiment of the present invention. [Diagram 2] FIG. 13 is a diagram showing an image of a test signal relative to a video signal. [Diagram 3] 5 is a diagram showing the relationship between parameters related to the test signal writing circuit and test signals; FIG. [Figure 4] FIG. 2 is a diagram illustrating a configuration example of a horizontal test signal drawing circuit. [Diagram 5] FIG. 2 is a diagram illustrating a configuration example of a vertical test signal drawing circuit. [Figure 6] FIG. 13 is a diagram for explaining a method of drawing a test signal for each sub-image. [Figure 7] FIG. 11 is a diagram showing an example of parameters of each sub-image used in the horizontal and vertical test signal drawing circuit. [Figure 8] FIG. 13 is a diagram showing an example of a timing chart of the horizontal and vertical test signal drawing circuit. [Figure 9] FIG. 2 is a diagram illustrating a configuration example of an enlargement display circuit. [Figure 10] FIG. 13 is a diagram showing the line width of the crossing portion of the test signal expanded four times. [Figure 11] 11 is a diagram for explaining RAM input / output control when enlarging a crossing portion of a test signal. FIG. [Figure 12]13 is a diagram showing an example of the configuration of a write enable generation circuit and a write address generation circuit in a RAM write control unit of the enlargement display circuit. FIG. [Figure 13] 13 is a diagram showing an example of the configuration of a read enable generation circuit in a RAM read control unit of the enlargement display circuit. FIG. [Figure 14] 13 is a diagram showing an example of the configuration of a read address generation circuit in a RAM read control unit of the enlargement display circuit. FIG. [Figure 15] FIG. 13 is a diagram illustrating an example of a timing chart of a read enable generation circuit. [Figure 16] FIG. 13 is a diagram illustrating an example of a timing chart of a read address generation circuit. [Figure 17] 11 is a diagram illustrating an example of the configuration of an enlarged signal generating unit and an enlarged test signal drawing unit. FIG. [Figure 18] FIG. 1 is a diagram illustrating an example of a processing flow of a video transmission device according to a conventional technique. [Figure 19] FIG. 1 is a diagram illustrating a screen configuration when splitting / combining in the 4K video SQD format. [Figure 20] FIG. 2 is a diagram illustrating the mapping structure and data stream structure of each sub-image. [Figure 21] FIG. 13 is a diagram for explaining bit assignments of XYZ and LN words and the frame structure of each sub-image. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0015] A video transmission device according to an embodiment of the present invention will be described with reference to the drawings. Fig. 1 shows an example of a processing flow of a video transmission device according to an embodiment of the present invention. A transmitter and a receiver of the video transmission device are each equipped with an input / output circuit for a 4-split 2K video signal, and generally, the drawing of a test signal is often processed on the transmitter side, and the display of the test signal is often processed on the receiver side. The video processing shown in Fig. 1 is equipped with a common input / output interface for the transmitter and the receiver, and is a common module that can be applied to either device.

[0016] The video transmission device of this example has a test signal drawing circuit A for drawing a line-shaped test signal (i.e., a test line) on the outline (i.e., side) of each sub-image, which corresponds to the composite boundary, and an enlarged display circuit B for partially enlarging and displaying the test signal, so that the presence or absence of display misalignment in a 4K video restored by combining four 2K videos (sub-images) can be easily determined. Note that the process of correcting the phase of a 4K video signal of the SQD format input from the outside to the video transmission device inside the device (processing shown by symbols 100 to 103) is the same as the conventional technology.

[0017] Test signal drawing circuit A has a line number detection unit 1, a pixel detection unit 2, a horizontal / vertical test signal drawing unit 3, and a delay adjustment unit 4. In general, test signal drawing circuit A detects the line number and pixel sample (position) number from each of the sub-images (a) to (d) after phase correction, and replaces the data of the outline portion that becomes the synthesis boundary when synthesizing each sub-image with fixed test data, thereby realizing drawing of the test signal. The operation of test signal drawing circuit A will be described in detail below.

[0018] First, the test signal drawing circuit A detects the video line number decoded value LNDEC from each of the phase-corrected sub-images (a) to (d) in the line number detection unit 1. Specifically, the line number detection unit 1 determines the signal position on the stream by referring to the TRS timing signal EAV1W, which indicates the beginning of the video line and is output from the previous phase control unit 102. Note that since each sub-image has already been phase-adjusted, the TRS timing signal EAV1W is common to all sub-images.

[0019] After reading out the line number decoded value LNDEC written at the position specified by the TRS reference, the pixel detector 2 generates a counter CNTR for identifying the position (sample) of each pixel in the image. By detecting the line number and the pixel, the position of each pixel in the image signal becomes clear, making it possible to determine the position for drawing the test signal.

[0020] The horizontal / vertical test signal drawing unit 3 performs drawing processing of the test signal for each sub-image signal at a position determined by line number detection and pixel detection. There are horizontal test signals, which are test signals in the horizontal direction, and vertical test signals, which are test signals in the vertical direction. Since the test signals are displayed at different positions for each sub-image, drawing processing is performed for each sub-image. The delay adjustment unit 4 is a correction circuit for a fixed delay amount that takes into account the processing delay in generating the test signal. The processing delay is constant depending on the circuit, and the delay adjustment unit 4 corrects the fixed delay amount. This completes the operation of the test signal drawing processing circuit A.

[0021] The enlarged display circuit B has a RAM write control unit 5, a video buffer 6, a RAM read control unit 7, an enlarged signal creation unit 8, and an enlarged test signal drawing unit 9. In general, the enlarged display circuit B stores each sub-image signal subjected to test signal drawing in a video buffer, and when reading out the sub-image signal from the video buffer in the target enlarged display area, it performs processing to cause the control signal for the read process to be repeatedly read in the horizontal and vertical directions according to the enlargement magnification, thereby realizing a partial enlarged display of the test signal. The operation of the enlarged display circuit B will be described in detail below.

[0022] First, the enlargement display circuit B temporarily stores each sub-image signal (i.e., each sub-image signal in which a test signal is drawn) output from the horizontal / vertical test signal drawing unit 3 of the test signal drawing circuit A in a video buffer 6 which is a RAM (Random Access Memory).At that time, the RAM write control 5 controls writing to the video buffer 6 based on the line number decoded value LNDEC detected from the sub-image signal and the counter CNTR indicating the pixel position.

[0023] The enlarged display process is performed by a read process from the video buffer 6 by the RAM read control 7. As an example, the test signal is enlarged by continuously reading out the signal of the same line over multiple lines and continuously reading out the signal of the same pixel position over multiple pixels based on the position of the target enlarged display area on the 4K video. The enlarged display area is, for example, an area of ​​a predetermined size centered on the intersection of the horizontal test signal and the vertical test signal. The signals of the sub-images read from the video buffer 6 are synthesized into one enlarged test signal by the enlargement signal creation unit 8.

[0024] The enlarged test signal drawing unit 9 creates a video signal in which the enlarged test signal is drawn by overwriting an arbitrary sub-image signal with the enlarged test signal output from the enlarged signal creation unit 8. A signal specifying the sub-image into which the enlarged image is to be drawn is given to the enlarged test signal drawing unit 9 as a display area selection SIN. It is possible to select whether or not to perform drawing processing of the test signal and the enlarged test signal. A signal specifying whether or not to perform drawing processing is given to the horizontal / vertical test signal drawing unit 3 and the enlarged test signal drawing unit 9 as display control ON / OFF. This completes the operation of the enlarged display circuit B.

[0025] Fig. 2 shows a plotted image of a test signal for a video signal input to a video transmission device. Fig. 2(a) shows a plotted image of a test signal by test signal plotting circuit A. The upper part of Fig. 2(a) shows a plotted image of a test signal for a 4K video, in which test signals of two different colors (e.g., red and blue) are plotted side by side with the vertical and horizontal centers of the video as the boundaries. In other words, test signals of different colors are plotted on two opposing sides of two sub-images that are adjacent to each other.

[0026] The lower part of Fig. 2(a) shows the image of the test signal drawn for each sub-image. In each sub-image, a horizontal test signal is drawn along either the upper or lower edge, which corresponds to the outline of the image, and a vertical test signal is drawn along either the left or right edge. Whether the test signal is drawn on the upper or lower edge, and whether the test signal is drawn on the left or right edge is determined for each sub-image. Specifically, the sub-image (a) constituting the upper left part of the 4K image has the test signal drawn on the lower and right edges. The sub-image (b) constituting the upper right part of the 4K image has the test signal drawn on the lower and left edges. The sub-image (c) constituting the lower left part of the 4K image has the test signal drawn on the upper and right edges. The sub-image (d) constituting the lower right part of the 4K image has the test signal drawn on the upper and left edges.

[0027] FIG. 2(b) shows the portion shown by the dashed line in FIG. 2(a), that is, the enlarged test signal obtained by enlarging the intersection of the test signal by the enlargement display circuit B. The upper part of FIG. 2(b) shows an enlarged view in a normal state, and it can be seen that the lines drawn with the same width on either side of the composite boundary of the screen are displayed with the same width even in the composited 4K image. In other words, all test signals are multiple lines and have the same number of lines. The lower part of FIG. 2(b) shows an enlarged view of a state in which a display shift has occurred in some sub-images. In the illustrated example, the horizontal test signal is displayed thinly because the sub-image (c) is shifted vertically to the negative side (upper side), and the vertical test signal is displayed thinly because the sub-image (d) is further shifted horizontally to the negative side (left side). In this way, it is possible to easily grasp the presence or absence of a shift during composition and the direction of the shift by simply checking the state of the composite boundary.

[0028] Figure 2(c) shows an example of drawing an enlarged test signal on any sub-image. In the example shown, the enlarged test signal is drawn on sub-image (d). By enlarging the image in this way, it is possible to clearly check the state of the synthesis boundary even in the synthesized image.

[0029] Here, as a premise for the test signal drawing circuit A and the enlarged display circuit B of this example, the screen configuration when dividing / combining in the 4K video SQD method will be described with reference to Fig. 19. A 4K video with an effective display area of ​​3840 pixels x 2160 lines is divided into 2K size sub-image images of 1920 pixels x 1080 lines along the center lines in the vertical and horizontal directions. The sub-image is the effective display area of ​​the 2K video, and constitutes a video frame to which timing signals such as EAV (End of Active Video) and SAV (Start of Active Video), horizontal auxiliary areas (H Blanking), vertical auxiliary areas (V Blanking), etc. are added. The signal that serializes this frame becomes the SDI signal.

[0030] Similarly, among the SMPTE standards for configuring SDI video signals, the SDI technology related to the test signal drawing circuit A and the enlarged display circuit B in this example will be described with reference to Figures 20 and 21. As explained in the prior art, the sub-image is configured with 10-bit parallel signals (data streams) of luminance and color difference.

[0031] Figure 20(a) shows a mapping structure (Mapping Structure 1) that arranges the color difference signals Cb, Cr in a 4:2:2 ratio relative to the luminance signal Y. Inside the device, the entire 4K video is treated as an 80-bit parallel signal. Figure 20(b) shows the arrangement of header signals in the luminance signal and color difference signal. The numbers in the figure are values ​​for the domestic standard frame frequency of 60 / 1.001Hz. For both luminance and chrominance, one line is 2200 samples. Of this, the period of 280 samples excluding the 1920 samples of the video signal width is the horizontal blanking period where header information and auxiliary data can be inserted.

[0032] For both the luminance signal and the color difference signal, the start of the blanking period other than the effective image is the four words EAV indicating the end of the image. The first three words of EAV are prefix information (3FF,000,000) with a fixed value, and the next word is identification information XYZ. At the end of the blanking period, there is SAV indicating the start of the effective image, which is four words like EAV. EAV is followed by two words (LN0, LN1) describing the line number. The line number is 11-bit data and is inserted at the bit position shown in FIG. 21(a). Among the breakdown of XYZ, the F, V, and H signals (hereinafter referred to as "FVH") related to the test signal drawing circuit A and the enlarged display circuit B in this example are inserted at the bit position shown in FIG. 21(a). FVH indicates the position of EAV or SAV in the image frame, and it is possible to determine the insertion position of EAV or SAV by reading the value. FIG. 21(b) shows the relationship between the FVH value and the position on the frame. Reading the EAV, line number, and FVH as described above is a prerequisite for creating a test signal and for the drawing process.

[0033] Next, the drawing of the test signal using the parameters of sub-image (a) will be described. Similar processing is applied to both the luma and chroma streams. FIG. 3 shows the relationship between the parameters of the test signal drawing circuit A and the test signal. The left diagram of FIG. 3 shows the state where only the horizontal test signal is drawn from 280 to 1919 horizontal samples of the effective image, at a height of n to 1121 vertical lines. The right diagram of FIG. 3 shows the state where only the vertical test signal is drawn from 42 to 1121 vertical lines, at a height of p to 1919 horizontal samples of the effective image.

[0034] 4 shows an example of the configuration of a horizontal test signal drawing circuit A1, which is a part of the test signal drawing circuit A. The line detection section 1 in the figure has a counter 11, a comparator 12, a flip-flop 13, a latch 14, and an LN decoding section 15. The pixel detection section 2 has a comparator 21, a comparator 22, an RS flip-flop 23, a logical AND operator 24, and a flip-flop 25. The horizontal test signal drawing section 3a, which constitutes a part of the horizontal / vertical test signal drawing section 3, has a flip-flop 31 and a switch 32.

[0035] The horizontal test signal drawing circuit A1 operates with a clock CLK at a speed for processing one word of data, and the other circuits described below operate in the same manner. A counter 11 is initialized by a TRS timing signal EAV1W input from the phase control unit 102 in Fig. 1. Based on the counter value CNTR output from the counter 11, a comparator 12 generates a timing signal LNEn with a count value of "4" or "5", which is the superimposition position of the line number data. This timing signal LNEn is provided to a latch 14 as an enable signal.

[0036] The sub-image signal input to the horizontal test signal drawing circuit A1 is delayed and adjusted by the flip-flop 13 before being input to the latch 14, which outputs two words LN describing the line number in the EAV. Next, the LN decoding unit 15 detects a line number decoded value LNDEC from LN and inputs it to the comparator 21. The comparator 21 outputs H-TstEn as a judgment result when the line number is between n and 1121, which is the horizontal test signal period, and outputs V-TstEn as a judgment result when the line number is between 42 and 1121, which is the vertical test signal period.

[0037] At the same time, the comparator 22 sets the set (S) / reset (R) of the RS flip-flop 23 so that the counter value CNTR becomes positive logic when it is in the range of 280 to 1919, which is the horizontal test signal period. The logical product calculator 24 calculates a logical product H-TstVar of the output of the RS flip-flop 23 and the determination result H-TstEn of the horizontal test signal period output from the comparator 21. H-TstVar is delayed and adjusted by the flip-flop 25, and then provided to the switch 32 as a switch control signal.

[0038] The sub-image signal that has been delay-adjusted by the flip-flop 31 is input to the switch 32. The switch 32 switches the input sub-image signal to a constant C1 in response to H-TstVar, thereby obtaining a horizontal test signal H-TstDt that draws the horizontal test signal. Here, the constant C1 is a set value that corresponds to the drawing color of the horizontal test signal.

[0039] 5 shows an example of the configuration of a vertical test signal drawing circuit A2, which is a part of the test signal drawing circuit A. The pixel detection section 2 in the figure has a comparator 21, a comparator 26, an RS flip-flop 27, and a logical AND operator 28. Moreover, the vertical test signal drawing section 3b, which constitutes a part of the horizontal / vertical test signal drawing section 3, has a flip-flop 33, a flip-flop 34, and a switch 35.

[0040] In the vertical test signal drawing circuit A2, a comparator 26 sets the set (S) / reset (R) of an RS flip-flop 27 so that the counter value CNTR is positive logic when it is in the range of p to 1919, which is the vertical test signal period. A logical AND calculator 28 calculates a logical AND V-TstVar of the output of the RS flip-flop 27 and the determination result V-TstEn of the vertical test signal period output from the comparator 21. V-TstVar is delayed and adjusted by a flip-flop 34, and then is provided to a switch 35 as a switching control signal.

[0041] The horizontal test signal H-TstDt, which has been delay-adjusted by the flip-flop 33, is input to the switch 35. The switch 35 switches the horizontal test signal H-TstDt to a constant C2 in accordance with V-TstVar, thereby obtaining a horizontal / vertical test signal HV-TstDt that draws the horizontal test signal and the vertical test signal. Here, the constant C2 is a set value in accordance with the drawing color of the vertical test signal.

[0042] Here, in the horizontal and vertical test signal drawing circuits A1 and A2 in Fig. 4 and Fig. 5, the vertical test signal is drawn after the horizontal test signal, but in order to identify the state of the composite boundary, it is effective to change the drawing order according to the displayed image. This point will be explained with reference to Fig. 6. For example, the hatched and shaded parts in Fig. 6(a) are test signals to be drawn, and indicate that the drawing positions are different for each sub-image. For each sub-image, the horizontal test signal and the vertical test signal are drawn in the order shown in Fig. 6(b) at the positions specified in Fig. 6(a). That is, for sub-images (a) and (b), the vertical test signal is drawn after the horizontal test signal, and for sub-images (c) and (d), the horizontal test signal is drawn after the vertical test signal. By drawing in this order, it becomes possible to draw the crossing lines as shown in Fig. 6(c).

[0043] Fig. 7 shows an example of parameters for each sub-image used in the horizontal / vertical test signal drawing circuits A1 and A2 of Fig. 4 and Fig. 5. In Fig. 7, as the setting values ​​for drawing the horizontal test signal, for sub-images (a) and (b), the V upper limit of the comparator 21 is set to n1, the V lower limit is set to 1121, and the set (S) of the RS flip-flop 23 is set to 280, and the reset (R) is set to 1919. For sub-images (c) and (d), the V upper limit of the comparator 21 is set to 42, the V lower limit is set to n2, and the set (280) and reset (R) of the RS flip-flop 23 is set to 1919. In addition, as the setting values ​​for drawing the vertical test signal, for sub-images (a) and (c), the V upper limit of the comparator 21 is set to 42, the V lower limit is set to 1121, and the RS flip-flop 27 is set to set to p1 and reset to 1919. For sub-images (b) and (d), the V upper limit of the comparator 21 is set to 42, the V lower limit is set to 1121, and the RS flip-flop 27 is set to set to 280 and reset to p2.

[0044] The drawing colors of the horizontal test signal and the vertical test signal are determined by the constants C1 and C2 as described above. As an example, the lower part of Fig. 7 shows an example of constants when drawing in red. That is, when drawing in red with a luminance level of 75% using 10-bit Y / C data, Y=0CC and C is a repetition of Cb (=1B3) and Cr (=1E1).

[0045] Fig. 8 shows an example of a timing chart of the horizontal and vertical test signal drawing circuits A1, A2 of Fig. 4 and Fig. 5. According to Fig. 8, it can be seen that the horizontal test signal H-TstDt becomes a constant C1 at pixel positions of 280 to 1919 samples of the video signal indicated by the word counter (CNTR), and the horizontal and vertical test signal HV-TstDt is overwritten with a constant C2 of the vertical test signal at pixel positions p to 1919 samples.

[0046] Next, the enlarged display of the test signal by the enlargement display circuit B will be described. Fig. 9 shows an example of the configuration of the enlargement display circuit B. The enlargement display circuit B has a video buffer 6, which is a RAM that stores the signal under test, as its core, and includes a RAM write control unit 5 that generates a write signal to the video buffer 6, a RAM read control unit 7 that performs enlargement processing when reading from the video buffer 6, an enlargement signal creation unit 8 that creates an enlarged signal to be displayed, and an enlargement test signal drawing unit 9 that multiplexes the enlargement signal onto the input stream. The enlargement test signal output EXP-TstDt for each sub-image is read from the video buffer 6, integrated by the enlargement signal drawing unit 8, and then multiplexed onto the input stream by the enlargement test signal drawing unit 9.

[0047] Fig. 10 shows how the line width of the intersection of the test signal is enlarged four-fold by controlling the input and output of the RAM (video buffer 6) implemented in the enlargement processing circuit B. As parameters indicating the area of ​​the sub-image unit, the RAM input has a size of horizontal pixels = h1-h2 and vertical lines = v1-v2, and the RAM output has a size of horizontal pixels = H1-H2 and vertical lines = V1-V2.

[0048] With reference to FIG. 11, the RAM input / output control when enlarging the intersection of the test signals will be described. The RAM write control unit 5 controls data writing to the RAM so as to obtain a memory configuration as shown in the table of FIG. 11. That is, the address ADR is set to pixels h1 to h2 for the write line v1, and the input signal DT is written. In addition, a LAST flag that identifies the last data of the line is also written at the same time as the input signal. Then, after writing the line v1, the signal of the next line v(+1) is written in the same manner. This is repeated to write the signals of all pixels corresponding to the area to be enlarged as data of consecutive addresses ADR.

[0049] The read order example on the right side of the table in Figure 11 shows the flow of the RAM data read operation when enlarging by 4 times. It shows that after the signal of the same line (v1) is read out four times repeatedly, the transition to the read of the next line v(+1) is made. In this way, the vertical line width is enlarged by repeating the read out a number of times according to the enlargement ratio. Note that the horizontal line width is enlarged by the repeated read control of the same address, which will be described later.

[0050] Fig. 12 shows an example of the configuration of the RAM write control unit 5. Fig. 12(a) shows an example of the configuration of a write enable WE generation circuit in the RAM write control unit 5, and Fig. 12(b) shows an example of the configuration of a write address WADR generation circuit in the RAM write control unit 5. The write enable WE generation circuit has a comparator 51, a comparator 52, and a logical AND operator 53. The write address WADR generation circuit has a comparator 54, a comparator 55, a logical AND operator 56, and an address counter 57.

[0051] First, a method for generating the write enable signal WE will be described with reference to FIG. 12(a). Based on the counter value CNTR and the line number decoded value LNDEC generated by the circuit in FIG. 4, the horizontal and vertical sizes of the area to be enlarged are determined and set as the write enable signal WE. More specifically, comparators 51 and 52 in the form of window comparators are used to decode each area in the horizontal and vertical directions. In the horizontal direction, the comparator 52 detects whether the range is h1≦CNTR≦h2. In the vertical direction, the comparator 51 detects whether the range is v1≦LNDEC≦v2. The logical product of the outputs of these comparators 51 and 52 is calculated by a logical product calculator 53 to obtain the write enable signal WE.

[0052] Next, a method of generating the write address WADR will be described with reference to FIG. 12(b). WADR is generated as the output of the address counter 57. The address counter 57 is initialized when the input stream reaches the position of LNDEC=v2 and CNTR=h2, which is the final data of the area to be enlarged. The address counter 57 then increments the counter using the active period of WE as a count enable. The input stream reaching the position of LNDEC=v2 is detected by the comparator 54, and the input stream reaching the position of CNTR=h2 is detected by the comparator 55. The logical product of the outputs of these comparators 54 and 55 is calculated by the logical product calculator 56, and is given to the address counter 57 as an initialization signal. The timing of the horizontal line of the area to be enlarged reaching the final data h2 is written to the RAM as LASTw together with the video signal for use in subsequent processing. Using the WE and WADR generated as described above, all data in the area to be enlarged is written to the RAM while incrementing the RAM write address, as in the memory configuration example shown in FIG. 11.

[0053] 13 and 14 show configuration examples of the RAM read control unit 7. FIG. 13 shows a configuration example of a generation circuit of the read enable RE, and FIG. 14 shows a configuration example of a generation circuit of the read address RADR. The generation circuit of the read enable RE has a comparator 71a, a comparator 71b, a logical product operator 71c, a counter 72a, a comparator 72b, a logical sum operator 72c, a comparator 73a, and a logical product operator 73b. The generation circuit of the read address RADR has a comparator 74a, a comparator 74b, a logical product operator 74c, a logical sum operator 74d, a logical sum operator 74e, a line counter 75a, a comparator 75b, a pixel counter 76a, an adder 76b, a flip-flop 76c, an address counter 77a, a flip-flop 77b, and an adder 78.

[0054] First, a method for generating the read enable RE will be described with reference to Fig. 13. The counter 72a counts the number of pixels in the enlarged display area. The comparator 71a detects that the line number decoded value LNDEC of the video stream is within lines V1 to V2 of the enlarged display area. Similarly, the comparator 71b detects that the counter value CNTR indicating the pixel position of the video stream is within samples H1 to H2. The logical product of the outputs of these comparators 71a and 71b is calculated by a logical product calculator 71c to produce a signal DRWEN indicating the enlarged display area.

[0055] The counter 72a sequentially increments with DRWEN as a count enable to obtain an output HCTR. The HCTR counter value is decoded by the comparator 73a and the comparator 72b. The comparator 72b is used to set a parameter M (=X-1) according to the enlargement amount X by which the pixels stored in the RAM are stretched in the horizontal direction. For example, in the case of enlargement by 4 times, M=3. The counter 72a is initialized by the output of the comparator 72b or EAV1W indicating the beginning of each line, which is given through the OR operator 72c. This makes the counter 72a a cyclic counter according to the horizontal enlargement magnification.

[0056] On the other hand, the comparator 73a decodes the HCTR value=0 and generates the timing for extending the RAM read timing to the set number of pixels. The logical product of the outputs COMP and DRWEN of the comparator 73a is calculated by the logical product calculator 73b to become the read enable RE. The read enable RE extends the intra-line data stored in the RAM to the set period within the enlarged display area, and becomes a timing signal for reading it discretely.

[0057] Next, a method of generating the read address RADR will be described with reference to FIG. 14. The line counter 75a is a counter that counts the number of times line data is repeatedly read from the RAM in order to enlarge the line width in the vertical direction. The line counter 75a is initialized at the head position of the enlarged display area where the line number decoded value LNDEC of the video stream is the V1 line (read-out head line set value) and the pixel position CNTR is the H1 sample (read-out head pixel set value). The line counter 75a then increments the counter value LCTR according to LASTr, which indicates the reading of the final value of each line data. Note that the comparator 74a detects that the line number decoded value LNDEC of the video stream is the V1 line, and the comparator 74b detects that the pixel position CNTR is the H1 sample. The logical product of the outputs of these comparators 74a and 74b is calculated by the logical product calculator 74c and is given to the line counter 75a as an initialization signal via the logical sum calculator 74d.

[0058] The comparator 75b detects that the number of reads of line data LCTR has reached N, and outputs an enable signal ADDEN to the adder 76b in the subsequent stage. The ADDEN signal indicating that the number of reads has reached N is provided to the line counter 75a as an initialization signal via the OR calculator 74d. This causes the line counter 75a to function as a cyclic counter according to the vertical enlargement magnification.

[0059] The pixel counter 76a counts the number of read pixels, and its output PCTR is used to update the address corresponding to the read line number. The logical sum calculator 74e calculates the logical sum CTRLD of the start position of each line in the enlarged display area where the counter value CNTR is H1 (the output of the comparator 74b) and the line data final value LASTr, and provides this as an initialization signal to the pixel counter 76a and the address counter 77a. In response to this initialization signal, the pixel counter 76a sets the counter value PCTR to its initial value (=1). The pixel counter 76a increments the counter value PCTR in response to a clock synchronized with the word data, using DRWEN, which indicates that the video stream is within the enlarged display area, as a count enable.

[0060] The adder 76b performs addition processing in units of the number of words for one line of the write area by enabling the addition processing with ADDEN. The UADR output from the adder 76b is input to the adder 78 as a line address for reading from the RAM after delay adjustment by the flip-flop 76c.

[0061] The address counter 77a is a counter that generates a read address within one line. The address counter 77a counts with DRWEN indicating that the video stream is within the enlarged display area as a count enable, and increments the counter value LADR after initializing it according to CTRLD. The output LADR of the address counter 77a is input to an adder 78 as a pixel address for RAM readout after delay adjustment by a flip-flop 77b.

[0062] The adder 78 sequentially adds the input UADR (upper address) and LADR (lower address) to obtain the read address RADR of the RAM. As a result, the data in one line stored in the RAM is repeatedly read out the number of times set by the parameter N, and after the set number of times has elapsed, a read address is generated that transitions the line data to be read out to the next line.

[0063] Fig. 15 shows an example of a timing chart of the read enable RE generation circuit shown in Fig. 13. Fig. 15 shows an example in the case of M=3, that is, in the case of setting to stretch by 4 pixels in the horizontal direction, and it can be seen that the read data DT from the RAM is stretched as set by the RE generation process.

[0064] Fig. 16 shows an example of a timing chart of the generation circuit of the read address RADR shown in Fig. 14. Fig. 16 shows an example in the case of N=4, that is, in the case of setting to extend four lines, and it can be seen that the addresses of the same line data are set for four consecutive lines by the RADR generation process.

[0065] 17 shows an example of the configuration of the enlarged signal generating unit 8 and the enlarged test signal drawing unit 9. The enlarged signal generating unit 8 has a switch 80. The enlarged test signal drawing unit 9 has a switch 91a, a flip-flop 91b, a logical sum calculator 92a, a switch 92b, a switch 92c, and a logical product calculator 93.

[0066] The enlarged test signals EXP-TstDt(a)-(d) obtained by reading out each sub-image from the RAM shown in FIG. 9 are input to a switch 80. The switch 80 switches between and outputs EXP-TstDt(a)-(d) using the enlarged display areas DRWEN(a)-(d) as switching signals. That is, the switch 80 selects and outputs a video signal corresponding to an active switching signal. Here, the signal selected by switching has a data configuration of luminance EXP-TstDt(Y) and color difference EXP-TstDt(C). The luminance signal EXP-TstDt(Y) is input to a switch 92b, and the color difference signal EXP-TstDt(C) is input to a switch 92c.

[0067] The video transmission device can arbitrarily select an area for displaying the enlarged test signal on a sub-image basis, and a switch 91a selects one of the horizontal / vertical test signals HV-TstDt(a)-(d) for each sub-image according to a selection signal SIN. Here, the selected horizontal / vertical test signal has a data configuration of luminance and chrominance, and after being delayed and adjusted by a flip-flop 91b, the luminance signal Stream(Y) is input to a switch 92b, and the chrominance signal Stream(C) is input to a switch 92c.

[0068] The logical sum calculator 92a calculates the logical sum of the enlarged drawing areas DRWEN(a)-(d) of each sub-image. According to the output of the logical sum calculator 92a, the switch 92b switches between outputting Stream(Y) or EXP-TstDt(Y), and the switch 92c similarly switches between outputting Stream(C) or EXP-TstDt(C). This makes it possible to draw a test signal of a target color. Furthermore, the logical sum calculator 93 calculates the logical product of the display control ON / OFF arbitrarily selected by the video transmission device and DRWEN, and provides the result as a switching signal to the switches 92b and 92c, thereby making it possible to select whether or not to display the enlarged test signal.

[0069] As described above, the video transmission device of this example is configured to receive a video signal composed of four sub-images (2K images) obtained by dividing a 4K image to be transmitted in the horizontal and vertical directions, draw a test signal of a predetermined color along the sides corresponding to the boundaries dividing the 4K image for each of the four sub-images constituting the video signal, and output a video signal composed of a plurality of divided images on which the test signal is drawn. As a result, the 4K image restored based on the video signal output from the video transmission device of this example will display horizontal and vertical synthesis boundaries. Therefore, it is easy to know whether there is a deviation during synthesis just by looking at the state of the horizontal and vertical synthesis boundaries. As a result, it is possible to determine whether the divided image processing inside the device is appropriate.

[0070] In addition, in the video transmission device of this example, the test signal drawn on each of the multiple sub-images is multiple lines and the number of lines is the same, so that the presence or absence of misalignment during composition can be grasped simply by checking the line width of the composition boundary in the horizontal and vertical directions of the video output.

[0071] In addition, in the video transmission device of this example, two adjacent sub-images are configured so that test signals of different colors are drawn on the two opposing sides of each other. Therefore, if a shift occurs during composition, it is easy to know which sub-image is shifted in which direction.

[0072] In addition, the video transmission device of this example is configured to generate an enlarged test signal that enlarges the intersection of the horizontal and vertical composite boundaries based on the multiple sub-images on which the test video is drawn, and further draw the enlarged test signal on one of the multiple divided videos. This makes it easier to check the state of the horizontal and vertical composite boundaries that are output as video, and makes it easier to grasp the presence or absence of misalignment during composition.

[0073] Here, in the above description, an example is given of a case where 4K video in the SQD format is transmitted, but the present invention is not limited to this, and can be applied to cases where video in other formats is transmitted. Also, in the above description, an example is given of a case where a video to be transmitted is divided into four, but the present invention can be applied to cases where the number of divisions of the video to be transmitted is increased.

[0074] Although the embodiments of the present invention have been described above, these embodiments are merely illustrative and do not limit the technical scope of the present invention. The present invention can take various other embodiments, and various modifications such as omissions and substitutions can be made without departing from the gist of the present invention. These embodiments and modifications are included in the scope and gist of the invention described in this specification, etc., and are included in the scope of the invention described in the claims and their equivalents.

[0075] Furthermore, the present invention can be provided not only as devices such as those described above or as a system composed of these devices, but also as methods executed by these devices, programs for causing a processor to realize the functions of these devices, and storage media for storing such programs in a computer-readable format. [Industrial Applicability]

[0076] The present invention can be used in a video transmission device that receives as input a video signal composed of a plurality of divided videos obtained by dividing a video to be transmitted in the horizontal and vertical directions. [Explanation of symbols]

[0077] 1: Line number detection unit, 2: Pixel detection unit, 3: Horizontal and vertical test signal drawing unit, 3a: Horizontal test signal drawing unit, 3b: Vertical test signal drawing unit, 4: Delay adjustment unit, 5: RAM write control unit, 6: Video buffer, 7: RAM read control unit, 8: Enlarged signal creation unit, 9: Enlarged test signal drawing unit, 11, 72a: Counter, 12, 21, 22, 26, 51, 52, 54, 55, 71a, 71b, 72b, 73a, 74a, 74b, 75b: Comparator, 13, 25, 31, 33, 34, 76c, 77b, 91b: Flip-flop, 14: Latch, 15: LN decoding unit, 23, 27: RS flip-flop, 24, 28, 53, 56, 71c, 73b, 74c, 93: logical AND operator, 32, 35, 80, 91a, 92b, 92c: switch, 57, 77a: address counter, 72c, 74d, 74e, 92a: logical OR operator, 75a: line counter, 76a: pixel counter, 76b, 78: adder, 100: SDI receiving circuit, 100a: receiver, 100b: SDI decoding unit, 101: TRS detection unit, 102: phase control unit, 103: phase correction unit,

Claims

1. In a video transmission device to which a video signal composed of a plurality of divided videos obtained by dividing a video to be transmitted in the horizontal and vertical directions is input, For each of the plurality of divided images constituting the input video signal, a test signal of a predetermined color is drawn along a side corresponding to a boundary line dividing the video to be transmitted, and a video signal composed of the plurality of divided images on which the test signal is drawn is output; In this case, the video transmission device generates an enlarged test signal that enlarges the portion where the horizontal composite boundary and the vertical composite boundary intersect based on the multiple divided images on which the test signal is drawn, and draws the enlarged test signal on one of the multiple divided images.

2. 2. The video transmission device according to claim 1, A video transmission device, characterized in that the test signal drawn on each of the plurality of divided videos is a plurality of lines, the number of lines being the same.

3. 3. The video transmission device according to claim 1, A video transmission device, characterized in that test signals of different colors are drawn on two opposing sides of two adjacent divided videos.

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