Integrated Optical Phased Array Electronic Control

Abstract

Controlling the optical phased array includes applying an optical phase shift by an array of phase shifter (PS) elements, each PS element applying an optical phase shift based on an input voltage signal applied across a first terminal and a second terminal of the PS element to provide an output voltage signal from the array of driver elements. During a charging period, each driver element provides an output voltage signal to determine a corresponding input voltage signal applied across at least one of the plurality of PS elements, and an array of switches controls connectivity between the plurality of driver elements and corresponding PS elements, such that all second terminals of all PS elements in the array of PS elements are maintained at a common voltage. The total number of switches in the array of switches is at least as large as the total number of PS elements in the array of PS elements.

Description

[Technical field]

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS This application claims priority to and the benefit of U.S. Provisional Application No. 62 / 984,883, filed March 4, 2020, and entitled “Integrated Optical Phased Array Electronic Control.”

[0002] STATEMENT REGARDING FEDERALLY SPONSORED RESEARCH This invention was made with Government support under DARPA Contract No. HR0011-16-C-0108. The Government has certain rights in this invention.

[0003] The present disclosure relates to integrated optical phased array electronic control. [Background technology]

[0004] Various techniques can be used to control the phase of light waves emitted from emitter elements in an optical phased array, such as an optical phased array formed in a photonic integrated circuit (PIC). Some of these techniques integrate phase shifter elements that are controlled by a control circuit and optically coupled to the emitter elements in the PIC. The characteristics of the optical phase shifter elements can affect the control circuit architecture. For example, for a two-dimensional array of emitter elements, there can be a corresponding two-dimensional array of thermal phase shifter elements. These thermal phase shifters induce an optical phase shift based on a refractive index change due to temperature. The temperature can be controlled, for example, by currents applied in a row-column arrangement. However, for phase shifter elements other than thermal phase shifters (e.g., capacitive phase shifter elements), there can be interference from such row-column signal arrangements due to crosstalk from selected elements to unselected elements. Summary of the Invention

[0005] In one aspect, in general, an apparatus includes an array of emitter elements, an array of phase shifter elements, each phase shifter element configured to apply an optical phase shift to a light wave propagating through the phase shifter element and to a corresponding radiator element, the optical phase shift being based on an input voltage signal applied across a first terminal and a second terminal of the phase shifter element, an array of driver elements, each driver element configured to provide an output voltage signal during a charging period to determine a corresponding input voltage signal applied across at least one of the phase shifter elements, all second terminals of all the phase shifter elements in the array of phase shifter elements being maintained at a common voltage during the charging period, and an array of switches configured to control connectivity of the driver elements to corresponding phase shifter elements during the charging period, wherein a total number of switches in the array of switches is at least as large as a total number of phase shifter elements in the array of phase shifter elements.

[0006] Aspects can include one or more of the following features.

[0007] An array of phase shifter elements is provided in a photonic integrated circuit.

[0008] An array of driver elements is provided on an electronic integrated circuit which is connected to the photonic integrated circuit.

[0009] An array of switches is provided on an electronic integrated circuit.

[0010] At least one of the driver elements in the array of driver elements includes a digital-to-analog converter whose output voltage is coupled to a plurality of the switches in the array of switches.

[0011] The electronic integrated circuit includes a plurality of capacitors coupled to switches that store charge accumulated during a charging period from an output voltage signal provided by a driver element, the capacitors providing an input voltage signal applied across a phase shifter element.

[0012] The output voltage signal is coupled to a first terminal of one or more phase shifter elements selected in response to an array of switches, and the input voltage signal is provided based on the capacitive characteristics of the phase shifter elements.

[0013] An array of switches is provided in a photonic integrated circuit.

[0014] At least two driver elements in an array of multiple driver elements include digital-to-analog converters whose outputs are coupled to multiple phase shifter elements in different corresponding rows, and multiple column enable signals control connectivity from each of the multiple phase shifter elements in the row to a selected column of multiple phase shifter elements consisting of a single phase shifter element.

[0015] An input voltage signal is provided based on the capacitive characteristics of the phase shifter elements.

[0016] An array of driver elements is provided on the photonic integrated circuit, and an array of switches is provided on the photonic integrated circuit.

[0017] At least two driver elements in an array of multiple driver elements include digital-to-analog converters whose outputs are coupled to multiple phase shifter elements in different corresponding rows, and multiple column enable signals control connectivity from each of the multiple phase shifter elements in the row to a selected column of multiple phase shifter elements consisting of a single phase shifter element.

[0018] An input voltage signal is provided based on the capacitive characteristics of the phase shifter elements.

[0019] Each phase shifter element in an array of phase shifter elements includes a reverse-biased diode device.

[0020] At least one of the phase shifter elements in an array of phase shifter elements includes a plurality of reverse-biased diode devices connected in series with each other.

[0021] At least one of the phase shifter elements in an array of phase shifter elements includes a reverse biased diode device connected directly to an inductor.

[0022] Each switch in the array of switches includes at least a first terminal, a second terminal and a third terminal, and a flow of current between the first terminal and the second terminal is controlled based on a voltage or current applied to the third terminal.

[0023] In another aspect, in general, a method of controlling an optical phased array includes applying an optical phase shift by a plurality of phase shifter elements in an array, each phase shifter element applying an optical phase shift to an optical wave propagating through the phase shifter element and to a corresponding radiator element of the optical phased array, the optical phase shift being based on an input voltage signal applied across a first terminal and a second terminal of the phase shifter element, providing output voltage signals from a plurality of driver elements in an array, each driver element providing an output voltage signal during a charging period to determine a corresponding input voltage signal applied across at least one of the plurality of phase shifter elements, all second terminals of the plurality of phase shifter elements in an array of phase shifter elements being maintained at a common voltage during the charging period, and managing a plurality of switches in an array to control connectivity between the plurality of driver elements and corresponding phase shifter elements during the charging period, wherein a total number of switches in the plurality of switches in an array is at least as large as a total number of phase shifter elements in the plurality of phase shifter elements in an array of phase shifter elements.

[0024] Aspects can include one or more of the following features.

[0025] The charging period includes a period of periodic refresh cycles during which the input voltage signal is refreshed based on the capacitive characteristics of the phase shifter elements.

[0026] Managing the array of switches to control connectivity of the driver elements includes selecting a first switch coupled to a first phase shifter element from a group of phase shifter elements to allow current flow to the first phase shifter element during a charging period, and selecting switches coupled to all other phase shifter elements in the group other than the first phase shifter element to substantially prevent current flow during the charging period.

[0027] Aspects may have one or more of the following advantages.

[0028] The techniques described herein can be used to electronically control integrated optical phased arrays for beam steering purposes. Photonic integrated circuits (PICs) with optical phased arrays feature an ever-increasing number of emitters (e.g., hundreds to tens of thousands or more emitter elements). Each optical phase shifter element coupled to a corresponding emitter element can be controlled using individual phase control to steer the radiation beam formed from the interference between light waves emitted from different emitter elements. Individual optical phase shifter elements (or simply "phase shifter elements") can be electronically controlled by adjusting the voltage across or by adjusting the current through the element. In some system implementations, one or more electronic integrated circuits (EICs) include digital-to-analog converters (DACs) to provide individual optical phase shifter control. In such systems, the EICs can be closely co-designed to meet system constraints including small footprint and low power consumption. Some implementations, described in more detail below, use series switches, each coupled to each phase shifter element, to allow the ability to uniquely address each phase shifter element without undesirable voltage crosstalk with unselected phase shifter elements.

[0029] Other features and advantages will become apparent from the following description, and from the drawings and claims. [Brief description of the drawings]

[0030] The present disclosure is best understood from the following detailed description when read in conjunction with the accompanying drawings, in which: It is emphasized that, according to common practice, the various features of the drawings are not to scale, and on the contrary, dimensions of the various features have been arbitrarily expanded or reduced for clarity.

[0031] [Figure 1] FIG. 1 is a schematic diagram of an exemplary OPA system. [Diagram 2] FIG. 2 is a set of circuit diagrams for a first-order electrical model of an exemplary optical phase shifter. [Diagram 3]FIG. 1 is a schematic diagram of an exemplary OPA system. [Figure 4] FIG. 1 is a schematic diagram of an exemplary OPA system. [Diagram 5] FIG. 1 is a schematic diagram of an exemplary OPA system. [Figures 6A-6C] 6A, 6B, and 6C are plots of example transfer functions for linearizing a code to a phase shift response of a non-linear DAC circuit. [Figure 7] 1 is a flowchart of an exemplary procedure for operating an OPA system. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0032] For an optical phased array (OPA) system with a relatively large number (e.g., thousands) of optical phase shifter elements, it is useful to have an optimized electronic driver circuit in which each individual driver is configured to have a small footprint, low power consumption, and tight electro-optical integration to meet system constraints. This system circuit architecture can utilize device characteristics to reduce the burden on each driver cell, lowering area, power consumption, and packaging complexity. Such an OPA system can be used in any of a variety of contexts, such as, for example, optical transmitter and / or receiver nodes in a LiDAR system or a free-space optical communication system.

[0033] An exemplary OPA system 100 configured for a sample and hold circuit architecture that controls an array of phase shifter (PS) elements 102 of an OPA formed in a PIC 104 is shown in FIG. 1. For example, the phase shifter elements 102 can be implemented as diode structures. The diode structures can be fabricated using silicon photonics fabrication procedures, where light waves are coupled into and out of the phase shifter elements 102 using a network of optical waveguides, and electrical signals (e.g., voltage and / or current) are coupled into and out of the phase shifter elements 102 using a network of wires. The electrical signals control the phase shift applied by the phase shifter elements 102. The resulting phase-shifted light waves are emitted from emitter elements (not shown) that are optically coupled to the output of the corresponding phase shifter elements 102. The resulting coherent interference light waves form a light beam that can be steered according to the applied phase shift. This is described in detail in U.S. Patent Application Publication No. 2020 / 0393737 and U.S. Patent No. 10,809,591. Each of one or more (L counts, where L≧1) control EICs 106-1,...,106-L (commonly referred to as control EICs 106) includes M driver groups 108-1,...,108-M (commonly referred to as driver groups 108), where each driver group 108 holds N driver cells 110-1,...,110-N (commonly referred to as driver cells 110). The packaging interface includes a connection network 120 between connection structures 122 (e.g., copper pillars, wire bonds, solder bumps, gold stud bumps, or other forms of electronic connections) to establish electrical connections between the control EIC 106 and the PIC 104. Alternatively, other examples of OPA systems include monolithic integrated systems using integrated circuits (ICs) with all the elements of the control EIC 106 and the PIC 104, where wires can be fabricated within the IC to provide electrical connections from the driver cells 110 to the unique phase shifter elements 102. Each driver cell 110 includes an analog switch 112 (e.g., a pass gate or a transmission gate that may be implemented using one or more transistors), a sample capacitor 114 (capacity C samp, and a buffer 116 (which may have a single, fixed, or variable gain). The analog switch 112 is in a non-conducting (or "open") state when inactive and establishes a signal conduction path between the input terminal and the output terminal when activated ("closed") based on a control input. The driver group 108 includes a driver element in the form of a single digital-to-analog converter (DAC) 109. An analog output of the DAC 109 is connected to each of the N driver cells 110 in the driver group 108.

[0034] This exemplary architecture requires only one DAC 109 for each driver group 108 of N driver cells 110, thereby reducing the circuit area used within the control EIC 106. The DAC 109 can charge the sample capacitor 114 of a driver cell if that driver cell's analog switch 112 is active. In some implementations, multiple sample capacitors 114 can be sequentially charged by the DAC 109 with only one analog switch 112 in a driver group 108 being active (i.e., closed) at a time. A controller (e.g., a digital controller), which may be included on-chip, includes control interface circuitry 118 within each control EIC 106 to provide the appropriate digital value to the input of each DAC 109. The controller also manages the control of each analog switch 112 to ensure that the correct sample capacitor 114 in a driver group 108 is charged at a given time. The number N of driver cells 110 per driver group 108 can be chosen based on factors including the slew rate of the DAC 109, the parasitic loading of the phase shifter devices, and / or steering time estimated by the system architect. While this exemplary architecture provides area advantages in that only one DAC circuit is required per N driver cells, in other exemplary architectures, multiple DACs or other forms of driver elements configured to drive analog current signals to charge sample capacitors 114 may be included in one or more driver groups.

[0035] Although in the example of FIG. 1 the phase shifter elements 102 are shown in a schematic diagonal arrangement, the physical locations of the phase shifter elements 102 on the substrate of the PIC 104 can be laid out in any distribution, such as a two-dimensional (e.g., row-column) physical arrangement as present in some of the implementations described below (e.g., FIGS. 4 and 5), even if there is no row-column control signal arrangement as present in some of the implementations described below (e.g., FIGS. 4 and 5). Another feature of the OPA system 100 described herein and other OPA system implementations is the connection of the second terminals of all of the phase shifter elements 102 to a common voltage reference 124. For example, the voltage reference 124 can be a zero voltage ground plane or a non-zero fixed voltage source (e.g., a DC supply voltage). The nature of the electrical relationship between the phase shifter elements 102 can mitigate potential bottlenecks otherwise experienced in some row-column control signal arrangements that over-constrain the voltages at the two terminals of the phase shifter elements.

[0036] To avoid additional manufacturing complexity and cost, many modern silicon photonic manufacturing processes do not propose monolithically integrated transistors. In the example of the OPA system 100 shown in FIG. 1, the electronics shown as one or many control EICs 106 (L≧1) are separately manufactured using conventional CMOS processes and then co-packaged with the PIC 104, which is separately manufactured using silicon photonics processes. This example architecture is tolerant to high phase shifter device leakage, high parasitic packaging capacitance, and resistive (thermal) optical phase shifter devices. In this system, the packaging complexity, which is directly proportional to the number of connections (e.g., copper pillars or solder bumps), is still O(n) with respect to the number of phase shifter elements (n=L×M×N). However, similar advantages can be achieved in other examples where some or all circuit elements in the control EIC 106 are monolithically integrated with the PIC 104 in the same wafer manufacturing process. Separate single or multiple EICs may be useful in some implementations when there are limitations on the number of elements that can be driven by a particular type of DAC circuit, or when there are limitations on the number of DACs that can be included in an EIC or PIC, for example, due to the size of the DAC circuit.

[0037] The device-level characteristics of the optical phase shifter have potential impacts on the circuit architecture. Figure 2 shows several example circuits 200A, 200B, 200C and 200D, which correspond to first-order electrical equivalent circuits for different devices that may be used to implement the phase shifter element 102, where the equivalent circuits model the device in its domain of use. In circuit 200A, thermal-based devices are primarily resistive and may be used in parallel with small parasitic capacitances and with drivers (not shown) that can continuously source and / or sink current. For the purpose of low power consumption, circuit 200B is primarily a thermal-based device with capacitance C depSuch a device has a parasitic series resistance R s And, R leak 200C and a device leakage path represented by . If the leakage current is high enough, the open loop device voltage will drop more than a certain amount compared to the voltage associated with the least significant bit (LSB) within a given refresh period, so the device will be considered primarily resistive and will require a driver that can source current continuously. However, if the leakage current is small, the device can hold its set voltage within a certain time. A technique that can be used to reduce leakage current in an optical phase shifter device is by building the device using several diode-based devices connected in series with each other, as shown in circuit 200C. Another potential benefit associated with this series diode configuration is that electric field hot spots are reduced. This can also improve the reliability of the optical phase shifter device. Additionally, an inductor can be added to the device to improve speed through inductive peaking, as shown in circuit 200D. This is described in detail in Suman Sah, Xinmin Yu, and Deukhyoun Heo, “Design and Analysis of a Wideband 15-35-GHz Quadrature Phase Shifter With Inductive Loading,” IEEE Transactions on Microwave Theory and Techniques, Vol. 61. No. 8, p. 3024-3033 (August 2013).

[0038] If the leakage path is small enough that in an open circuit configuration (i.e., when not actively charging via a closed analog switch), the voltage across the optical phase shifter does not drop significantly over a particular refresh period, then the capacitive charge storage characteristics of the phase shifter element 102 can be used in place of a dedicated sample capacitor 114, as described in more detail below.

[0039] When the phase shifter elements are primarily capacitive (e.g., reverse-biased diodes acting as varactors), a streamlined version of the sample-and-hold architecture is possible, as in the exemplary OPA system 300 shown in FIG. 3. An array of capacitive optical phase shifter elements 302 is arranged in the PIC 304 into L×M phase shifter groups 303-1, ..., 303-L×M (commonly referred to as phase shifter groups 303). One or more (L counts, where L≧1) control EICs 306-1, ..., 306-L (commonly referred to as control EICs 306) each include M driver groups 308-1, ..., 308-M (commonly referred to as driver groups 308). Here, each driver group 308 includes a DAC 309 as a driver element that provides a current to charge the phase shifter elements 302. The DAC used as the driver element supplies the current by providing an output voltage according to a predetermined digital value. In other implementations of the driver elements, the output voltage provided may be determined in response to any type of input. In the case of capacitive phase shifter elements, the (typically nonlinear) current provided substantially stops flowing when the output voltage from the driver element is substantially the same as the input voltage across the corresponding phase shifter element. A set of N analog switches 312 (e.g., pass gates or transmission gates that may be implemented using one or more transistors) provide controllable connections between the DACs 309 in the driver group 308 and the individual phase shifter elements 302 in the corresponding phase shifter group 303 of the PIC 304. In some implementations, only one analog switch 312 per driver group 308 is active (i.e., closed) at a time, thereby allowing a given DAC 309 to connect to a single phase shifter element 302 at a time. A controller (e.g., a digital controller), which may be included on-chip, controls the appropriate analog switches 312 to connect the DACs 309 in the driver group 308 to an appropriate phase shifter element 302 in the PIC 304. The packaging interface includes a connection network 320 between connection structures 322 and a common voltage reference 324 connecting the terminals of all of the phase shifter elements 302 .

[0040] If the phase shifter element 302 is capacitive in nature (e.g., a reverse-biased diode with minimal leakage current), the phase shifter element 309 can effectively act as its own sample and hold capacitor. Over time, a phase shifter element 309 in open circuit mode (i.e., not actively charging through a closed analog switch) will experience a voltage drop. The controller can ensure that the voltage of the phase shifter element 302 is refreshed prior to a voltage drop having a significant system impact. The controller can allow for smart refreshing. For example, some high voltage optical phase shifters require more frequent refreshing than their lower voltage counterparts. This exemplary architecture has the advantage of requiring only one DAC 309 per N phase shifter elements 302, and also has the advantage of eliminating the dedicated sample capacitor 114 and buffer 116, saving additional layout area and power. Several system considerations can influence the grouping scheme. For example, the slew rate of the DAC, the parasitic capacitance of the phase shifter device, the voltage drop due to leakage, and the system steering time specifications can all affect how many phase shifter elements 302 can be associated with one DAC 309. However, the packaging complexity is still O(n) with respect to the number of phase shifter elements (n=L×M×N).

[0041] It may be difficult (e.g., cost prohibitive) for silicon photonics processes to provide a full-featured monolithically integrated CMOS with the process capabilities required to provide a complete beam steering controller. For example, a phase shifter with a high 2π reverse bias voltage may require thick oxide power transistors, or the digital control electronics may require leading-edge process nodes. However, providing a limited set of low performance transistors that can function as analog switches in a photonic integrated circuit is not so difficult, thus providing the advantage of a system architecture that allows the control electronics to be fabricated in a separate CMOS process. An exemplary OPA system 400 using such an architecture is shown in FIG. 4. An array of phase shifter (PS) elements 402 is arranged in a PIC 404 into L×M phase shifter groups 403-1, ..., 403-L×M (generally referred to as phase shifter groups 403). One or more (L counts, where L>=1) control EICs 406-1, ..., 406-L (generally referred to as control EICs 406) each include M driver groups 408-1, ..., 408-M (generally referred to as driver groups 408), where each driver group 408 includes N driver elements, which in this example are DACs 409-1, ..., 409-N (generally referred to as DACs 409). In this example, the control EIC 406 is closely co-packaged with the PIC 404, and the packaging interface 420 includes connection structures 422 that provide electrical connections between the DACs 409 and a row of C phase shifter elements 402. A controller (e.g., a digital controller), which may be included on-chip, includes interface circuitry 418 within each control EIC 406 to provide appropriate digital values ​​to the input of each DAC 409 and to provide C column enable signals (i.e., column 1 enable, ..., column C enable) that control the activation of analog switches 412 so that a single DAC 409 can charge individual phase shifter elements 402 that are arranged in a row of phase shifter elements that are electrically coupled to the analog output of that DAC 409.In the PIC 404, the L×M×N×C phase shifter elements 402 are organized into N rows and C columns in each of the L×M phase shifter groups 403. In some implementations, the logical grouping of the row-column arrangement also corresponds to the physical row-column arrangement of the phase shifter elements 402 on the PIC 404 substrate. The grouping of the DAC 409 and the phase shifter elements 402 can be determined based on system architecture tradeoffs. Some examples of this architecture rely on the ability of each phase shifter element 402 to act as its own sample capacitor, as described above. The advantage of this architecture of the OPA system 400 compared to the architecture of the OPA system 300 or the OPA system 100 is that the packaging complexity can potentially be reduced from O(n) to O(√n) (n=L×M×N×C). In the example OPA system 400, the analog switch 412 is represented as an n-channel metal-oxide-semiconductor (NMOS) transistor, but may be, for example, a bipolar junction transistor (BJT), a p-channel metal-oxide-semiconductor (PMOS) transistor, or a pass gate, or any similarly functioning circuit element.

[0042] Silicon photonics processes incorporating CMOS transistors can be used to integrate some or all of the control circuitry into a PIC that contains both photonic components and waveguides that carry optical signals, and electronic components and wires that carry electrical signals. FIG. 5 shows an example of a monolithically integrated OPA system 500. This avoids the need for the complexities associated with packaging multiple integrated circuits. An array of phase shifter (PS) elements 502 are arranged into M phase shifter groups 503-1, ..., 503-M (commonly referred to as phase shifter groups 503) in a monolithic PIC 504 that contains the electronic elements of the previously separated EIC. In this example, N DACs 509-1, ..., 509-N (commonly referred to as DACs 509) are included in each phase shifter group 503. A controller (e.g., a digital controller), which may be included on-chip, includes interface circuitry 518 to provide appropriate digital values ​​to the inputs of each DAC 509 and to provide C column enable signals (i.e., column 1 enable, ..., column C enable). The column enable signals control activation of analog switches 512 so that a single DAC 509 can charge individual phase shifter elements 502 arranged in a row of phase shifter elements that are electrically coupled to the analog output of that DAC 509. Each phase shifter element 502 can act as its own sample capacitor, reducing system power due to small parasitic capacitance and effectively eliminating packaging complexity due to monolithic integration.

[0043] Generally, DAC circuits are designed with linearity as a circuit goal. However, in some implementations of OPA systems, there are advantages to having a nonlinear DAC circuit. FIG. 6A shows an example of a phase shifter response that illustrates how a device implementing one of the phase shifter elements can have a nonlinear relationship between the applied voltage (based on the amount of charge stored in the device's capacitive charge storage) and the resulting optical phase shift. An example of the associated nonlinear relationship between a particular digital code value input to a nonlinear DAC and the resulting DAC analog voltage at the output of the nonlinear DAC is shown in FIG. 6B. The effect of devices with these characteristics being cascaded together is that the DAC digital input code value can be linearly phase shifted as shown in FIG. 6C. Alternatively, in some implementations, a nonlinear DAC can be used to save power or area in the system, and calibration can be performed elsewhere in the system.

[0044] 7 shows a flow chart of an exemplary procedure 700 for operating an OPA system described herein in which an operating voltage close to a target voltage is maintained by charge delivery to associated capacitors and / or by characteristic capacitance of the phase shifter elements themselves during a periodic refresh cycle that includes a series of charging periods. The procedure 700 includes an operating loop 702 in which there are certain voltages being driven by driver elements to control the phase shift of various phase shifter elements. In each pass of the operating loop 702, the procedure 700 includes managing 704 an array of switches to control connectivity between the driver elements and corresponding phase shifter elements during the charging period. The procedure 700 includes a refresh loop 706 in which the driver elements are electrically connected to the phase shifter elements. Each driver element provides an output voltage 708 during the charging period to determine a corresponding input voltage signal to be applied across at least one of the phase shifter elements. The procedure 700 includes applying 710 an optical phase shift by the phase shifter elements of the array. Each phase shifter element applies an optical phase shift to an optical wave propagating through the phase shifter element and to a corresponding radiator element of the optical phased array, where the optical phase shift is based on an input voltage signal applied between a first terminal and a second terminal of the phase shifter element. In some implementations, all second terminals of all phase shifter elements in an array of phase shifter elements are maintained at a common voltage during a charging period. In some implementations, a total number of switches in an array of switches is at least as large as a total number of phase shifter elements in an array of phase shifter elements.

[0045] While the present disclosure has been described in connection with certain embodiments, it is to be understood that the present disclosure is not limited to the disclosed embodiments, but on the contrary, is intended to cover various modifications and equivalent arrangements included within the scope of the appended claims, which scope is to be accorded the broadest interpretation so as to encompass all modifications and equivalent structures permitted under law.

Claims

1. An apparatus comprising: an array of multiple radiator elements; an array of phase shifter elements, each configured to apply an optical phase shift to a light wave propagating through the phase shifter element and to a corresponding radiator element, the optical phase shift being based on an input voltage signal applied across a first terminal and a second terminal of the phase shifter element; an array of driver elements, each driver element configured to provide an output voltage signal to determine a corresponding input voltage signal applied across at least one of the phase shifter elements during a charging period associated with charging at least one of the phase shifter elements or a capacitor associated with at least one of the phase shifter elements, and wherein all of the second terminals of all of the phase shifter elements in the array of phase shifter elements are maintained at a common voltage during the charging period; an array of switches configured to control connectivity between the driver elements and corresponding phase shifter elements during the charging period; Including, An apparatus, wherein a total number of switches in the array of multiple switches is at least as large as a total number of phase shifter elements in the array of multiple phase shifter elements.

2. The apparatus of claim 1 , wherein the array of phase shifter elements is disposed in a photonic integrated circuit.

3. The apparatus of claim 2 , wherein the array of driver elements is provided on an electronic integrated circuit that is connected to the photonic integrated circuit.

4. The apparatus of claim 3 , wherein the array of switches is disposed on the electronic integrated circuit.

5. 5. The apparatus of claim 4, wherein at least one of the driver elements in the array of driver elements includes a digital-to-analog converter having an output voltage coupled to more than one of the switches in the array of switches.

6. the electronic integrated circuit includes a plurality of capacitors coupled to switches for storing charge accumulated from output voltage signals provided by the plurality of driver elements during the charging period; The apparatus of claim 5 , wherein the multiple capacitors provide an input voltage signal that is applied across the multiple phase shifter elements.

7. the output voltage signal is coupled to a first terminal of one or more of the phase shifter elements selected in response to a plurality of switches in the array; The apparatus of claim 5 , wherein the input voltage signal is provided based on a capacitive characteristic of the multiple phase shifter elements.

8. The apparatus of claim 3 , wherein the array of switches is disposed in the photonic integrated circuit.

9. At least two driver elements in the array of driver elements include digital-to-analog converters having outputs coupled to phase shifter elements in different corresponding rows; 9. The apparatus of claim 8, wherein a plurality of column enable signals control connectivity of a selected column of phase shifter elements to a single phase shifter element from each of the corresponding rows of phase shifter elements.

10. The apparatus of claim 9 , wherein the input voltage signal is provided based on a capacitive characteristic of the multiple phase shifter elements.

11. The apparatus of claim 2 , wherein the array of driver elements is disposed on the photonic integrated circuit and the array of switches is disposed on the photonic integrated circuit.

12. At least two driver elements in the array of driver elements include digital-to-analog converters having outputs coupled to phase shifter elements in different corresponding rows; 12. The apparatus of claim 11, wherein a plurality of column enable signals control connectivity of a selected column of phase shifter elements to a single phase shifter element from each of the corresponding rows of phase shifter elements.

13. The apparatus of claim 12 , wherein the input voltage signal is provided based on a capacitive characteristic of the multiple phase shifter elements.

14. 2. The apparatus of claim 1, wherein each phase shifter element in the array of phase shifter elements comprises a reverse-biased diode device.

15. 15. The apparatus of claim 14, wherein at least one of the phase shifter elements in the array of phase shifter elements comprises a plurality of reverse-biased diode devices connected in series with each other.

16. 15. The apparatus of claim 14, wherein at least one of the phase shifter elements in the array of phase shifter elements includes a reverse-biased diode device connected directly to an inductor.

17. 2. The apparatus of claim 1, wherein each switch in the array of switches includes at least a first terminal, a second terminal, and a third terminal, and a flow of current between the first terminal and the second terminal is controlled based on a voltage or current applied to the third terminal.

18. 1. A method for controlling an optical phased array, comprising: applying an optical phase shift by an array of phase shifter elements, each phase shifter element applying an optical phase shift to a light wave propagating through the phase shifter element and to a corresponding radiator element of the optical phased array, the optical phase shift being based on an input voltage signal applied across a first terminal and a second terminal of the phase shifter element; providing output voltage signals from an array of driver elements, each driver element providing an output voltage signal to determine a corresponding input voltage signal applied across at least one of the phase shifter elements during a charging period associated with charging at least one of the phase shifter elements or a capacitor associated with at least one of the phase shifter elements, and all second terminals of all of the phase shifter elements in an array of phase shifter elements being maintained at a common voltage during the charging period; managing an array of switches to control connectivity between said driver elements and corresponding phase shifter elements during said charging period; Including, A method, wherein a total number of switches in the array of switches is at least as large as a total number of phase shifter elements in the array of phase shifter elements.

19. 20. The method of claim 18, wherein the charging interval comprises a period of a periodic refresh cycle during which the input voltage signal is refreshed based on capacitive characteristics of the multiple phase shifter elements.

20. Managing the array of switches to control connectivity of the driver elements includes: selecting a first switch coupled to a first phase shift element from the group of the plurality of phase shift elements to permit current flow to the first phase shift element during the charging period; selecting switches coupled to all phase shifter elements other than a first phase shifter element in said group to substantially prevent current flow during said charging period; 20. The method of claim 18, comprising:

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