Drift and Noise Compensated Memristive Devices

Abstract

The memristor memory device includes a memristive memory cell, an input terminal, an output terminal, and a gate terminal. The input terminal and the output terminal are directly attached to the memristive memory cell, and the gate terminal is electrically isolated from the memristive memory cell. The gate terminal is configured to receive an electrical signal for volatile modulation of the conductance of the memristive memory cell to achieve compensation for non-ideal conductance modulation of the memristor memory device.

Description

[Technical field]

[0001] Disclosed herein are memristor memory devices comprising memristive memory cells. More specifically, the present disclosure is directed to methods of operating memristor memory devices comprising memristive memory cells. [Background technology]

[0002] Multi-Level Cell (MLC) storage is a typical way to achieve increased capacity and therefore lower the cost per bit in memory technologies. For this, for example, Phase Change Memory (PCM), which exploits the thermally induced resistivity change of chalcogenide components for non-volatile data storage, is a new solid-state memory technology. PCM has several characteristics such as high cycle endurance, low read / write latency, and good scalability that make it an interesting candidate not only to extend and eventually replace existing flash memory, but also to enable disruptive changes in future computing systems. The latter stems from PCM's potential ability to act as both storage (non-volatile, cheap, large capacity) and memory (fast, durable) due to its universal properties. Summary of the Invention

[0003] According to one embodiment disclosed herein, a memristive memory device including a memristive memory cell may be provided. The memristive memory device may include an input terminal, an output terminal, and a gate terminal. The input terminal and the output terminal may be directly attached to the memristive memory cell, and the gate terminal may be electrically isolated from the memristive memory cell. The gate terminal may be configured to receive an electrical signal for volatile modulation of the conductance of the memristive memory cell. Thereby, non-ideal conductance modulation of the memristive memory device may be compensated for.

[0004] According to another aspect disclosed herein, a method of operating a memristive memory device comprising a memristive memory cell may be provided. The memristive memory device may comprise an input terminal, an output terminal, and a gate terminal, and the input terminal and the output terminal may be directly attached to the memristive memory cell. The gate terminal may be electrically isolated from the memristive memory cell. The method may further include providing an electrical signal for volatile modulation of the conductance of the memristive memory cell. Thereby, non-ideal conductance modulation of the memristive memory device may be compensated.

[0005] The embodiments of the present invention are described with reference to different subject matters. In particular, some embodiments are described with reference to claims in the form of a method, whereas other embodiments are described with reference to claims in the form of an apparatus. However, a person skilled in the art will infer from the above and following description that, unless otherwise informed, any combination of features belonging to a subject matter of a certain form, as well as any combination between features relating to different subject matters, in particular between features of a claim in the form of a method and a claim in the form of an apparatus, is considered as disclosed in this document.

[0006] The above-defined aspects, and further aspects of the various embodiments, will be apparent from and will be explained with reference to the example embodiments described below, to which the invention is not limited. Various embodiments may be described as having certain advantages, however, some embodiments may not have these potential advantages, and these potential advantages are not necessarily required for all embodiments.

[0007] Embodiments will now be described, by way of example only, with reference to the following drawings, in which: [Brief description of the drawings]

[0008] [Figure 1]FIG. 2 is a block diagram of one embodiment of a memristor memory device of the present invention comprising a memristive memory cell according to some embodiments. [Diagram 2] FIG. 1 is a block diagram of the functional principle of the proposed system and method according to some embodiments. [Diagram 3] FIG. 2 is a block diagram of one embodiment of a crossbar array having memristor memory devices in accordance with some embodiments. [Figure 4] FIG. 1 is a block diagram of one embodiment of a crossbar array having a temperature noise and resistance drift compensation unit in accordance with some embodiments. [Diagram 5] 1 is a diagram of a first experimental proof of the proposed system and method according to some embodiments. [Figure 6] FIG. 11 is a diagram of a second experimental proof of the proposed system and method according to some embodiments. [Figure 7] 1 is a flowchart of one embodiment of a method of operating a memristor memory device comprising memristive memory cells in accordance with some embodiments. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0009] For PCM to become a viable technology for higher volume production, several issues may need to be addressed. First and foremost, the reliability of the technology should be brought to a level similar to that of existing technologies. Experimental results and simulations suggest that thermal disturbance and resistance drift are the most important potential reliability issues for PCM memory technology. Thermal disturbance refers to the problem of a cell's state being inappropriately altered by programming another cell and its surroundings (thermal process talk). Resistance drift, on the other hand, is a phenomenon that follows, for example, the increase in resistivity of the amorphous phase of many chalcogenide materials over time. Drift is due to structural relaxation and stress relief in the amorphous matrix and is particularly unfavorable in multilevel cell storage, since random fluctuations of the programmed resistance of closely spaced levels may cause them to overlap and thus lead to decoding errors. This task may be addressed by the technical solution proposed here.

[0010] In the context of this description, the following definitions, terms or expressions, or combinations thereof, may be used:

[0011] The term "memristor memory device" (a portmanteau of memristor = memory resistor) is a memory device based on memristive cells, i.e. memristors. It may refer to a nonlinear, usually two-terminal, electrical component that associates charge with magnetic flux linkage, but is here implemented as a three-terminal device. For the device, typically a phase change material (PCM) may be used. Such a PCM may change its resistivity between several different levels by going from an amorphous to a crystalline phase. This change may be thermally induced. In this way, a multi-level cell (MLC) storage device may be formed, comprising several memristive memory cells.

[0012] The term "memristive memory cell" may refer to the memristor core unit or memristive memory cell of a memory device. A memristive memory cell may comprise a phase change material and may store data by changing its resistivity. Typically, during read, a selected bit line of a crossbar array with multiple memristive memory cells at its crosspoints is biased to a constant voltage (typically a few hundred mV) by a voltage regulator. The sensed current i read may be captured by a capacitor and the resulting voltage is then digitized by an on-chip cyclic analog-to-digital converter. Additionally, the read characteristics can be calibrated by the use of an on-chip reference polysilicon resistor. For programming, a voltage generated off-chip is applied to the programming current i prog This count can then be mirrored onto selected bit lines for the desired duration of a programming pulse, which can change the mix of crystalline and amorphous phases of the PCM.

[0013] The term "gate terminal" can refer to a (third) electrode adjacent to, but electrically isolated from, the PCM of a memristive memory cell. Charges at the gate terminal and at the gate itself can affect the behavior of the PCM, i.e., each single memristive memory cell, and therefore also the behavior within a memristive memory device by wiring the gates of multiple single memristive memory cells.

[0014] The term "volatile modulation" (specifically, gate-induced volatile modulation) may refer to the forced modification of the resistivity of a memristive memory cell device by an applied gate voltage.

[0015] The term "non-ideal conductance modulation" can refer to effects in PCM-based devices, such as memristor memory devices that include multiple memristive memory cells using PCM, due to temperature-based effects and resistance drift effects.

[0016] The term "resistance drift" may refer to the phenomenon according to which the resistivity of the amorphous phase of a phase change material (e.g., a chalcogenide) increases over time. Drift may be caused by structural relaxation and stress relief in the amorphous matrix of the PCM and is particularly undesirable in multilevel cell storage devices due to the random variation in the program to resistance of closely spaced resistance levels. Despite the use of adaptive level thresholds, the bit error rate of MLC PCMs deteriorates over time as the noise margin between adjacent levels tends to increase. This is because drift is a random process and therefore the increase in resistance of each cell invoices in a stochastic manner. Also, the rate of increase, i.e., the drift exponent, is itself a random variable. While it is true that the average drift exponent increases with the cell resistance, significant variations are typically observed around the mean value. As a result of this, a few cells in each resistance distribution exhibit drift exponents that are distinct from the others. For example, the drift versus time trajectories of two such cells programmed at adjacent levels “2” and “3” may show that the cell levels after programming are quite far apart, but eventually shift closer together and eventually cross each other at later time instances and with shift exponents that deviate from the average behavior.

[0017] The term "thermal disturbance drift of resistance" can refer to the undesirable effect of thermal changes in memristive memory cells that unintentionally change the state of a cell by programming another cell in its vicinity, and is relevant for PCMs, since the latter is due to the state changes used in the family that can cause thermal interference between adjacent cells in small device dimensions. Disturbances in the resistance state can also result from variations in chip temperature due to thermal changes in the environment.

[0018] The term "filamentary memristor" may refer to a memristive switching effect in an insulating or semiconducting solid electrolyte that occurs due to the formation of a conductive channel (filament).

[0019] The term "crossbar array" may refer to a structure of conductive lines that cross each other. The horizontal lines may define word lines, while the vertically oriented lines may be denoted as bit lines. Each intersection of the word lines and bit lines may comprise an electrical or electronic device connected at one end to the word line and the respective bit line. In this concept, a crossbar array with a plurality of memristive memory cells may constitute the core building blocks of a memristor memory device, with a memristive memory cell at each intersection.

[0020] The term "temperature effect control unit" may denote an electronic unit adapted to counteract the above-mentioned thermal disturbance effects.

[0021] The term "resistance drift correction unit" may denote an electronic unit adapted to counteract the above-mentioned resistance drift effects present in a PCM.

[0022] The proposed memristor memory device comprising memristive memory cells may provide multiple advantages, contributions and technical effects.

[0023] Essentially, it may overcome the current challenges of PCM-based memristive memory devices and lay the foundation for them to become a viable technology (potentially replacing flash memory) for more productive memory, and potentially computing devices. By overcoming the negative effects caused by thermal disturbance and resistance drift effects, i.e. volatile conductance modulation, it may increase the reliability of PCM-based memory technologies. In detail, the stochastic manifestation of resistance drift effects has a significant negative impact on currently available PCM-based memristive memory devices, which may be overcome with the proposed concept.

[0024] In particular, the gate terminal can be used to counteract the resistance drift effect. The required additional electronic components in the form of a temperature compensation unit and a resistance drift compensation unit are insignificant when compared to the resulting technical effect as shown by experimental evidence. The compensation unit can be used for larger memristors of multiple memristor memory devices or memory units comprising multiple memristor memory devices. In particular, the random process based resistance drift effect can be exploited by the dynamically adapted gate signal generated by the resistance drift compensation unit.

[0025] In the following, additional embodiments of memristive memory devices (which are also applicable to the related methods) are described.

[0026] According to one embodiment of a memristor memory device, non-ideal conductance modulation may include at least resistance drift over time and / or temperature-induced perturbation of resistance. These may be the primary effects adversely affecting the reliability of memristor memory devices. However, other non-ideal conductance modulations may be addressed and potentially restored by the use of gate structures adjacent to the PCM of the memristor memory cell.

[0027] According to one embodiment of a memristor memory, the memristive memory cell may comprise a phase change material or a filamentary electrolyte. These are typical examples of PCMs. However, other types of base materials for memristive memory cells may be used to apply the inventive concept proposed here, as long as the negative temperature effect, or resistance drift, or both, affect the PCM and related devices.

[0028] According to a useful embodiment of the memristor memory device, the memristor memory device may comprise a plurality (particularly, two or more) of memristor memory cells, where a gate terminal is common to a plurality of the memristor memory cells. In an industrial scale memristor memory device, potentially millions of memristor memory cells may be combined to form a memristor memory device. At least some of the memristor memory cells may have gates electrically connected thereto. They may allow influencing the memristor memory cells connected to a common gate line. Thus, a group of memristor memory cells of the memristor memory device may be influenced by gate charge to counteract negative temperature effects and resistance drift.

[0029] According to an advantageous embodiment of the memristor memory device, a plurality of memristor memory devices may be arranged in a crossbar array to form a memristor memory unit. The memristor memory unit may be a core component of the memristor memory device. In this manner, a memristor memory cell may be addressable by a word line and a bit line when one of the memristor memory cells is located at the intersection of the word line and the bit line, respectively.

[0030] According to another advantageous embodiment, the memristor memory device may further comprise a temperature effect control unit, the output of which may be adapted to provide a temperature effect control signal corresponding to a temperature difference ΔT between an ideal working temperature of the memristor memory device and a non-ideal dynamically changing temperature of the memristor memory device. This may advantageously reflect the temperature evolution of the memristor memory device over time, particularly the actual temperature during read operations and historical temperature evolution, by write (i.e., programming) operations. By having access to the temperature evolution over time, the temperature effect control unit may compensate for the associated effects by anticipating the associated effects of the temperature evolution over time.

[0031] According to a further advantageous embodiment of the memristor memory device, the temperature effect control unit comprises a temperature sensor electrically connected to the temperature effect control unit and a temperature effect control signal having a value V T,gate to a group of gate terminals of selected ones of the multiple memristor memory devices. T,gate and a conversion unit. The group can range from a single memristive memory cell to an entire memristive memory cell. Advantageously, memristive memory cells that together exhibit closely related temperature dependencies can be grouped together. The temperature sensor can generate a signal that depends on the actual temperature of the two or more memristive memory devices.

[0032] According to a further enhanced embodiment of the memristor memory device, the pre-calibrated ΔT / V T,gate The conversion unit converts the digital temperature effect control signal connected to the gate terminals of the multiple memristor memory devices that make up the memristor memory unit into an analog value V T,gate The memory device may further include a first digital-to-analog converter adapted to convert a volatile modulation due to temperature effects of the resistance of the group of memristive memory cells (i.e., devices) into a signal such that the volatile modulation due to temperature effects of the resistance of the group of memristive memory cells (i.e., devices) may be corrected and / or compensated for.

[0033] According to another advantageous embodiment, the memristor memory device may further comprise a resistance drift correction unit, the output of which is adapted to provide a resistance drift control signal corresponding to a resistance difference ΔR between a target resistance of the memristor memory device and a read resistance of the memristor memory device. The read resistance may be measured immediately after a programming / writing operation. This may define a reference value for the resistivity of each memristor memory cell. Based on this value, a correction or compensation signal for the gate may be generated.

[0034] According to a further enhanced embodiment of the memristor memory device, the resistance drift correction unit is configured to provide a resistance drift correction control signal having a value V R Voltage ,gate to a group of gate terminals of selected ones of the plurality of memristor memory devices. R,gate A conversion unit may further be included. As in the case of temperature compensation, the group may range from a single memristive memory cell to an entire memristive memory cell. Advantageously, memristive memory cells that together exhibit closely related temperature dependencies may be grouped.

[0035] According to another further enhanced embodiment of the memristor memory device, ΔR / V R,gate The conversion unit converts the digital resistive effect control signal into an analog value V, which is connected to the gate terminals of the multiple memristor memory devices that make up the memristor memory unit. R,gate The memory cell may further include a second digital-to-analog converter adapted to convert the signal into a volatile modulation due to resistance drift effects of the resistance of the group of memristive memory cells.

[0036] According to a further embodiment, the memristor memory unit may comprise a plurality of memristor memory devices arranged in a crossbar array, each memristor memory device comprising a memristive memory cell, the memristor memory device comprising an input terminal (particularly adjacent to the memristive memory cell), an output terminal, and a gate terminal, the input terminal and the output terminal may be directly attached to the memristive memory cell. Thereby, the gate terminal may be electrically isolated from the memristive memory cell, and the gate terminal may be configured to receive an electrical signal for volatile modulation of the conductance of the memristive memory cell. Thereby, non-ideal conductance modulation of the memristor memory device may be compensated. The memristor memory unit may further comprise a temperature effect control unit adapted to generate a portion of the received electrical signal based on a temperature-based resistance drift effect of each memristor memory device, and a resistance drift compensation unit adapted to generate another portion of the received electrical signal based on a time-dependent resistance drift effect of each memristor memory device. Thus, in a memristor memory device comprising multiple memristor memory units, each memristor memory unit may comprise a separate correction / compensation unit such that different areas within the memristor memory device may be processed separately, for example based on local differences between the memristor memory units.

[0037] In the following a detailed description of the figures is given. All instructions in the figures are schematic. First a block diagram of one embodiment of the inventive memristor memory device comprising memristor memory cells is given. Then further embodiments and embodiments of a method of operating a memristor memory device comprising memristor memory cells are described.

[0038] 1 is a block diagram of one embodiment of a memristor memory device 100 comprising a memristive memory cell 102. The memristor memory device (MME) may be based on, for example, a PCM or a filamentary electrolyte. The memristor memory device 100 comprises at least the memristor memory cell 102, as well as an input terminal (drain via electrical connection 106) 104, an output terminal (source via electrical connection 110) 108, and a gate terminal 112.

[0039] The input terminal 104 and the output terminal 108 are directly attached to the memristive memory cell 102, and the gate terminal 112 is electrically isolated from the memristive memory cell 102, for example, by a dielectric (non-conductive) layer 116. The gate terminal 112 is configured to receive an electrical signal (via line 114) for volatile modulation of the memristive memory cell's conductance to provide correction or compensation for non-ideal conductance modulation of the memristive memory device 102.

[0040] Figure 2 is a block diagram of the functional principle 200 of the proposed system and method. A memristive memory cell 202 (as the core of a memristor memory device) can be programmed by a signal 204. After programming the memristive memory cell to a certain resistance level, the target resistance 206 is known (either by being read immediately after programming or by being read from a look-up table, for example). To compensate for resistance drift effects during a read operation, the gate 212 of the memristive memory cell 202 can be utilized for a volatile modulation of the device conductance. Thereby, the output V of the gate gate is scaled proportionally to the difference ΔR in the measured resistance and the target resistance. The proportionality constant can be defined to correct for drift with various degrees of accuracy. The reference unit 208 scales the value ΔR ref It can deliver the necessary signals corresponding to the

[0041] Furthermore, the gate 212 can also be used to correct temperature noise effects (temperature-induced drift) during the read process on the resistance of the memristive cell 202. For this purpose, the gate 212 is utilized for a volatile modulation of the device conductance (corresponding to the resistance drift). The output of the gate V gate scales proportionally to the difference ΔT between the temperature of the chip under ideal conditions and the temperature 210 of the chip (as measured by the sensor) under non-ideal, dynamically changing conditions (e.g., affected by "programming heat" or other environmental temperature changes). The proportionality constant can be defined to correct for drift with various degrees of accuracy.

[0042] Thus, the memristive memory cell unit can be corrected for both resistance drift and thermal disturbance during a read operation. Furthermore, any non-ideal conductance modulation can be corrected and / or compensated for by gate signal actions independent of the conductance state of the PCM of the memristive memory cell 202.

[0043] 3 is a block diagram of one embodiment of a crossbar array 300 having memristor memory devices 302. The crossbar array 300 includes horizontal word lines 304 (only one of which is labeled with a reference numeral) and vertical bit lines 310 (only one of which is labeled with a reference numeral) for addressing a plurality of memristor memory devices 302 at each cross point. The word lines 304 and bit lines 310 are used to address each memristor memory device 302. The word lines 304 can be made conductive by terminals 306, 308, 312. The terminal for the bit line 310 is not explicitly shown. The crossbar array 300 represents an i×j matrix of columns of memristor memory devices 302.

[0044] Additionally, gate contacts (not numbered) are shown for each memristor memory device 302. These gate contacts are diagonally connected to the word lines 304 and bit lines 310. The diagonal gate lines (not explicitly numbered) connect multiple memristor memory devices 302 across the diagonally arranged intersections of the word lines 304 and bit lines 310. Gate voltages may be applied to the gate terminals 314,...,320. Each gate voltage is effective only for the addressed memristor memory device 302. During read, a current I i can be captured and converted by an analog-to-digital converter. ij The top right column 322 may be implemented as a reference resistor.

[0045] 4 is a block diagram 400 of one embodiment of a crossbar array 300 having a temperature noise compensation unit and a resistance drift compensation unit 402, 404. The output signals of the crossbar array 300 (including the output signals of the string of reference resistors 322 (see FIG. 3)) are fed back to the resistance drift compensation unit 404 by an analog-to-digital converter 406 as a differential signal R 11 -R ij where the pre-calibrated ΔR / V R,gate A signal is generated, converted by a digital-to-analog converter 408 connected to a gate (control) signal unit 410, and addressed to each gate line in the crossbar array 300 (via symbolic connection 412) to compensate for the effects of resistance drift during a read operation.

[0046] Further, the temperature compensation unit 402 includes a temperature sensor and converts the measured temperature of the crossbar array 300 into a signal corresponding to a temperature difference between the measured temperature of the crossbar array 300 and the memristive memory cells or an ideal temperature of the crossbar array 300, thereby compensating for the effects of thermal disturbances that adversely affect the expected resistance levels of two or more memristive memory cells of the crossbar array 300. Also, herein, the pre-calibrated ΔT / V T,gate A conversion is performed, which is converted by a digital to analog converter 414 and sent via symbolic connections 412 to a gate (control) signal unit 410 for addressing the respective gate lines in the crossbar array 300.

[0047] FIG. 5 is a diagram 500 of the first experimental proof of concept of the proposed system and method. The X-axis shows the time that the resistance (Y-axis, left side) changes over time. The right Y-axis shows the voltage V gate is shown, and the respective change in resistance drift can be observed after about 100 seconds. Drift correction using gates can reduce the drift coefficient by more than three orders of magnitude.

[0048] FIG. 6 shows a diagram 600 of a second experimental proof of concept of the proposed system and method. The top diagram is a typical uncorrected resistance drift effect over time. The middle diagram shows the corrected resistance values ​​showing only a drift factor of −0.006. The bottom partial diagram shows a standard deviation of the drift factor of about 0.02.

[0049] Thus, the experimental results demonstrate that thermal disturbances and resistance drift can be very effectively addressed by the method and associated system proposed here for the practical use of memristor memory devices in industrial applications.

[0050] 7 is a flow chart of one embodiment of a method 700 of operating a memristive memory device including a memristive memory cell. The method 700 includes, at operation 702, providing a memristive memory device having an input terminal, an output terminal, and a gate terminal, where the input terminal and the output terminal are directly attached to the memristive memory cell and the gate terminal is electrically isolated from the memristive memory cell.

[0051] The method 700 also includes, in operation 704, providing an electrical signal for volatile modulation of the conductance of the memristive memory cell, thereby compensating for non-ideal conductance modulation to the memristor memory device (as described above), in operation 706.

[0052] The description of various embodiments has been given for illustrative purposes, but is not exhaustive and is not limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terminology used in this specification has been selected to best explain the principles, practical applications, or technical improvements of the embodiments over the art found in the market, or to enable those skilled in the art to understand the embodiments disclosed herein.

[0053] Various embodiments may be embodied as systems and methods. Aspects of various embodiments are described herein with reference to flowchart illustrations of methods and / or block diagrams of apparatus (systems). It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer readable program instructions.

[0054] The flowcharts and / or block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments. In this regard, each block in the flowcharts or block diagrams may represent a module, segment, or portion of instructions that includes two or more executable instructions for performing a particular logical function. In some alternative implementations, the functions shown in the blocks may occur out of the order shown in the figures. For example, two blocks shown in succession may in fact be executed substantially simultaneously, or in some cases the blocks may be executed in the reverse order, depending on the functionality involved. It should also be noted that each block of the block diagrams and / or flowchart diagrams, and combinations of blocks in the block diagrams and / or flowchart diagrams, may be implemented by a special-purpose hardware-based system that performs a particular function or act, or executes a combination of special-purpose hardware instructions and computer instructions.

[0055] The terminology used herein is merely for the purpose of describing certain embodiments and is not intended to limit the present invention. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and / or "comprising" as used herein specify the presence of stated features, integers, steps, operations, elements, or components, or combinations thereof, but do not exclude the presence or addition of two or more other features, integers, steps, operations, elements, components, or groups thereof, or combinations thereof.

[0056] Corresponding structures, materials, acts, and equivalents of all means or step-plus-function elements in the following claims include any structure, material, or act for performing a function in combination with other claimed elements as specifically claimed. The description of various embodiments has been presented for purposes of illustration and description, but is not intended to be exhaustive or to limit the invention in the disclosed form. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the invention. The embodiments have been chosen and described in order to best explain the principles and practical application of the invention, and to enable those skilled in the art to understand the invention in various embodiments with various modifications suitable for the particular use contemplated.

Claims

1. 1. A memristor memory device comprising memristive memory cells, the memristor memory device comprising: An input terminal; An output terminal; a gate terminal; the input terminal and the output terminal are directly attached to the memristive memory cell; the gate terminal is electrically isolated from the memristive memory cell; the gate terminal is configured to receive an electrical signal for volatile modulation of a conductance of the memristive memory cell to compensate for non-ideal conductance modulation of the memristor memory device; and a temperature effect control unit, the output of which is adapted to provide a temperature effect control signal corresponding to a temperature difference ΔT between an ideal working temperature of the memristor memory device and a non-ideal dynamically changing temperature of the memristor memory device. Memristor memory devices.

2. 1. A memristor memory device comprising memristive memory cells, the memristor memory device comprising: An input terminal; An output terminal; a gate terminal; the input terminal and the output terminal are directly attached to the memristive memory cell; the gate terminal is electrically isolated from the memristive memory cell; the gate terminal is configured to receive an electrical signal for volatile modulation of a conductance of the memristive memory cell to compensate for non-ideal conductance modulation of the memristor memory device; a resistance drift correction unit adapted to provide a resistance drift control signal whose output corresponds to a resistance difference ΔR between a target resistance of the memristor memory device and a read resistance of the memristor memory device. Memristor memory devices.

3. The memristor memory device of claim 1 or 2, wherein the memristive memory cells comprise a phase change material or a filamentary electrolyte.

4. the memristor memory device comprises a plurality of the memristive memory cells; The gate terminal is common to the plurality of memristive memory cells.

3. The memristor memory device of claim 1 or 2.

5. 5. The memristor memory device of claim 4, wherein the plurality of memristor memory devices are arranged in a crossbar array to form a memristor memory unit.

6. The memristor memory device comprising a plurality of the memristive memory cells, The temperature effect control unit includes: a temperature sensor electrically connected to the temperature effect control unit; a pre-calibrated ΔT / VT,gate conversion unit that supplies a voltage of value VT as the temperature effect control signal to a group of gate terminals of selected ones of the plurality of memristor memory devices; Further comprising: The memristor memory device of claim 1 .

7. The pre-calibrated ΔT / VT,gate conversion unit is a first digital-to-analog converter adapted to convert a digital temperature effect control signal provided to the gate terminals of the plurality of memristor memory devices constituting a memristor memory unit into an analog value V,gate signal; 7. The memristor memory device of claim 6, further comprising:

8. The memristor memory device comprising a plurality of the memristive memory cells, The resistance drift correction unit includes: and a ΔR / VR gate conversion unit configured to supply a voltage of value VR to a group of gate terminals of selected ones of the plurality of memristor memory devices as a resistance drift correction control signal. The memristor memory device of claim 2 .

9. The ΔR / VR gate conversion unit includes: a second digital-to-analog converter adapted to convert the digital resistive effect control signal into an analog value VR gate signal provided to the gate terminals of the plurality of memristor memory devices constituting a memristor memory unit; The memristor memory device of claim 8 .

10. a plurality of memristor memory devices arranged in a crossbar array; Each of the memristor memory devices comprises: a memristive memory cell; An input terminal; An output terminal; Gate terminal and Equipped with the input terminal and the output terminal are directly attached to the memristive memory cell; the gate terminal is electrically isolated from the memristive memory cell; the gate terminal is configured to receive an electrical signal for volatile modulation of a conductance of the memristive memory cell to compensate for non-ideal conductance modulation of the memristor memory device; a temperature effect control unit adapted to generate a portion of the received electrical signal based on a temperature-based resistance drift effect of each of the memristor memory devices; a resistance drift compensation unit adapted to generate another portion of the received electrical signal based on a time-dependent resistance drift effect of each of the memristor memory devices; Further equipped Memristor memory unit.

11. 1. A method of operating a memristor memory device comprising memristive memory cells, comprising: the memristor memory device comprises an input terminal, an output terminal, and a gate terminal, the input terminal and the output terminal being directly attached to the memristive memory cell, and the gate terminal being electrically isolated from the memristive memory cell; providing an electrical signal for volatile modulation of a conductance of the memristive memory cell to compensate for non-ideal conductance modulation of the memristor memory device; providing, by a temperature effect control unit, a temperature effect control signal corresponding to a temperature difference ΔT between an ideal working temperature of the memristor memory device and a non-ideal dynamically changing temperature of the memristor memory device; A method comprising:

12. the temperature effect control unit further comprising a temperature sensor electrically connected to the temperature effect control unit; providing a voltage of value VT,gate to said gate terminal as said temperature effect control signal by a pre-calibrated ΔT / VT,gate conversion unit; The method of claim 11 further comprising:

13. converting, by a first digital-to-analog converter that is part of the pre-calibrated ΔT / VT,gate conversion unit, the digital temperature effect control signal into an analog value VT,gate signal that is provided to the gate terminal; The method of claim 12 further comprising:

14. 1. A method of operating a memristor memory device comprising memristive memory cells, comprising: the memristor memory device comprises an input terminal, an output terminal, and a gate terminal, the input terminal and the output terminal being directly attached to the memristive memory cell, and the gate terminal being electrically isolated from the memristive memory cell; providing an electrical signal for volatile modulation of a conductance of the memristive memory cell to compensate for non-ideal conductance modulation of the memristor memory device; providing, by a resistance drift correction unit, a resistance drift control signal corresponding to a resistance difference ΔR between a target resistance of the memristor memory device and a read resistance of the memristor memory device; A method comprising:

15. providing a voltage of value VR to said gate terminal as a resistance drift correction control signal by a ΔR / VR gate conversion unit that is part of said resistance drift correction unit; The method of claim 14 further comprising:

16. The ΔR / VR gate conversion unit converts the digital resistive effect control signal into an analog value VR gate signal provided to the gate terminal by a second digital-to-analog converter. The method of claim 15 further comprising:

17. 1. A method of operating a memristor memory device comprising memristive memory cells, comprising: the memristor memory device comprises an input terminal, an output terminal, and a gate terminal, the input terminal and the output terminal being directly attached to the memristive memory cell, and the gate terminal being electrically isolated from the memristive memory cell; providing an electrical signal for volatile modulation of a conductance of the memristive memory cell to compensate for non-ideal conductance modulation of the memristor memory device; providing, by a temperature effect control unit, a temperature effect control signal corresponding to a temperature difference ΔT between an ideal working temperature of the memristor memory device and a non-ideal dynamically changing temperature of the memristor memory device; and providing, by a resistance drift correction unit, a resistance drift control signal corresponding to a resistance difference ΔR between a target resistance of the memristor memory device and a read resistance of the memristor memory device. method.

18. a) the memristive memory cell includes a phase change material or a filamentary electrolyte; and b) the memristor memory device includes a plurality of the memristive memory cells, and the gate terminal is common to the plurality of the memristive memory cells. The method of any of claims 11 to 17, wherein a condition selected from the group consisting of:

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