Semiconductor Integrated Circuit

Abstract

To provide a semiconductor integrated circuit that can improve a withstand voltage without causing a significant decrease in MAG or MSG.SOLUTION: A semiconductor integrated circuit includes input terminals 110a, 110b, output terminals 120a, 120b, and a multi-stage connection unit 130 in which a plurality of MOS transistors 131 are connected in a plurality of stages between the input terminals and the output terminals. The multi-stage connection unit includes input stage transistors 1311a, 1311b connected to the input terminals and output stage transistors 1312a, 1312b connected to the output terminals as MOS transistors. A thickness T2 of a gate insulating film of the output stage transistor is equal to a thickness T1 of the gate insulating film of the input stage transistor, and a gate length L2 of the output stage transistor is longer than a gate length L1 of the input stage transistor.SELECTED DRAWING: Figure 4

Description

[Technical field]

[0001] The disclosure herein relates to semiconductor integrated circuits. [Background technology]

[0002] Patent Document 1 discloses a semiconductor integrated circuit having a multi-stage connection section in which a plurality of transistors are connected in multiple stages. The contents of the prior art documents are incorporated by reference as explanations of technical elements in this specification. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2007-135097 A Summary of the Invention [Problem to be solved by the invention]

[0004] In Patent Document 1, a transistor having a higher breakdown voltage than the input stage transistor is used as the output stage transistor. The gate insulating film of the output stage transistor is thicker than the gate insulating film of the input stage transistor. Therefore, the effect of the scaling law for the thickness of the gate insulating film cannot be obtained, and there is a risk that the maximum available power gain (MAG) and the maximum stable power gain (MSG) will be significantly reduced. In the above-mentioned viewpoints, or in other viewpoints not mentioned, further improvements are required for semiconductor integrated circuits. MAG is an abbreviation for Maximum Available Gain. MSG is an abbreviation for Maximum Stable power Gain.

[0005] One disclosed object is to provide a semiconductor integrated circuit capable of improving the withstand voltage without causing a significant decrease in MAG or MSG. [Means for solving the problem]

[0006] The semiconductor integrated circuit disclosed herein comprises: Input terminals (110a, 110b), Output terminals (120, 120a, 120b); a multistage connection section (130) in which a plurality of MOS transistors (131) are connected in multiple stages between an input terminal and an output terminal; The multi-stage connection unit has, as MOS transistors, input stage transistors (1311a, 1311b) connected to an input terminal and output stage transistors (1312, 1312a, 1312b) connected to an output terminal, The thickness of the gate insulating film of the output stage transistor is equal to the thickness of the gate insulating film of the input stage transistor, The gate length of the output stage transistor is longer than the gate length of the input stage transistor.

[0007] According to the disclosed semiconductor integrated circuit, the output stage transistor has a gate insulating film having a thickness equal to that of the input stage transistor, and a gate length longer than that of the input stage transistor, which results in improved breakdown voltage without causing a significant decrease in MAG or MSG.

[0008] The various aspects disclosed in this specification adopt different technical means to achieve their respective objectives. The claims and the parenthetical symbols described in this section are merely illustrative of the corresponding relationship with the embodiments described below, and are not intended to limit the technical scope. The objectives, features, and effects disclosed in this specification will become clearer with reference to the following detailed description and the accompanying drawings. [Brief description of the drawings]

[0009] [Figure 1] FIG. 1 is a diagram showing MAG or MSG and the frequency dependence of the K factor. [Diagram 2] 1 is a circuit diagram showing a millimeter wave radar system according to a first embodiment. [Diagram 3] FIG. 1 is a circuit diagram showing a semiconductor integrated circuit. [Figure 4]FIG. 4 is a circuit diagram showing a multi-stage connection section. [Diagram 5] FIG. 2 is a diagram showing voltage amplitudes at a plurality of nodes and between the nodes; [Figure 6] FIG. 11 is a diagram showing the relationship between gate length and allowable voltage. [Figure 7] FIG. 13 illustrates the effect of gate length on MAG / MSG and K-factor. [Figure 8] FIG. 13 is a diagram showing the gate length dependency of the input impedance of an output stage transistor. [Figure 9] 13 is a diagram showing a plurality of nodes and voltage amplitudes between the nodes in a semiconductor integrated circuit according to a second embodiment. FIG. [Figure 10] FIG. 11 is a circuit diagram showing a semiconductor integrated circuit according to a third embodiment. [Figure 11] FIG. 13 is a circuit diagram showing a multi-stage connection section in a semiconductor integrated circuit according to a fourth embodiment. [Figure 12] FIG. 13 is a circuit diagram showing a multi-stage connection section in a semiconductor integrated circuit according to a fifth embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0010] In recent years, applications of high-frequency circuits using advanced CMOS processes with gate lengths of 100 nm or less have been proposed. Specific examples include millimeter-wave radar using the 24 GHz and 79 GHz bands, and fifth-generation mobile communication systems using the 28 GHz and 39 GHz bands. Power amplifiers used in such millimeter-wave bands have low MAG (maximum available power gain) and MSG (maximum stable power gain), which indicate the high-frequency gain performance of transistors. Therefore, for millimeter-wave power amplifiers, the circuit design is required to bring out the best in the device performance. CMOS is an abbreviation for Complementary Metal Oxide Semiconductor.

[0011] In the circuit design of power amplifiers, it is generally recognized that improving the saturated output power while maintaining reliability is an important issue. In order to increase the output power, it is necessary to increase the bias current of the circuit or to increase the voltage swing. Increasing the bias current is undesirable because it increases power consumption. Increasing the voltage swing places a large voltage swing between the source and drain in the case of CMOS devices, exceeding the specified breakdown voltage and affecting reliability. In particular, in the case of power amplifiers using fine CMOS processes, the gate length is short, which makes it easy for the electric field to become high, and device degradation due to hot carrier injection (HCI) becomes an issue. HCI is an abbreviation for Hot Carrier Injection.

[0012] Thus, in a power amplifier, there is a trade-off between high output power and reliability. To solve this problem, it is known that a power amplifier uses a cascode connection in which a common-source transistor and a common-gate transistor are stacked vertically. In the technology represented by the above-mentioned Patent Document 1, in order to achieve high output and high voltage resistance in a cascode connection circuit, a high-voltage transistor with a thicker gate insulating film than the common-source transistor in the input stage is used as the common-gate transistor forming the output stage.

[0013] Figure 1 shows the results of a simulation of the frequency dependence of MAG or MSG, which indicates the high-frequency gain characteristics of an NMOS transistor, and the K factor, which indicates circuit stability, when using a PDK provided by a foundry. Here, an NMOS transistor with a gate length of 40 nm, gate width of 1 μm, and total gate width of 60 μm was used, and a power supply voltage of 1.1 V and a gate bias voltage of 0.7 V were applied. PDK is an abbreviation for Process Design Kit. In what follows, MAG or MSG may be referred to as MAG / MSG. In Figure 1, the solid line indicates MAG / MSG, and the dashed line indicates the K factor. The part of the solid line where K≧1 indicates MAG, and the part where K<1 indicates MSG.

[0014] From Figure 1, it is clear that the MAG / MSG decreases as the frequency increases. In particular, above 60 GHz, the MAG / MSG falls below 10 dB. When using in such a high frequency band, it is important in designing the amplifier circuit to maximize the performance of the transistor.

[0015] In reality, MAG / MSG will be lower due to the influence of parasitic components attached to each node, which is dependent on the layout. Also, the frequency at which the K factor is 1 will shift to the lower frequency side as the influence of parasitic components becomes greater. In addition, high-frequency amplifier circuits must have input and output impedance matching circuits, and the matching circuits themselves cause signal loss, further degrading the gain by a few dB.

[0016] In this way, the higher the frequency, the lower the MAG / MSG ratio of the transistors. Therefore, in a power amplifier, it is not always optimal to use high-voltage transistors as the cascode-connected output stage transistors.

[0017] For example, in a cascode connection, if the output stage common-gate transistor is made a high-voltage version, the MAG / MSG will generally be lower. This effect cannot be ignored, especially when considering applications in radar and 5G communications using quasi-millimeter and millimeter wave bands. This is because, even with the same gate length and / or the same total gate width, the gate insulating film becomes relatively thick, so the effect of the scaling law for the thickness of the gate insulating film cannot be obtained, and the transistor performance decreases.

[0018] In addition, if a high-voltage transistor is used for the gate-grounded transistor in the output stage, the minimum gate length that can be selected is limited. Generally, multiple film thicknesses are available as options for transistors provided by CMOS foundries. For example, in the 40-nm generation process, multiple film thicknesses of transistors can be selected as products from among normal voltage versions with thin gate insulation films, medium voltage versions with medium-thick gate insulation films, and high voltage versions with thick gate insulation films. The standard power supply voltage for normal voltage versions is 1.1V, the standard power supply voltage for medium voltage versions is 1.8V, and the standard power supply voltage for high voltage versions is 2.5V.

[0019] Specific examples of the minimum selectable gate length under the design rules are 40 nm for normal voltage versions, 150 nm for medium voltage versions, and 270 nm for high voltage versions. In this way, the minimum gate length is stipulated according to the voltage (gate insulating film thickness). Therefore, when using high voltage transistors, the gate length cannot be selected according to the required reliability due to the restriction on the minimum gate length. In other words, it is not possible to optimize reliability for high frequency characteristics and voltage resistance.

[0020] Also, using a high-voltage version as the gate-grounded transistor in the output stage does not necessarily optimize reliability. Reliability refers to time-dependent dielectric breakdown (TDDB), HCI, and breakdown at PN junctions in transistors when they are operated with AC at high frequencies. TDDB is an abbreviation for Time Dependent Dielectric Breakdown. Gate insulating film breakdown due to TDDB and fluctuations and deterioration of transistor characteristics due to HCI occur through different mechanisms. For this reason, when reliability standards are set targeting the same life span and cumulative failure rate, it may differ depending on the situation as to whether TDDB or HCI will become a problem first.

[0021] Specifically, when an AC signal is input to a transistor in a simulation to verify its operation, there are cases where the Vgs amplitude has a margin relative to the TDDB reliability standard, but the Vds amplitude does not have enough margin relative to the HCI reliability standard. In such cases, there is no need to address the TDDB reliability issue, and only the HCI reliability issue needs to be addressed. In other words, this shows that there is no need to thicken the gate insulating film to increase resistance to TDDB, and only the HCI resistance needs to be increased. A high-voltage transistor with a thick gate insulating film is required when the Vgs amplitude exceeds the reliability standard, but this is not always necessary. Vgs is the voltage between the gate and source. Vds is the voltage between the drain and source. However, in the technology represented by Patent Document 1, the problems of TDDB and HCI are not discussed separately. In addition, the amplifier is not quantitatively designed based on the reliability standard calculated based on the failure mechanism. The problem of using a high-voltage version for the output stage transistor is not limited to power amplifiers. It is a problem of semiconductor integrated circuits having a multi-stage connection section in which multiple MOS transistors are connected in multiple stages.

[0022] Hereinafter, several embodiments will be described with reference to the drawings. In addition, by assigning the same reference numerals to corresponding components in each embodiment, duplicated explanations may be omitted. When only a part of the configuration is described in each embodiment, the configuration of the other embodiment described above can be applied to the other parts of the configuration. In addition to the combination of configurations explicitly stated in the description of each embodiment, configurations of several embodiments can be partially combined together even if not explicitly stated, as long as there is no particular problem with the combination.

[0023] (First embodiment) First, the circuit configuration of a millimeter wave radar system to which the semiconductor integrated circuit of this embodiment is applied will be described with reference to FIG.

[0024] <Circuit configuration of millimeter wave radar system> 2 can measure the distance to and relative speed of an object by emitting modulated radio waves in the 79 GHz band in front of the vehicle and measuring the waves reflected by the object. The millimeter wave radar system 10 includes a controller 20 and an MMIC 30. MMIC is an abbreviation for Monolithic Microwave Integrated Circuit.

[0025] The controller 20 measures the distance and relative speed of the target object based on the signal input from the MMIC 30. The controller 20 is configured using, for example, a microcomputer incorporating a CPU 21, a memory 22 such as ROM, RAM, etc., an A / D converter 23, and an I / O 24. At least a part of the functions of the controller 20 may be mounted on the MMIC 30. In this embodiment, an example is shown in which each function of the control system is mounted on the controller 20.

[0026] The MMIC 30 is configured by integrating each section on a single semiconductor chip made of silicon or the like. The MMIC 30 includes a digital section 31, an interface 32, a PLL section 33, a high frequency switch 34, a buffer amplifier section 35, a frequency doubler 36, a transmitter section 37, and a receiver section 38. PLL is an abbreviation for Phase Locked Loop. The MMIC 30 also includes an output terminal 39 that outputs a local oscillation signal to the outside, and an input terminal 40 that inputs a local oscillation signal from the outside. In the following, the local oscillation signal is referred to as an LO signal. LO is an abbreviation for Local oscillation.

[0027] The digital section 31 has a register 31a, a non-volatile memory 31b, and a control section 31c. The digital section 31 is capable of communicating with the outside of the MMIC 30 via an interface 32. The outside includes the controller 20 and an external device (not shown). When measuring the distance to and relative speed of an object, the MMIC 30 and the controller 20 are connected.

[0028] The register 31a is a section in which data related to the switching of the high frequency switch 34 and data related to the gains of various amplifiers in the buffer amplifier section 35 are written. The register 31a can be written by the controller 20 or an external device via the interface 32.

[0029] The non-volatile memory 31b is a portion in which the correction values ​​for manufacturing variations are written. The non-volatile memory 31b can be written only once. Once the correction values ​​specific to each chip are written to the non-volatile memory 31b, they are stored without being erased.

[0030] The control unit 31c is a digital circuit, and transmits control signals to each analog high-frequency block in the chip based on the data written in the register 31a. Specifically, it switches the high-frequency switch 34 and transmits control signals for setting gains to various amplifiers in the buffer amplifier unit 35. The control unit 31c also transmits the correction values ​​written in the non-volatile memory 31b to each unit that performs correction. As described above, in this embodiment, each function of the control system is mounted in the controller 20, but when at least some of the functions are mounted in the MMIC 30, they are mounted in the digital unit 31.

[0031] The PLL unit 33 has a VCO and a feedback loop circuit (not shown). The feedback loop circuit controls the output signal of the VCO. The PLL unit 33 generates a 40 GHz band LO signal modulated by a method such as FMCW, and outputs the signal to the high frequency switch 34. VCO is an abbreviation for Voltage Controlled Oscillator. FMCW is an abbreviation for Frequency Modulated Continuous Wave.

[0032] The high frequency switch 34 switches the path by receiving a control signal from the control unit 31c based on the data written in the register 31a. When the controller 20 is connected to the MMIC 30, a control signal from the controller 20 is input via the interface 32, and data is written to the register 31a. Then, a control signal based on the data written in the register 31a is transmitted from the control unit 31c to the high frequency switch 34. As a result, the high frequency switch 34 connects the PLL unit 33 to the buffer amplifier unit 35.

[0033] Furthermore, when an external device (not shown) is connected to the MMIC 30, a control signal from the external device is input via the interface 32, thereby writing data to the register 31a. Then, a control signal based on the data written to the register 31a is transmitted from the control unit 31c to the high frequency switch 34. As a result, the high frequency switch 34 connects the input terminal 40 to the buffer amplifier unit 35.

[0034] The buffer amplifier 35 amplifies the LO signal output from the PLL unit 33 or the LO signal input from the input terminal 40 via the high-frequency switch 34, and distributes the signal to the frequency doubler 36, the transmitter 37, and the output terminal 39. The buffer amplifier 35 is sometimes referred to as a distribution amplifier.

[0035] The buffer amplifier 35 has a plurality of amplifiers constituted by high frequency amplifiers. Each amplifier amplifies the LO signal. The amplifiers arranged before and after the branch point inside the buffer amplifier 35 have, for example, the same circuit configuration. Each amplifier is constituted by a variable gain amplifier whose gain can be varied. The gain setting value of each amplifier is written as data in the register 31a, and is transmitted to each amplifier as a control signal from the control unit 31c. During normal radar operation, the LO signal output from the PLL unit 33 is amplified by each amplifier of the buffer amplifier 35, and then input to the transmission unit 37 and the reception unit 38 via the frequency doubler 36.

[0036] For the sake of simplicity, control lines for transmitting various control signals are not shown in Fig. 2. The number of amplifiers included in the buffer amplifier unit 35 is also arbitrary. For example, although an example is shown in which there are two amplifiers on the path from the input terminal 40 to the output terminal 39, there may be one amplifier, or three or more amplifiers.

[0037] The frequency doubler 36 doubles the frequency of the LO signal transmitted from the buffer amplifier 35, and transmits the converted LO signal to the receiver 38. The frequency doubler 36 is sometimes referred to as a frequency multiplier.

[0038] The transmitting unit 37 has a plurality of transmitters 370. The transmitters 370 are provided for each transmission channel. The transmitting unit 37 of this embodiment has n transmission channels TX1ch to TXnch. Each of the transmitters 370 has a phase shifter 371, a frequency doubler 372, and a power amplifier 373. The phase shifter 371, the frequency doubler 372, and the power amplifier 373 are connected in cascade.

[0039] The phase shifter 371 controls the phase in the corresponding transmission channels TX1ch to TXnch. The phase shifter 371 may be provided before the frequency doubler 372, or after the frequency doubler 372. In this embodiment, the phase shifter 371 is provided before the frequency doubler 372.

[0040] Frequency doubler 372 doubles the frequency of the signal input from phase shifter 371 and outputs the doubled frequency to power amplifier 373. Another frequency multiplier, for example a frequency tripler that outputs a frequency three times the input signal frequency, can be used instead of frequency doubler 372. Power amplifier 373 amplifies the power of the high frequency signal that has passed through phase shifter 371 and frequency doubler 372.

[0041] The output of the transmitter 370 in each of the transmission channels TX1ch to TXnch is connected to the feeding point of the corresponding antenna element AT formed on a printed circuit board (not shown). Then, the high-frequency signal transmitted from the transmitter 370 in each of the transmission channels TX1ch to TXnch is finally radiated as a modulated radio wave through the antenna element AT toward the target.

[0042] The receiving unit 38 has a plurality of receivers 380. The receiver 380 is provided for each receiving channel. The receiving unit 38 of this embodiment has m receiving channels RX1ch to RXmch. The number of receiving channels m may be the same as the number of transmitting channels n, or may be different. The receiver 380 has an LNA 381, a mixer 382, ​​and an IFA 383. The receiver 380 is connected to the antenna element AR of the corresponding receiving channel RX1ch to RXmch. LNA is an abbreviation for Low Noise Amplifier. IFA is an abbreviation for Intermediate frequency Amplifier.

[0043] The reflected waves from the target object are input to each receiver 380 via a plurality of antenna elements AR. The LNA 381 of each receiver 380 amplifies the received signal input via the corresponding antenna element AR and outputs the amplified signal to the mixer 382. The mixer 382 converts the received signal to a lower intermediate frequency using the LO signal whose frequency has been doubled by the frequency doubler 36.

[0044] The IFA 383 is configured by, for example, a variable gain amplifier. The IFA 383 amplifies the signal transmitted from the mixer 382 according to a setting value set in the register 31a, and outputs the amplified signal to the A / D converter 23 of the controller 20. The controller 20 performs signal processing based on the digital data converted by the A / D converter 23, thereby calculating the distance to the target object and the relative speed.

[0045] Although the millimeter wave radar system 10 has been described as having only one MMIC 30, the present invention is not limited to this. The millimeter wave radar system 10 may have multiple MMICs 30. For example, in a configuration having two MMICs 30, one chip may operate as a master and the other chip may operate as a slave. Specifically, only the PLL unit 33 of one chip may be operated in oscillation, and the generated LO signal may be output from the output terminal 39 and input from the input terminal 40 of the other chip. This increases the number of transmission channels and reception channels of the millimeter wave radar system 10, thereby improving the performance of the millimeter wave radar system 10.

[0046] <Circuit configuration of semiconductor integrated circuit> Next, the circuit configuration of the semiconductor integrated circuit will be described with reference to Fig. 3. The semiconductor integrated circuit has a multi-stage connection section in which a plurality of MOS transistors (MOSFETs) are connected in multiple stages. In this embodiment, an example in which the semiconductor integrated circuit is applied to a buffer amplifier section 35 is shown. MOSFET is an abbreviation for Metal Oxide Semiconductor Field Effect Transistor.

[0047] 2, in MMIC 30 used in the 79 GHz band, buffer amplifier 35 configured by a semiconductor integrated circuit distributes a 40 GHz band LO signal to transmitter 37 and receiver 38. The 40 GHz band LO signal generated by PLL unit 33 is distributed through buffer amplifier 35 to frequency doubler 372 on the transmitter 37 side and frequency doubler 36 on the receiver 38 side.

[0048] Since high power must be input to the frequency doublers 36, 372, the buffer amplifier 35 (semiconductor integrated circuit) is required to have high output power, as is required for a power amplifier. In addition, since the buffer amplifier 35 (semiconductor integrated circuit) has the role of distributing a reference signal to multiple channels provided in the transmitter 37 and receiver 38, it may operate in a saturated output power region. Therefore, high reliability against life degradation such as HCI and TDDB specified in AEC-Q100 is required. AEC is an abbreviation for Automotive Electronics Council. Q100 is a category of integrated circuits.

[0049] 3, the semiconductor integrated circuit 100 includes input terminals 110a and 110b, output terminals 120a and 120b, a multistage connection section 130, an input matching circuit 140, and an output matching circuit 150. As described above, the semiconductor integrated circuit 100 is a part of the MMIC 30. In other words, the semiconductor integrated circuit 100 is configured as a single semiconductor chip made of silicon or the like.

[0050] The multi-stage connection section 130 is provided between a pair of input terminals 110a, 110b and a pair of output terminals 120a, 120b. The multi-stage connection section 130 of this embodiment forms a differential amplifier circuit. The multi-stage connection section 130 will be described in detail later.

[0051] The input matching circuit 140 and the output matching circuit 150 each have a transformer and a capacitor, and are matched to a frequency of 40 GHz band. Specifically, the input matching circuit 140 has a first transformer 141, a fixed capacitor 142, and variable capacitors 143a and 143b. The first transformer 141 has a primary winding 1411 and a secondary winding 1412. In this embodiment, the turn ratio of the primary winding 1411 and the secondary winding 1412 is 1:2. The fixed capacitor 142 is connected between signal lines 144a and 144b connected to the primary winding 1411. The signal lines 144a and 144b are a pair of differential signal lines.

[0052] The variable capacitors 143a and 143b are respectively connected between signal lines 145a and 145b connected to the secondary winding 1412 and the ground. The signal lines 145a and 145b are a pair of differential signal lines. The signal line 145a is connected to the input terminal 110a, and the signal line 145b is connected to the input terminal 110b. The first transformer 141 of this embodiment is a center-tapped transformer. The primary winding 1411 is grounded, and a predetermined bias voltage (for example, about 0.7 V) lower than the power supply voltage Vdd is applied to the secondary winding 1412.

[0053] The output matching circuit 150 has a second transformer 151, variable capacitances 152a and 152b, and a fixed capacitance 153. The second transformer 151 has a primary winding 1511 and a secondary winding 1512. In this embodiment, the turn ratio of the primary winding 1511 and the secondary winding 1512 is 2:1. The variable capacitances 152a and 152b are connected between signal lines 154a and 154b connected to the primary winding 1511 and the ground, respectively. The signal lines 154a and 154b are a pair of differential signal lines. The signal line 154a is connected to the output terminal 120a, and the signal line 154b is connected to the output terminal 120b. The fixed capacitance 153 is connected between signal lines 155a and 155b connected to the secondary winding 1512. The signal lines 155a and 155b are a pair of differential signal lines.

[0054] The second transformer 151 is also a center-tapped transformer. The secondary winding 1512 is grounded, and a power supply voltage Vdd is applied to the primary winding 1511. The above-mentioned signal lines 144a, 145a, 154a, and 155a may be referred to as positive-phase signal lines, for example. In this case, the signal lines 144b, 145b, 154b, and 155b are referred to as negative-phase signal lines.

[0055] The capacitance of the matching circuit is not limited to the above example. For example, a fixed capacitance may be replaced with a variable capacitance, or a variable capacitance may be replaced with a fixed capacitance. A part of the capacitance may be eliminated. The turns ratio of the transformer is not limited to the above example. Instead of a matching circuit having a transformer and a capacitance, a matching circuit using other inductors or transmission lines may be used.

[0056] <Circuit configuration of multi-stage connection section> Next, the circuit configuration of the multi-stage connection section will be described with reference to Figures 3 and 4. In Figure 4, the gate resistor 134 on the output stage side is omitted.

[0057] As shown in FIG. 3 and FIG. 4, the multistage connection section 130 has a plurality of MOS transistors 131. The plurality of MOS transistors 131 are connected in a multistage manner between the input terminals 110a, 110b and the output terminals 120a, 120b. Specifically, the multistage connection section 130 has a two-stage structure. The plurality of MOS transistors 131 include input stage transistors 1311a, 1311b and output stage transistors 1312a, 1312b. The input stage may be referred to as the lower stage, and the output stage may be referred to as the upper stage. The input stage transistors 1311a, 1311b are source-grounded transistors whose sources are grounded to ground (GND). The output stage transistors 1312a, 1312b are gate-grounded transistors whose gates are grounded to a power supply voltage.

[0058] The input stage transistor 1311a, whose source is grounded, and the output stage transistor 1312a, whose gate is grounded, are connected in cascode. Similarly, the input stage transistor 1311b, whose source is grounded, and the output stage transistor 1312b, whose gate is grounded, are connected in cascode. In this way, the multi-stage connection section 130 is a cascode connection section made up of a plurality of MOS transistors 131.

[0059] Specifically, the gate of the input stage transistor 1311a is connected to the input terminal 110a, and the gate of the input stage transistor 1311b is connected to the input terminal 110b. The sources of the input stage transistors 1311a and 1311b are each grounded. The drain of the output stage transistor 1312a is connected to the output terminal 120a, and the drain of the output stage transistor 1312b is connected to the output terminal 120b. The drain of the input stage transistor 1311a and the source of the output stage transistor 1312a are connected to each other. The drain of the input stage transistor 1311b and the source of the output stage transistor 1312b are connected to each other.

[0060] The multistage connection section 130 further includes neutralizing capacitances 132 and 133. The neutralizing capacitance 132 is connected between the gate of the input stage transistor 1311a and the drain of the input stage transistor 1311b. The neutralizing capacitance 133 is connected between the gate of the input stage transistor 1311b and the drain of the input stage transistor 1311a. In this manner, the multistage connection section 130 is cross-coupled. The value of the neutralizing capacitance 132 is set to be approximately equal to the value of the parasitic capacitance Cgd between the gate and drain of the input stage transistors 1311a and 1311b. Similarly, the value of the neutralizing capacitance 133 is set to be approximately equal to the value of the parasitic capacitance Cgd between the gate and drain of the input stage transistors 1311a and 1311b. Note that "approximately equal" does not necessarily mean a perfect match, but allows for a deviation due to manufacturing variations.

[0061] Since the multistage connection unit 130 operates in a high frequency band of 40 GHz, in the case of a cascode connection without a neutralizing capacitance, the MAG / MSG is low. In this embodiment, the neutralizing capacitances 132 and 133 cross-couple the gate of one of the input stage transistors 1311a and 1311b forming a differential pair and the drain of the other, so that the degradation of high frequency characteristics due to the parasitic capacitance Cgd can be reduced. In addition, even if the input / output impedance of the multistage connection unit 130 changes, the K factor can be stabilized.

[0062] <Structure of MOS Transistor> Next, the structure of the MOS transistor will be described. In the present embodiment, the MMIC 30 including the semiconductor integrated circuit 100 is formed using a 40 nm generation bulk CMOS semiconductor process. In this process, a plurality of transistors with different gate insulating film thicknesses are provided. The gate insulating film is usually provided as an oxide film.

[0063] Specifically, as described above, transistors with multiple film thicknesses can be selected from a normal breakdown voltage version, a medium breakdown voltage version, a high breakdown voltage version, etc. The normal breakdown voltage version is a transistor having a thin gate insulating film and a standard power supply voltage defined as 1.1V. The medium breakdown voltage version is a transistor having an intermediate gate insulating film and a standard power supply voltage of 1.8V. The high breakdown voltage version is a transistor having a thick gate insulating film and a standard power supply voltage of 2.5V. The minimum gate length selectable by the design rule is 40 nm for the 1.1V system transistor, 150 nm for the 1.8V system transistor, and 270 nm for the 2.5V system transistor. Note that the standard power supply voltage indicates the value of the power supply voltage applied during normal operation as defined in the design manual, PDK, etc. Specifically, it indicates the value of the power supply voltage marked as a 1.1V system transistor, a 1.5V system transistor, a 1.8V system transistor, a 2.5V system transistor, a 3.3V system transistor, etc.

[0064] In the present embodiment, as all the MOS transistors 131 constituting the multi-stage connection portion 130, a normal breakdown voltage version (1.1V system transistor) capable of selecting the minimum gate length provided by the process is used. Also, as an example, for all the MOS transistors 131, the gate width is set to 1 μm, the number of fingers is set to 60, and the total gate width is set to 60 μm.

[0065] On one hand, regarding the gate length, the input-stage transistors 1311a and 1311b with source grounded are made different from the output-stage transistors 1312a and 1312b with gate grounded. Specifically, regarding the gate length of the input-stage transistors 1311a and 1311b, it is set to the minimum of 40 nm in the normal breakdown voltage version. Regarding the gate length of the output-stage transistors 1312a and 1312b, it is set to 80 nm, which is longer than the minimum value of 40 nm defined by the design rules.

[0066] Here, as shown in FIG. 4, for each of the input-stage transistors 1311a and 1311b, the thickness of the gate insulating film is defined as T1, the total gate width is defined as W1, and the gate length is defined as L1. Also, for each of the output-stage transistors 1312a and 1312b, the thickness of the gate insulating film is defined as T2, the total gate width is defined as W2, and the gate length is defined as L2. In this embodiment, the input-stage transistors 1311a and 1311b and the output-stage transistors 1312a and 1312b of the multi-stage connection part 130 satisfy the relationship of T1 = T2, W1 = W2, and L1 < L2.

[0067] The gate length of the MOS transistor 131 in each of the input stage and the output stage of the multi-stage connection part 130 is not limited to the above example. As will be described later, the gate length may be determined according to the voltage amplitude between the source and the drain of the MOS transistor 131 in each stage.

[0068] <Method for setting gate length> Next, based on FIGS. 5 and 6, a method for setting the size of the gate length will be described. First, the transient response of the voltage amplitude between each node and between nodes when a high-frequency signal is input to the multi-stage connection part will be described.

[0069] Fig. 5 shows the voltage amplitude at each node and between nodes when the input voltage is varied from -10 dBm to 0 dBm in 2 dB steps at 40 GHz and input to the input terminal of the input matching circuit 140 in the semiconductor integrated circuit 100 having the circuit configuration shown in Fig. 3. However, as an initial condition in the simulation, the gate length of the output stage transistors 1312a and 1312b is set to a value equal to the gate length of the input stage transistors 1311a and 1311b, specifically, 40 nm. In other words, the simulation result in Fig. 5 is the result of a reference example in which the gate length of the output stage transistors is different from that of this embodiment in a circuit configuration equivalent to this embodiment.

[0070] As shown in FIG. 3, node N1 is provided on the signal line on the primary side of the first transformer. Node N2 is provided between the gate of the input stage transistor and the secondary winding of the first transformer. Node N3 is provided between the drain of the input stage transistor and the source of the output stage transistor. Node N4 is provided between the drain of the output stage transistor and the primary winding of the second transformer. Node N5 is provided on the signal line on the secondary side of the second transformer. Node N6 is a connection point between the gate of the output stage transistor on the positive phase side and the gate of the output stage transistor on the negative phase side. FIG. 5 shows six voltage amplitudes in total: node N1, node N2, node N3, between nodes N4-N3, between nodes N4-N6, and node N5. In the differential configuration, the solid line indicates the voltage amplitude on the positive phase side, and the dashed line indicates the voltage amplitude on the negative phase side.

[0071] For normal voltage 1.1V transistors using thin gate insulating films, design rules provided by foundries, etc. stipulate that the standard power supply voltage of 1.1V is normally applied to operate the circuit. On the other hand, the allowable voltage depends on the life, product defect rate and operating temperature of the target semiconductor product, and is allowed to be up to a voltage higher than the standard power supply voltage of 1.1V.

[0072] As an example of the calculation value of the allowable voltage when the above-mentioned conditions of the life, product failure rate and operating temperature are considered for the simulation result of the voltage amplitude in FIG. 5, the allowable voltage for HCI of a transistor with a gate length of 40 nm, i.e., the allowable voltage Vds between the source and drain, is set to 1.25V. Also, the allowable voltage for TDDB, i.e., the allowable voltage Vgs between the gate and source, is set to 1.5V. In this way, for the same semiconductor product's life, product failure rate and operating temperature conditions, TDDB may have a larger margin in voltage amplitude than HCI. The reason why the allowable voltage for TDDB and HCI is different for the same target operating time failure rate is because degradation occurs by different mechanisms. Note that the allowable voltage for HCI and the allowable voltage for TDDB described above are merely examples. Please note that these allowable voltage values ​​depend on the target product life, Si junction temperature, circuit configuration, etc.

[0073] The voltage amplitude of node N3 indicates the amplitude of the voltage Vds between the source and drain of the input stage transistor. As shown in Figure 5, the voltage Vds of the input stage (lower stage) is about 0.7V even at the maximum input of 0dBm, which does not exceed the allowable voltage of 1.25V for HCI. Therefore, the input stage transistor meets the reliability criteria for HCI.

[0074] The voltage amplitude between nodes N4 and N3 indicates the amplitude of the voltage Vds between the source and drain of the output stage transistor. As shown in Figure 5, the voltage Vds of the output stage (upper stage) is about 1.4 V at the maximum input of 0 dBm, which exceeds the allowable voltage of 1.25 V. Therefore, the output stage transistor does not meet the reliability standard of HCI.

[0075] The voltage amplitude of node N2 indicates the amplitude of the voltage Vgs between the gate and source of the input stage transistor. As shown in Figure 5, the input stage voltage Vgs is about 1.1 V at the maximum input of 0 dBm, which does not exceed the allowable voltage of 1.5 V for TDDB. Therefore, the input stage transistor meets the reliability criteria for TDDB.

[0076] Although not shown, since the gate of the output stage transistor is grounded in a high frequency manner, the voltage of the node N6 is constant in a transient state, the fluctuation of the output stage voltage Vgs is small, and the output stage voltage Vgs does not exceed the allowable voltage of 1.5V. Similarly, the voltage amplitude between the nodes N4 and N6 shown in FIG. 5 indicates the amplitude of the voltage Vdg between the gate and drain of the output stage transistor. The voltage Vdg of the output stage (upper stage) is about 1.0V at the maximum input of 0dBm, which does not exceed the allowable voltage of 1.5V. Therefore, the output stage transistor also meets the reliability standard of TDDB. From the viewpoint of TDDB, it is clear that there is no need to use a high-voltage transistor with a thick gate insulating film for the output stage transistor.

[0077] From the above, it has become clear that the amplitude of the voltage Vds between the source and drain of the output stage transistor is most likely to be a problem in terms of reliability in the multistage connection unit 130. When the multistage connection unit 130 is an amplifier having a cascode connection as in this embodiment, the signal amplified by the input stage transistor is input to the output stage transistor, so the voltage Vds of the output stage transistor is a problem in terms of reliability.

[0078] As shown in Fig. 5, the amplitude at node N2 on the secondary side is larger than that at node N1 on the primary side, but this is because a transformer with a turns ratio of 1:2 is used, and power is conserved. The amplitude ratio can be varied by changing the ratio of the turns. The same is true for output matching circuit 150.

[0079] The simulation results in Fig. 5 show that the allowable voltage between the source and drain of the output stage transistor is insufficient. Next, the dependency of the allowable voltage on the gate length will be explained.

[0080] The degree of degradation due to HCI with respect to the gate length of the MOS transistor, that is, the allowable voltage, can be calculated by performing a reliability test using a TEG circuit. FIG. 6 shows the relationship between the gate length and the allowable voltage in a normal breakdown voltage version. In FIG. 6, the allowable voltage at a gate length of 40 nm is normalized to 1 and shown. TEG is an abbreviation for Test Element Group.

[0081] As described above, the voltage Vds of the output stage transistor is about 1.4 V at a maximum input of 0 dBm. As shown in FIG. 6, when the gate length is set to 80 nm, the allowable voltage increases by 1.13 times with respect to 1.25 V when the gate length is 40 nm, reaching about 1.41 V. Thus, when the gate length of the output stage transistor is set to 80 nm, the reliability standard of HCI can be satisfied. From this relationship, the gate length L2 of the output stage transistors 1312a and 1312b of the present embodiment is set to 80 nm.

[0082] Here, in the actual design, after setting the gate length of the output stage transistor to 80 nm, the simulation in FIG. 5 is performed to confirm whether the voltage amplitudes between each node and between nodes are within the allowable voltage. Although the setting of the gate length of the output stage transistor has been described, the gate lengths of other MOS transistors can also be determined based on the relationship with the allowable voltage shown in FIG. 6.

[0083] <Influence of Gate Length on MAG / MSG> Next, based on FIGS. 7 and 8, the relationship between the gate length and MAG / MSG will be described. That is, the influence of the gate length on MAG / MSG will be described.

[0084] FIG. 7 shows the results of a simulation of the dependence of MAG / MSG and K factor on neutralization capacitance for the multistage connection section 130. In FIG. 7, Cneu on the horizontal axis indicates the value of neutralization capacitance. The sharp peak side indicates the K factor. In this simulation, the gate length of the output stage transistors 1312a and 1321b was changed to 40 nm, 80 nm, 120 nm, and 160 nm while the gate length of the input stage transistors 1311a and 1311b was fixed to 40 nm. The solid line indicates 40 nm, the dashed line indicates 80 nm, the dashed line indicates 120 nm, and the dashed line indicates 160 nm. The total gate width was set to 60 μm for both. The bias conditions were 0.7 V for the input terminals 110a and 110b shown in FIG. 4, 1.1 V for the output terminals 120a and 120b, and 1.1 V for the power supply voltage Vdd. That is, a bias of 0.7 V was applied to the gates of the input stage transistors 1311a and 1311b, and a bias of 1.1 V was applied to the gates and drains of the output stage transistors 1312a and 1321b, respectively.

[0085] High-frequency amplifiers are usually used in a range where the K factor is 1 or more to ensure stability against abnormal oscillation. More preferably, they are used near the peak value of the K factor. As shown in Figure 7, for example, in the 40 GHz band, even if the gate length of the output stage transistor is increased from 40 nm to 80 nm, 120 nm, and 160 nm, there is almost no degradation in MAG / MSG in the range where the K factor is 1 or more. In the 80 GHz band, even if the gate length is increased from 40 nm to 120 nm, there is almost no degradation in MAG / MSG in the range where the K factor is 1 or more.

[0086] However, MAG / MSG does not remain unchanged due to variations in the gate length of the output stage transistor. As the input impedance changes according to the gate length, MAG / MSG at the multi-stage connection section 130 also changes. For example, in the 40 GHz band graph in Figure 7, when the gate length of the output stage transistor changes from 40 nm to 80 nm, MAG / MSG changes by about 1 dB in the region where the K factor is 1 or more.

[0087] Figure 8 shows the input impedance of the output stage transistor as seen from the source terminal side. Here, the total gate width is 60 μm, and the gate length is changed from 40 nm to 160 nm. From the Smith chart in Figure 8, we can see that the longer the gate length is, the greater the series resistance component is, and also that the longer the gate length is, the greater the parallel parasitic capacitance is.

[0088] What is essentially important is not the increase or decrease (fluctuation) in MAG / MSG due to the increase in gate length shown in Figure 7, but the fact that the increase in gate length shown in Figure 6 improves the source-drain breakdown voltage of the output stage transistor compared to when the same gate length is used. A change in gate length changes the input impedance of the output stage transistor, causing MAG / MSG to increase or decrease, but even if MAG / MSG decreases, the effect of improving the breakdown voltage is not lost.

[0089] <Summary of the First Embodiment> In this embodiment, the input stage transistors 1311a and 1311b and the output stage transistors 1312a and 1312b constituting the multistage connection unit 130 use transistors of the same voltage resistance version. That is, the thickness T2 of the gate insulating film of the output stage transistors 1312a and 1312b is equal to the thickness T1 of the gate insulating film of the input stage transistors 1311a and 1311b. This makes it possible to suppress a decrease in MAG / MSG by adopting a higher voltage resistance version than the input stage transistors 1311a and 1311b as the output stage transistors 1312a and 1312b and thereby preventing the effect of the scaling law from being obtained. This effect is more prominent when considering applications at high operating frequencies such as millimeter wave radar and 5G communication.

[0090] Also, while satisfying the relationship of T1 = T2 for the gate insulating film, the input-stage transistors 1311a and 1311b and the output-stage transistors 1312a and 1312b satisfy the relationship of L1 < L2 for the gate length. As described above, as the gate length of the output-stage transistors 1312a and 1312b, instead of using the minimum size of 40 nm, a gate length longer than 40 nm, for example, 80 nm, is selected according to the voltage amplitude. From the above, the breakdown voltage can be improved without causing a significant decrease in MAG / MSG. In particular, the breakdown voltage due to HCI can be improved. As a result, as the entire amplifier including the multi-stage connection portion 130, it becomes possible to achieve higher output power and high power-added efficiency under the same circuit current.

[0091] To improve the breakdown voltage, when using a medium breakdown voltage version or a high breakdown voltage version instead of the normal breakdown voltage version as the output-stage transistor, the minimum selectable gate length is 150 nm for the medium breakdown voltage version and 270 nm for the high breakdown voltage version, so a gate length shorter than that cannot be selected. On the other hand, in this embodiment, based on the relationship between the gate length and the allowable voltage shown in FIG. 6, an arbitrary gate length according to the voltage amplitude can be selected. Since the gate length can be selected according to the required reliability standard, the resistance to HCI can be optimized without causing a significant decrease in MAG / MSG.

[0092] In this embodiment, when forming the multi-stage connection portion 130, it is not necessary to manufacture a plurality of types of transistors having different gate insulating film thicknesses. Thereby, an additional mask can be made unnecessary, the manufacturing process can be simplified, and the manufacturing cost can be reduced.

[0093] In this embodiment, an example is shown in which the multi-stage connection part 130 is a cascode connection part having a two-stage structure including input-stage transistors 1311a and 1311b with source grounded and output-stage transistors 1312a and 1312b with gate grounded. However, the multi-stage connection part 130 may include multiple stages of gate-grounded transistors. That is, the number of stages of the multi-stage connection part 130 may be three or more. In the case of three or more stages, there will be at least one stage of intermediate-stage transistors with gate grounded between the input-stage transistors with source grounded and the output-stage transistors with gate grounded. Also in the multi-stage connection part 130 with three or more stages, by satisfying the relationship of T1 = T2 and L1 < L2 at least for the input-stage transistors and the output-stage transistors, the breakdown voltage can be improved without causing a significant decrease in MAG / MSG.

[0094] For example, in the case of the multi-stage connection part 130 having a three-stage structure, there will be one stage of intermediate-stage transistors with gate grounded between the input-stage transistors with source grounded and the output-stage transistors with gate grounded. In this case, the film thickness T3 of the gate insulating film of the intermediate-stage transistors is substantially equal to the film thickness T1 of the input-stage transistors and the film thickness T2 of the output-stage transistors. Regarding the gate length L3 of the intermediate-stage transistors, for example, it may be equal to the gate length L1 of the input-stage transistors, or may be shorter than the gate length L1. It may also be set as the length between the gate length L2 of the output-stage transistors and the gate length L1. Preferably, it may be determined based on the relationship between the gate length and the allowable voltage described above. By thus selecting the gate length according to the voltage amplitude at each stage, it becomes possible to configure the MOS transistors at all stages with transistors of the same breakdown voltage version. Therefore, the manufacturing process can be simplified and the manufacturing cost can be reduced.

[0095] In this embodiment, an example has been shown in which the multistage connection section 130 is a cascode connection section having a common-source transistor as an input stage transistor and a common-gate transistor. However, the multistage connection is not limited to the cascode connection. The input stage transistor is not limited to the common-source. The output stage transistor is not limited to the common-gate. In addition, the configuration in which a plurality of MOS transistors 131 are connected in multiple stages is not limited to the cascade connection. The multistage connection section 130 may have, for example, an impedance matching circuit (element) between the input stage transistor and the output stage transistor. Regardless of the presence or absence of an impedance matching circuit between stages in the multistage connection section 130, in this embodiment, the relationship between the thickness of the gate insulating film and the gate length of the input stage transistor and the output stage transistor is specified.

[0096] Although an example in which the semiconductor integrated circuit 100 is applied to the buffer amplifier unit 35 has been described, the present invention is not limited to this. The semiconductor integrated circuit 100 can also be applied to other amplifiers. The semiconductor integrated circuit 100 can be applied to the power amplifier 373 and the LNA 381 in the above-mentioned millimeter wave radar system 10. In addition, although the present embodiment has been described using a 40 nm generation bulk CMOS as an example, the present invention is not limited to this and can be applied to semiconductor processes of various generations of gate lengths. The device structure is not limited to bulk CMOS, and the present invention can also be applied to device structures such as SOI MOSFET and FinFET. SOI is an abbreviation for Silicon on Insulator.

[0097] Second embodiment This embodiment is a modification based on the previous embodiment, and the description of the previous embodiment can be used. In the previous embodiment, a standard power supply voltage is applied to the semiconductor integrated circuit 100 to perform normal operation. Alternatively, the semiconductor integrated circuit 100 may be operated in overdrive mode.

[0098] The circuit configuration of the semiconductor integrated circuit 100 and the multi-stage connection unit 130 is the same as that described in the preceding embodiment. In this embodiment, a voltage exceeding the standard power supply voltage of 1.1 V is applied as the power supply voltage Vdd. That is, a voltage exceeding the standard power supply voltage is applied to the drains of the output stage transistors 1312a and 1312b. This overdrives the semiconductor integrated circuit 100, further improving the power added efficiency.

[0099] 9, like Fig. 5, shows the voltage amplitude at each node and between nodes when the input voltage is varied in 2 dB steps from -10 dBm to 0 dBm at 40 GHz and input to the input terminal of the input matching circuit 140. Here, the applied power supply voltage Vdd is set to 1.3 V, which is higher than the standard power supply voltage of 1.1 V.

[0100] As shown in FIG. 9, the maximum amplitude of the voltage Vds between the nodes N4 and N3, i.e., between the source and drain of the output stage transistor, is 1.62V. As in the previous embodiment, this exceeds the allowable voltage of 1.25V when the gate length is 40nm, and does not satisfy the reliability standard of HCI. From the relationship between the gate length and the allowable voltage shown in FIG. 6, the gate length that ensures reliability for the voltage amplitude of 1.62V is 160nm. If the gate length is set to 160nm, the allowable voltage increases by 1.31 times compared to 40nm, becoming 1.63V. Thus, the problem of HCI reliability can be solved. In the actual design, the gate length of the output stage transistor is set to 160nm, and the simulation of FIG. 9 is performed to confirm whether the voltage amplitude at each node and between the nodes is within the allowable voltage. In this embodiment, the gate length of the output stage transistors 1312a and 1312b is set to 160nm. The other configurations are the same as those of the previous embodiment.

[0101] <Summary of the second embodiment> In this embodiment, as in the previous embodiment, the gate length is selected according to the voltage amplitude, so that the withstand voltage against HCI can be improved without causing a significant drop in MAG / MSG. Since the withstand voltage against HCI can be improved, the power supply voltage can be increased beyond the standard power supply voltage of 1.1V, which is the power supply voltage during normal operation, enabling overdrive operation. This makes it possible to achieve improvements in the power added efficiency and output power of the amplifier while maintaining reliability.

[0102] When performing overdrive operation, the power supply voltage applied to the drain of the output stage transistor is not limited to the above example (1.3V). It may be any voltage that exceeds the standard power supply voltage of 1.1V. For example, it may be 1.2V or 1.5V.

[0103] The overdrive operation is also used for purposes other than improving the power added efficiency at room temperature. For example, it is used to correct manufacturing variations in the temperature characteristics of the element, the threshold voltage Vth, and the like. As an example, the performance of the MOS transistor 131 is lower at high temperatures than at room temperature, and higher at low temperatures than at room temperature. For this reason, the power supply voltage Vdd is set to the standard power supply voltage of 1.1 V at room temperature, 0.9 V at low temperatures, and 1.3 V at high temperatures. In this way, when the element temperature is high, the overdrive operation is performed.

[0104] Third embodiment This embodiment is a modification of the preceding embodiment as a basic form, and the description of the preceding embodiment can be used. In the preceding embodiment, the semiconductor integrated circuit is applied to an amplifier. Instead of this, the semiconductor integrated circuit may be applied to a frequency multiplier.

[0105] 10, the semiconductor integrated circuit 100 of this embodiment constitutes a frequency multiplier, specifically a frequency doubler. This semiconductor integrated circuit 100 can be applied to the frequency doublers 36, 372 in the above-mentioned millimeter wave radar system 10. The semiconductor integrated circuit 100 constituting the frequency doubler includes a pair of input terminals 110a, 110b, one output terminal 120, a multi-stage connection section 130, an input matching circuit 140, and an output matching circuit 150.

[0106] The multi-stage connection section 130 is configured by connecting a plurality of MOS transistors 131 in multiple stages between the input terminals 110a, 110b and the output terminal 120. The MOS transistor 131 has a pair of input stage transistors 1311a, 1311b and one output stage transistor 1312. The input stage transistors 1311a, 1311b are all connected to the source ground. The output stage transistor 1312 is connected to the gate ground. The gates of the input stage transistors 1311a, 1311b are connected to the corresponding input terminals 110a, 110b. The drains of the input stage transistors 1311a, 1311b are connected to the source of the output stage transistor 1312. That is, the input stage transistors 1311a, 1311b and the output stage transistor 1312 are connected in multiple stages. The drain of the output stage transistor 1312 is connected to the output terminal 120. The multi-stage connection section 130 is a frequency conversion section that converts the frequency of an input signal to double.

[0107] As in the previous embodiment, the input matching circuit 140 and the output matching circuit 150 each include a transformer and a capacitor. The input matching circuit 140 includes a first transformer 141 and a fixed capacitor 142. The output matching circuit 150 includes a second transformer 151 and a fixed capacitor 153.

[0108] In the second transformer 151, one end of the primary winding 1511 is connected to the output terminal 120 via a signal line 154. A power supply voltage Vdd is applied to the other end of the primary winding 1511. The configuration on the secondary winding 1512 side is the same as in the preceding embodiment. As described in the preceding embodiment, the configurations of the input matching circuit 140 and the output matching circuit 150 can be selected from various configurations. The turn ratio of the first transformer 141 and the second transformer 151 is also not particularly limited.

[0109] The above-mentioned semiconductor integrated circuit 100 also has the same problem as the previous embodiment. That is, if the output stage transistor is made of the same voltage-resistant version as the input stage transistor and has the same gate length as the input stage transistor, the amplitude of the voltage Vds of the output stage transistor will exceed the allowable voltage for HCI. For this reason, the gate length is also determined in this embodiment based on the relationship between the gate length and the allowable voltage shown in FIG.

[0110] Specifically, normal voltage type (1.1V type) transistors are used for all MOS transistors 131. The gate length of input stage transistors 1311a and 1311b is set to 40 nm, which is the minimum for normal voltage type. The gate length of output stage transistor 1312 is set to a value according to the amplitude of voltage Vds of the output stage transistor, and is set to a value longer than the gate length of input stage transistors 1311a and 1311b.

[0111] <Summary of the third embodiment> In this embodiment, in a semiconductor integrated circuit 100 forming a frequency multiplier, the thicknesses of the gate insulating films of the input stage transistor and the output stage transistor are made equal, and the gate length of the output stage transistor is made longer than that of the input stage transistor. This makes it possible to improve the output power while ensuring the withstand voltage against HCI, as in the amplifier described in the preceding embodiment. By using the relationship shown in Figure 6, an arbitrary gate length can be selected according to the voltage amplitude.

[0112] In the semiconductor integrated circuit 100 constituting a frequency doubler, the input stage transistor of the multi-stage connection section 130 is not limited to being source-grounded. Also, the output stage transistor is not limited to being gate-grounded. The present invention can also be applied to the semiconductor integrated circuit 100 constituting a frequency multiplier other than a frequency doubler, for example, a frequency tripler that converts a frequency into three times the frequency.

[0113] (Fourth embodiment) This embodiment is a modification based on the preceding embodiment, and the description of the preceding embodiment can be incorporated. In the preceding embodiment, the total gate widths of the input-stage transistors and the output-stage transistors were made equal. Instead, the total gate width of the output-stage transistors may be made longer than the total gate width of the input-stage transistors.

[0114] FIG. 11 shows the multi-stage connection part 130 in the semiconductor integrated circuit 100 of this embodiment. The circuit configuration is the same as that of the preceding embodiment (see FIG. 4). In this embodiment, the input-stage transistors 1311a and 1311b and the output-stage transistors 1312a and 1312b of the multi-stage connection part 130 satisfy the relationships of T1 = T2, W1 < W2, and L1 < L2. Thus, even for the total gate width, it is made different between the input stage and the output stage. For other configurations, they are the same as the configurations described in the first embodiment.

[0115] <Summary of the Fourth Embodiment> As described in the preceding embodiment (see FIG. 8), as the gate length L2 of the output-stage transistors 1312a and 1312b is increased, the series resistance component of the impedance of the output-stage transistors 1312a and 1312b increases. In this embodiment, in accordance with this, by increasing the total gate width W2 of the output-stage transistors 1312a and 1312b, the influence of the series resistance component can be relatively reduced.

[0116] Note that it is also possible to achieve impedance matching by adding elements such as parallel capacitance and series inductance between the stages of the multi-stage connection part 130. However, generally in high-frequency circuits in the millimeter-wave band, since the matching circuit itself has losses, adding elements may not be desirable in some cases. According to this embodiment, it becomes possible to adjust the influence caused by increasing the gate length L2 without adding elements for impedance matching between the stages.

[0117] (Fifth Embodiment) This embodiment is a modified example based on the preceding embodiment, and the description of the preceding embodiment can be incorporated. In the preceding embodiment, for example, the total gate widths of the input-stage transistors and the output-stage transistors were made equal. In another preceding embodiment, the total gate width of the output-stage transistors was made longer than the total gate width of the input-stage transistors. Instead, the total gate width of the output-stage transistors may be made shorter than the total gate width of the input-stage transistors.

[0118] FIG. 12 shows the multi-stage connection portion 130 among the semiconductor integrated circuits 100 of the present embodiment. The circuit configuration is the same as that of the preceding embodiment (see FIG. 4). In the present embodiment, the input-stage transistors 1311a and 1311b and the output-stage transistors 1312a and 1312b of the multi-stage connection portion 130 satisfy the relationships of T1 = T2, W1>W2, and L1<L2. Thus, even for the total gate width, it is made different between the input stage and the output stage. For other configurations, they are the same as those described in the first embodiment.

[0119] <Summary of the Fifth Embodiment> As described in the preceding embodiment (see FIG. 8), as the gate length L2 of the output-stage transistors 1312a and 1312b is increased, the parallel capacitance component of the impedance of the output-stage transistors 1312a and 1312b increases. In the present embodiment, in accordance with this, by shortening the total gate width W2 of the output-stage transistors 1312a and 1312b, the influence of the parallel capacitance component can be relatively reduced. Thereby, it becomes possible to adjust the influence caused by increasing the gate length L2 without adding an impedance matching element between the stages.

[0120] (Other Embodiments) The disclosure in this specification and drawings, etc. is not limited to the exemplified embodiments. The disclosure includes the exemplified embodiments and modifications by those skilled in the art based thereon. For example, the disclosure is not limited to the combination of parts and / or elements shown in the embodiments. The disclosure can be implemented by various combinations. The disclosure can have additional parts that can be added to the embodiments. The disclosure includes the omission of parts and / or elements of the embodiments. The disclosure includes the substitution or combination of parts and / or elements between one embodiment and another embodiment. The disclosed technical scope is not limited to the description of the embodiments. Some disclosed technical scopes are indicated by the description of the claims, and should be interpreted as including all modifications within the meaning and scope equivalent to the description of the claims.

[0121] The disclosure in the specification and drawings is not limited by the claims. The disclosure in the specification and drawings includes the technical ideas described in the claims, and extends to more diverse and broader technical ideas than the technical ideas described in the claims. Therefore, various technical ideas can be extracted from the disclosure in the specification and drawings without being bound by the claims.

[0122] Although an example in which the semiconductor integrated circuit 100 constitutes a differential signal amplifier has been shown, the present invention is not limited to this. It is also applicable to a single-phase signal amplifier as long as it has a configuration including a multistage connection unit 130. In this case, it is possible to achieve the same effects as the preceding embodiment that is premised on a differential signal. [Explanation of symbols]

[0123] 10... millimeter wave radar system, 20... controller, 21... CPU, 22... memory, 23... A / D converter, 24... I / O, 30... MMIC, 31... digital section, 31a... register, 31b... non-volatile memory, 31c... control section, 32... interface, 33... PLL section, 34... high frequency switch, 35... buffer amplifier section, 36... frequency doubler, 37... transmitter section, 370... transmitter, 371... phase shifter, 372... frequency doubler, 373... power amplifier, 38... receiver section, 380... receiver, 381... LNA, 382... mixer, 383... IFA, 39... output terminal, 40... input terminal, 100... semiconductor integrated circuit, 110a, 100b... input terminal, 120, 120a, 120b... output terminal, 130 ...multi-stage connection section, 131...MOS transistor, 1311a, 1311b...input stage transistor (source-grounded transistor), 1312, 1312a, 1312b...output stage transistor (gate-grounded transistor), 132, 133...neutralization capacitance, 134...gate resistor, 140...input matching circuit, 141...first transformer, 1411...primary winding, 1412...secondary winding, 142...fixed capacitance, 143a, 143b...variable capacitance, 144a, 144b, 145a, 145b...signal line, 150...output matching circuit, 151...second transformer, 1511...primary winding, 1512...secondary winding, 152a, 152b...variable capacitance, 153...fixed capacitance, 154a, 154b, 155a, 155b...signal line

Claims

1. Input terminals (110a, 110b); Output terminals (120, 120a, 120b); a multistage connection section (130) in which a plurality of MOS transistors (131) are connected in multiple stages between the input terminal and the output terminal; The multistage connection unit has, as the MOS transistors, input stage transistors (1311a, 1311b) connected to the input terminal and output stage transistors (1312, 1312a, 1312b) connected to the output terminal, a thickness of a gate insulating film of the output stage transistor is equal to a thickness of a gate insulating film of the input stage transistor; a gate length of the output stage transistor is longer than a gate length of the input stage transistor.

2. 2. The semiconductor integrated circuit according to claim 1, wherein the multistage connection section is a cascode connection section having a common-source transistor as the input stage transistor and a common-gate transistor as the output stage transistor.

3. 3. The semiconductor integrated circuit according to claim 1, wherein said MOS transistors include only said input stage transistors and said output stage transistors.

4. an input matching circuit (140) connected to the input terminal; an output matching circuit (150) connected to the output terminal; 4. The semiconductor integrated circuit according to claim 1, which operates in a quasi-millimeter wave or millimeter wave band.

5. 5. The semiconductor integrated circuit according to claim 1, wherein the gate length of the MOS transistor in each stage is set based on a relationship with an allowable source-drain voltage.

6. 6. The semiconductor integrated circuit according to claim 1, wherein the multistage connection section forms a differential amplifier circuit.

7. 7. The semiconductor integrated circuit according to claim 6, wherein the multistage connection section includes a pair of the input stage transistors and a pair of capacitances cross-coupled to the pair of the input stage transistors.

8. 6. The semiconductor integrated circuit according to claim 1, wherein the multi-stage connection section forms a frequency multiplier circuit.

9. 9. The semiconductor integrated circuit according to claim 1, wherein a total gate width of said output stage transistor is greater than a total gate width of said input stage transistor.

10. 9. The semiconductor integrated circuit according to claim 1, wherein a total gate width of said output stage transistor is shorter than a total gate width of said input stage transistor.

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