Method for manufacturing a semiconductor device

Abstract

To provide a semiconductor device having favorable electrical characteristics.SOLUTION: A semiconductor device has: a first oxide; first and second conductors on the first oxide; a first insulator on the first conductor; a second insulator on the second conductor; a third insulator on the first and second insulators; a second oxide arranged on the first oxide, between the first and second conductors; a fourth insulator on the second oxide; a third conductor on the fourth insulator; a fifth insulator in contact with an upper surface of the third insulator, an upper surface of the second oxide, an upper surface of the fourth insulator, and an upper surface of the third conductor; a fourth conductor buried in an opening formed on the first, third, and fifth insulators, being in contact with the first conductor; and a fifth conductor buried in an opening formed on the second, third, and fifth insulators, being in contact with the second conductor. The third insulator has a region having a higher nitrogen concentration than the other region of the third insulator, in the vicinity of an interface with the fourth conductor and in the vicinity of an interface with the fifth conductor.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] TECHNICAL FIELD One embodiment of the present invention relates to a semiconductor device and a manufacturing method of the semiconductor device, or to a semiconductor wafer, a module, and an electronic device.

[0002] In this specification and the like, a semiconductor device refers to any device that can function by utilizing semiconductor characteristics. Semiconductor elements such as transistors, semiconductor circuits, arithmetic devices, and memory devices are all embodiments of semiconductor devices. Display devices (such as liquid crystal display devices and light-emitting display devices), projection devices, lighting devices, electro-optical devices, power storage devices, memory devices, semiconductor circuits, imaging devices, and electronic devices may be considered to include semiconductor devices.

[0003] Note that one aspect of the present invention is not limited to the above technical field. One aspect of the invention disclosed in the present specification etc. relates to an object, a method, or a manufacturing method. Alternatively, one aspect of the present invention relates to a process, a machine, a manufacture, or a composition of matter. [Background technology]

[0004] In recent years, the development of semiconductor devices has progressed, and LSIs, CPUs, and memories are mainly used. A CPU is a collection of semiconductor elements having semiconductor integrated circuits (at least transistors and memories) separated from a semiconductor wafer and on which electrodes serving as connection terminals are formed.

[0005] Semiconductor circuits (IC chips) such as LSIs, CPUs, and memories are mounted on circuit boards, such as printed wiring boards, and used as components in a variety of electronic devices.

[0006] In addition, a technology for constructing a transistor using a semiconductor thin film formed on a substrate having an insulating surface is attracting attention. Such transistors are widely used in electronic devices such as integrated circuits (ICs) and image display devices (also simply referred to as display devices). Silicon-based semiconductor materials are widely known as semiconductor thin films that can be used in transistors, but oxide semiconductors are also attracting attention as other materials.

[0007] It is also known that a transistor using an oxide semiconductor has an extremely low leakage current in a non-conducting state. For example, a low-power consumption CPU that utilizes the low leakage current characteristic of a transistor using an oxide semiconductor has been disclosed (see Patent Document 1). In addition, a memory device that can retain stored data for a long period of time by utilizing the low leakage current characteristic of a transistor using an oxide semiconductor has been disclosed (see Patent Document 2).

[0008] Furthermore, in recent years, with the trend toward smaller and lighter electronic devices, there is an increasing demand for higher density integrated circuits, and there is also a demand for improved productivity in the manufacture of semiconductor devices including integrated circuits. [Prior art documents] [Patent documents]

[0009] [Patent Document 1] JP 2012-257187 A [Patent Document 2] JP 2011-151383 A Summary of the Invention [Problem to be solved by the invention]

[0010] An object of one embodiment of the present invention is to provide a semiconductor device having favorable electrical characteristics. Another object of one embodiment of the present invention is to provide a semiconductor device having normally-off electrical characteristics. Another object of one embodiment of the present invention is to provide a semiconductor device with favorable reliability. Another object of one embodiment of the present invention is to provide a semiconductor device having large on-state current. Another object of one embodiment of the present invention is to provide a semiconductor device having high frequency characteristics. Another object of one embodiment of the present invention is to provide a semiconductor device that can be miniaturized or highly integrated. Another object of one embodiment of the present invention is to provide a semiconductor device with high productivity.

[0011] An object of one embodiment of the present invention is to provide a semiconductor device capable of retaining data for a long period of time.An object of one embodiment of the present invention is to provide a semiconductor device with a high data writing speed.An object of one embodiment of the present invention is to provide a semiconductor device with high design freedom.An object of one embodiment of the present invention is to provide a semiconductor device whose power consumption can be reduced.An object of one embodiment of the present invention is to provide a novel semiconductor device.

[0012] Note that the description of these problems does not preclude the existence of other problems. Note that one embodiment of the present invention does not necessarily solve all of these problems. Note that problems other than these will become apparent from the description of the specification, drawings, claims, etc., and it is possible to extract problems other than these from the description of the specification, drawings, claims, etc. [Means for solving the problem]

[0013] One aspect of the present invention is a semiconductor device comprising a first oxide, a first conductor and a second conductor on the first oxide, a first insulator on the first conductor, a second insulator on the second conductor, a third insulator on the first insulator and the second insulator, a second oxide disposed between the first conductor and the second conductor on the first oxide, a fourth insulator on the second oxide, a third conductor on the fourth insulator, and a top surface of the third insulator, a top surface of the second oxide, a top surface of the fourth insulator, and a top surface of the third insulator. The semiconductor device has a fifth insulator in contact with an upper surface of a conductor, a fourth conductor embedded in an opening formed in the first insulator, the third insulator, and the fifth insulator and in contact with the first conductor, and a fifth conductor embedded in an opening formed in the second insulator, the third insulator, and the fifth insulator and in contact with the second conductor, wherein the third insulator has regions near its interface with the fourth conductor and near its interface with the fifth conductor that have a higher nitrogen concentration than other regions of the third insulator.

[0014] Furthermore, in the above, it is preferable that the first conductor has a region near the interface with the fourth conductor which has a higher nitrogen concentration than other regions of the first conductor, and the second conductor has a region near the interface with the fifth conductor which has a higher nitrogen concentration than other regions of the second conductor.

[0015] Another aspect of the present invention is a semiconductor device comprising a first insulator, a first conductor on the first insulator, a second insulator on the first conductor, a first oxide on the second insulator, a second conductor and a third conductor on the first oxide, a third insulator on the second conductor, a fourth insulator on the third conductor, a fifth insulator on the third insulator and the fourth insulator, a second oxide disposed between the second conductor and the third conductor on the first oxide, a sixth insulator on the second oxide, a fourth conductor on the sixth insulator, a seventh insulator in contact with an upper surface of the fifth insulator, an upper surface of the second oxide, an upper surface of the sixth insulator, and an upper surface of the fourth conductor, and a seventh insulator in contact with an upper surface of the fifth insulator, an upper surface of the second oxide, an upper surface of the sixth insulator, and an upper surface of the fourth conductor. the fifth insulator has a top surface and a side surface thereof, a side surface of the fifth insulator, a side surface of the second insulator, and an eighth insulator in contact with the top surface of the first insulator, a fifth conductor embedded in an opening formed in the third insulator, the fifth insulator, the seventh insulator, and the eighth insulator and in contact with the second conductor, and a sixth conductor embedded in an opening formed in the fourth insulator, the fifth insulator, the seventh insulator, and the eighth insulator and in contact with the third conductor, wherein the fifth insulator has regions near its interface with the fifth conductor, near its interface with the sixth conductor, and near its interface with the eighth insulator, where the nitrogen concentration is higher than in other regions of the fifth insulator.

[0016] Furthermore, in the above, it is preferable that the second conductor has a region near the interface with the fifth conductor which has a higher nitrogen concentration than other regions of the second conductor, and the third conductor has a region near the interface with the sixth conductor which has a higher nitrogen concentration than other regions of the third conductor.

[0017] Another embodiment of the present invention is a method for manufacturing a semiconductor device having first to fifth conductors, first to fifth insulators, and first and second oxides, the method including: forming a first oxide over a substrate, a first conductor layer over the first oxide, and a first insulator layer over the first conductor layer; depositing a third insulator over the first insulator layer; forming an opening in the third insulator reaching the first insulator layer; removing a region of the first conductor layer and the first insulating layer overlapping the opening; forming a first conductor, a second conductor, a first insulator, and a second insulator; depositing a first oxide film between the first conductor and the second conductor so as to be in contact with the first oxide; depositing a first insulating film over the first oxide film; and depositing a first conductive film over the first insulating film. a fifth insulator is formed on the third insulator, the second oxide, the fourth insulator, and the third conductor; an opening reaching the first conductor is formed in the first insulator, the third insulator, and the fifth insulator, and an opening reaching the second conductor is formed in the second insulator, the third insulator, and the fifth insulator; a microwave treatment is performed in an atmosphere containing nitrogen; a fourth conductor is formed to be embedded in the opening reaching the first conductor, and a fifth conductor is formed to be embedded in the opening reaching the second conductor.

[0018] In the above, the microwave treatment is preferably carried out under reduced pressure.

[0019] One embodiment of the present invention is a method for manufacturing a semiconductor device having first and second conductors, first to seventh insulators, and first and second oxides, the method including forming a first insulator over a substrate, forming a first conductor over the first insulator, forming a second insulator over the first conductor, forming a third insulator over the second insulator, forming a first oxide over the third insulator, forming a fourth insulator over the first oxide, forming a first opening in the fourth insulator that reaches the first oxide, forming a first oxide film in the first opening to be in contact with the first oxide and the fourth insulator, forming a first insulating film over the first oxide film, forming a first conductive film over the first insulating film, and forming a fourth insulating film over a portion of the first oxide film, a portion of the first insulating film, and a portion of the first conductive film. a sixth insulator is deposited in contact with the fourth insulator, the second oxide, the fifth insulator, and the second conductor; a part of the sixth insulator, a part of the fourth insulator, a part of the third insulator, and a part of the second insulator are removed to form a second opening reaching the first insulator; a seventh insulator is deposited covering the sixth insulator, the fourth insulator, the third insulator, and the second insulator and in contact with the first insulator at the second opening; the deposition of the third insulator, the fourth insulator, and the first insulating film is performed using a gas having molecules containing silicon atoms, and the molecules containing silicon atoms have 3 or less hydrogen atoms per silicon atom.

[0020] In the above, after the second opening is formed, a microwave treatment is preferably performed in an atmosphere containing nitrogen.

[0021] In the above, it is preferable that the molecules containing silicon atoms do not contain hydrogen atoms.In the above, it is preferable that the gas having molecules containing silicon atoms does not contain hydrogen atoms.

[0022] In the above, it is preferable that the first insulator and the seventh insulator are less permeable to hydrogen than the fourth insulator.

[0023] In the above, the fourth insulator is preferably formed by PECVD or APCVD, and the first insulating film is preferably formed by PEALD or thermal ALD. Effect of the Invention

[0024] According to one embodiment of the present invention, a semiconductor device having favorable electrical characteristics can be provided. According to one embodiment of the present invention, a semiconductor device having normally-off electrical characteristics can be provided. According to one embodiment of the present invention, a semiconductor device with favorable reliability can be provided. According to one embodiment of the present invention, a semiconductor device having large on-state current can be provided. According to one embodiment of the present invention, a semiconductor device having high frequency characteristics can be provided. According to one embodiment of the present invention, a semiconductor device which can be miniaturized or highly integrated can be provided. According to one embodiment of the present invention, a semiconductor device with high productivity can be provided.

[0025] Alternatively, it is possible to provide a semiconductor device capable of retaining data for a long period of time. Alternatively, it is possible to provide a semiconductor device with high data writing speed. Alternatively, it is possible to provide a semiconductor device with high design freedom. Alternatively, it is possible to provide a semiconductor device with low power consumption. Alternatively, it is possible to provide a novel semiconductor device.

[0026] Note that the description of these effects does not preclude the existence of other effects. Note that one embodiment of the present invention does not need to have all of these effects. Note that effects other than these will become apparent from the description in the specification, drawings, claims, etc., and it is possible to extract effects other than these from the description in the specification, drawings, claims, etc. [Brief description of the drawings]

[0027] [Figure 1] 1A, 1B, 1C, and 1D are a top view and a cross-sectional view of a semiconductor device according to one embodiment of the present invention. [Diagram 2] 2A, 2B, 2C, and 2D are top views and cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Diagram 3] 3A, 3B, 3C, and 3D are top views and cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 4] 4A, 4B, 4C, and 4D are top views and cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Diagram 5] 5A, 5B, 5C, and 5D are top views and cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 6] 6A, 6B, 6C, and 6D are top views and cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 7] 7A, 7B, 7C, and 7D are top views and cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 8] 8A, 8B, 8C, and 8D are top views and cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 9] 9A, 9B, 9C, and 9D are top views and cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 10] 10A, 10B, 10C, and 10D are top views and cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 11] 11A, 11B, 11C, and 11D are top views and cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 12] 12A, 12B, 12C, and 12D are top views and cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 13] 13A, 13B, 13C, and 13D are top views and cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 14]14A, 14B, 14C, and 14D are top views and cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 15] FIG. 15 is a top view illustrating a microwave processing apparatus according to one embodiment of the present invention. [Figure 16] FIG. 16 is a cross-sectional view illustrating a microwave processing apparatus according to one embodiment of the present invention. [Figure 17] FIG. 17 is a cross-sectional view illustrating a microwave processing apparatus according to one embodiment of the present invention. [Figure 18] 18A, 18B, 18C, and 18D are a top view and a cross-sectional view of a semiconductor device according to one embodiment of the present invention. [Figure 19] 19A, 19B, 19C, and 19D are a top view and a cross-sectional view of a semiconductor device according to one embodiment of the present invention. [Figure 20] 20A, 20B, 20C, and 20D are a top view and a cross-sectional view of a semiconductor device according to one embodiment of the present invention. [Figure 21] 21A and 21B are cross-sectional views of a semiconductor device according to one embodiment of the present invention. [Figure 22] FIG. 22 is a cross-sectional view illustrating a configuration of a memory device according to one embodiment of the present invention. [Figure 23] FIG. 23 is a cross-sectional view illustrating a configuration of a memory device according to one embodiment of the present invention. [Figure 24] 24A and 24B are block diagrams illustrating configuration examples of a memory device according to one embodiment of the present invention. [Diagram 25] 25A, 25B, 25C, 25D, 25E, 25F, 25G, and 25H are circuit diagrams illustrating configuration examples of a memory device according to one embodiment of the present invention. [Figure 26] 26A and 26B are schematic diagrams of a semiconductor device according to one embodiment of the present invention. [Figure 27] 27A, 27B, 27C, 27D, and 27E are schematic diagrams of a memory device according to one embodiment of the present invention. [Figure 28]28A, 28B, 28C, 28D, 28E1, 28E2, and 28F are diagrams showing electronic devices according to one embodiment of the present invention. [Figure 29] FIG. 29 is a schematic diagram showing the structure of a sample according to an embodiment of the present invention. [Diagram 30] 30A, 30B, and 30C are diagrams showing STEM images of a sample according to an embodiment of the present invention. [Diagram 31] FIG. 31 is a diagram showing the results of EDX analysis of a sample according to an embodiment of the present invention. [Diagram 32] 32A, 32B, and 32C are diagrams showing the results of SIMS analysis of a sample according to an embodiment of the present invention. [Diagram 33] 33A and 33B are diagrams showing the resistivity of a sample according to an embodiment of the present invention. [Diagram 34] 34A and 34B are diagrams showing the results of SIMS analysis of a sample according to an embodiment of the present invention. [Diagram 35] FIG. 35 is a schematic diagram showing the structure of a sample according to an embodiment of the present invention. [Diagram 36] FIG. 36 is a diagram showing the results of SIMS analysis of a sample according to an embodiment of the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0028] Hereinafter, the embodiments will be described with reference to the drawings. However, it will be easily understood by those skilled in the art that the embodiments can be implemented in many different ways, and that the modes and details can be changed in various ways without departing from the spirit and scope of the present invention. Therefore, the present invention should not be interpreted as being limited to the description of the following embodiments.

[0029] In addition, in the drawings, the size, thickness of layers, or areas may be exaggerated for clarity. Therefore, the scale is not necessarily limited. The drawings are schematic illustrations of ideal examples, and are not limited to the shapes or values ​​shown in the drawings. For example, in an actual manufacturing process, layers, resist masks, etc. may be unintentionally thinned by etching or other processes, but this may not be reflected in the drawings to facilitate understanding. In addition, in the drawings, the same reference numerals are used in common between different drawings for the same parts or parts having similar functions, and repeated explanations may be omitted. In addition, when referring to similar functions, the same hatch pattern may be used and no particular reference numeral may be attached.

[0030] In order to facilitate understanding of the invention, particularly in top views (also called "plan views") and perspective views, some components may be omitted from the drawings. Also, some hidden lines may be omitted from the drawings.

[0031] In addition, in this specification, ordinal numbers such as first, second, etc. are used for convenience and do not indicate the order of steps or stacking. Therefore, for example, "first" can be appropriately replaced with "second" or "third" for explanation. In addition, the ordinal numbers described in this specification and the like may not match the ordinal numbers used to specify one embodiment of the present invention.

[0032] In addition, in this specification, the terms "above" and "below" indicating the arrangement are used for convenience in order to explain the positional relationship between the components with reference to the drawings. In addition, the positional relationship between the components changes as appropriate depending on the direction in which each component is depicted. Therefore, the terms are not limited to those described in the specification, and can be rephrased appropriately depending on the situation.

[0033] For example, when it is explicitly stated in this specification that X and Y are connected, the case where X and Y are electrically connected, the case where X and Y are functionally connected, and the case where X and Y are directly connected are considered to be disclosed in this specification, etc. Therefore, it is not limited to a specific connection relationship, for example, a connection relationship shown in a figure or text, and a connection relationship other than that shown in a figure or text is also considered to be disclosed in the figure or text.

[0034] Here, X and Y are objects (for example, a device, an element, a circuit, a wiring, an electrode, a terminal, a conductive film, a layer, etc.).

[0035] Furthermore, the functions of the source and drain may be interchanged when transistors of different polarities are used, when the direction of current changes during circuit operation, etc. For this reason, in this specification and the like, the terms source and drain may be used interchangeably.

[0036] In this specification and the like, depending on the structure of a transistor, the channel width in a region where a channel is actually formed (channel formation region) (hereinafter also referred to as "effective channel width") may differ from the channel width shown in a top view of the transistor (hereinafter also referred to as "apparent channel width"). For example, when a gate covers a side surface of a semiconductor, the effective channel width may be larger than the apparent channel width, and the influence of this may not be negligible. For example, in a fine transistor in which a gate covers a side surface of a semiconductor, the proportion of the channel formation region formed on the side surface of the semiconductor may be large. In that case, the effective channel width is larger than the apparent channel width.

[0037] In such a case, it may be difficult to estimate the effective channel width by actual measurement. For example, in order to estimate the effective channel width from the design value, it is necessary to assume that the shape of the semiconductor is known. Therefore, if the shape of the semiconductor is not precisely known, it is difficult to accurately measure the effective channel width.

[0038] In this specification, when simply described as a channel width, it may refer to an apparent channel width. Alternatively, when simply described as a channel width, it may refer to an effective channel width. Note that the values ​​of the channel length, channel width, effective channel width, apparent channel width, etc. can be determined by analyzing a cross-sectional TEM image, etc.

[0039] Note that the impurity of a semiconductor refers to, for example, anything other than the main component constituting the semiconductor. For example, an element with a concentration of less than 0.1 atomic % can be said to be an impurity. The inclusion of an impurity may cause, for example, an increase in the density of states (DOS) of the semiconductor or a decrease in crystallinity. When the semiconductor is an oxide semiconductor, examples of impurities that change the characteristics of the semiconductor include, for example, Group 1 elements, Group 2 elements, Group 13 elements, Group 14 elements, Group 15 elements, and transition metals other than the main components of the oxide semiconductor, such as hydrogen, lithium, sodium, silicon, boron, phosphorus, carbon, and nitrogen. In the case of an oxide semiconductor, water may also function as an impurity. In addition, in the case of an oxide semiconductor, for example, oxygen vacancies may be formed due to the inclusion of an impurity. In addition, when the semiconductor is silicon, examples of impurities that change the characteristics of the semiconductor include, for example, Group 1 elements, Group 2 elements, Group 13 elements, and Group 15 elements excluding oxygen and hydrogen.

[0040] In this specification and the like, silicon oxynitride refers to a material having a composition that contains more oxygen than nitrogen, and silicon nitride oxide refers to a material having a composition that contains more nitrogen than oxygen.

[0041] In this specification and the like, the term "insulator" can be replaced with an insulating film or an insulating layer, the term "conductor" can be replaced with a conductive film or a conductive layer, and the term "semiconductor" can be replaced with a semiconductor film or a semiconductor layer.

[0042] In addition, in this specification, "parallel" refers to a state in which two straight lines are arranged at an angle of -10 degrees or more and 10 degrees or less. Therefore, it also includes the case of -5 degrees or more and 5 degrees or less. "Approximately parallel" refers to a state in which two straight lines are arranged at an angle of -30 degrees or more and 30 degrees or less. "Perpendicular" refers to a state in which two straight lines are arranged at an angle of 80 degrees or more and 100 degrees or less. Therefore, it also includes the case of 85 degrees or more and 95 degrees or less. "Approximately perpendicular" refers to a state in which two straight lines are arranged at an angle of 60 degrees or more and 120 degrees or less.

[0043] In this specification, a barrier film refers to a film that has the function of suppressing the permeation of impurities such as water and hydrogen, and oxygen, and when the barrier film has conductivity, it may be called a conductive barrier film.

[0044] In this specification and the like, the term "metal oxide" refers to an oxide of a metal in a broad sense. Metal oxides are classified into oxide insulators, oxide conductors (including transparent oxide conductors), oxide semiconductors (also referred to as oxide semiconductors or simply OS), and the like. For example, when a metal oxide is used for a semiconductor layer of a transistor, the metal oxide may be referred to as an oxide semiconductor. In other words, an OS FET or an OS transistor can be rephrased as a transistor having an oxide or an oxide semiconductor.

[0045] In this specification and the like, normally-off means that when no potential is applied to the gate or when a ground potential is applied to the gate, the current flowing through the transistor per 1 μm of channel width is 1×10 -20 A or less, 1×10 at 85℃ -18 A or less, or 1×10 at 125°C -16 This means that it is A or lower.

[0046] (Embodiment 1) An example of a semiconductor device including the transistor 200 of one embodiment of the present invention and a manufacturing method thereof will be described below.

[0047] <Example of semiconductor device configuration> 1A, 1B, 1C, and 1D are a top view and a cross-sectional view of a transistor 200 according to one embodiment of the present invention and the periphery of the transistor 200. FIG.

[0048] FIG. 1A is a top view of a semiconductor device having a transistor 200. FIG. 1B and FIG. 1C are cross-sectional views of the semiconductor device. FIG. 1B is a cross-sectional view of a portion indicated by a dashed line A1-A2 in FIG. 1A, and is also a cross-sectional view of the transistor 200 in the channel length direction. FIG. 1C is a cross-sectional view of a portion indicated by a dashed line A3-A4 in FIG. 1A, and is also a cross-sectional view of the transistor 200 in the channel width direction. FIG. 1D is a cross-sectional view of a portion indicated by a dashed line A5-A6 in FIG. 1A. Note that some elements are omitted from the top view of FIG. 1A for clarity.

[0049] The semiconductor device of one embodiment of the present invention includes an insulator 212 on a substrate (not shown), an insulator 214 on the insulator 212, a transistor 200 on the insulator 214, an insulator 280 on the transistor 200, an insulator 282 on the insulator 280, an insulator 283 on the insulator 282, and an insulator 274 on the insulator 283. The insulators 212, 214, 280, 282, 283, and 274 function as interlayer films. The semiconductor device also includes a conductor 240 (conductor 240a and conductor 240b) that is electrically connected to the transistor 200 and functions as a plug. A conductor 246 (conductor 246a and conductor 246b) that is electrically connected to the conductor 240 and functions as a wiring is provided over the insulator 274 and the conductor 240.

[0050] The conductor 240 includes a first conductor and a second conductor disposed inside the first conductor. The height of the top surface of the conductor 240 and the height of the top surface of the insulator 274 can be approximately the same. In the transistor 200, the first conductor of the conductor 240 and the second conductor of the conductor 240 are stacked, but the present invention is not limited to this. For example, the conductor 240 may be configured to have a single layer or a stacked structure of three or more layers. When the structure has a stacked structure, the structures may be distinguished by giving ordinal numbers in the order of formation.

[0051] 1, the transistor 200 described in this embodiment is preferably formed over an insulator 212 and has a top surface and side surfaces covered with an insulator 283. Furthermore, in a top view, the insulator 283 and the insulator 212 are preferably in contact with each other on the outside of the transistor 200, and the transistor 200 is preferably sealed with the insulator 283 and the insulator 212.

[0052] [Transistor 200] As shown in FIG. 1 , the transistor 200 includes an insulator 216 on an insulator 214, a conductor 205 (conductor 205a and conductor 205b) disposed so as to be embedded in the insulator 216, an insulator 222 on the insulator 216 and on the conductor 205, an insulator 224 on the insulator 222, an oxide 230a on the insulator 224, an oxide 230b on the oxide 230a, and an oxide 230b on the oxide 230b. 3a and oxide 243b, conductor 242a on oxide 243a, conductor 242b on oxide 243b, insulator 272a on conductor 242a, insulator 272b on conductor 242b, oxide 230c on oxide 230b, insulator 250 on oxide 230c, and conductor 260 (conductor 260a and conductor 260b) located on insulator 250 and overlapping with oxide 230c. In addition, oxide 230c contacts the side of oxide 243a, the side of oxide 243b, the side of conductor 242a, and the side of conductor 242b. Conductor 260 has conductor 260a and conductor 260b, and conductor 260a is arranged to surround the bottom and side of conductor 260b. 1B, the upper surface of the conductor 260 is disposed so as to be substantially aligned with the upper surface of the insulator 250 and the upper surface of the oxide 230c. Also, the insulator 282 contacts the upper surfaces of the conductor 260, the insulator 250, the oxide 230c, and the insulator 280.

[0053] In the following, the oxide 243a and the oxide 243b may be collectively referred to as the oxide 243. The conductor 242a and the conductor 242b may be collectively referred to as the conductor 242. The conductor 242a and the conductor 242b may be collectively referred to as the conductor 242. The insulator 272a and the insulator 272b may be collectively referred to as the insulator 272.

[0054] In the transistor 200, the conductor 260 functions as a gate of the transistor, and the conductors 242a and 242b function as a source electrode and a drain electrode, respectively. The transistor 200 is formed in a self-aligned manner such that the conductor 260, which functions as a gate, fills an opening formed by the insulator 280 or the like. By forming the conductor 260 in this manner, it is possible to reliably place the conductor 260 in the region between the conductors 242a and 242b without alignment.

[0055] Furthermore, at least one of the insulators 212, 214, 222, 272 (hereinafter, the insulators 272a and 272b may be collectively referred to as the insulators 272), 282, and 283 preferably has a function of suppressing the diffusion of hydrogen (e.g., at least one of hydrogen atoms, hydrogen molecules, etc.) or water molecules. In particular, the insulators 212 and 283 preferably have a high function of suppressing the diffusion of hydrogen (e.g., at least one of hydrogen atoms, hydrogen molecules, etc.) or water molecules. Furthermore, at least one of the insulators 212, 214, 222, 272, 282, and 283 preferably has a function of suppressing the diffusion of oxygen (e.g., at least one of oxygen atoms, oxygen molecules, etc.). For example, at least one of the insulators 212, 214, 222, 272, 282, and 283 preferably has a lower permeability to one or both of oxygen and hydrogen than the insulator 224. At least one of the insulators 212, 214, 222, 272, 282, and 283 preferably has a lower permeability to one or both of oxygen and hydrogen than the insulator 250. At least one of the insulators 212, 214, 222, 272, 282, and 283 preferably has a lower permeability to one or both of oxygen and hydrogen than the insulator 280.

[0056] For example, aluminum oxide, hafnium oxide, gallium oxide, indium gallium zinc oxide, silicon nitride, silicon nitride oxide, or the like can be used as the insulators 212, 214, 222, 272, 282, and 283. In particular, it is preferable to use silicon nitride or silicon nitride oxide, which have a higher hydrogen barrier property, as the insulators 212 and 283.

[0057] 1, in one aspect of the semiconductor device shown in the present embodiment, the insulators 214, 216, 222, 224, 280, and 282 are patterned, and the insulator 283 covers them. That is, the insulator 283 contacts the upper surface and side surface of the insulator 282, the side surface of the insulator 280, the side surface of the insulator 224, the side surface of the insulator 222, the side surface of the insulator 216, the side surface of the insulator 214, and the upper surface of the insulator 212. As a result, the insulators 214, 216, 222, 224, 280, and 282, including the oxide 230, are isolated from the outside by the insulators 283 and 212.

[0058] Moreover, it is preferable that the oxide 230 has an oxide 230a on the insulator 224, an oxide 230b on the oxide 230a, and an oxide 230c disposed on the oxide 230b and at least a portion of which is in contact with the upper surface of the oxide 230b. Here, it is preferable that the side surface of the oxide 230c is provided in contact with the oxide 243a, the oxide 243b, the conductor 242a, the conductor 242b, the insulator 272a, the insulator 272b, and the insulator 280.

[0059] In the transistor 200, a three-layer structure of the oxide 230a, the oxide 230b, and the oxide 230c is shown in the channel formation region and its vicinity, but the present invention is not limited to this. For example, a single layer of the oxide 230b, a two-layer structure of the oxide 230b and the oxide 230a, a two-layer structure of the oxide 230b and the oxide 230c, or a stacked structure of four or more layers may be provided. For example, the oxide 230c may be a two-layer structure, and a stacked structure of four layers may be provided.

[0060] In the transistor 200, a metal oxide functioning as an oxide semiconductor (hereinafter also referred to as an oxide semiconductor) is preferably used for the oxide 230 (the oxide 230a, the oxide 230b, and the oxide 230c) including the channel formation region. For example, the metal oxide functioning as an oxide semiconductor preferably has an energy gap of 2 eV or more, preferably 2.5 eV or more. By using a metal oxide with such a large energy gap, the leakage current (off-state current) in the non-conducting state of the transistor 200 can be made extremely small. By using such a transistor, a semiconductor device with low power consumption can be provided.

[0061] For example, a metal oxide such as In-M-Zn oxide (wherein element M is one or more elements selected from aluminum, gallium, yttrium, tin, copper, vanadium, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, etc.) may be used as the oxide 230. In particular, element M may be aluminum, gallium, yttrium, or tin. Alternatively, oxide 230 may be In-M oxide, In-Zn oxide, or M-Zn oxide.

[0062] The oxide 230 includes an oxide 230a, an oxide 230b on the oxide 230a, and an oxide 230c on the oxide 230b. By having the oxide 230a below the oxide 230b, it is possible to suppress the diffusion of impurities from structures formed below the oxide 230a to the oxide 230b. Also, by having the oxide 230c on the oxide 230b, it is possible to suppress the diffusion of impurities from structures formed above the oxide 230c to the oxide 230b.

[0063] The oxide 230 preferably has a laminated structure made of oxides having different atomic ratios of metal atoms. Specifically, in the metal oxide used for the oxide 230a, the atomic ratio of element M among the constituent elements is preferably larger than the atomic ratio of element M among the constituent elements in the metal oxide used for the oxide 230b. In addition, in the metal oxide used for the oxide 230a, the atomic ratio of element M to In is preferably larger than the atomic ratio of element M to In in the metal oxide used for the oxide 230b. In addition, in the metal oxide used for the oxide 230b, the atomic ratio of In to element M is preferably larger than the atomic ratio of In to element M in the metal oxide used for the oxide 230a. In addition, the oxide 230c can use a metal oxide that can be used for the oxide 230a or the oxide 230b.

[0064] Specifically, the oxide 230a may be a metal oxide having an atomic ratio of In:Ga:Zn=1:3:4 or 1:1:0.5. The oxide 230b may be a metal oxide having an atomic ratio of In:Ga:Zn=4:2:3 or 1:1:1. The oxide 230c may be a metal oxide having an atomic ratio of In:Ga:Zn=1:3:4, Ga:Zn=2:1, or Ga:Zn=2:5. Specific examples of the oxide 230c having a layered structure include a layered structure of In:Ga:Zn=4:2:3 [atomic ratio] and In:Ga:Zn=1:3:4 [atomic ratio], a layered structure of Ga:Zn=2:1 [atomic ratio] and In:Ga:Zn=4:2:3 [atomic ratio], a layered structure of Ga:Zn=2:5 [atomic ratio] and In:Ga:Zn=4:2:3 [atomic ratio], and a layered structure of gallium oxide and In:Ga:Zn=4:2:3 [atomic ratio].

[0065] Moreover, the oxide 230b is preferably crystalline. For example, it is preferable to use a c-axis aligned crystalline oxide semiconductor (CAAC-OS) described later. Crystalline oxides such as CAAC-OS have few impurities and defects (oxygen vacancies, etc.), and have a dense structure with high crystallinity. This can suppress the extraction of oxygen from the oxide 230b by the source electrode or drain electrode. As a result, even if a heat treatment is performed, the extraction of oxygen from the oxide 230b can be reduced, and the transistor 200 is stable against high temperatures (so-called thermal budget) in the manufacturing process.

[0066] It is also preferable that the energy of the conduction band minimum of the oxide 230a and the oxide 230c is higher than that of the oxide 230b, or, in other words, that the electron affinity of the oxide 230a and the oxide 230c is smaller than that of the oxide 230b.

[0067] Here, the electron affinity or the energy level Ec at the bottom of the conduction band can be obtained from the ionization potential Ip, which is the difference between the vacuum level and the energy Ev at the top of the valence band, and the energy gap Eg. The ionization potential Ip can be measured, for example, using an ultraviolet photoelectron spectroscopy (UPS) device. The energy gap Eg can be measured, for example, using a spectroscopic ellipsometer.

[0068] In addition, at the junctions of the oxides 230a, 230b, and 230c, the energy level of the conduction band minimum changes gradually. In other words, it can be said that the energy level of the conduction band minimum at the junctions of the oxides 230a, 230b, and 230c changes continuously or is a continuous junction. To achieve this, it is preferable to reduce the defect level density of the mixed layer formed at the interface between the oxides 230a and 230b and at the interface between the oxides 230b and 230c.

[0069] Moreover, the main path of carriers is the oxide 230b. By configuring the oxide 230a and the oxide 230c as described above, it is possible to reduce the defect state density at the interface between the oxide 230a and the oxide 230b and at the interface between the oxide 230b and the oxide 230c. Therefore, the influence of the interface scattering on the carrier conduction is reduced, and the transistor 200 can obtain a high on-current and high frequency characteristics.

[0070] It is preferable to use an oxide semiconductor with a low carrier concentration for the oxide 230 (for example, the oxide 230b). In order to reduce the carrier concentration of the oxide semiconductor, the impurity concentration in the oxide semiconductor may be reduced to reduce the density of defect states. In this specification and the like, a low impurity concentration and a low density of defect states are referred to as high-purity intrinsic or substantially high-purity intrinsic. Note that examples of impurities in an oxide semiconductor include hydrogen, nitrogen, alkali metals, alkaline earth metals, iron, nickel, and silicon.

[0071] In particular, hydrogen contained in oxide semiconductors reacts with oxygen that bonds with metal atoms to form water, which creates oxygen vacancies (V O In addition, defects in which hydrogen is inserted into the oxygen vacancy (hereafter referred to as V O H.) can function as a donor and generate electrons that serve as carriers. Some of the hydrogen can bond with oxygen that bonds to metal atoms to generate electrons that serve as carriers. Therefore, a transistor using an oxide semiconductor that contains a lot of hydrogen is likely to have normally-on characteristics. Furthermore, hydrogen in an oxide semiconductor is easily mobile due to stress such as heat or an electric field; therefore, if an oxide semiconductor contains a lot of hydrogen, the reliability of the transistor may be deteriorated.

[0072] V O H can function as a donor for an oxide semiconductor. However, it is difficult to quantitatively evaluate the defects. Therefore, in an oxide semiconductor, the oxide semiconductor may be evaluated by the carrier concentration instead of the donor concentration. Therefore, in this specification and the like, the carrier concentration assuming a state in which no electric field is applied may be used as a parameter of the oxide semiconductor instead of the donor concentration. In other words, the "carrier concentration" described in this specification and the like may be rephrased as the "donor concentration".

[0073] From the above, when an oxide semiconductor is used for the oxide 230, V in the oxide 230 O It is preferable to reduce H as much as possible and make it high-purity intrinsic or substantially high-purity intrinsic. O In order to obtain an oxide semiconductor with sufficiently reduced H, it is important to remove impurities such as moisture and hydrogen from the oxide semiconductor (sometimes referred to as dehydration or dehydrogenation treatment) and to supply oxygen to the oxide semiconductor to compensate for oxygen vacancies (sometimes referred to as oxygen addition treatment). O By using an oxide semiconductor in which impurities such as H are sufficiently reduced for a channel formation region of a transistor, stable electrical characteristics can be obtained.

[0074] However, even if the oxide semiconductor is formed so that the hydrogen concentration is reduced, there is a risk that hydrogen may be taken in from the conductor 240 in contact with the oxide semiconductor. The conductor 240 is a conductor that functions as a via, and is disposed so as to be embedded in the openings formed in the insulators 274 and 280. Here, the insulators 274 and 280 are insulating films that function as interlayer films, and it is preferable to use an insulator containing silicon, such as silicon oxide or silicon oxynitride. When forming such insulators 274 and 280, SiH 4 Silicon hydrides such as SiH are often used as the source gas. 4 When a source gas containing silicon hydride such as silicon hydride is decomposed during film formation, a large amount of highly reactive hydrogen (e.g., hydrogen radicals) is generated, and a large amount of hydrogen may be incorporated into the formed insulators 274 and 280. Some of the large amount of hydrogen incorporated into the insulators 274 and 280 may diffuse into the conductor 240 functioning as a via due to a heat treatment or the like during the manufacturing process of the transistor 200. The hydrogen may then diffuse to the oxide 230 through the conductor 240. In this manner, the hydrogen concentration in the oxide semiconductor may increase through the conductor 240.

[0075] In contrast, in the transistor 200 shown in this embodiment, regions 241 having a higher nitrogen concentration than other regions are formed in the insulator 274 and the insulator 280 near the interface with the conductor 240a and near the interface with the conductor 240b, thereby reducing the intrusion of hydrogen from the insulator 274 and the insulator 280 into the conductor 240.

[0076] 1, region 241 may be divided into region 241a formed in insulator 280 near the interface with conductor 240a, region 241b formed in insulator 280 near the interface with conductor 240b, and region 241c formed in insulator 274 near the interfaces with conductor 240a and conductor 240b. Also, as shown in FIG. 1, region 241c may be formed in the vicinity of the upper surface of insulator 274.

[0077] Region 241 is preferably formed with a thickness of, for example, 1 nm or more, and more preferably with a thickness of 1.5 nm or more, in insulator 274 and insulator 280. Region 241 can also be formed with a thickness of, for example, 50 nm or less, or 20 nm or less, or 10 nm or less, in insulator 274 and insulator 280.

[0078] Region 241 has a higher nitrogen concentration than other regions of insulator 274 and insulator 280. Region 241a and region 241b have a higher nitrogen concentration than at least some of the other regions of insulator 280. Region 241c has a higher nitrogen concentration than at least some of the other regions of insulator 274. Region 241 may have a lower oxygen concentration than other regions of insulator 274 and insulator 280.

[0079] The region 241 can be formed by solid-phase nitriding the surfaces of the insulators 274 and 280 in a state where the conductor 240 is not provided and openings are formed in the insulators 272, 280, 282, 283, and 274. The solid-phase nitriding of the insulators 274 and 280 can be performed by performing a plasma treatment in an atmosphere containing nitrogen. Such a treatment may be referred to as a nitrogen plasma treatment below. In the nitrogen plasma treatment, nitrogen gas is turned into plasma using microwaves or high frequency waves such as RF, and the nitrogen plasma is applied to the insulators 280 and 274 to perform solid-phase nitriding near the surfaces.

[0080] In addition, the nitrogen plasma treatment is preferably performed using an apparatus having a power supply that generates high density plasma using microwaves, for example. Hereinafter, the plasma treatment using microwaves is sometimes referred to as microwave treatment, and the apparatus having a power supply that generates high density plasma using microwaves is sometimes referred to as microwave treatment apparatus. The microwave treatment apparatus may also have a power supply that applies RF to the substrate side. In an atmosphere containing nitrogen, high density plasma can be used to generate high density nitrogen radicals. Furthermore, applying RF to the substrate side can efficiently guide ions generated by high density plasma into the insulators 274 and 280. Furthermore, the microwave treatment in an atmosphere containing nitrogen is preferably performed under reduced pressure, with the pressure being 400 Pa or less, preferably 200 Pa or less, more preferably 60 Pa or less, and even more preferably 12 Pa or less. Furthermore, the nitrogen flow rate ratio (N 2 / N 2 +Ar) is preferably 50% or less, and more preferably 10% to 30%. The processing temperature may be, for example, about 400° C. In this specification and the like, the processing temperature is not limited to the substrate temperature during processing, but includes the set temperature of the processing apparatus.

[0081] The above-described region 241 has a function of suppressing the diffusion of hydrogen (e.g., at least one of hydrogen atoms, hydrogen molecules, etc.). The region 241 preferably has lower hydrogen permeability than the insulator 274 or the insulator 280, for example. Such a region 241 is formed between the conductor 240 and the insulators 274 and 280, thereby reducing the amount of hydrogen contained in the insulators 274 and 280 that is mixed into the conductor 240. Thus, the amount of hydrogen that diffuses from the conductor 240 to the conductor 242 and the oxide 230 can be reduced. Note that the region 241 preferably also has a function of suppressing the diffusion of oxygen.

[0082] By providing the region 241 between the insulator 280 and the conductor 240, the hydrogen concentration in the oxide 230 can be reduced. For example, the hydrogen concentration of the oxide 230b obtained by secondary ion mass spectrometry (SIMS) is 1×10 20 atoms / cm 3 Less than 1 x 10 19 atoms / cm 3 less than 5×10 18 atoms / cm 3 less than 1×10 18 atoms / cm 3 By using the oxide 230 in which impurities such as hydrogen are sufficiently reduced for the channel formation region of the transistor 200, the transistor 200 can have normally-off characteristics, and thus the transistor 200 can have stable electrical characteristics and improved reliability.

[0083] In addition, when an oxide semiconductor is used for the oxide 230, the carrier concentration of the oxide semiconductor in a region functioning as a channel formation region is 1×10 18 cm -3 It is preferable that the value is less than 1×10 17 cm -3 More preferably, it is less than 1×10 16 cm -3 More preferably, it is less than 1×10 13 cm -3 More preferably, it is less than 1×10 12 cm -3 Note that the lower limit of the carrier concentration of the oxide semiconductor in the region functioning as a channel formation region is not particularly limited, but is preferably, for example, 1×10 -9 cm -3 It can be said that:

[0084] Moreover, when forming the region 241, the nitrogen plasma treatment is performed in a state in which an opening reaching the conductor 242a and an opening reaching the conductor 242b are formed in the insulators 272, 280, 282, 283, and 274. As a result, a region 244a having a higher nitrogen concentration than other regions of the conductor 242a is formed near the interface between the conductor 242a and the conductor 240a (near the surface of the conductor 242a when formed), and a region 244b having a higher nitrogen concentration than other regions of the conductor 242b is formed near the interface between the conductor 242b and the conductor 240b (near the surface of the conductor 242b when formed). Note that hereinafter, the region 244a and the region 244b may be collectively referred to as the region 244.

[0085] When a metal nitride, such as tantalum nitride, is used as the conductor 242, the region 244 preferably has a resistivity approximately equal to that of the other regions of the conductor 242. For example, the resistivity of the region 244 is preferably 130% or less of the resistivity of the other regions of the conductor 242. In this way, the region 244 does not significantly impede the conductivity of the conductor 242 that functions as a source electrode or a drain electrode. Therefore, even if the region 241 is formed by the nitrogen plasma treatment, there is no need to perform a special post-treatment on the conductor 242. In addition, by providing the region 244 having a higher nitrogen concentration than the other regions of the conductor 242, the amount of hydrogen diffusing from the conductor 240 to the conductor 242 may be further reduced.

[0086] Further, in the insulator 280, the insulator 224, and the insulator 216, a region 245 having a higher nitrogen concentration than other regions of the insulator 280, the insulator 224, and the insulator 216 may be formed near the interface with the insulator 283. The region 245 is formed on the side surface of the insulator 280, the insulator 224, and the insulator 216 as shown in FIG. 1. The region 245 preferably has a similar configuration to the region 241. The region 245 as described above has a function of suppressing the diffusion of hydrogen (e.g., at least one of hydrogen atoms, hydrogen molecules, etc.). The region 245 preferably has a lower hydrogen permeability than the insulators 280, the insulator 224, and the insulator 216, for example. The region 245 can be formed by nitrogen plasma treatment in the same manner as the region 241. Therefore, the description of the region 241 can be referred to for details of the configuration of the region 245 and the method of forming the region 245.

[0087] Such a region 245 is formed between the insulator 280, the insulator 224, and the insulator 216 and the insulator 283, thereby making it possible to reduce the intrusion of hydrogen contained in the insulator 274 into the insulator 280, etc. Thus, the amount of hydrogen diffusing from the insulator 280, etc. to the oxide 230 can be further reduced.

[0088] By forming the region 245 on the side surfaces of the insulator 280, the insulator 224, and the insulator 216 before forming the insulator 283, even if a CVD method or the like that generates a large amount of hydrogen in a chamber is used to form the insulator 283, it is possible to reduce the intrusion of the hydrogen into the insulator 280, the insulator 224, and the insulator 216. Therefore, since a film formation method with good step coverage such as a CVD method can be used to form the insulator 283, the insulator 283 can be formed without forming a step discontinuity or a pinhole on the step of the insulator 280 or the like. This allows the transistor 200 to be sealed with the insulator 283 and the insulator 212.

[0089] Note that the conductor 240 penetrates the insulator 283, and since the region 241 is provided in contact with the conductor 240 as described above, it is also possible to reduce hydrogen that enters the inside of the insulator 283 via the conductor 240. In this way, the transistor 200 can be more reliably sealed with the insulator 283, the insulator 212, and the region 241, and it is possible to reduce impurities such as hydrogen contained in the insulator 274, etc. from entering from outside the insulator 283.

[0090] In addition, by forming interlayer insulating films (insulator 216, insulator 274, insulator 280, etc.) and gate insulating films (insulator 224, insulator 250, etc.) using a source gas that does not contain hydrogen atoms or has a low hydrogen atom content, the hydrogen concentration in these insulating films can be reduced, thereby reducing the amount of hydrogen that enters the channel formation region of the oxide semiconductor.

[0091] In the deposition of the insulating film, a gas having a molecule containing silicon atoms is mainly used as the deposition gas. In order to reduce the hydrogen contained in the insulating film, it is preferable that the molecule containing silicon atoms contains fewer hydrogen atoms, and it is more preferable that the molecule containing silicon atoms does not contain hydrogen atoms. Of course, deposition gases other than the gas having the molecule containing silicon atoms also preferably contain fewer hydrogen atoms, and it is more preferable that they do not contain hydrogen atoms.

[0092] The above silicon-containing molecules are called Si x -R y For example, the functional group R is an isocyanate group (-N=C=O), a cyanate group (-OC≡N), a cyano group (-C≡N), a diazo group (=N 2 ), azide group (-N 3 ), nitroso group (-NO), and nitro group (-NO 2) can be used. For example, 1≦x≦3 and 1≦y≦8 can be used. As such a molecule containing a silicon atom, for example, tetraisocyanate silane, tetracyanate silane, tetracyanosilane, hexaisocyanate silane, octaisocyanate silane, etc. can be used. Here, molecules in which the same type of functional group is bonded to the silicon atom are exemplified, but the present embodiment is not limited to this. A configuration in which different types of functional groups are bonded to the silicon atom may also be used.

[0093] Also, for example, a halogen (Cl, Br, I, or F) may be used as the functional group R. For example, 1≦x≦2 and 1≦y≦6 may be satisfied. As a molecule containing such a silicon atom, for example, tetrachlorosilane (SiCl 4 ), hexachlorodisilane (Si 2 Cl 6 ) or the like can be used. Although an example in which chlorine is used as the functional group has been shown, halogens other than chlorine, such as bromine, iodine, and fluorine, can also be used as the functional group. Also, a configuration in which different types of halogens are bonded to silicon atoms can be used.

[0094] The deposition of the insulators 216, 274, 280, 224, and 250 may be performed by a chemical vapor deposition (CVD) method using a gas having molecules containing silicon atoms as described above. The CVD method has a relatively high deposition rate and is therefore suitable for depositing the insulators 280, 274, and 216, which have thick films.

[0095] As the CVD method, it is preferable to use a plasma enhanced CVD (PECVD) method using plasma or a thermal CVD (TCVD) method using heat. When using a thermal CVD method, an atmospheric pressure CVD (APCVD) method in which a film is formed under atmospheric pressure may be used, or a low pressure CVD (LPCVD) method in which a film is formed under a reduced pressure lower than atmospheric pressure may be used.

[0096] When the insulators 216, 274, 280, 224, and 250 are formed by using a CVD method, it is preferable to use an oxidizing agent. 2 , O 3 , NO, NO 2 , N 2 O, N 2 O 3 , N 2 O 4 , N 2 O 5 , CO, CO 2 It is preferable to use a gas that does not contain hydrogen atoms, such as

[0097] Alternatively, the insulators 216, 274, 280, 224, and 250 may be deposited by ALD (Atomic Layer Deposition). In ALD, a first source gas (hereinafter referred to as a precursor, which may also be referred to as a precursor or a metal precursor) and a second source gas (hereinafter referred to as a reactant, which may also be referred to as a reactant or a non-metal precursor) for reaction are alternately introduced into a chamber, and the introduction of these source gases is repeated to deposit the film.

[0098] In the ALD method, by forming a film while switching the source gas, atoms can be deposited one layer at a time by utilizing the self-controllability that is a property of atoms. Therefore, the ALD method can form a very thin film, a film on a structure with a high aspect ratio, a film with few defects such as pinholes, and a film with excellent coverage. For this reason, the ALD method is suitable for forming the insulator 250 and the insulator 224.

[0099] As the ALD method, a thermal ALD method in which a reaction between a precursor and a reactant is carried out using only thermal energy may be used, or a plasma enhanced ALD (PEALD) method in which a plasma excited reactant is used may be used.

[0100] When the ALD method is used, the gas having the silicon atom-containing molecule may be used as a precursor and the oxidizing agent may be used as a reactant, which can greatly reduce the amount of hydrogen taken into the insulators 216, 274, 280, 224, and 250.

[0101] In the above, an example was shown in which the molecule containing silicon atoms does not contain hydrogen atoms, but the present embodiment is not limited to this. In the above molecule containing silicon atoms, a part of the functional group bonded to the silicon atom may be replaced with a hydrogen atom. However, the hydrogen atom contained in the molecule containing silicon atoms may be replaced with a hydrogen atom such as silane (SiH 4 ) or less. In other words, the above-mentioned molecule containing silicon atoms preferably has 3 or less hydrogen atoms per silicon atom. It is more preferable that the gas containing the above-mentioned molecule containing silicon atoms has 3 or less hydrogen atoms per silicon atom.

[0102] As described above, by forming at least one of insulator 216, insulator 274, insulator 280, insulator 224, and insulator 250 by a film formation method using a gas in which hydrogen atoms have been reduced or removed, the amount of hydrogen contained in these insulating films can be reduced. In particular, by forming insulator 216, insulator 224, insulator 280, and insulator 250, which are formed in the region sealed by insulator 283 and insulator 212 together with oxide 230, by the above film formation method, the hydrogen concentration in the sealed region can be reduced, and further hydrogen mixed in from the outside can be reduced by insulator 283, insulator 212, and region 241, which is more preferable.

[0103] As shown in FIG. 1B, FIG. 1C, and FIG. 1D, the transistor 200 has a structure in which the insulator 282 and the insulator 250 are in direct contact with each other. With such a structure, oxygen contained in the insulator 280 is less likely to be absorbed by the conductor 260. Therefore, the oxygen contained in the insulator 280 can be efficiently supplied to the oxide 230a and the oxide 230b via the oxide 230c, so that oxygen vacancies in the oxide 230a and the oxide 230b can be reduced, and the electrical characteristics and reliability of the transistor 200 can be improved. In addition, impurities such as hydrogen contained in the insulator 280 can be prevented from being mixed into the insulator 250, so that the hydrogen concentration in the insulator 250 and the oxide 230 can be further reduced. Thus, adverse effects on the electrical characteristics and reliability of the transistor 200 can be suppressed. Silicon nitride, silicon nitride oxide, aluminum oxide, or hafnium oxide can be used as the insulator 282.

[0104] As described above, a semiconductor device having stable electrical characteristics and improved reliability with suppressed fluctuation in electrical characteristics can be provided. Alternatively, a semiconductor device having normally-off electrical characteristics can be provided. Alternatively, a semiconductor device having a transistor with large on-state current can be provided. Alternatively, a semiconductor device having a transistor with high frequency characteristics can be provided. Alternatively, a semiconductor device having a transistor with small off-state current can be provided.

[0105] A detailed structure of a semiconductor device including the transistor 200 according to one embodiment of the present invention will be described below.

[0106] The conductor 205 is disposed so as to overlap the oxide 230 and the conductor 260. In addition, the conductor 205 is preferably embedded in the insulators 214 and 216.

[0107] Here, the conductor 260 may function as a first gate (also referred to as a top gate) electrode. The conductor 205 may function as a second gate (also referred to as a bottom gate) electrode. In this case, the Vth of the transistor 200 can be controlled by changing the potential applied to the conductor 205 independently of the potential applied to the conductor 260. In particular, by applying a negative potential to the conductor 205, the Vth of the transistor 200 can be made higher than 0 V, and the off-current can be reduced. Therefore, applying a negative potential to the conductor 205 can reduce the drain current when the potential applied to the conductor 260 is 0 V, compared to not applying a negative potential.

[0108] Note that the conductor 205 is preferably larger than the size of a region of the oxide 230 that does not overlap with the conductor 242a and the conductor 242b, as shown in FIG. 1A. In particular, as shown in FIG. 1C, the conductor 205 preferably extends also in a region outside the end of the oxide 230 that intersects with the channel width direction. That is, outside the side surface of the oxide 230 in the channel width direction, the conductor 205 and the conductor 260 preferably overlap with each other through an insulator. Alternatively, by providing the conductor 205 to be large, local charging (referred to as charge-up) may be alleviated in a process using plasma in a manufacturing process after the formation of the conductor 205. However, one embodiment of the present invention is not limited thereto. The conductor 205 may overlap with at least the oxide 230 located between the conductor 242a and the conductor 242b.

[0109] Furthermore, it is preferable that the height of the bottom surface of the conductor 260 in the region where the oxide 230a and the oxide 230b do not overlap with the conductor 260 is located at a position lower than the height of the bottom surface of the oxide 230b, with respect to the bottom surface of the insulator 224. Furthermore, the difference between the height of the bottom surface of the conductor 260 in the region where the oxide 230b and the conductor 260 do not overlap with each other is 0 nm or more and 100 nm or less, preferably 3 nm or more and 50 nm or less, and more preferably 5 nm or more and 20 nm or less.

[0110] In this manner, the conductor 260 functioning as a gate covers the side and top surfaces of the oxide 230b in the channel formation region via the oxide 230c and the insulator 250, and the electric field of the conductor 260 is easily applied to the entire oxide 230b in the channel formation region. This makes it possible to increase the on-current of the transistor 200 and improve the frequency characteristics. In this specification, the structure of a transistor in which the electric fields of the first gate and the second gate electrically surround the channel formation region is called a surrounded channel (S-channel) structure.

[0111] The conductor 205a is preferably a conductor that suppresses the permeation of impurities such as water or hydrogen, and oxygen. For example, titanium, titanium nitride, tantalum, or tantalum nitride can be used. The conductor 205b is preferably a conductive material mainly composed of tungsten, copper, or aluminum. Although the conductor 205 is illustrated as having two layers, it may have a multi-layer structure of three or more layers.

[0112] Here, it is preferable to successively form different types of films, that is, an oxide semiconductor, an insulator or conductor located under the oxide semiconductor, and an insulator or conductor located over the oxide semiconductor, without exposure to the air, because this makes it possible to form a substantially high-purity intrinsic oxide semiconductor film in which the concentration of impurities (particularly, hydrogen and water) is reduced.

[0113] At least one of the insulators 212, 214, 222, 272, 282, and 283 preferably functions as a barrier insulating film that suppresses impurities such as water or hydrogen from entering the transistor 200 from the substrate side or from above. Therefore, at least one of the insulators 212, 214, 222, 272, 282, and 283 preferably functions as a barrier insulating film that suppresses impurities such as water or hydrogen from entering the transistor 200 from the substrate side or from above. 2 O, NO, NO 2 It is preferable to use an insulating material that has a function of suppressing the diffusion of impurities such as copper atoms (the impurities are unlikely to permeate through the insulating material), or that has a function of suppressing the diffusion of oxygen (for example, at least one of oxygen atoms, oxygen molecules, etc.) (the oxygen is unlikely to permeate through the insulating material).

[0114] For example, it is preferable to use silicon nitride or silicon nitride oxide as the insulator 212 and the insulator 283, and aluminum oxide or hafnium oxide as the insulator 214, the insulator 222, the insulator 272, and the insulator 282. This can suppress impurities such as water or hydrogen from the substrate side to the transistor 200 side through the insulator 212 and the insulator 214. Alternatively, it is possible to suppress the diffusion of oxygen contained in the insulator 224 or the like to the substrate side through the insulator 212 and the insulator 214. It is also possible to suppress the diffusion of impurities such as water or hydrogen from the insulator 274 or the like disposed above the insulators 272, 282, and 283 to the transistor 200 side. In this way, it is preferable to have a structure in which the transistor 200 is surrounded by the insulators 212, 214, 222, 272, 282, and 283, which have the function of suppressing the diffusion of impurities such as water or hydrogen, and oxygen.

[0115] In addition, it may be preferable to reduce the resistivity of the insulator 212 and the insulator 283. For example, it is preferable to reduce the resistivity of the insulator 212 and the insulator 283 to approximately 1×10 13By setting the resistivity at Ωcm, the insulator 212 and the insulator 283 may be able to reduce charge-up of the conductor 205, the conductor 242, or the conductor 260 in a process using plasma or the like in a semiconductor device manufacturing process. 10 Ωcm or more 1×10 15 Ωcm or less.

[0116] The insulators 216, 280, and 274 preferably have a lower dielectric constant than the insulator 214. By using a material with a low dielectric constant as an interlayer film, the parasitic capacitance generated between wirings can be reduced. For example, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide to which fluorine has been added, silicon oxide to which carbon has been added, silicon oxide to which carbon and nitrogen have been added, silicon oxide having vacancies, or the like may be used as the insulators 216, 280, and 274 as appropriate.

[0117] The insulator 222 and the insulator 224 function as gate insulators.

[0118] Here, the insulator 224 in contact with the oxide 230 preferably releases oxygen by heating. In this specification, oxygen released by heating is sometimes referred to as excess oxygen. For example, the insulator 224 may be made of silicon oxide, silicon oxynitride, or the like as appropriate. By providing an insulator containing oxygen in contact with the oxide 230, oxygen vacancies in the oxide 230 can be reduced and the reliability of the transistor 200 can be improved.

[0119] Specifically, it is preferable to use an oxide material from which a portion of oxygen is released by heating as the insulator 224. The oxide material from which oxygen is released by heating is an oxide material from which the amount of released oxygen molecules is 1.0×10 18 molecules / cm 3 More than 1.0×10 19 molecules / cm3 More preferably, 2.0×10 19 molecules / cm 3 or more than 3.0×10 20 molecules / cm 3 The oxide film is one having the above-mentioned properties. The surface temperature of the film during the TDS analysis is preferably in the range of 100° C. or more and 700° C. or less, or 100° C. or more and 400° C. or less.

[0120] The insulator 222 preferably functions as a barrier insulating film that prevents impurities such as water or hydrogen from entering the transistor 200 from the substrate side. For example, the insulator 222 preferably has lower hydrogen permeability than the insulator 224. By surrounding the insulator 224 and the oxide 230 with the insulator 222 and the insulator 283, impurities such as water or hydrogen can be prevented from entering the transistor 200 from the outside.

[0121] Furthermore, it is preferable that the insulator 222 has a function of suppressing the diffusion of oxygen (e.g., at least one of oxygen atoms, oxygen molecules, etc.) (the oxygen is less likely to permeate). For example, it is preferable that the insulator 222 has lower oxygen permeability than the insulator 224. This is because the insulator 222 has a function of suppressing the diffusion of oxygen and impurities, which can reduce the diffusion of oxygen contained in the oxide 230 below the insulator 222. Furthermore, it is possible to suppress the conductor 205 from reacting with the insulator 224 or the oxygen contained in the oxide 230.

[0122] The insulator 222 may be an insulator containing an oxide of one or both of aluminum and hafnium, which are insulating materials. As an insulator containing an oxide of one or both of aluminum and hafnium, it is preferable to use aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), or the like. When the insulator 222 is formed using such a material, the insulator 222 functions as a layer that suppresses the release of oxygen from the oxide 230 and the intrusion of impurities such as hydrogen from the periphery of the transistor 200 into the oxide 230.

[0123] Alternatively, for example, aluminum oxide, bismuth oxide, germanium oxide, niobium oxide, silicon oxide, titanium oxide, tungsten oxide, yttrium oxide, or zirconium oxide may be added to these insulators. Alternatively, these insulators may be nitrided. Silicon oxide, silicon oxynitride, or silicon nitride may be stacked on the above insulators.

[0124] The insulator 222 may be made of, for example, aluminum oxide, hafnium oxide, tantalum oxide, zirconium oxide, lead zirconate titanate (PZT), strontium titanate (SrTiO 3 ) or (Ba,Sr)TiO 3 Insulators containing so-called high-k materials such as (BST) may be used in a single layer or a multilayer. As transistors become smaller and more highly integrated, problems such as leakage current may occur due to the thinning of the gate insulator. By using a high-k material for the insulator that functions as the gate insulator, it is possible to reduce the gate potential during transistor operation while maintaining the physical film thickness.

[0125] The insulator 222 and the insulator 224 may have a laminated structure of two or more layers. In this case, the laminated structure is not limited to being made of the same material, and may be made of different materials.

[0126] Furthermore, the oxide 243 (oxide 243a and oxide 243b) may be disposed between the oxide 230b and the conductor 242 (conductor 242a and conductor 242b) functioning as a source electrode or a drain electrode. Since the conductor 242 and the oxide 230 are not in contact with each other, it is possible to prevent the conductor 242 from absorbing oxygen from the oxide 230. In other words, by preventing the oxidation of the conductor 242, it is possible to prevent a decrease in the conductivity of the conductor 242. Therefore, it is preferable that the oxide 243 has a function of suppressing the oxidation of the conductor 242.

[0127] Therefore, it is preferable that the oxide 243 has a function of suppressing oxygen permeation. By disposing the oxide 243 having a function of suppressing oxygen permeation between the conductor 242 functioning as a source electrode or a drain electrode and the oxide 230b, the electrical resistance between the conductor 242 and the oxide 230b can be reduced, which is preferable. With such a structure, the electrical characteristics and reliability of the transistor 200 can be improved.

[0128] A metal oxide having element M may be used as the oxide 243. In particular, the element M may be aluminum, gallium, yttrium, or tin. The oxide 243 preferably has a higher concentration of element M than the oxide 230b. Gallium oxide may be used as the oxide 243. A metal oxide such as In-M-Zn oxide may be used as the oxide 243. Specifically, in the metal oxide used for the oxide 243, the atomic ratio of element M to In is preferably greater than the atomic ratio of element M to In in the metal oxide used for the oxide 230b. The film thickness of the oxide 243 is preferably 0.5 nm or more and 5 nm or less, and more preferably 1 nm or more and 3 nm or less. The oxide 243 is preferably crystalline. When the oxide 243 is crystalline, the release of oxygen in the oxide 230 can be suitably suppressed. For example, if the oxide 243 has a crystal structure such as a hexagonal crystal structure, the release of oxygen in the oxide 230 may be suppressed.

[0129] Incidentally, the oxide 243 does not necessarily have to be provided. In that case, when the conductor 242 (conductor 242a and conductor 242b) comes into contact with the oxide 230, oxygen in the oxide 230 may diffuse into the conductor 242, and the conductor 242 may be oxidized. When the conductor 242 is oxidized, the conductivity of the conductor 242 is likely to decrease. The diffusion of oxygen in the oxide 230 into the conductor 242 can be rephrased as the conductor 242 absorbing the oxygen in the oxide 230.

[0130] Furthermore, oxygen in the oxide 230 may diffuse into the conductor 242 (conductor 242a and conductor 242b), forming a foreign layer between the conductor 242a and the oxide 230b and between the conductor 242b and the oxide 230b. Since the foreign layer contains more oxygen than the conductor 242, the foreign layer is presumed to have insulating properties. In this case, the three-layer structure of the conductor 242, the foreign layer, and the oxide 230b can be regarded as a three-layer structure made of a metal-insulator-semiconductor, and may be called a MIS (Metal-Insulator-Semiconductor) structure or a diode junction structure mainly based on the MIS structure.

[0131] In addition, the above-mentioned different layer is not limited to being formed between the conductor 242 and the oxide 230b. For example, the different layer may be formed between the conductor 242 and the oxide 230c, between the conductor 242 and the oxide 230b, and between the conductor 242 and the oxide 230c.

[0132] A conductor 242 (conductor 242a and conductor 242b) functioning as a source electrode and a drain electrode is provided over the oxide 243. The thickness of the conductor 242 is, for example, 1 nm or more and 50 nm or less, preferably 2 nm or more and 25 nm or less.

[0133] As the conductor 242, it is preferable to use a metal element selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, and lanthanum, or an alloy containing the above-mentioned metal elements as a component, or an alloy combining the above-mentioned metal elements. For example, it is preferable to use tantalum nitride, titanium nitride, tungsten, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, oxides containing lanthanum and nickel, etc. In addition, tantalum nitride, titanium nitride, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, and oxides containing lanthanum and nickel are preferable because they are conductive materials that are difficult to oxidize, or materials that maintain conductivity even when oxygen is absorbed.

[0134] The insulator 272 is preferably provided in contact with the top surface of the conductor 242 and functions as a barrier layer. This structure can suppress the absorption of excess oxygen contained in the insulator 280 by the conductor 242. Furthermore, suppressing oxidation of the conductor 242 can suppress an increase in contact resistance between the transistor 200 and the wiring. Thus, the transistor 200 can have favorable electrical characteristics and reliability.

[0135] Therefore, the insulator 272 preferably has a function of suppressing the diffusion of oxygen. For example, the insulator 272 preferably has a function of suppressing the diffusion of oxygen more than the insulator 280. As the insulator 272, for example, an insulator containing an oxide of one or both of aluminum and hafnium may be formed. As the insulator 272, for example, an insulator containing aluminum nitride may be used.

[0136] 1B, 1C, and 1D, the insulator 272 is in contact only with the upper surface of the conductor 242, but this embodiment is not limited to this. For example, the insulator 272 may be in contact with the upper surface and side surface of the conductor 242, the side surface of the oxide 243, the side surface of the oxide 230b, and the side surface of the oxide 230a.

[0137] The insulator 250 functions as a gate insulator. The insulator 250 is preferably disposed in contact with the upper surface of the oxide 230c. The insulator 250 can be silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide doped with fluorine, silicon oxide doped with carbon, silicon oxide doped with carbon and nitrogen, or silicon oxide having vacancies. In particular, silicon oxide and silicon oxynitride are preferable because they are stable against heat.

[0138] Like the insulator 224, the insulator 250 is preferably formed using an insulator that releases oxygen when heated. By providing an insulator that releases oxygen when heated as the insulator 250 in contact with the top surface of the oxide 230c, oxygen can be effectively supplied to the channel formation region of the oxide 230b. Also, like the insulator 224, it is preferable that the concentration of impurities such as water or hydrogen in the insulator 250 be reduced. The film thickness of the insulator 250 is preferably 1 nm or more and 20 nm or less.

[0139] A metal oxide may be provided between the insulator 250 and the conductor 260. The metal oxide preferably suppresses oxygen diffusion from the insulator 250 to the conductor 260. By providing a metal oxide that suppresses oxygen diffusion, the diffusion of oxygen from the insulator 250 to the conductor 260 is suppressed. In other words, a decrease in the amount of oxygen supplied to the oxide 230 can be suppressed. Also, oxidation of the conductor 260 by oxygen from the insulator 250 can be suppressed.

[0140] Moreover, the metal oxide may function as a part of the gate insulator. Therefore, when silicon oxide or silicon oxynitride is used for the insulator 250, it is preferable to use a metal oxide that is a high-k material having a high relative dielectric constant. By forming the gate insulator into a laminated structure of the insulator 250 and the metal oxide, it is possible to obtain a laminated structure that is stable against heat and has a high relative dielectric constant. Therefore, it is possible to reduce the gate potential applied during transistor operation while maintaining the physical thickness of the gate insulator. Also, it is possible to reduce the equivalent oxide thickness (EOT) of the insulator that functions as the gate insulator.

[0141] Specifically, it is possible to use a metal oxide containing one or more selected from hafnium, aluminum, gallium, yttrium, zirconium, tungsten, titanium, tantalum, nickel, germanium, magnesium, etc. In particular, it is preferable to use an insulator containing an oxide of either or both of aluminum and hafnium, such as aluminum oxide, hafnium oxide, or an oxide containing aluminum and hafnium (hafnium aluminate).

[0142] Alternatively, the metal oxide may function as a part of the gate. In this case, a conductive material containing oxygen may be provided on the channel formation region side. By providing the conductive material containing oxygen on the channel formation region side, oxygen released from the conductive material is easily supplied to the channel formation region.

[0143] In particular, it is preferable to use a conductive material containing oxygen and a metal element contained in the metal oxide in which the channel is formed as a conductor functioning as a gate. The conductive material containing the metal element and nitrogen described above may also be used. Indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, and indium tin oxide with added silicon may also be used. Indium gallium zinc oxide containing nitrogen may also be used. By using such a material, hydrogen contained in the metal oxide in which the channel is formed may be captured. Or, hydrogen mixed in from an external insulator may be captured.

[0144] Although the conductor 260 is shown as having a two-layer structure in FIG. 1, it may have a single-layer structure or a laminated structure of three or more layers.

[0145] The conductor 260a is a hydrogen atom, a hydrogen molecule, a water molecule, a nitrogen atom, a nitrogen molecule, or a nitrogen oxide molecule (N 2 O, NO, NO 2 It is preferable to use a conductive material having a function of suppressing the diffusion of impurities such as copper atoms, etc., or oxygen (e.g., at least one of oxygen atoms, oxygen molecules, etc.).

[0146] Furthermore, since the conductor 260a has a function of suppressing oxygen diffusion, it is possible to suppress a decrease in conductivity due to oxidation of the conductor 260b caused by oxygen contained in the insulator 250. As a conductive material having a function of suppressing oxygen diffusion, it is preferable to use, for example, tantalum, tantalum nitride, ruthenium, or ruthenium oxide.

[0147] Moreover, it is preferable that the conductor 260b is made of a conductive material mainly composed of tungsten, copper, or aluminum. Since the conductor 260 also functions as wiring, it is preferable that a conductor having high conductivity is used. For example, a conductive material mainly composed of tungsten, copper, or aluminum can be used. The conductor 260b may have a laminated structure, for example, a laminated structure of titanium or titanium nitride and the above-mentioned conductive material.

[0148] The insulator 280 preferably includes, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon oxide doped with fluorine, silicon oxide doped with carbon, silicon oxide doped with carbon and nitrogen, or silicon oxide having vacancies. In this way, by using a silicon-based oxide as the insulator 280 and performing the above-mentioned nitriding plasma treatment, the solid-phase nitrided regions 241 and 245 can be easily formed. In particular, silicon oxide and silicon oxynitride are preferable because they are thermally stable. In particular, materials such as silicon oxide, silicon oxynitride, and silicon oxide having vacancies are preferable because they can easily form a region containing oxygen that is desorbed by heating. The insulator 280 may also have a structure in which the above-mentioned materials are stacked, for example, a structure in which a silicon oxynitride film formed by a CVD method is stacked on a silicon oxide film formed by a sputtering method. Silicon nitride may also be stacked on top of the silicon oxide film.

[0149] It is preferable that the concentration of impurities such as water or hydrogen is reduced in the insulator 280. In addition, the upper surface of the insulator 280 may be flattened.

[0150] In addition, in FIG. 1B, FIG. 1C, and FIG. 1D, the region 245 is formed near the interface between the insulator 280 and the insulator 283, but this embodiment is not limited to this. For example, in the case where the hydrogen atmosphere is not excessively generated during the formation of the insulator 283, the region 245 may not be formed in the insulator 280. Similarly, the region 245 may not be formed for the insulators 224 and 216. In this case, instead of forming the region 245, it is preferable to form an insulating film having high hydrogen barrier properties similar to the insulator 272, etc., by covering the insulators 216, 222, 224, 280, and 282. As such an insulating film having high hydrogen barrier properties, for example, a silicon nitride film or a silicon nitride oxide film may be used. When a silicon nitride film is used, the film may be formed by the PEALD method or the PECVD method using the gas in which the hydrogen atoms are reduced or removed as described above. When the PEALD method is used, nitrogen radicals obtained by plasmatizing nitrogen gas may be used as the reactant.

[0151] The insulators 282 and 283 preferably function as barrier insulating films that suppress impurities such as water or hydrogen from entering the insulator 280 from above. The insulators 282 and 283 preferably function as barrier insulating films that suppress oxygen transmission. The insulators 282 and 283 may be made of, for example, aluminum oxide, silicon nitride, or silicon nitride oxide. For example, the insulator 282 may be made of aluminum oxide, which has a high barrier property against oxygen, and the insulator 283 may be made of silicon nitride or silicon nitride oxide, which has a high barrier property against hydrogen.

[0152] It is preferable to provide an insulator 274 functioning as an interlayer film over the insulator 283. Like the insulator 224, the insulator 274 preferably has a reduced concentration of impurities such as water or hydrogen.

[0153] The conductor 240a and the conductor 240b are preferably made of a conductive material mainly composed of tungsten, copper, or aluminum. The conductor 240a and the conductor 240b may have a laminated structure. Although the conductor 240a and the conductor 240b are circular in top view in FIG. 1A, this is not limiting. For example, the conductor 240a and the conductor 240b may be substantially circular such as an ellipse, polygonal such as a rectangle, or polygonal such as a rectangle with rounded corners in top view.

[0154] Furthermore, when the conductor 240 has a layered structure, it is preferable to use a conductive material having a function of suppressing the permeation of impurities such as water or hydrogen, and oxygen, for the conductor in contact with the region 241. For example, it is preferable to use tantalum, tantalum nitride, titanium, titanium nitride, ruthenium, or ruthenium oxide. Furthermore, the conductive material having a function of suppressing the permeation of impurities such as water or hydrogen, and oxygen, may be used in a single layer or a layered structure. By using the conductive material, it is possible to further reduce impurities such as water or hydrogen diffusing from the insulator 280 and the like from being mixed into the oxide 230 through the conductors 240a and 240b. It is also possible to prevent oxygen added to the insulator 280 from being absorbed by the conductors 240a and 240b. In addition, since the region 241 has a high barrier property against oxygen, it is possible to further reduce the absorption of oxygen by the conductors 240a and 240b.

[0155] Conductors 246 (conductors 246a and 246b) may be disposed in contact with the upper surface of conductor 240a and the upper surface of conductor 240b to function as wiring. Conductor 246 is preferably made of a conductive material containing tungsten, copper, or aluminum as a main component. The conductor may have a laminated structure, for example, a laminate of titanium or titanium nitride and the above-mentioned conductive material. The conductor may be formed so as to be embedded in an opening provided in an insulator.

[0156] <Materials for semiconductor devices> The following describes constituent materials that can be used in the semiconductor device.

[0157] <Substrate> The substrate on which the transistor 200 is formed may be, for example, an insulating substrate, a semiconductor substrate, or a conductive substrate. Examples of insulating substrates include a glass substrate, a quartz substrate, a sapphire substrate, a stabilized zirconia substrate (such as an yttria stabilized zirconia substrate), and a resin substrate. Examples of semiconductor substrates include a semiconductor substrate made of silicon, germanium, or a compound semiconductor substrate made of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, or gallium oxide. Examples of semiconductor substrates include a semiconductor substrate having an insulating region inside the semiconductor substrate, such as an SOI (Silicon On Insulator) substrate. Examples of conductive substrates include a graphite substrate, a metal substrate, an alloy substrate, and a conductive resin substrate. Examples of substrates include a substrate having a metal nitride, a substrate having a metal oxide, and the like. Examples of substrates include a substrate having a conductor or semiconductor provided on an insulating substrate, a substrate having a conductor or insulator provided on a semiconductor substrate, and a substrate having a semiconductor or insulator provided on a conductive substrate. Alternatively, a substrate provided with elements may be used. The elements provided on the substrate include a capacitor element, a resistor element, a switch element, a light-emitting element, a memory element, and the like.

[0158] <Insulator> Examples of the insulator include oxides, nitrides, oxynitrides, nitride oxides, metal oxides, metal oxynitrides, and metal nitride oxides, each of which has insulating properties.

[0159] For example, as transistors become smaller and more highly integrated, problems such as leakage current can occur due to thinner gate insulators. By using a high-k material for the insulator that functions as the gate insulator, it is possible to reduce the voltage required for transistor operation while maintaining the physical film thickness. On the other hand, by using a material with a low dielectric constant for the insulator that functions as the interlayer film, it is possible to reduce the parasitic capacitance that occurs between wiring. Therefore, it is best to select materials according to the function of the insulator.

[0160] Further, examples of insulators with a high relative dielectric constant include gallium oxide, hafnium oxide, zirconium oxide, oxides having aluminum and hafnium, oxynitrides having aluminum and hafnium, oxides having silicon and hafnium, oxynitrides having silicon and hafnium, and nitrides having silicon and hafnium.

[0161] Examples of insulators with a low dielectric constant include silicon oxide, silicon oxynitride, silicon nitride oxide, silicon oxide with fluorine added, silicon oxide with carbon added, silicon oxide with carbon and nitrogen added, silicon oxide with voids, or resin.

[0162] In addition, the transistor using an oxide semiconductor can have stable electrical characteristics by being surrounded by an insulator having a function of suppressing the permeation of impurities such as hydrogen and oxygen. As the insulator having a function of suppressing the permeation of impurities such as hydrogen and oxygen, for example, an insulator containing boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, or tantalum may be used in a single layer or a stacked layer. Specifically, as the insulator having a function of suppressing the permeation of impurities such as hydrogen and oxygen, a metal oxide such as aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, or tantalum oxide, or a metal nitride such as aluminum nitride, aluminum titanium nitride, titanium nitride, silicon nitride oxide, or silicon nitride can be used.

[0163] The insulator that functions as the gate insulator is preferably an insulator having a region containing oxygen that is released by heating. For example, by using a structure in which silicon oxide or silicon oxynitride having a region containing oxygen that is released by heating is in contact with the oxide 230, oxygen vacancies in the oxide 230 can be compensated for.

[0164] <Conductor> As the conductor, it is preferable to use a metal element selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, lanthanum, etc., or an alloy containing the above-mentioned metal elements as a component, or an alloy combining the above-mentioned metal elements. For example, it is preferable to use tantalum nitride, titanium nitride, tungsten, nitride containing titanium and aluminum, nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxide containing strontium and ruthenium, oxide containing lanthanum and nickel, etc. In addition, tantalum nitride, titanium nitride, nitride containing titanium and aluminum, nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxide containing strontium and ruthenium, oxide containing lanthanum and nickel are conductive materials that are difficult to oxidize, or materials that maintain conductivity even when oxygen is absorbed, so they are preferable. Furthermore, a semiconductor having high electrical conductivity, typified by polycrystalline silicon containing an impurity element such as phosphorus, or a silicide such as nickel silicide may be used.

[0165] A plurality of conductive layers formed of the above-mentioned materials may be stacked. For example, a stacked structure may be formed by combining the above-mentioned material containing a metal element and a conductive material containing oxygen. A stacked structure may be formed by combining the above-mentioned material containing a metal element and a conductive material containing nitrogen. A stacked structure may be formed by combining the above-mentioned material containing a metal element, a conductive material containing oxygen, and a conductive material containing nitrogen.

[0166] In addition, when an oxide is used for the channel formation region of a transistor, it is preferable to use a stacked structure in which a material containing the above-mentioned metal element and a conductive material containing oxygen are combined for a conductor functioning as a gate. In this case, it is preferable to provide the conductive material containing oxygen on the channel formation region side. By providing the conductive material containing oxygen on the channel formation region side, oxygen released from the conductive material is easily supplied to the channel formation region.

[0167] In particular, it is preferable to use a conductive material containing oxygen and a metal element contained in the metal oxide in which the channel is formed as a conductor functioning as a gate. The conductive material containing the metal element and nitrogen described above may also be used. For example, a conductive material containing nitrogen, such as titanium nitride or tantalum nitride, may also be used. Indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, or indium tin oxide to which silicon has been added may also be used. Indium gallium zinc oxide containing nitrogen may also be used. By using such a material, hydrogen contained in the metal oxide in which the channel is formed may be captured. Alternatively, hydrogen mixed in from an external insulator may be captured.

[0168] <Metal oxide> It is preferable to use a metal oxide that functions as an oxide semiconductor as the oxide 230. Hereinafter, metal oxides that can be used as the oxide 230 according to the present invention will be described.

[0169] The metal oxide preferably contains at least indium or zinc. In particular, it is preferable that the metal oxide contains indium and zinc. In addition to these, it is preferable that the metal oxide contains aluminum, gallium, yttrium, tin, etc. In addition, it may contain one or more elements selected from boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, etc.

[0170] Here, the case where the metal oxide is an In-M-Zn oxide having indium, element M, and zinc is considered. The element M is aluminum, gallium, yttrium, tin, or the like. Other elements applicable to the element M include boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, and the like. However, there are cases where the element M may be a combination of a plurality of the above-mentioned elements.

[0171] In this specification and the like, metal oxides containing nitrogen may also be collectively referred to as metal oxides. Furthermore, metal oxides containing nitrogen may also be referred to as metal oxynitrides.

[0172] [Metal oxide structures] Oxide semiconductors (metal oxides) are classified into single-crystal oxide semiconductors and other non-single-crystal oxide semiconductors, such as CAAC-OS, polycrystalline oxide semiconductors, nc-OS, amorphous-like oxide semiconductors (a-like OS), and amorphous oxide semiconductors.

[0173] CAAC-OS has a c-axis orientation and a distorted crystal structure in which multiple nanocrystals are connected in the ab-plane direction. The distortion refers to a portion where the lattice orientation changes between a region with a uniform lattice arrangement and a region with a different uniform lattice arrangement in the region where multiple nanocrystals are connected.

[0174] Nanocrystals are basically hexagonal, but may be non-regular hexagonal. In addition, the lattice arrangement may be pentagonal or heptagonal due to the distortion. It is difficult to confirm clear grain boundaries in CAAC-OS even near the distortion. In other words, it is found that the formation of grain boundaries is suppressed by the distortion of the lattice arrangement. This is because CAAC-OS can tolerate distortion due to the lack of dense arrangement of oxygen atoms in the ab-plane direction and the change in the bond distance between atoms due to the substitution of metal elements.

[0175] CAAC-OS also tends to have a layered crystal structure (also referred to as a layered structure) in which a layer containing indium and oxygen (hereinafter, In layer) and a layer containing element M, zinc, and oxygen (hereinafter, (M, Zn) layer) are stacked. Note that indium and element M can be substituted for each other, and when element M in an (M, Zn) layer is substituted for indium, it can also be expressed as an (In, M, Zn) layer. When indium in an In layer is substituted for element M, it can also be expressed as an (In, M) layer.

[0176] CAAC-OS is a metal oxide with high crystallinity. On the other hand, it is difficult to confirm clear crystal boundaries in CAAC-OS, so it is said that the decrease in electron mobility caused by crystal boundaries is unlikely to occur. In addition, since the crystallinity of metal oxides can be decreased by the inclusion of impurities or the generation of defects, CAAC-OS is unlikely to have impurities or defects (oxygen vacancies (V O It can be said that metal oxides with CAAC-OS have low oxygen vacancy. Therefore, metal oxides with CAAC-OS have stable physical properties. Therefore, metal oxides with CAAC-OS have high heat resistance and reliability.

[0177] The nc-OS has periodic atomic arrangement in a microscopic region (for example, a region of 1 nm to 10 nm, particularly a region of 1 nm to 3 nm). In addition, the nc-OS does not show regularity in the crystal orientation between different nanocrystals. Therefore, no orientation is seen throughout the film. Therefore, depending on the analysis method, the nc-OS may be indistinguishable from an a-like OS or an amorphous oxide semiconductor.

[0178] Indium-gallium-zinc oxide (hereinafter referred to as IGZO), a type of metal oxide containing indium, gallium, and zinc, may have a stable structure when made into the above-mentioned nanocrystals. In particular, since IGZO tends to have difficulty in crystal growth in the atmosphere, it may be structurally more stable when made into small crystals (for example, the above-mentioned nanocrystals) rather than large crystals (here, crystals of several mm or several cm).

[0179] The a-like OS is a metal oxide having a structure between the nc-OS and an amorphous oxide semiconductor. The a-like OS has a pore or low-density region. That is, the a-like OS has lower crystallinity than the nc-OS and CAAC-OS.

[0180] Oxide semiconductors (metal oxides) have a variety of structures and each structure has different characteristics. The oxide semiconductor of one embodiment of the present invention may include two or more of an amorphous oxide semiconductor, a polycrystalline oxide semiconductor, an a-like OS, an nc-OS, and a CAAC-OS.

[0181] Note that in the semiconductor device of one embodiment of the present invention, the structure of the oxide semiconductor (metal oxide) is not particularly limited; however, it is preferable that the oxide semiconductor have crystallinity. For example, the oxide 230 can have a CAAC-OS structure, and the oxide 243 can have a hexagonal crystal structure. When the oxide 230 and the oxide 243 have the above crystal structures, a highly reliable semiconductor device can be obtained. Furthermore, the oxide 230a, the oxide 230c, and the oxide 243 can have approximately the same composition.

[0182] [impurities] Here, the influence of each impurity in the metal oxide will be described.

[0183] Furthermore, when an alkali metal or alkaline earth metal is contained in a metal oxide, defect levels may be formed and carriers may be generated. Therefore, a transistor using a metal oxide containing an alkali metal or alkaline earth metal in a channel formation region is likely to have normally-on characteristics. For this reason, it is preferable to reduce the concentration of the alkali metal or alkaline earth metal in the metal oxide. Specifically, the concentration of the alkali metal or alkaline earth metal in the metal oxide (concentration obtained by SIMS) is reduced to 1×10 18 atoms / cm 3 Less than or equal to 2×10 16 atoms / cm 3 To the following:

[0184] In addition, hydrogen contained in the metal oxide may react with oxygen bonded to metal atoms to form water, forming oxygen vacancies. Hydrogen may enter the oxygen vacancies, generating electrons that serve as carriers. In addition, some of the hydrogen may bond with oxygen bonded to metal atoms to generate electrons that serve as carriers. Therefore, a transistor using a metal oxide that contains hydrogen is likely to have normally-on characteristics. For this reason, it is preferable to reduce hydrogen in the metal oxide as much as possible.

[0185] It is preferable to use a highly crystalline thin film as the metal oxide used as the semiconductor of the transistor. By using the thin film, the stability or reliability of the transistor can be improved. For example, the thin film may be a thin film of a single crystal metal oxide or a thin film of a polycrystalline metal oxide. However, a high temperature or laser heating process is required to form a thin film of a single crystal metal oxide or a thin film of a polycrystalline metal oxide on a substrate. This increases the cost of the manufacturing process and also reduces the throughput.

[0186] <Method for manufacturing semiconductor device> Next, a manufacturing method of a semiconductor device having the transistor 200 according to the present invention shown in FIG. 1 will be described with reference to FIGS. 2 to 14. In addition, A in each of FIGS. 2 to 14 shows a top view. In addition, B in each of FIGS. 2 to 14 is a cross-sectional view corresponding to a portion indicated by a dashed line A1-A2 in A, and is also a cross-sectional view in the channel length direction of the transistor 200. In addition, C in each of FIGS. 2 to 14 is a cross-sectional view corresponding to a portion indicated by a dashed line A3-A4 in A, and is also a cross-sectional view in the channel width direction of the transistor 200. In addition, D in each of FIGS. 2 to 14 is a cross-sectional view corresponding to a portion indicated by a dashed line A5-A6 in A. Note that in the top view A in each of FIGS. 2 to 14, some elements are omitted for clarity.

[0187] First, a substrate (not shown) is prepared, and the insulator 212 is formed on the substrate. The insulator 212 can be formed by sputtering, chemical vapor deposition (CVD), molecular beam epitaxy (MBE), pulsed laser deposition (PLD), atomic layer deposition (ALD), or the like.

[0188] CVD methods can be classified into plasma enhanced CVD (PECVD), which uses plasma, thermal CVD (TCVD), which uses heat, and photo CVD (Photo CVD), which uses light. They can also be divided into metal CVD (MCVD) and metal organic CVD (MOCVD), depending on the source gas used. They can also be divided into atmospheric pressure CVD (APCVD), which deposits films under atmospheric pressure, and low pressure CVD (LPCVD), which deposits films under reduced pressure below atmospheric pressure, depending on the pressure used during film formation.

[0189] The plasma CVD method can obtain a high-quality film at a relatively low temperature. Moreover, the thermal CVD method is a film formation method that can reduce plasma damage to the object to be processed because it does not use plasma. For example, wiring, electrodes, elements (transistors, capacitive elements, etc.) included in a semiconductor device may be charged up by receiving electric charge from plasma. At this time, the wiring, electrodes, elements, etc. included in the semiconductor device may be destroyed by the accumulated electric charge. On the other hand, in the case of the thermal CVD method that does not use plasma, such plasma damage does not occur, so the yield of the semiconductor device can be increased. Furthermore, in the thermal CVD method, plasma damage does not occur during film formation, so a film with few defects can be obtained.

[0190] As the ALD method, a thermal ALD method in which a reaction between a precursor and a reactant is carried out using only thermal energy, a plasma enhanced ALD method in which a plasma excited reactant is used, or the like can be used.

[0191] The ALD method utilizes the self-regulating nature of atoms to deposit atoms one layer at a time, and thus has the following advantages: extremely thin films can be formed; films can be formed on structures with high aspect ratios; films can be formed with fewer defects such as pinholes; films can be formed with excellent coverage; and films can be formed at low temperatures. In the PEALD method, the use of plasma can be preferable because it allows films to be formed at lower temperatures. Note that some precursors used in the ALD method contain impurities such as carbon. For this reason, films formed by the ALD method may contain more impurities such as carbon than films formed by other film formation methods. Note that the amount of impurities can be quantified using X-ray photoelectron spectroscopy (XPS).

[0192] The CVD method and the ALD method are different from the film formation method in which particles emitted from a target or the like are deposited, and are film formation methods in which a film is formed by a reaction on the surface of a workpiece. Therefore, they are film formation methods that are not easily affected by the shape of the workpiece and have good step coverage. In particular, the ALD method has excellent step coverage and excellent thickness uniformity, so it is suitable for coating the surface of an opening with a high aspect ratio. However, since the ALD method has a relatively slow film formation speed, it may be preferable to use it in combination with other film formation methods such as the CVD method, which has a fast film formation speed.

[0193] In the CVD method and the ALD method, the composition of the film obtained can be controlled by the flow rate ratio of the raw material gases. For example, in the CVD method and the ALD method, a film of any composition can be formed by changing the flow rate ratio of the raw material gases. In addition, for example, in the CVD method and the ALD method, a film whose composition changes continuously can be formed by changing the flow rate ratio of the raw material gases while forming the film. When forming a film while changing the flow rate ratio of the raw material gases, the time required for film formation can be shortened compared to the case of forming a film using multiple film formation chambers because no time is required for transportation and pressure adjustment. Therefore, the productivity of semiconductor devices can be increased in some cases.

[0194] In this embodiment, silicon nitride is formed as the insulator 212 by a CVD method. In this manner, by using an insulator such as silicon nitride through which copper does not easily permeate as the insulator 212, even if a metal that easily diffuses, such as copper, is used for a conductor in a layer (not shown) below the insulator 212, the metal can be prevented from diffusing into the upper layer through the insulator 212. Furthermore, by using an insulator such as silicon nitride through which impurities such as water or hydrogen do not easily permeate, the diffusion of impurities such as water or hydrogen from the layer below the insulator 212 can be prevented.

[0195] Next, the insulator 214 is deposited over the insulator 212. The insulator 214 can be deposited by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. In this embodiment, aluminum oxide is used as the insulator 214.

[0196] Next, the insulator 216 is deposited over the insulator 214. The insulator 216 can be deposited by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. In this embodiment, silicon oxide or silicon oxynitride is used as the insulator 216. The insulator 216 is preferably deposited by a deposition method using a gas in which hydrogen atoms are reduced or removed as described above. This allows the hydrogen concentration in the insulator 216 to be reduced.

[0197] Next, an opening is formed in the insulator 216, reaching the insulator 214. The opening may be, for example, a groove or a slit. The opening may be an area where an opening is formed. The opening may be formed by wet etching, but dry etching is preferable for fine processing. For the insulator 214, it is preferable to select an insulator that functions as an etching stopper film when etching the insulator 216 to form a groove. For example, when a silicon oxide film or a silicon oxynitride film is used for the insulator 216 that forms the groove, the insulator 214 may be a silicon nitride film, an aluminum oxide film, or a hafnium oxide film.

[0198] After the opening is formed, a conductive film that becomes the conductor 205a is formed. The conductive film preferably contains a conductor that has a function of suppressing oxygen permeation. For example, tantalum nitride, tungsten nitride, titanium nitride, or the like can be used. Alternatively, it can be a laminated film of tantalum, tungsten, titanium, molybdenum, aluminum, copper, or a molybdenum-tungsten alloy. The conductive film that becomes the conductor 205a can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

[0199] In this embodiment, the conductive film that becomes the conductor 205a has a multi-layer structure. First, a tantalum nitride film is formed by sputtering, and titanium nitride is laminated on the tantalum nitride. By using such a metal nitride as the lower layer of the conductor 205b, even if a metal that easily diffuses, such as copper, is used for the conductive film that becomes the conductor 205b described later, the metal can be prevented from diffusing out of the conductor 205a.

[0200] Next, a conductive film that becomes the conductor 205b is formed. The conductive film can be formed by a plating method, a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. In this embodiment, a low-resistance conductive material such as copper is formed as the conductive film that becomes the conductor 205b.

[0201] Next, a CMP process (Chemical Mechanical Polishing) is performed to remove the conductive film that will become the conductor 205a and a part of the conductive film that will become the conductor 205b, thereby exposing the insulator 216. As a result, the conductor 205a and the conductor 205b remain only in the openings. This makes it possible to form the conductor 205 with a flat upper surface. Note that the CMP process may remove a part of the insulator 216 (see FIG. 2).

[0202] In the above description, the conductor 205 is formed so as to be embedded in the opening of the insulator 216, but the present embodiment is not limited to this. For example, the conductor 205 may be formed on the insulator 214, the insulator 216 may be formed on the conductor 205, and the insulator 216 may be subjected to CMP treatment to remove a part of the insulator 216 and expose the surface of the conductor 205.

[0203] Next, the insulator 222 is formed on the insulator 216 and the conductor 205. As the insulator 222, an insulator containing one or both of an oxide of aluminum and hafnium may be formed. Note that as the insulator containing one or both of an oxide of aluminum and hafnium, it is preferable to use aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), or the like. The insulator containing one or both of an oxide of aluminum and hafnium has a barrier property against oxygen, hydrogen, and water. When the insulator 222 has a barrier property against hydrogen and water, the hydrogen and water contained in the structure provided around the transistor 200 are prevented from diffusing into the inside of the transistor 200 through the insulator 222, and the generation of oxygen vacancies in the oxide 230 can be suppressed.

[0204] The insulator 222 can be formed by sputtering, CVD, MBE, PLD, ALD, or the like.

[0205] Next, the insulator 224 is formed on the insulator 222. The insulator 224 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. In this embodiment, silicon oxide or silicon oxynitride is used as the insulator 224. The insulator 224 is preferably formed by a film formation method using a gas in which hydrogen atoms are reduced or removed as described above. This allows the hydrogen concentration of the insulator 224 to be reduced. Since the insulator 224 becomes the insulator 224 in contact with the oxide 230a in a later process, it is preferable that the hydrogen concentration be reduced in this manner.

[0206] It is preferable to carry out a heat treatment subsequently. The heat treatment may be carried out at 250°C or higher and 650°C or lower, preferably 300°C or higher and 500°C or lower, and more preferably 320°C or higher and 450°C or lower. The heat treatment is carried out in a nitrogen or inert gas atmosphere, or in an atmosphere containing 10 ppm or higher, 1% or higher, or 10% or higher of an oxidizing gas. The heat treatment may be carried out under reduced pressure. Alternatively, the heat treatment may be carried out in a nitrogen or inert gas atmosphere, and then in an atmosphere containing 10 ppm or higher, 1% or higher, or 10% or higher of an oxidizing gas to compensate for the desorbed oxygen.

[0207] In this embodiment, treatment is performed in a nitrogen atmosphere at 400° C. for 1 hour, and then treatment is continuously performed in an oxygen atmosphere at 400° C. for 1 hour. By this heat treatment, impurities such as water and hydrogen contained in the insulator 224 can be removed.

[0208] Alternatively, the heat treatment may be performed after the formation of the insulator 222. The heat treatment can be performed under the above-described heat treatment conditions.

[0209] Here, in order to form an excess oxygen region in the insulator 224, a plasma treatment including oxygen may be performed under reduced pressure. For the plasma treatment including oxygen, it is preferable to use an apparatus having a power source that generates high density plasma using, for example, microwaves. Alternatively, the apparatus may have a power source that applies high frequency such as RF to the substrate side. By using high density plasma, high density oxygen radicals can be generated, and by applying RF to the substrate side, the oxygen radicals generated by the high density plasma can be efficiently guided into the insulator 224. Alternatively, after performing a plasma treatment including an inert gas using this apparatus, a plasma treatment including oxygen may be performed to compensate for the desorbed oxygen. Note that impurities such as water and hydrogen contained in the insulator 224 can be removed by appropriately selecting the conditions of the plasma treatment. In that case, heat treatment does not need to be performed.

[0210] Here, for example, aluminum oxide may be formed on the insulator 224 by a sputtering method, and CMP may be performed until the aluminum oxide reaches the insulator 224. By performing the CMP, the surface of the insulator 224 can be planarized and smoothed. By disposing the aluminum oxide on the insulator 224 and performing CMP, it becomes easy to detect the end point of CMP. In addition, a part of the insulator 224 may be polished by CMP, and the thickness of the insulator 224 may become thin, but the thickness may be adjusted when the insulator 224 is formed. By planarizing and smoothing the surface of the insulator 224, it may be possible to prevent a deterioration in the coverage of the oxide to be formed later, and to prevent a decrease in the yield of the semiconductor device. In addition, by forming an aluminum oxide film on the insulator 224 by a sputtering method, oxygen can be added to the insulator 224, which is preferable.

[0211] Next, oxide film 230A and oxide film 230B are formed in this order on insulator 224 (see FIG. 2). It is preferable to form the oxide films in succession without exposing them to the air. By forming the films without exposing them to the air, it is possible to prevent impurities or moisture from the air environment from adhering to oxide film 230A and oxide film 230B, and it is possible to keep the vicinity of the interface between oxide film 230A and oxide film 230B clean.

[0212] The oxide film 230A and the oxide film 230B can be formed by using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

[0213] For example, when the oxide film 230A and the oxide film 230B are formed by sputtering, oxygen or a mixed gas of oxygen and a rare gas is used as the sputtering gas. By increasing the ratio of oxygen contained in the sputtering gas, the excess oxygen in the formed oxide film can be increased. In addition, when the oxide film is formed by sputtering, the above-mentioned In-M-Zn oxide target can be used.

[0214] In particular, during the formation of the oxide film 230A, some of the oxygen contained in the sputtering gas may be supplied to the insulator 224. Therefore, the ratio of oxygen contained in the sputtering gas for the oxide film 230A may be 70% or more, preferably 80% or more, and more preferably 100%.

[0215] When the oxide film 230B is formed by a sputtering method, an oxygen-deficient oxide semiconductor is formed when the ratio of oxygen contained in the sputtering gas is set to more than 30%, preferably more than 5% and less than 20%. A transistor using an oxygen-deficient oxide semiconductor for a channel formation region can have relatively high field-effect mobility. In addition, the crystallinity of the oxide film can be improved by forming the film while heating the substrate. However, one embodiment of the present invention is not limited thereto. When the oxide film 230B is formed by a sputtering method, an oxygen-excessive oxide semiconductor is formed when the ratio of oxygen contained in the sputtering gas is set to more than 30% and less than 100%, preferably more than 70% and less than 100%. A transistor using an oxygen-excessive oxide semiconductor for a channel formation region can have relatively high reliability.

[0216] In this embodiment, the oxide film 230A is formed by sputtering using a target with an atomic ratio of In:Ga:Zn=1:1:0.5 (2:2:1) or 1:3:4. The oxide film 230B is formed by sputtering using a target with an atomic ratio of In:Ga:Zn=4:2:4.1 or 1:1:1. Each oxide film may be formed according to the characteristics required for the oxide 230 by appropriately selecting the film formation conditions and atomic ratio.

[0217] Next, a heat treatment may be performed. The heat treatment conditions described above can be used for the heat treatment. The heat treatment can remove impurities such as water and hydrogen in the oxide film 230A and the oxide film 230B. In this embodiment, the treatment is performed in a nitrogen atmosphere at a temperature of 400° C. for one hour, and then the treatment is performed in an oxygen atmosphere at a temperature of 400° C. for one hour.

[0218] Next, the oxide film 243A is formed on the oxide film 230B (see FIG. 2). The oxide film 243A can be formed by sputtering, CVD, MBE, PLD, ALD, or the like. The atomic ratio of Ga to In in the oxide film 243A is preferably greater than the atomic ratio of Ga to In in the oxide film 230B. In this embodiment, the oxide film 243A is formed by sputtering using a target with an atomic ratio of In:Ga:Zn=1:3:4.

[0219] Next, a conductive film 242A is formed on the oxide film 243A (see FIG. 2). The conductive film 242A can be formed by using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

[0220] Next, the insulating film 272A is formed on the conductive film 242A (see FIG. 2). The insulating film 272A can be formed by sputtering, CVD, MBE, PLD, ALD, or the like. The insulating film 272A is preferably an insulating film having a function of suppressing oxygen permeation. For example, aluminum oxide, silicon nitride, silicon oxide, or gallium oxide may be formed by sputtering or ALD.

[0221] Next, the oxide film 230A, the oxide film 230B, the oxide film 243A, the conductive film 242A, and the insulating film 272A are processed into an island shape using lithography to form the oxide 230a, the oxide 230b, the oxide layer 243B, the conductive layer 242B, and the insulating layer 272B (see FIG. 3). Here, the oxide 230a, the oxide 230b, the oxide layer 243B, the conductive layer 242B, and the insulating layer 272B are formed so that at least a part of them overlaps with the conductor 205. In addition, this processing can be performed using a dry etching method or a wet etching method. Processing using the dry etching method is suitable for fine processing. In addition, in this process, the film thickness of the region of the insulator 224 that does not overlap with the oxide 230a may become thin.

[0222] In the lithography method, first, the resist is exposed through a mask. Next, the exposed area is removed or left using a developer to form a resist mask. Next, a conductor, a semiconductor, an insulator, or the like can be processed into a desired shape by etching through the resist mask. For example, a resist mask may be formed by exposing the resist using KrF excimer laser light, ArF excimer laser light, EUV (Extreme Ultraviolet) light, or the like. Also, a liquid immersion technique may be used in which a liquid (e.g., water) is filled between the substrate and the projection lens and exposure is performed. Also, an electron beam or an ion beam may be used instead of the light described above. When an electron beam or an ion beam is used, a mask is not required. To remove the resist mask, a dry etching process such as ashing may be performed, a wet etching process may be performed, a wet etching process may be performed after the dry etching process, or a dry etching process may be performed after the wet etching process.

[0223] Alternatively, a hard mask made of an insulator or a conductor may be used instead of the resist mask. When using a hard mask, an insulating film or a conductive film that will be a hard mask material is formed on the conductive film 242A, a resist mask is formed thereon, and the hard mask material is etched to form a hard mask with a desired shape. Etching of the conductive film 242A and the like may be performed after removing the resist mask, or may be performed while leaving the resist mask. In the latter case, the resist mask may disappear during etching. After etching of the conductive film 242A and the like, the hard mask may be removed by etching. On the other hand, if the material of the hard mask does not affect a later process or can be used in a later process, it is not necessarily necessary to remove the hard mask.

[0224] As the dry etching apparatus, a capacitively coupled plasma (CCP) etching apparatus having parallel plate electrodes can be used. The capacitively coupled plasma etching apparatus having parallel plate electrodes can be configured to apply a high frequency power supply to one of the parallel plate electrodes. Alternatively, it can be configured to apply a plurality of different high frequency power supplies to one of the parallel plate electrodes. Alternatively, it can be configured to apply a high frequency power supply of the same frequency to each of the parallel plate electrodes. Alternatively, it can be configured to apply a high frequency power supply of different frequencies to each of the parallel plate electrodes. Alternatively, a dry etching apparatus having a high density plasma source can be used. As the dry etching apparatus having a high density plasma source, for example, an inductively coupled plasma (ICP) etching apparatus or the like can be used.

[0225] Here, since the insulating layer 272B functions as a mask for the conductor layer 242B, the conductor layer 242B does not have a curved surface between the side surface and the top surface, as shown in FIGS. 3C and 3D. As a result, the conductors 242a and 242b shown in FIG. 1 have angular ends where the side surface and the top surface intersect. Since the end where the side surface and the top surface of the conductor 242 intersect is angular, the cross-sectional area of ​​the conductor 242 is larger than when the end has a curved surface. This reduces the resistance of the conductor 242, and therefore the on-current of the transistor 200 can be increased.

[0226] In addition, it is preferable that the side surfaces of the oxide 230a, the oxide 230b, the oxide layer 243B, the conductor layer 242B, and the insulator layer 272B are approximately perpendicular to the upper surface of the insulator 222. By having the side surfaces of the oxide 230a, the oxide 230b, the oxide layer 243B, the conductor layer 242B, and the insulator layer 272B be approximately perpendicular to the upper surface of the insulator 222, it is possible to reduce the area and increase the density when providing a plurality of transistors 200. However, this is not limited to the above, and a configuration may be used in which the angles formed by the side surfaces of the oxide 230a, the oxide 230b, the oxide layer 243B, the conductor layer 242B, and the insulator layer 272B and the upper surface of the insulator 222 are low.

[0227] Next, the insulator 280 is formed on the insulator 224, the oxide 230a, the oxide 230b, the oxide layer 243B, the conductor layer 242B, and the insulator layer 272B (see FIG. 4). The insulating film to be the insulator 280 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. For example, a silicon oxide film may be formed as the insulator 280 by a sputtering method, and a silicon oxide film may be formed thereon by a PEALD method or a thermal ALD method. In addition, the insulator 280 is preferably formed by a film formation method using a gas in which hydrogen atoms have been reduced or removed as described above. This allows the hydrogen concentration in the insulator 280 to be reduced.

[0228] Next, the insulator 280 is subjected to CMP processing to form the insulator 280 with a flat upper surface (see FIG. 4). Note that, similarly to the insulator 224, a film of aluminum oxide may be formed on the insulator 280 by, for example, a sputtering method, and CMP may be performed until the aluminum oxide reaches the insulator 280.

[0229] Next, high frequency waves such as microwaves or RF may be irradiated to the insulator 280, the oxide 230b, and the oxide 230a. The irradiated high frequency waves such as microwaves or RF penetrate the insulator 280, the oxide 230b, and the oxide 230a, and remove hydrogen therein. In particular, in the oxide 230a and the oxide 230b, a reaction occurs in which the bond of VoH is broken, in other words, "V O The reaction "H → Vo + H" occurs, resulting in dehydrogenation. Some of the hydrogen generated at this time combines with oxygen to form H 2 Hydrogen may be removed from the oxide 230 and the insulator 280 as O. A part of the hydrogen may be gettered to the conductor 242. In this manner, the hydrogen concentration in the insulator 280, the oxide 230b, and the oxide 230a can be reduced by irradiating with microwaves or high frequency waves such as RF. The irradiation with microwaves or high frequency waves such as RF may be performed before the CMP process.

[0230] Also, oxygen gas may be turned into plasma by microwaves or high frequency waves such as RF to form oxygen radicals. That is, plasma treatment may be performed in an atmosphere containing oxygen in the insulator 280, the oxide 230b, and the oxide 230a. Hereinafter, such treatment may be referred to as oxygen plasma treatment. Furthermore, the formed oxygen radicals can supply oxygen to the insulator 280, the oxide 230b, and the oxide 230a. Furthermore, when plasma treatment is performed in an atmosphere containing oxygen in the insulator 280, the oxide 230b, and the oxide 230a, the oxide 230 may be configured to be less susceptible to irradiation of microwaves or high frequency waves such as RF.

[0231] For the oxygen plasma treatment, it is preferable to use a microwave treatment device having a power source that generates high-density plasma using microwaves. The microwave treatment device may also have a power source that applies RF to the substrate side. By using high-density plasma, high-density oxygen radicals can be generated. By applying RF to the substrate side, oxygen ions generated by high-density plasma can be efficiently guided into the insulator 280 and the oxide 230. The oxygen plasma treatment is preferably performed under reduced pressure, with the pressure being 60 Pa or more, preferably 133 Pa or more, more preferably 200 Pa or more, and even more preferably 400 Pa or more. The oxygen flow rate ratio (O 2 / O 2 +Ar) is preferably 50% or less, and more preferably 10% to 30%. The treatment temperature is preferably 750°C or less, and more preferably 500°C or less, for example, about 400°C. After the oxygen plasma treatment, a heat treatment may be performed without exposing the substrate to the outside air. The temperature of the heat treatment may be 750°C or less, and more preferably 500°C or less.

[0232] In addition, after the oxygen plasma treatment, the nitrogen plasma treatment described above may be performed continuously without exposure to the outside air. The oxygen plasma treatment and the nitrogen plasma treatment may be performed in the same chamber, or in different chambers of a multi-chamber type processing apparatus. This allows a solid-phase nitrided region similar to the region 241 to be formed on the surface of the insulator 280, so that the insulator 280, whose hydrogen concentration has been reduced by the oxygen plasma treatment, is prevented from being newly mixed with hydrogen.

[0233] Next, a part of the insulator 280, a part of the insulator layer 272B, the conductor layer 242B, and a part of the oxide layer 243B are processed to form an opening that reaches the oxide 230b (see FIG. 5). The opening is preferably formed so as to overlap the conductor 205. By forming the opening, the oxide 243a, the oxide 243b, the conductor 242a, the conductor 242b, the insulator 272a, and the insulator 272b are formed.

[0234] A part of the insulator 280, a part of the insulator layer 272B, the conductor layer 242B, and a part of the oxide layer 243B can be processed by dry etching or wet etching. Processing by the dry etching method is suitable for fine processing. The processing may be performed under different conditions. For example, a part of the insulator 280 may be processed by dry etching, a part of the insulator layer 272B may be processed by wet etching, and the oxide layer 243B and a part of the conductor layer 242B may be processed by dry etching.

[0235] By carrying out the conventional dry etching and other processes, impurities resulting from etching gases and the like may adhere to or diffuse into the surface or interior of the oxide 230a, the oxide 230b, etc. Examples of impurities include fluorine and chlorine.

[0236] In order to remove the above-mentioned impurities, cleaning is performed. The cleaning method includes wet cleaning using a cleaning solution, plasma treatment using plasma, and cleaning by heat treatment, and the above cleaning methods may be appropriately combined.

[0237] As the wet cleaning, a cleaning process may be performed using an aqueous solution of oxalic acid, phosphoric acid, ammonia water, hydrofluoric acid, or the like diluted with carbonated water or pure water, or ultrasonic cleaning using pure water or carbonated water may be performed.

[0238] After the etching or cleaning, a heat treatment may be performed. The heat treatment may be performed, for example, at 100° C. or higher and 450° C. or lower, more preferably 350° C. or higher and 400° C. or lower. The heat treatment is performed in an atmosphere of nitrogen gas or an inert gas, or an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas. For example, the heat treatment is preferably performed in an oxygen atmosphere. This supplies oxygen to the oxide 230a and the oxide 230b, thereby reducing the oxygen deficiency V OThe heat treatment may be performed under reduced pressure. Alternatively, after the heat treatment in an oxygen atmosphere, the heat treatment may be performed in a nitrogen atmosphere without exposure to the air.

[0239] Next, the oxide film 230C is formed (see FIG. 6). A heat treatment may be performed before the oxide film 230C is formed. The heat treatment is preferably performed under reduced pressure and the oxide film 230C is formed continuously without exposure to the atmosphere. The heat treatment is preferably performed in an atmosphere containing oxygen. By performing such a treatment, the moisture and hydrogen adsorbed on the surface of the oxide 230b can be removed, and the moisture concentration and hydrogen concentration in the oxide 230a and the oxide 230b can be further reduced. The temperature of the heat treatment is preferably 100° C. or more and 400° C. or less, more preferably 150° C. or more and 350° C. or less. In this embodiment, the heat treatment is performed at a temperature of 200° C. under reduced pressure.

[0240] Here, it is preferable that the oxide film 230C is provided so as to contact at least a part of the side surface of the oxide 230a, a part of the side surface and a part of the top surface of the oxide 230b, a part of the side surface of the oxide 243, a part of the side surface of the conductor 242, a part of the side surface of the insulator 272, and a side surface of the insulator 280. By being surrounded by the oxide 243, the insulator 272, and the oxide film 230C, the decrease in conductivity of the conductor 242 due to oxidation in the subsequent steps can be suppressed.

[0241] The oxide film 230C can be formed by sputtering, CVD, MBE, PLD, ALD, or the like. The atomic ratio of Ga to In in the oxide film 230C is preferably greater than the atomic ratio of Ga to In in the oxide film 230B. In this embodiment, the oxide film 230C is formed by sputtering using a target with an atomic ratio of In:Ga:Zn=1:3:4.

[0242] The oxide film 230C may be a laminated film. For example, a film may be formed by sputtering using a target having an atomic ratio of In:Ga:Zn=4:2:4.1, and then a film may be formed by sputtering using a target having an atomic ratio of In:Ga:Zn=1:3:4.

[0243] When the oxide film 230C is formed, some of the oxygen contained in the sputtering gas may be supplied to the oxide 230a and the oxide 230b. Alternatively, when the oxide film 230C is formed, some of the oxygen contained in the sputtering gas may be supplied to the insulator 280. Therefore, the proportion of oxygen contained in the sputtering gas for the oxide film 230C may be 70% or more, preferably 80% or more, and more preferably 100%.

[0244] Next, a heat treatment may be performed. The heat treatment may be performed under reduced pressure, and the insulating film 250A may be formed continuously without exposure to the atmosphere. By performing the heat treatment, moisture and hydrogen adsorbed on the surface of the oxide film 230C can be removed, and the moisture concentration and hydrogen concentration in the oxide 230a, the oxide 230b, and the oxide film 230C can be further reduced. The temperature of the heat treatment is preferably 100° C. or more and 400° C. or less. In this embodiment, the temperature of the heat treatment is 200° C.

[0245] Next, the insulating film 250A is formed on the oxide film 230C (see FIG. 6). The insulating film 250A can be formed by sputtering, CVD, MBE, PLD, ALD, or the like. The insulating film 250A is preferably formed by a film formation method using a gas in which hydrogen atoms are reduced or removed as described above. This allows the hydrogen concentration of the insulating film 250A to be reduced. Since the insulating film 250A becomes the insulator 250 that contacts the oxide 230c in a later process, it is preferable that the hydrogen concentration is reduced in this way. After the insulating film 250A is formed, irradiation with microwaves or high frequency waves such as RF or oxygen plasma treatment, which were performed after the insulator 280 was formed, may be performed.

[0246] Next, the conductive film 260Aa and the conductive film 260Ab are formed (see FIG. 7). The conductive film 260Aa and the conductive film 260Ab can be formed by using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. For example, it is preferable to use a CVD method. In this embodiment, the conductive film 260Aa is formed by using the ALD method, and the conductive film 260Ab is formed by using the CVD method.

[0247] Next, the oxide film 230C, the insulating film 250A, the conductive film 260Aa and the conductive film 260Ab are polished by CMP until the insulator 280 is exposed, thereby forming the oxide 230c, the insulator 250 and the conductor 260 (the conductor 260a and the conductor 260b) (see FIG. 8).

[0248] Next, heat treatment may be performed. In this embodiment, the treatment is performed in a nitrogen atmosphere at a temperature of 400° C. for 1 hour. The heat treatment can reduce the moisture and hydrogen concentrations in the insulators 250 and 280. Note that after the heat treatment, the insulator 282 may be formed without exposure to the air.

[0249] Next, the insulator 282 is formed on the conductor 260, the oxide 230c, the insulator 250, and the insulator 280. The insulator 282 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like (see FIG. 9). As the insulating film to be the insulator 282, for example, it is preferable to form an aluminum oxide film by a sputtering method. By forming the insulator 282 in an atmosphere containing oxygen by using a sputtering method, oxygen can be added to the insulator 280 while forming the film. At this time, it is preferable to form the insulator 280 while heating the substrate. Furthermore, it is preferable to form the insulator 282 in contact with the upper surface of the conductor 260, because this can suppress the oxygen contained in the insulator 280 from being absorbed by the conductor 260 in a subsequent heat treatment.

[0250] Next, a part of the insulator 282, a part of the insulator 280, a part of the insulator 224, a part of the insulator 222, a part of the insulator 216, and a part of the insulator 214 are processed to form an opening that reaches the insulator 212 (see FIG. 10). The opening may be formed so as to surround the transistor 200. Alternatively, the opening may be formed so as to surround a plurality of transistors 200. Thus, in the opening, a part of the side surface of the insulator 282, a part of the side surface of the insulator 280, a part of the side surface of the insulator 224, a part of the side surface of the insulator 222, a part of the side surface of the insulator 216, and a part of the side surface of the insulator 214 are exposed.

[0251] A dry etching method or a wet etching method can be used for processing a part of the insulator 282, a part of the insulator 280, a part of the insulator 224, a part of the insulator 222, a part of the insulator 216, and a part of the insulator 214. Processing by the dry etching method is suitable for fine processing. In addition, the processing may be performed under different conditions.

[0252] Next, nitrogen plasma treatment is performed to form regions 245 having a higher nitrogen concentration than other regions of insulators 280, 224, and 216 on the exposed side surfaces of insulators 280, 224, and 216 (see FIG. 10). In the nitrogen plasma treatment, nitrogen gas is turned into plasma using microwaves or high frequency waves such as RF, and the nitrogen plasma is allowed to act to cause solid-phase nitridation near the side surfaces of insulators 280, 224, and 216. In the nitrogen plasma treatment, it is preferable to introduce a rare gas such as argon in addition to nitrogen gas.

[0253] As the nitrogen plasma treatment, for example, a microwave treatment is preferably performed in which nitrogen gas is converted into plasma by microwaves. In the microwave treatment in an atmosphere containing nitrogen, it is preferable to generate high-density plasma using a microwave treatment apparatus described later. The microwave treatment apparatus may have a power source for applying RF to the substrate side. In an atmosphere containing nitrogen, high-density nitrogen radicals can be generated by using high-density plasma. Furthermore, by applying RF to the substrate side, ions generated by high-density plasma can be efficiently guided into the insulator 280, the insulator 224, and the insulator 216. Furthermore, the microwave treatment in an atmosphere containing nitrogen is preferably performed under reduced pressure, with the pressure being 400 Pa or less, preferably 200 Pa or less, more preferably 60 Pa or less, and even more preferably 12 Pa or less. Furthermore, the nitrogen flow rate ratio (N 2 / N 2 +Ar) is preferably 50% or less, and more preferably 10% to 30%. The treatment temperature may be, for example, about 400°C.

[0254] At this time, high frequency waves such as microwaves or RF may be irradiated to the insulator 280. The irradiated microwaves or high frequency waves such as RF may penetrate the insulator 280, the oxide 230b, and the oxide 230a, and may remove hydrogen therein. For example, in the oxide 230a and the oxide 230b, a reaction occurs in which the bond of VoH is broken, in other words, "V O The reaction "H → Vo + H" occurs, resulting in dehydrogenation. Some of the hydrogen generated at this time combines with oxygen to form H 2 As O, hydrogen may be removed from the oxide 230 and the insulator 280. Also, some of the hydrogen may be gettered to the conductor 242.

[0255] Although not shown, the nitrogen plasma treatment that forms region 245 may also solid-phase nitride the side surfaces of the openings in insulators 214, 222, and 282.

[0256] Next, the insulator 283 is formed to cover the insulators 282, 280, 224, 222, 216, and 214 (see FIG. 11). As shown in FIG. 11, the insulator 283 contacts the insulator 212 at the bottom of the opening. That is, the upper and side surfaces of the transistor 200 are surrounded by the insulator 283, and the lower surface is surrounded by the insulator 212. In this manner, by surrounding the transistor 200 with the insulator 283 and the insulator 212, which have high barrier properties, it is possible to prevent moisture and hydrogen from entering from the outside.

[0257] The insulator 283 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. As described above, by forming the region 245 on the side surfaces of the insulator 280, the insulator 224, and the insulator 216 before forming the insulator 283, even if a film formation method that generates a large amount of hydrogen in a chamber is used for forming the insulator 283, it is possible to reduce the intrusion of the hydrogen into the insulator 280, the insulator 224, and the insulator 216. Therefore, a film formation method with good step coverage such as a PECVD method can be used for forming the insulator 283, so that the insulator 283 can be formed on the steps of the insulator 280 and the like without forming step discontinuities or pinholes.

[0258] Next, a heat treatment may be performed. In this embodiment, the treatment is performed in a nitrogen atmosphere at a temperature of 400° C. for one hour. This heat treatment allows the oxygen added by the formation of the insulator 282 to diffuse into the insulator 280, and further to be supplied to the oxide 230a and the oxide 230b via the oxide 230c. In this way, by performing an oxygen-adding treatment on the oxide 230, oxygen vacancies in the oxide 230 (oxide 230b) can be repaired by oxygen, in other words, the reaction of "Vo+O→null" can be promoted. Furthermore, the supplied oxygen reacts with the hydrogen remaining in the oxide 230 to convert the hydrogen into H 2 O. This causes the hydrogen remaining in the oxide 230 to recombine with the oxygen vacancies and form V. OIt is possible to suppress the formation of H. Note that the heat treatment may be performed after the insulator 282 is formed, not only after the insulator 283 is formed.

[0259] Next, the insulator 274 is deposited on the insulator 283 (see FIG. 12). The insulator 274 can be deposited by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. The insulator 274 is preferably deposited by a deposition method using a gas in which hydrogen atoms are reduced or removed as described above. This allows the hydrogen concentration in the insulator 274 to be reduced.

[0260] Next, the insulator 274 is subjected to a CMP process to form an insulator 274 with a flat upper surface (see FIG. 12).

[0261] Next, an opening 255a reaching the conductor 242a is formed in the insulators 272a, 280, 282, 283, and 274, and an opening 255b reaching the conductor 242b is formed in the insulators 272b, 280, 282, 283, and 274 (see FIG. 12). The openings may be formed by using a lithography method. Note that, although the openings 255a and 255b are circular in top view in FIG. 12A, the openings 255a and 255b are not limited to this. For example, the openings 255a and 255b may be substantially circular such as an ellipse, polygonal such as a rectangle, or polygonal such as a rectangle with rounded corners in top view.

[0262] Next, nitrogen plasma treatment is performed to form a region 241 having a higher nitrogen concentration than other regions of the insulator 274 and the insulator 280 on the exposed upper surface and side surface of the insulator 274 and the insulator 280 (see FIG. 13). A region 241a is formed on the inner wall of the opening 255a of the insulator 280, a region 241b is formed on the inner wall of the opening 255b of the insulator 280, and a region 241c is formed on the upper surface of the insulator 274, the inner wall of the opening 255a, and the inner wall of the opening 255b. In the nitrogen plasma treatment, nitrogen gas is turned into plasma using microwaves or high frequency waves such as RF, and the nitrogen plasma is allowed to act on the exposed upper surface vicinity and side surface vicinity of the insulator 274 and the insulator 280 to perform solid-phase nitridation. In the nitrogen plasma treatment, it is preferable to introduce a rare gas such as argon in addition to nitrogen gas.

[0263] As the nitrogen plasma treatment, for example, a microwave treatment is preferably performed in which nitrogen gas is converted into plasma by microwaves. In the microwave treatment in an atmosphere containing nitrogen, it is preferable to generate high-density plasma using a microwave treatment apparatus described later. The microwave treatment apparatus may have a power source that applies RF to the substrate side. In an atmosphere containing nitrogen, high-density nitrogen radicals can be generated by using high-density plasma. By applying RF to the substrate side, ions generated by high-density plasma can be efficiently guided into the insulator 274 and the insulator 280. In addition, the microwave treatment in an atmosphere containing nitrogen is preferably performed under reduced pressure, with the pressure being 400 Pa or less, preferably 200 Pa or less, more preferably 60 Pa or less, and even more preferably 12 Pa or less. In addition, the nitrogen flow rate ratio (N 2 / N 2 +Ar) is preferably 50% or less, and more preferably 10% to 30%. The treatment temperature may be, for example, about 400°C.

[0264] The above-described region 241 has a function of suppressing the diffusion of hydrogen (for example, at least one of hydrogen atoms, hydrogen molecules, and the like). When such a region 241 is formed between the conductor 240 and the insulator 274 and the insulator 280, it is possible to reduce the amount of hydrogen contained in the insulator 274 and the insulator 280 from being mixed into the conductor 240. Therefore, it is possible to reduce the amount of hydrogen diffusing from the conductor 240 to the conductor 242 and the oxide 230. By using the oxide 230 in which impurities such as hydrogen are sufficiently reduced for the channel formation region of the transistor 200, it is possible to achieve normally-off characteristics, thereby achieving stable electrical characteristics and improved reliability.

[0265] During the nitrogen plasma treatment, high frequency waves such as microwaves or RF may be irradiated to the insulator 274 and the insulator 280. The irradiated high frequency waves such as microwaves or RF may penetrate the insulator 274, the insulator 280, the oxide 230b, and the oxide 230a, and may remove hydrogen therein.

[0266] In addition, in the nitrogen plasma treatment, the conductor 242a is exposed at the bottom of the opening 255a, and the conductor 242b is exposed at the bottom of the opening 255b. As a result, a region 244a having a higher nitrogen concentration than the other regions of the conductor 242a is formed near the surface of the conductor 242a, and a region 244b having a higher nitrogen concentration than the other regions of the conductor 242b is formed near the surface of the conductor 242b. It is preferable that the region 244 has a resistivity approximately equal to that of the other regions of the conductor 242. Therefore, the region 244 does not significantly hinder the conductivity of the conductor 242 that functions as a source electrode or a drain electrode. Therefore, even if the region 241 is formed by the nitrogen plasma treatment, there is no need to perform a special post-treatment on the conductor 242.

[0267] When an insulating film corresponding to region 241 is formed by using a CVD method or the like, the insulating film is also formed on conductor 242, and therefore a process of removing only the insulating film at the bottom of openings 255a and 255b is required. However, as shown in the present embodiment, by using nitrogen plasma treatment to form region 241 functioning as a barrier film only on the side surfaces of openings 255a and 255b, an extra removal process is not required, and the productivity of the semiconductor device can be improved.

[0268] Also, although not shown, the nitrogen plasma treatment that forms region 241 may cause solid-phase nitridation not only of region 244 but also of the sides of the openings in insulators 272a, 272b, 282, and 283.

[0269] Next, a conductive film that becomes the conductor 240a and the conductor 240b is formed. The conductive film that becomes the conductor 240a and the conductor 240b is preferably a laminated structure including a conductor that has a function of suppressing the permeation of impurities such as water and hydrogen. For example, it can be a laminated structure of tantalum nitride, titanium nitride, or the like, and tungsten, molybdenum, copper, or the like. The conductive film that becomes the conductor 240 can be formed by using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

[0270] Next, a CMP process is performed to remove a portion of the conductive film that will become the conductors 240a and 240b, and expose the upper surface of the insulator 274 (which may also be referred to as region 241c). As a result, the conductive film remains only in the openings 255a and 255b, and thus the conductors 240a and 240b with flat upper surfaces can be formed (see FIG. 14). Note that the CMP process removes a portion of the upper surface of the insulator 274, and in some cases the region 241c formed near the upper surface of the insulator 274 is also removed at the same time.

[0271] Next, a conductive film is formed to become the conductor 246. The conductive film to become the conductor 246 can be formed by sputtering, CVD, MBE, PLD, ALD, or the like.

[0272] Next, the conductive film that becomes the conductor 246 is processed by lithography to form the conductor 246a in contact with the top surface of the conductor 240a and the conductor 246b in contact with the top surface of the conductor 240b (see FIG. 1).

[0273] Through the above steps, a semiconductor device including the transistor 200 illustrated in Fig. 1 can be manufactured. As illustrated in Fig. 2 to Fig. 14, the transistor 200 can be manufactured by the method for manufacturing a semiconductor device described in this embodiment.

[0274] <Microwave processing equipment> A microwave processing apparatus that can be used in the above-described method for manufacturing a semiconductor device will be described below.

[0275] First, the configuration of a manufacturing apparatus that reduces the inclusion of impurities during the manufacture of semiconductor devices and the like will be described with reference to FIGS.

[0276] 15 is a schematic top view of a single-wafer multi-chamber manufacturing apparatus 2700. The manufacturing apparatus 2700 includes an atmosphere-side substrate supply chamber 2701 having a cassette port 2761 for accommodating a substrate and an alignment port 2762 for aligning the substrate, an atmosphere-side substrate transfer chamber 2702 for transferring the substrate from the atmosphere-side substrate supply chamber 2701, a load lock chamber 2703a for loading the substrate and for reducing the pressure in the chamber from atmospheric pressure or from reduced pressure to atmospheric pressure, an unload lock chamber 2703b for unloading the substrate and for switching the pressure in the chamber from reduced pressure to atmospheric pressure or from atmospheric pressure to reduced pressure, a transfer chamber 2704 for transferring the substrate in a vacuum, a chamber 2706a, a chamber 2706b, a chamber 2706c, and a chamber 2706d.

[0277] The atmospheric side substrate transfer chamber 2702 is connected to a load lock chamber 2703a and an unload lock chamber 2703b, the load lock chamber 2703a and the unload lock chamber 2703b are connected to a transfer chamber 2704, and the transfer chamber 2704 is connected to a chamber 2706a, a chamber 2706b, a chamber 2706c, and a chamber 2706d.

[0278] A gate valve GV is provided at the connection between each chamber, and each chamber can be independently maintained in a vacuum state, except for the atmosphere side substrate supply chamber 2701 and the atmosphere side substrate transfer chamber 2702. A transfer robot 2763a is provided in the atmosphere side substrate transfer chamber 2702, and a transfer robot 2763b is provided in the transfer chamber 2704. Substrates can be transferred within the manufacturing apparatus 2700 by the transfer robot 2763a and the transfer robot 2763b.

[0279] The back pressure (total pressure) of the transfer chamber 2704 and each chamber is, for example, 1×10 -4 Pa or less, preferably 3×10 -5 Pa or less, more preferably 1×10 -5 The partial pressure of gas molecules (atoms) with a mass-to-charge ratio (m / z) of 18 in the transfer chamber 2704 and each chamber is, for example, 3×10 -5 Pa or less, preferably 1×10 -5 Pa or less, more preferably 3×10 -6 The partial pressure of gas molecules (atoms) with m / z of 28 in the transfer chamber 2704 and each chamber is, for example, 3×10 -5 Pa or less, preferably 1×10 -5 Pa or less, more preferably 3×10 -6 The partial pressure of gas molecules (atoms) with m / z of 44 in the transfer chamber 2704 and each chamber is, for example, 3×10 -5 Pa or less, preferably 1×10 -5 Pa or less, more preferably 3×10 -6 Pa or less.

[0280] The total pressure and partial pressure in the transfer chamber 2704 and each chamber can be measured using a mass spectrometer. For example, a quadrupole mass spectrometer (also called Q-mass) Qulee CGM-051 manufactured by ULVAC, Inc. may be used.

[0281] In addition, it is desirable that the transfer chamber 2704 and each chamber have a configuration with little external or internal leakage. For example, the leak rate of the transfer chamber 2704 and each chamber is 3×10 -6 Pa·m 3 / s or less, preferably 1×10 -6 Pa·m 3 / s or less. For example, the leak rate of a gas molecule (atom) with m / z of 18 is 1×10 -7 Pa·m 3 / s or less, preferably 3×10 -8 Pa·m 3 / s or less. For example, the leak rate of a gas molecule (atom) with m / z of 28 is 1×10 -5 Pa·m 3 / s or less, preferably 1×10 -6 Pa·m 3 / s or less. For example, the leak rate of a gas molecule (atom) with m / z of 44 is 3×10 -6 Pa·m 3 / s or less, preferably 1×10 -6 Pa·m 3 / s or less.

[0282] The leak rate can be derived from the total pressure and partial pressure measured using the mass spectrometer mentioned above. The leak rate depends on external and internal leaks. External leaks are gases that flow in from outside the vacuum system due to tiny holes or poor seals. Internal leaks are caused by leaks from partitions such as valves in the vacuum system and gases released from internal components. To keep the leak rate below the above values, measures must be taken to prevent both external and internal leaks.

[0283] For example, the opening and closing parts of the transfer chamber 2704 and each chamber may be sealed with a metal gasket. The metal gasket is preferably made of a metal coated with iron fluoride, aluminum oxide, or chromium oxide. Metal gaskets have higher adhesion than O-rings and can reduce external leakage. In addition, by using a passivated metal coated with iron fluoride, aluminum oxide, chromium oxide, or the like, the release of gas containing impurities from the metal gasket is suppressed, and internal leakage can be reduced.

[0284] In addition, aluminum, chromium, titanium, zirconium, nickel, or vanadium, which emits less gas containing impurities, is used as the members constituting the manufacturing apparatus 2700. The above-mentioned members may be coated with an alloy containing iron, chromium, nickel, etc. The alloy containing iron, chromium, nickel, etc. is rigid, heat-resistant, and suitable for processing. Here, if the surface irregularities of the members are reduced by polishing or the like in order to reduce the surface area, the amount of emitted gas can be reduced.

[0285] Alternatively, the components of the manufacturing apparatus 2700 described above may be coated with iron fluoride, aluminum oxide, chromium oxide, or the like.

[0286] It is preferable that the components of the manufacturing apparatus 2700 are constructed solely from metal as much as possible. For example, even if a viewing window made of quartz or the like is installed, it is advisable to thinly coat the surface with iron fluoride, aluminum oxide, chromium oxide, or the like to suppress outgassing.

[0287] The adsorbed matter present in the transfer chamber 2704 and each chamber does not affect the pressure of the transfer chamber 2704 and each chamber because it is adsorbed to the inner walls, but it causes gas emission when the transfer chamber 2704 and each chamber are evacuated. Therefore, although there is no correlation between the leak rate and the exhaust speed, it is important to use a pump with high exhaust capacity to desorb as much of the adsorbed matter present in the transfer chamber 2704 and each chamber and evacuate them in advance. In addition, the transfer chamber 2704 and each chamber may be baked to promote the desorption of the adsorbed matter. By baking, the desorption speed of the adsorbed matter can be increased by about 10 times. Baking may be performed at 100°C or higher and 450°C or lower. At this time, if the adsorbed matter is removed while introducing an inert gas into the transfer chamber 2704 and each chamber, the desorption speed of water and the like that is difficult to desorb by only exhausting can be further increased. In addition, the desorption speed of the adsorbed matter can be further increased by heating the inert gas introduced to the same temperature as the baking temperature. Here, it is preferable to use a rare gas as the inert gas.

[0288] Alternatively, it is preferable to increase the pressure in the transfer chamber 2704 and each chamber by introducing an inert gas such as a heated rare gas or oxygen, and then evacuate the transfer chamber 2704 and each chamber again after a certain time has passed. By introducing a heated gas, it is possible to desorb adsorbed substances in the transfer chamber 2704 and each chamber, and it is possible to reduce impurities present in the transfer chamber 2704 and each chamber. It is effective to repeat this process 2 to 30 times, preferably 5 to 15 times. Specifically, by introducing an inert gas or oxygen having a temperature of 40° C. to 400° C., preferably 50° C. to 200° C., the pressure in the transfer chamber 2704 and each chamber is set to 0.1 Pa to 10 kPa, preferably 1 Pa to 1 kPa, and more preferably 5 Pa to 100 Pa, and the period for maintaining the pressure is 1 minute to 300 minutes, preferably 5 minutes to 120 minutes. Thereafter, the transfer chamber 2704 and each chamber are evacuated for a period of 5 to 300 minutes, preferably 10 to 120 minutes.

[0289] Next, chamber 2706b and chamber 2706c will be described with reference to the schematic cross-sectional view shown in FIG.

[0290] The chamber 2706b and the chamber 2706c are chambers capable of performing microwave processing on an object to be processed, for example. The chamber 2706b and the chamber 2706c differ only in the atmosphere during microwave processing. Since the other configurations are common, they will be described together below.

[0291] The chamber 2706b and the chamber 2706c have a slot antenna plate 2808, a dielectric plate 2809, a substrate holder 2812, and an exhaust port 2819. In addition, outside the chamber 2706b and the chamber 2706c, a gas supply source 2801, a valve 2802, a high frequency generator 2803, a waveguide 2804, a mode converter 2805, a gas pipe 2806, a waveguide 2807, a matching box 2815, a high frequency power supply 2816, a vacuum pump 2817, and a valve 2818 are provided.

[0292] The high frequency generator 2803 is connected to the mode converter 2805 via a waveguide 2804. The mode converter 2805 is connected to a slot antenna plate 2808 via a waveguide 2807. The slot antenna plate 2808 is disposed in contact with a dielectric plate 2809. The gas supply source 2801 is connected to the mode converter 2805 via a valve 2802. Gas is sent to the chambers 2706b and 2706c through a gas pipe 2806 passing through the mode converter 2805, the waveguide 2807, and the dielectric plate 2809. The vacuum pump 2817 has a function of exhausting gas and the like from the chambers 2706b and 2706c via the valve 281 and the exhaust port 2819. The high frequency power supply 2816 is connected to the substrate holder 2812 via a matching box 2815.

[0293] The substrate holder 2812 has a function of holding the substrate 2811. For example, the substrate holder 2812 has a function of electrostatically or mechanically chucking the substrate 2811. The substrate holder 2812 also has a function as an electrode to which power is supplied from a high frequency power supply 2816. The substrate holder 2812 also has an internal heating mechanism 2813 and has a function of heating the substrate 2811.

[0294] For example, a dry pump, a mechanical booster pump, an ion pump, a titanium sublimation pump, a cryopump, or a turbo molecular pump can be used as the vacuum pump 2817. A cryotrap may be used in addition to the vacuum pump 2827. The use of a cryopump and a cryotrap is particularly preferable because water can be efficiently exhausted.

[0295] The heating mechanism 2813 may be, for example, a heating mechanism that uses a resistance heating element or the like for heating. Alternatively, it may be a heating mechanism that uses heat conduction or heat radiation from a medium such as a heated gas for heating. For example, RTA (Rapid Thermal Annealing) such as GRTA (Gas Rapid Thermal Annealing) or LRTA (Lamp Rapid Thermal Annealing) can be used. GRTA performs heating processing using high-temperature gas. An inert gas is used as the gas.

[0296] The gas supply source 2801 may be connected to a refiner via a mass flow controller. It is preferable to use a gas with a dew point of -80° C. or less, preferably -100° C. or less. For example, oxygen gas, nitrogen gas, and rare gas (such as argon gas) may be used.

[0297] The dielectric plate 2809 may be made of, for example, silicon oxide (quartz), aluminum oxide (alumina), or yttrium oxide (yttria). A separate protective layer may be formed on the surface of the dielectric plate 2809. The protective layer may be made of magnesium oxide, titanium oxide, chromium oxide, zirconium oxide, hafnium oxide, tantalum oxide, silicon oxide, aluminum oxide, or yttrium oxide. The dielectric plate 2809 is exposed to a particularly high-density region of the high-density plasma 2810 described later, and thus damage to the dielectric plate 2809 can be mitigated by providing a protective layer. As a result, an increase in particles during processing can be suppressed.

[0298] The high frequency generator 2803 has a function of generating microwaves of, for example, 0.3 GHz to 3.0 GHz, 0.7 GHz to 1.1 GHz, or 2.2 GHz to 2.8 GHz. The microwaves generated by the high frequency generator 2803 are transmitted to the mode converter 2805 via the waveguide 2804. In the mode converter 2805, the microwaves transmitted as TE mode are converted to TEM mode. Then, the microwaves are transmitted to the slot antenna plate 2808 via the waveguide 2807. The slot antenna plate 2808 is provided with a plurality of slot holes, and the microwaves pass through the slot holes and the dielectric plate 2809. Then, an electric field is generated below the dielectric plate 2809, and a high density plasma 2810 can be generated. In the high density plasma 2810, ions and radicals according to the gas species supplied from the gas supply source 2801 exist. For example, oxygen radicals or nitrogen radicals exist.

[0299] At this time, the film on the substrate 2811 can be modified by the ions and radicals generated by the high density plasma 2810. It may be preferable to apply a bias to the substrate 2811 side using a high frequency power supply 2816. For the high frequency power supply 2816, an RF (Radio Frequency) power supply with a frequency of, for example, 13.56 MHz or 27.12 MHz may be used. By applying a bias to the substrate side, the ions in the high density plasma 2810 can be efficiently delivered to the depths of the openings of the film on the substrate 2811.

[0300] For example, in chamber 2706b, oxygen can be introduced from gas supply source 2801 to perform oxygen radical treatment using high-density plasma 2810, and in chamber 2706c, nitrogen can be introduced from gas supply source 2801 to perform nitrogen radical treatment using high-density plasma 2810.

[0301] Next, chamber 2706a and chamber 2706d will be described with reference to the schematic cross-sectional view shown in FIG.

[0302] The chamber 2706a and the chamber 2706d are chambers capable of irradiating the object to be treated with electromagnetic waves, for example. The only difference between the chamber 2706a and the chamber 2706d is the type of electromagnetic waves. As the other configurations are largely common, they will be described together below.

[0303] The chamber 2706a and the chamber 2706d each include one or more lamps 2820, a substrate holder 2825, a gas inlet 2823, and an exhaust port 2830. In addition, a gas supply source 2821, a valve 2822, a vacuum pump 2827, and a valve 2829 are provided outside the chamber 2706a and the chamber 2706d.

[0304] The gas supply source 2821 is connected to a gas inlet 2823 via a valve 2822. The vacuum pump 2828 is connected to an exhaust port 2830 via a valve 2829. The lamp 2820 is disposed facing a substrate holder 2825. The substrate holder 2825 has a function of holding a substrate 2824. The substrate holder 2825 also has an internal heating mechanism 2826 and has a function of heating the substrate 2824.

[0305] A light source having a function of emitting electromagnetic waves such as visible light or ultraviolet light may be used as the lamp 2820. For example, a light source having a function of emitting electromagnetic waves having a peak wavelength of 10 nm to 2500 nm, 500 nm to 2000 nm, or 40 nm to 340 nm may be used.

[0306] For example, lamp 2820 may be a light source such as a halogen lamp, a metal halide lamp, a xenon arc lamp, a carbon arc lamp, a high pressure sodium lamp, or a high pressure mercury lamp.

[0307] For example, the electromagnetic waves emitted from the lamps 2820 can be partially or completely absorbed by the substrate 2824 to modify a film on the substrate 2824. For example, defects can be generated or reduced, or impurities can be removed. If the process is performed while the substrate 2824 is heated, defects can be generated or reduced, or impurities can be removed efficiently.

[0308] Alternatively, for example, the substrate holder 2825 may be heated by electromagnetic waves emitted from the lamps 2820, thereby heating the substrate 2824. In that case, the substrate holder 2825 does not need to have the heating mechanism 2826 inside.

[0309] For the vacuum pump 2827, refer to the description of the vacuum pump 2817. For the heating mechanism 2826, refer to the description of the heating mechanism 2813. For the gas supply source 2821, refer to the description of the gas supply source 2801.

[0310] By using the above manufacturing apparatus, it is possible to modify the film while suppressing the inclusion of impurities in the processed object.

[0311] <Modifications of the semiconductor device> 18 to 21 will be used to describe an example of a semiconductor device including a transistor 200 according to one embodiment of the present invention, which is different from that described above in <Structural example of a semiconductor device>. Note that in the semiconductor device illustrated in FIGS. 18 to 21, structures having the same functions as those of the semiconductor device (see FIG. 1) illustrated in <Structural example of a semiconductor device> are denoted by the same reference numerals. Note that in this section, the materials described in detail in <Structural example of a semiconductor device> can be used as the materials for forming the transistor 200.

[0312] <Modification 1 of the semiconductor device> FIG. 18A is a top view of a semiconductor device having a transistor 200. FIG. 18B is a cross-sectional view corresponding to a portion indicated by a dashed line A1-A2 in FIG. 18A, and is also a cross-sectional view in the channel length direction of the transistor 200. FIG. 18C is a cross-sectional view corresponding to a portion indicated by a dashed line A3-A4 in FIG. 18A, and is also a cross-sectional view in the channel width direction of the transistor 200. FIG. 18D is a cross-sectional view corresponding to a portion indicated by a dashed line A5-A6 in FIG. In the top view of FIG. 18A, some elements are omitted for clarity.

[0313] 18 differs from the transistor 200 shown in FIG. 1 in that the insulators 224, 280, and 282 are patterned, and the insulators 283 and 222 seal them. That is, the insulator 283 contacts the top and side surfaces of the insulator 282, the side surfaces of the insulator 280, the side surfaces of the insulator 224, and the top surface of the insulator 222. Therefore, the region 245 is also formed in the insulators 280 and 224. Therefore, the insulators 224, 280, and 282, including the oxide 230, are isolated from the outside by the insulators 222 and 283.

[0314] By using such a structure, it is not necessary to pattern the insulators 214, 216, and 222, and therefore the process can be simplified and the productivity of the semiconductor device can be improved.

[0315] <Modification 2 of Semiconductor Device> FIG. 19A is a top view of a semiconductor device having a transistor 200. FIG. 19B is a cross-sectional view corresponding to the portion indicated by the dashed line A1-A2 in FIG. 19A, and is also a cross-sectional view in the channel length direction of the transistor 200. FIG. 19C is a cross-sectional view corresponding to the portion indicated by the dashed line A3-A4 in FIG. 19A, and is also a cross-sectional view in the channel width direction of the transistor 200. FIG. 19D is a cross-sectional view corresponding to the portion indicated by the dashed line A5-A6 in FIG. 19A. Note that in the top view of FIG. 19A, some elements are omitted for clarity.

[0316] Transistor 200 shown in Figure 19 differs from transistor 200 shown in Figure 1 in that insulator 214, insulator 216, insulator 222, insulator 224, insulator 280, and insulator 282 are not patterned. In transistor 200 shown in Figure 19, insulator 280, insulator 224, and insulator 216 are not patterned, and therefore region 245 is not formed.

[0317] By using such a structure, there is no need to pattern insulator 214, insulator 216, insulator 222, insulator 224, insulator 280, and insulator 282, thereby simplifying the process and improving the productivity of the semiconductor device.

[0318] Moreover, instead of the insulator 272a and the insulator 272b, an insulator 272 is provided to cover the insulator 224, the oxide 230a, the oxide 230b, the oxide 243, and the conductor 242. The insulator 272 can be an insulating film similar to the insulators 272a and the insulator 272b.

[0319] The upper surface and side surface of the conductor 242, the side surface of the oxide 243, the side surface of the oxide 230a, and the side surface of the oxide 230b are covered with the insulator 272, so that the diffusion of impurities such as hydrogen and water and oxygen from the side surface of the conductor 242 and the upper surface of the conductor 242 to the conductor 242 can be suppressed. In addition, the lower surface of the conductor 242 is in contact with the oxide 243, and the oxygen of the oxide 230b is blocked by the oxide 243 and is suppressed from diffusing to the conductor 242. Therefore, the diffusion of oxygen from the periphery of the conductor 242 to the conductor 242 can be suppressed, so that the oxidation of the conductor 242 can be suppressed. In addition, the diffusion of impurities such as hydrogen and water from the side surface of the oxide 230a and the side surface of the oxide 230b to the oxides 230a and 230b can be suppressed.

[0320] <Modification 3 of the semiconductor device> FIG. 20A is a top view of a semiconductor device having a transistor 200. FIG. 20B is a cross-sectional view corresponding to a portion indicated by a dashed line A1-A2 in FIG. 20A, and is also a cross-sectional view in the channel length direction of the transistor 200. FIG. 20C is a cross-sectional view corresponding to a portion indicated by a dashed line A3-A4 in FIG. 20A, and is also a cross-sectional view in the channel width direction of the transistor 200. FIG. 20D is a cross-sectional view corresponding to a portion indicated by a dashed line A5-A6 in FIG. 20A. Note that in the top view of FIG. 20A, some elements are omitted for clarity.

[0321] 1 in that the insulators 214, 216, 222, 224, and 280 are patterned, and the insulators 282 and 222 seal them. That is, the insulator 282 contacts the top surface and side surface of the insulator 280, the side surface of the insulator 224, the side surface of the insulator 222, the side surface of the insulator 216, the side surface of the insulator 214, and the top surface of the insulator 212. Here, the insulator 283 is formed on the insulator 282.

[0322] When manufacturing the transistor 200 shown in FIG. 20, after the formation of the conductor 260 and the like shown in FIG. 8, the process shown in FIG. 10 is performed without forming the insulator 282, and a part of the insulator 280, a part of the insulator 224, a part of the insulator 222, a part of the insulator 216, and a part of the insulator 214 are processed to form an opening reaching the insulator 212. Furthermore, nitrogen plasma treatment is performed to form a region 245 having a higher nitrogen concentration than the other regions of the insulator 280, the insulator 224, and the insulator 216 on the exposed top surface and side surface of the insulator 280, the exposed side surface of the insulator 224, and the exposed side surface of the insulator 216. Next, the insulator 283 is formed to cover the insulator 280, the insulator 224, the insulator 222, the insulator 216, and the insulator 214. Subsequent processes may be performed similarly to the processes shown in FIG. 11 and subsequent figures.

[0323] 1, in the transistor 200 shown in Fig. 20, a region 245 is also formed on the top surface of the insulator 280. The insulators 214, 216, 222, 224, and 280, which include the oxide 230 and the like, are isolated from the outside by the insulators 212, 282, and 283.

[0324] <Modification 4 of the semiconductor device> 21A and 21B show a configuration in which a plurality of transistors 200_1 to 200_n are encapsulated by an insulator 283 and an insulator 212. Note that although the transistors 200_1 to 200_n appear to be aligned in the channel length direction in Fig. 21A and 21B, this is not limited thereto. The transistors 200_1 to 200_n may be aligned in the channel width direction, may be arranged in a matrix, or may be arranged without any regularity.

[0325] As shown in FIG. 21A, a portion where the insulator 283 and the insulator 212 contact each other (hereinafter, may be referred to as a sealing portion 265) is formed outside the plurality of transistors 200_1 to 200_n. The sealing portion 265 is formed so as to surround the plurality of transistors 200_1 to 200_n. With such a structure, the plurality of transistors 200_1 to 200_n can be wrapped with the insulator 283 and the insulator 212. That is, the four side surfaces and the upper portion of the plurality of transistors 200_1 to 200_n can be wrapped with the insulator 283, and the lower portion can be wrapped with the insulator 212. In this manner, a plurality of transistor groups surrounded by the sealing portion 265 are provided on the substrate.

[0326] A region 245 is formed on the side surfaces of the insulators 280 , 224 , and 216 near the encapsulating portion 265 , and the transistor group surrounded by the encapsulating portion 265 is also surrounded by the region 245 .

[0327] Also, dicing lines (which may be called scribe lines, division lines, or cutting lines) may be provided overlapping the sealing portion 265. Since the substrate is divided along the dicing lines, a group of transistors surrounded by the sealing portion 265 is taken out as one chip.

[0328] 21A shows an example in which the plurality of transistors 200_1 to 200_n are surrounded by one sealing portion 265, but the present invention is not limited to this. As shown in Fig. 21B, the plurality of transistors 200_1 to 200_n may be surrounded by a plurality of sealing portions. In Fig. 21B, the plurality of transistors 200_1 to 200_n are surrounded by a sealing portion 265a and further surrounded by an outer sealing portion 265b.

[0329] In this manner, by using a structure in which the multiple transistors 200_1 to 200_n are surrounded by multiple sealing portions, the number of areas in contact with the insulator 283 and the insulator 212 increases, thereby improving the adhesion between the insulator 283 and the insulator 212. This makes it possible to more reliably seal the multiple transistors 200_1 to 200_n.

[0330] In this case, a dicing line may be provided so as to overlap sealing portion 265a or sealing portion 265b, or a dicing line may be provided between sealing portion 265a and sealing portion 265b.

[0331] According to one embodiment of the present invention, a semiconductor device having good electrical characteristics can be provided. According to one embodiment of the present invention, a semiconductor device having normally-off electrical characteristics can be provided. According to one embodiment of the present invention, a semiconductor device with high reliability can be provided. According to one embodiment of the present invention, a semiconductor device with large on-current can be provided. According to one embodiment of the present invention, a semiconductor device with high frequency characteristics can be provided. According to one embodiment of the present invention, a semiconductor device that can be miniaturized or highly integrated can be provided. According to one embodiment of the present invention, a semiconductor device with small off-current can be provided. According to one embodiment of the present invention, a semiconductor device with reduced power consumption can be provided. According to one embodiment of the present invention, a semiconductor device with high productivity can be provided.

[0332] (Embodiment 2) In this embodiment, one mode of a semiconductor device will be described with reference to FIGS.

[0333] [Storage device 1] 22 shows an example of a semiconductor device (memory device) using a capacitor according to one embodiment of the present invention. In the semiconductor device according to one embodiment of the present invention, a transistor 200 is provided above a transistor 300, and a capacitor 100 is provided above the transistors 300 and 200. Note that the transistor 200 described in the above embodiment can be used as the transistor 200.

[0334] The transistor 200 is a transistor in which a channel is formed in a semiconductor layer including an oxide semiconductor. Since the off-state current of the transistor 200 is small, stored data can be retained for a long time by using the transistor 200 in a memory device. In other words, a refresh operation is not required or the frequency of the refresh operation is extremely low, so that the power consumption of the memory device can be sufficiently reduced.

[0335] 22, a wiring 1001 is electrically connected to a source of a transistor 300, and a wiring 1002 is electrically connected to a drain of the transistor 300. A wiring 1003 is electrically connected to one of a source and a drain of the transistor 200, a wiring 1004 is electrically connected to a first gate of the transistor 200, and a wiring 1006 is electrically connected to a second gate of the transistor 200. The gate of the transistor 300 and the other of the source and drain of the transistor 200 are electrically connected to one electrode of the capacitor 100, and a wiring 1005 is electrically connected to the other electrode of the capacitor 100.

[0336] Moreover, the memory device shown in FIG. 22 can be arranged in a matrix to form a memory cell array.

[0337] <Transistor 300> The transistor 300 is provided on a substrate 311 and includes a conductor 316 functioning as a gate, an insulator 315 functioning as a gate insulator, a semiconductor region 313 formed of a part of the substrate 311, and a low-resistance region 314a and a low-resistance region 314b functioning as a source region or a drain region. The transistor 300 may be either a p-channel type or an n-channel type.

[0338] Here, in the transistor 300 shown in FIG. 22, a semiconductor region 313 (a part of a substrate 311) in which a channel is formed has a convex shape. A conductor 316 is provided so as to cover the side and top surface of the semiconductor region 313 via an insulator 315. Note that the conductor 316 may be made of a material that adjusts the work function. Such a transistor 300 is also called a FIN type transistor because it uses a convex portion of a semiconductor substrate. Note that an insulator that contacts the upper portion of the convex portion and functions as a mask for forming the convex portion may be provided. Note that, although a case where a convex portion is formed by processing a part of a semiconductor substrate has been shown here, a semiconductor film having a convex shape may be formed by processing an SOI substrate.

[0339] Note that the transistor 300 illustrated in FIG. 22 is just an example, and the structure is not limited thereto. An appropriate transistor may be used depending on the circuit configuration and driving method.

[0340] <Capacitive element 100> The capacitor 100 is provided above the transistor 200. The capacitor 100 has a conductor 110 functioning as a first electrode, a conductor 120 functioning as a second electrode, and an insulator 130 functioning as a dielectric.

[0341] For example, the conductor 112 and the conductor 110 over the conductor 246 can be formed at the same time. Note that the conductor 112 functions as a plug or a wiring electrically connected to the capacitor 100, the transistor 200, or the transistor 300.

[0342] 22, the conductor 112 and the conductor 110 are shown to have a single-layer structure, but are not limited to this configuration and may have a laminated structure of two or more layers. For example, a conductor having barrier properties and a conductor having high adhesion to the conductor having high conductivity may be formed between a conductor having barrier properties and a conductor having high conductivity.

[0343] The insulator 130 can be made of, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, aluminum oxynitride, aluminum nitride oxide, aluminum nitride, hafnium oxide, hafnium oxynitride, hafnium nitride oxide, hafnium nitride, or the like, and can be provided as a stacked layer or a single layer.

[0344] For example, it is preferable to use a laminated structure of a material with high dielectric strength, such as silicon oxynitride, and a high dielectric constant (high-k) material for the insulator 130. With this configuration, the capacitance element 100 can ensure sufficient capacitance by having an insulator with high dielectric constant (high-k), and the capacitance element 100 can have improved dielectric strength by having an insulator with high dielectric strength, thereby suppressing electrostatic breakdown of the capacitance element 100.

[0345] Examples of high dielectric constant (high-k) material insulators (materials with a high relative dielectric constant) include gallium oxide, hafnium oxide, zirconium oxide, oxides having aluminum and hafnium, oxynitrides having aluminum and hafnium, oxides having silicon and hafnium, oxynitrides having silicon and hafnium, and nitrides having silicon and hafnium.

[0346] On the other hand, materials with high dielectric strength (materials with low dielectric constant) include silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide with added fluorine, silicon oxide with added carbon, silicon oxide with added carbon and nitrogen, silicon oxide or resin with voids, etc.

[0347] <Wiring layer> Between each structure, a wiring layer having an interlayer film, wiring, plugs, etc. may be provided. Also, a plurality of wiring layers may be provided according to the design. Here, a conductor having a function as a plug or wiring may be collectively given the same symbol as a plurality of structures. Also, in this specification, the wiring and the plug electrically connected to the wiring may be integrated. That is, there are cases where a part of the conductor functions as the wiring, and cases where a part of the conductor functions as the plug.

[0348] For example, an insulator 320, an insulator 322, an insulator 324, and an insulator 326 are stacked in this order as an interlayer film over the transistor 300. A conductor 328, a conductor 330, and the like that are electrically connected to the capacitor 100 or the transistor 200 are embedded in the insulator 320, the insulator 322, the insulator 324, and the insulator 326. The conductor 328 and the conductor 330 function as plugs or wirings.

[0349] The insulator functioning as an interlayer film may also function as a planarizing film that covers the uneven shape underneath. For example, the top surface of the insulator 322 may be planarized by a planarization process using a chemical mechanical polishing (CMP) method or the like to enhance flatness.

[0350] A wiring layer may be provided on the insulator 326 and the conductor 330. For example, in Fig. 22, an insulator 350, an insulator 352, and an insulator 354 are stacked in this order. Furthermore, a conductor 356 is formed in the insulator 350, the insulator 352, and the insulator 354. The conductor 356 functions as a plug or a wiring.

[0351] Similarly, a conductor 218, a conductor constituting the transistor 200 (conductor 205), and the like are embedded in the insulators 210, 212, 214, and 216. Note that the conductor 218 functions as a plug or wiring electrically connected to the capacitor 100 or the transistor 300. Furthermore, an insulator 150 is provided over the conductor 120 and the insulator 130.

[0352] Here, it is preferable that region 217, which is a region that has been solid-phase nitrided like region 241 shown in the above embodiment, is formed in contact with the side surface of conductor 218. Region 217 is formed near the inner walls of openings formed in insulators 210 and 216. In other words, region 217 is provided between conductor 218 and insulators 210 and 216. Note that conductor 205 can be formed in parallel with conductor 218, and therefore region 217 may be formed in contact with the side surface of conductor 205.

[0353] Region 217 is formed near the side surfaces of insulator 210 and insulator 216, and therefore can suppress impurities such as water or hydrogen from insulator 210 or insulator 216 from being mixed into oxide 230 through conductor 218. In addition, by forming region 217, oxygen contained in insulator 210 or insulator 216 can be prevented from being absorbed by conductor 218.

[0354] Region 217 can be formed by the same method as region 241. For example, after forming an opening in which conductor 218 is to be embedded, nitrogen plasma treatment is performed to solid-phase nitride the side surfaces of insulator 210 and insulator 216 to form region 217. Note that if conductor 218 has sufficiently high oxidation resistance and the hydrogen concentration of insulator 216 and the like is sufficiently reduced, region 217 does not need to be provided.

[0355] Examples of insulators that can be used as the interlayer film include insulating oxides, nitrides, oxynitrides, nitride oxides, metal oxides, metal oxynitrides, and metal nitride oxides.

[0356] For example, by using a material with a low dielectric constant for the insulator that functions as an interlayer film, the parasitic capacitance generated between wirings can be reduced. Therefore, it is advisable to select a material according to the function of the insulator.

[0357] For example, the insulator 150, the insulator 210, the insulator 352, the insulator 354, etc. preferably have an insulator with a low relative dielectric constant. For example, the insulator preferably has silicon oxynitride, silicon nitride, silicon oxide to which fluorine has been added, silicon oxide to which carbon has been added, silicon oxide to which carbon and nitrogen have been added, silicon oxide having voids, or resin. Alternatively, the insulator preferably has a laminated structure of silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide to which fluorine has been added, silicon oxide to which carbon has been added, silicon oxide to which carbon and nitrogen has been added, or silicon oxide having voids, and resin. Silicon oxide and silicon oxynitride are thermally stable, and therefore can be combined with a resin to form a laminated structure that is thermally stable and has a low relative dielectric constant. Examples of the resin include polyester, polyolefin, polyamide (nylon, aramid, etc.), polyimide, polycarbonate, and acrylic.

[0358] Furthermore, when a transistor using an oxide semiconductor is surrounded by an insulator that has a function of suppressing the permeation of oxygen and impurities such as hydrogen, the electrical characteristics of the transistor can be stabilized. Therefore, the insulators 214, 212, and 350 can be made of insulators that have a function of suppressing the permeation of oxygen and impurities such as hydrogen.

[0359] As an insulator having a function of suppressing the permeation of impurities such as hydrogen and oxygen, for example, an insulator containing boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, or tantalum may be used in a single layer or a stacked layer. Specifically, as an insulator having a function of suppressing the permeation of impurities such as hydrogen and oxygen, metal oxides such as aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, or tantalum oxide, silicon nitride oxide, or silicon nitride may be used.

[0360] Conductors that can be used for wiring and plugs include materials containing one or more metal elements selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, etc. Also, semiconductors with high electrical conductivity, typified by polycrystalline silicon containing impurity elements such as phosphorus, and silicides such as nickel silicide may be used.

[0361] For example, the conductor 328, the conductor 330, the conductor 356, the conductor 218, the conductor 112, etc. can be formed of a single layer or a stack of conductive materials such as metal materials, alloy materials, metal nitride materials, or metal oxide materials formed from the above materials. It is preferable to use a high melting point material such as tungsten or molybdenum that has both heat resistance and conductivity, and it is preferable to use tungsten. Alternatively, it is preferable to form the conductor from a low resistance conductive material such as aluminum or copper. By using a low resistance conductive material, the wiring resistance can be reduced.

[0362] <Plug of Layer Including Oxide Semiconductor> As shown in the above embodiment, the region 241 is preferably formed in contact with the side surface of the conductor 240 functioning as a plug. The region 241 is formed near the inner walls of the openings formed in the insulators 224, 280, and 274. In other words, the region 241 is provided between the conductor 240 and the insulators 224, 280, and 274. Note that if the top surface of the insulator 274 is exposed when the region 241 is formed, the region 241 is also formed near the top surface of the insulator 274.

[0363] Region 241 is formed near the side surfaces of insulator 224, insulator 280, and insulator 274, and therefore can suppress impurities such as water or hydrogen from insulator 224, insulator 280, insulator 274, etc. from being mixed into oxide 230 through conductor 240. Furthermore, forming region 241 can prevent oxygen contained in insulator 224, insulator 280, and insulator 274 from being absorbed by conductor 240. Therefore, the amount of hydrogen diffusing from conductor 240 to conductor 242 and oxide 230 can be reduced.

[0364] Region 241 may be formed, for example, by forming an opening into which conductor 240 is to be embedded, and then performing nitrogen plasma treatment to solid-phase nitriding the side surfaces of insulators 224, 280, and 274.

[0365] As in the above embodiment, the transistor 200 is preferably sealed with the insulator 283 and the insulator 212. Furthermore, the region 245 is preferably formed near the interface between the insulator 216, the insulator 224, and the insulator 280 and the insulator 283. By forming the region 245 between the insulator 280, the insulator 224, and the insulator 216 and the insulator 283, it is possible to reduce the intrusion of hydrogen contained in the insulator 274 into the insulator 280, etc.

[0366] Here, the conductor 240 penetrates the insulator 283, and the conductor 218 penetrates the insulator 212, but as described above, the region 241 is provided in contact with the conductor 240, and the region 217 is provided in contact with the conductor 218. This can also reduce hydrogen that is mixed into the inside of the insulator 283 and the insulator 212 via the conductor 240 and the conductor 218. In this way, the transistor 200 can be more reliably sealed by the insulator 283, the insulator 212, the region 241, and the region 217, and it is possible to reduce impurities such as hydrogen contained in the insulator 274, etc. from being mixed in from outside the insulator 283.

[0367] Furthermore, as described in the above embodiment, the insulators 216, 224, 280, 250, and 274 are preferably formed by a film formation method using a gas in which hydrogen atoms are reduced or removed, thereby reducing the hydrogen concentrations in the insulators 216, 224, 280, 250, and 274.

[0368] 22, conductors 240 and 218, which are vias connected to conductor 242, are disposed in insulators 216, 224, 280, and 274. As described above, by reducing the hydrogen concentrations in insulators 216, 224, 280, and 274, the amount of hydrogen diffusing into conductor 242 and oxide 230 via conductors 240 and 218 can be further reduced.

[0369] In this manner, the hydrogen concentration in the silicon-based insulating film in the vicinity of the transistor 200 can be reduced, and the hydrogen concentration in the oxide 230 can be reduced.

[0370] <Dicing line> In the following, a dicing line (sometimes called a scribe line, a dividing line, or a cutting line) that is provided when a large-area substrate is divided into individual semiconductor elements to extract multiple semiconductor devices in chip form will be described. As a dividing method, for example, first, grooves (dicing lines) for dividing the semiconductor elements are formed in the substrate, and then the substrate is cut along the dicing lines to divide (split) the substrate into multiple semiconductor devices.

[0371] 22, for example, it is preferable to design the region where the insulator 283 and the insulator 212 contact each other so as to overlap the dicing line. That is, openings are provided in the insulators 280, 224, 222, 216, and 214 near the region that will become the dicing line provided on the outer edge of the memory cell having the multiple transistors 200.

[0372] That is, the insulator 212 and the insulator 283 are in contact with each other through the openings provided in the insulators 280, 224, 222, 216, and 214. For example, the insulators 212 and 283 may be formed using the same material and the same method. By providing the insulators 212 and 283 using the same material and the same method, adhesion can be improved. For example, it is preferable to use silicon nitride.

[0373] With this structure, the transistor 200 can be enclosed by the insulator 212 and the insulator 283. The insulator 212 and the insulator 283 have a function of suppressing diffusion of oxygen, hydrogen, and water, and therefore, even if the substrate is divided into a plurality of chips by dividing the substrate into each circuit region in which the semiconductor element described in this embodiment is formed, impurities such as hydrogen or water can be prevented from entering from the side direction of the divided substrate and diffusing into the transistor 200.

[0374] This structure can prevent excess oxygen in the insulator 280 and the insulator 224 from diffusing to the outside. Therefore, the excess oxygen in the insulator 280 and the insulator 224 is efficiently supplied to the oxide in which a channel is formed in the transistor 200. The oxygen can reduce oxygen vacancies in the oxide in which a channel is formed in the transistor 200. As a result, the oxide in which a channel is formed in the transistor 200 can be an oxide semiconductor with low density of defect states and stable characteristics. That is, fluctuations in the electrical characteristics of the transistor 200 can be suppressed and reliability can be improved.

[0375] The above is a description of the configuration example. By using this configuration, in a semiconductor device including a transistor having an oxide semiconductor, a change in electrical characteristics can be suppressed and reliability can be improved. Alternatively, a transistor including an oxide semiconductor with high on-state current can be provided. Alternatively, a transistor including an oxide semiconductor with low off-state current can be provided. Alternatively, a semiconductor device with reduced power consumption can be provided.

[0376] [Storage device 2] An example of a memory device using a semiconductor device according to one embodiment of the present invention is shown in Fig. 23. The memory device shown in Fig. 23 includes a transistor 400 in addition to the semiconductor device including the transistor 200, the transistor 300, and the capacitor 100 shown in Fig. 22.

[0377] The transistor 400 can control the second gate voltage of the transistor 200. For example, the first gate and the second gate of the transistor 400 are diode-connected to the source, and the source of the transistor 400 is connected to the second gate of the transistor 200. When the second gate of the transistor 200 is held at a negative potential in this configuration, the voltage between the first gate and the source of the transistor 400 and the voltage between the second gate and the source of the transistor 400 are 0 V. In the transistor 400, since the drain current when the second gate voltage and the first gate voltage are 0 V is very small, the negative potential of the second gate of the transistor 200 can be maintained for a long time without supplying power to the transistors 200 and 400. This allows the memory device including the transistor 200 and the transistor 400 to hold stored contents for a long time.

[0378] 23, the wiring 1001 is electrically connected to the source of the transistor 300, and the wiring 1002 is electrically connected to the drain of the transistor 300. The wiring 1003 is electrically connected to one of the source and drain of the transistor 200, the wiring 1004 is electrically connected to the gate of the transistor 200, and the wiring 1006 is electrically connected to the backgate of the transistor 200. The gate of the transistor 300 and the other of the source and drain of the transistor 200 are electrically connected to one of the electrodes of the capacitor 100, and the wiring 1005 is electrically connected to the other electrode of the capacitor 100. The wiring 1007 is electrically connected to the source of the transistor 400, the wiring 1008 is electrically connected to the gate of the transistor 400, the wiring 1009 is electrically connected to the backgate of the transistor 400, and the wiring 1010 is electrically connected to the drain of the transistor 400. Here, the wiring 1006, the wiring 1007, the wiring 1008, and the wiring 1009 are electrically connected to each other.

[0379] 22, the memory device illustrated in FIG. 23 can be arranged in a matrix to form a memory cell array. Note that one transistor 400 can control the second gate voltages of the multiple transistors 200. Therefore, it is preferable to provide fewer transistors 400 than the transistors 200. In addition, the memory device illustrated in FIG. 23 can seal the transistors 200 and 400 with insulators 212 and 283, similar to the memory device illustrated in FIG. 22.

[0380] <Transistor 400> The transistor 400 is formed in the same layer as the transistor 200 and can be manufactured in parallel. The transistor 400 includes a conductor 460 (conductor 460a and conductor 460b) functioning as a first gate, a conductor 405 (conductor 405a and conductor 405b) functioning as a second gate, an insulator 222 and an insulator 450 functioning as a gate insulating layer, an oxide 430c having a channel formation region, a conductor 442a, an oxide 443a, an oxide 431a, and an oxide 431b functioning as a source, a conductor 442b, an oxide 443b, an oxide 432a, and an oxide 432b functioning as a drain, a conductor 440 (conductor 440a and conductor 440b) functioning as a plug, and an insulator 472 (insulator 472a and insulator 472b) functioning as a barrier insulating film for the conductor 442. In addition, a portion of region 241 formed in insulator 280 and insulator 274 functions as a barrier layer for conductor 440.

[0381] In the transistor 400, the conductor 405 is in the same layer as the conductor 205. The oxide 431a and the oxide 432a are in the same layer as the oxide 230a, and the oxide 431b and the oxide 432b are in the same layer as the oxide 230b. The conductor 442 is in the same layer as the conductor 242. The oxide 443 is in the same layer as the oxide 243. The oxide 430c is in the same layer as the oxide 230c. The insulator 450 is in the same layer as the insulator 250. The conductor 460 is in the same layer as the conductor 260. The conductor 440 is in the same layer as the conductor 240. The insulator 472 is in the same layer as the insulator 272.

[0382] It is noted that structures formed in the same layer can be formed at the same time. For example, the oxide 430c can be formed by processing the oxide film that will become the oxide 230c.

[0383] The oxide 430c functioning as an active layer of the transistor 400 has reduced oxygen vacancies and reduced impurities such as hydrogen and water, similar to the oxide 230. As a result, the threshold voltage of the transistor 400 can be made higher than 0 V, the off-state current can be reduced, and the drain current when the second gate voltage and the first gate voltage are 0 V can be made extremely small.

[0384] The structures, methods, and the like described in this embodiment mode can be used in appropriate combination with structures, methods, and the like described in other embodiment modes and examples.

[0385] (Embodiment 3) In this embodiment, a transistor using an oxide as a semiconductor (hereinafter may be referred to as an OS transistor) and a memory device including a capacitor (hereinafter may be referred to as an OS memory device) according to one embodiment of the present invention will be described with reference to FIGS. 24 and 25. The OS memory device is a memory device including at least a capacitor and an OS transistor that controls charging and discharging of the capacitor. Since the off-state current of the OS transistor is extremely small, the OS memory device has excellent retention characteristics and can function as a nonvolatile memory.

[0386] <Storage device configuration example> 24A shows an example of the configuration of an OS memory device. The memory device 1400 includes a peripheral circuit 1411 and a memory cell array 1470. The peripheral circuit 1411 includes a row circuit 1420, a column circuit 1430, an output circuit 1440, and a control logic circuit 1460.

[0387] The column circuit 1430 includes, for example, a column decoder, a precharge circuit, a sense amplifier, and a write circuit. The precharge circuit has a function of precharging the wiring. The sense amplifier has a function of amplifying a data signal read from a memory cell. The wiring is connected to a memory cell in the memory cell array 1470, and will be described in detail later. The amplified data signal is output to the outside of the memory device 1400 as a data signal RDATA via the output circuit 1440. The row circuit 1420 includes, for example, a row decoder, a word line driver circuit, and the like, and can select a row to be accessed.

[0388] A low power supply voltage (VSS), a high power supply voltage (VDD) for the peripheral circuit 1411, and a high power supply voltage (VIL) for the memory cell array 1470 are supplied to the memory device 1400 from the outside as power supply voltages. In addition, control signals (CE, WE, RE), an address signal ADDR, and a data signal WDATA are input from the outside to the memory device 1400. The address signal ADDR is input to a row decoder and a column decoder, and WDATA is input to a write circuit.

[0389] The control logic circuit 1460 processes external input signals (CE, WE, RE) to generate control signals for the row decoder and column decoder. CE is a chip enable signal, WE is a write enable signal, and RE is a read enable signal. The signals processed by the control logic circuit 1460 are not limited to these, and other control signals may be input as necessary.

[0390] The memory cell array 1470 has a plurality of memory cells MC arranged in a matrix and a plurality of wirings. The number of wirings connecting the memory cell array 1470 and the row circuit 1420 is determined by the configuration of the memory cells MC, the number of memory cells MC in one column, etc. The number of wirings connecting the memory cell array 1470 and the column circuit 1430 is determined by the configuration of the memory cells MC, the number of memory cells MC in one row, etc.

[0391] 24A shows an example in which the peripheral circuit 1411 and the memory cell array 1470 are formed on the same plane, but the present embodiment is not limited to this. For example, as shown in FIG. 24B, the memory cell array 1470 may be provided so as to overlap a part of the peripheral circuit 1411. For example, a sense amplifier may be provided so as to overlap the memory cell array 1470 below.

[0392] FIG. 25 illustrates an example of a memory cell configuration that can be applied to the above-mentioned memory cell MC.

[0393] [DOSRAM] 25A to 25C show circuit configuration examples of a DRAM memory cell. In this specification and the like, a DRAM using a memory cell with one OS transistor and one capacitor may be called a DOSRAM (Dynamic Oxide Semiconductor Random Access Memory). The memory cell 1471 shown in FIG. 25A includes a transistor M1 and a capacitor CA. The transistor M1 includes a gate (sometimes called a front gate) and a back gate.

[0394] A first terminal of the transistor M1 is connected to a first terminal of the capacitance element CA, a second terminal of the transistor M1 is connected to a wiring BIL, a gate of the transistor M1 is connected to a wiring WOL, a back gate of the transistor M1 is connected to a wiring BGL, and a second terminal of the capacitance element CA is connected to a wiring CAL.

[0395] The wiring BIL functions as a bit line, and the wiring WOL functions as a word line. The wiring CAL functions as a wiring for applying a predetermined potential to the second terminal of the capacitor CA. When writing and reading data, it is preferable to apply a low-level potential to the wiring CAL. The wiring BGL functions as a wiring for applying a potential to the back gate of the transistor M1. The threshold voltage of the transistor M1 can be increased or decreased by applying an arbitrary potential to the wiring BGL.

[0396] The memory cell MC is not limited to the memory cell 1471, and the circuit configuration can be changed. For example, the memory cell MC may be configured such that the back gate of the transistor M1 is connected to the wiring WOL instead of the wiring BGL, as in the memory cell 1472 shown in FIG. 25B. For example, the memory cell MC may be configured as a single-gate transistor, that is, a memory cell configured with a transistor M1 without a back gate, as in the memory cell 1473 shown in FIG. 25C.

[0397] When the semiconductor device described in the above embodiment is used for the memory cell 1471 or the like, the transistor 200 can be used as the transistor M1, and the capacitor 100 can be used as the capacitor CA. By using an OS transistor as the transistor M1, the leakage current of the transistor M1 can be made extremely low. That is, since written data can be held by the transistor M1 for a long time, the frequency of refreshing the memory cell can be reduced. Furthermore, the refresh operation of the memory cell can be made unnecessary. Furthermore, since the leakage current is extremely low, multilevel data or analog data can be held in the memory cell 1471, the memory cell 1472, and the memory cell 1473.

[0398] Furthermore, in the DOSRAM, if a sense amplifier is provided so as to overlap under the memory cell array 1470 as described above, the bit line can be shortened. This reduces the bit line capacitance and the storage capacitance of the memory cell.

[0399] [NOSRAM] 25D to 25H show circuit configuration examples of a gain cell type memory cell having two transistors and one capacitor. The memory cell 1474 shown in FIG. 25D includes a transistor M2, a transistor M3, and a capacitor CB. The transistor M2 has a front gate (sometimes simply called a gate) and a back gate. In this specification and the like, a memory device having a gain cell type memory cell using an OS transistor as the transistor M2 may be called a nonvolatile oxide semiconductor RAM (NOSRAM).

[0400] A first terminal of the transistor M2 is connected to a first terminal of the capacitance element CB, a second terminal of the transistor M2 is connected to the wiring WBL, a gate of the transistor M2 is connected to the wiring WOL, and a back gate of the transistor M2 is connected to the wiring BGL. A second terminal of the capacitance element CB is connected to the wiring CAL. A first terminal of the transistor M3 is connected to the wiring RBL, a second terminal of the transistor M3 is connected to the wiring SL, and a gate of the transistor M3 is connected to the first terminal of the capacitance element CB.

[0401] The wiring WBL functions as a write bit line, the wiring RBL functions as a read bit line, and the wiring WOL functions as a word line. The wiring CAL functions as a wiring for applying a predetermined potential to the second terminal of the capacitance element CB. When writing data, while holding data, and when reading data, it is preferable to apply a low-level potential to the wiring CAL. The wiring BGL functions as a wiring for applying a potential to the back gate of the transistor M2. By applying an arbitrary potential to the wiring BGL, the threshold voltage of the transistor M2 can be increased or decreased.

[0402] Moreover, the memory cell MC is not limited to the memory cell 1474, and the circuit configuration can be changed as appropriate. For example, the memory cell MC may be configured such that the back gate of the transistor M2 is connected to the wiring WOL instead of the wiring BGL, as in the memory cell 1475 shown in FIG. 25E. For example, the memory cell MC may be configured such that the transistor M2 has a single gate structure, that is, a transistor M2 without a back gate, as in the memory cell 1476 shown in FIG. 25F. For example, the memory cell MC may be configured such that the wiring WBL and the wiring RBL are combined into a single wiring BIL, as in the memory cell 1477 shown in FIG. 25G.

[0403] When the semiconductor device described in the above embodiment is used for the memory cell 1474 or the like, the transistor 200 can be used as the transistor M2, the transistor 300 can be used as the transistor M3, and the capacitor CB can be used as the capacitor CB. By using an OS transistor as the transistor M2, the leakage current of the transistor M2 can be made extremely low. As a result, written data can be held by the transistor M2 for a long time, and therefore the frequency of refreshing the memory cell can be reduced. Furthermore, the refresh operation of the memory cell can be made unnecessary. Furthermore, since the leakage current is extremely low, multilevel data or analog data can be held in the memory cell 1474. The same applies to the memory cells 1475 to 1477.

[0404] Note that the transistor M3 may be a transistor having silicon in a channel formation region (hereinafter, may be referred to as a Si transistor). The conductivity type of the Si transistor may be an n-channel type or a p-channel type. The Si transistor may have a higher field-effect mobility than an OS transistor. Therefore, a Si transistor may be used as the transistor M3 functioning as a read transistor. By using a Si transistor as the transistor M3, the transistor M2 can be stacked on the transistor M3, thereby reducing the area occupied by the memory cell and achieving high integration of the memory device.

[0405] In addition, the transistor M3 may be an OS transistor. When OS transistors are used for the transistors M2 and M3, the memory cell array 1470 can be configured as a circuit using only n-type transistors.

[0406] FIG. 25H shows an example of a gain cell type memory cell having three transistors and one capacitor. A memory cell 1478 shown in FIG. 25H includes transistors M4 to M6 and a capacitor CC. The capacitor CC is provided as appropriate. The memory cell 1478 is electrically connected to wirings BIL, RWL, WWL, BGL, and GNDL. The wiring GNDL is a wiring that applies a low-level potential. Note that the memory cell 1478 may be electrically connected to wirings RBL and WBL instead of the wiring BIL.

[0407] The transistor M4 is an OS transistor having a backgate, and the backgate is electrically connected to the wiring BGL. The backgate and the gate of the transistor M4 may be electrically connected to each other. Alternatively, the transistor M4 does not necessarily have to have a backgate.

[0408] Note that the transistors M5 and M6 may be n-channel Si transistors or p-channel Si transistors, or the transistors M4 to M6 may be OS transistors. In this case, the memory cell array 1470 can be configured as a circuit using only n-type transistors.

[0409] When the semiconductor device described in the above embodiment is used for the memory cell 1478, the transistor 200 can be used as the transistor M4, the transistors M5 and M6 can be used as the transistor 300, and the capacitor CC can be used as the capacitor 100. By using an OS transistor as the transistor M4, the leakage current of the transistor M4 can be made extremely low.

[0410] Note that the configurations of the peripheral circuit 1411, the memory cell array 1470, and the like shown in this embodiment are not limited to those described above. The arrangement or functions of these circuits, wirings connected to the circuits, circuit elements, and the like may be changed, deleted, or added as necessary.

[0411] The structures, methods, and the like described in this embodiment mode can be used in appropriate combination with structures, methods, and the like described in other embodiment modes and examples.

[0412] (Embodiment 4) In this embodiment, an example of a chip 1200 on which a semiconductor device of the present invention is mounted is shown with reference to Fig. 26. A plurality of circuits (systems) are mounted on the chip 1200. A technology for integrating a plurality of circuits (systems) on a single chip in this manner is sometimes called a system on chip (SoC).

[0413] As shown in FIG. 26A, chip 1200 has a CPU (Central Processing Unit) 1211, a GPU (Graphics Processing Unit) 1212, one or more analog arithmetic units 1213, one or more memory controllers 1214, one or more interfaces 1215, one or more network circuits 1216, etc.

[0414] Chip 1200 is provided with bumps (not shown) and is connected to a first surface of a printed circuit board (PCB) 1201 as shown in Fig. 26B. In addition, a plurality of bumps 1202 are provided on the back side of the first surface of PCB 1201 and are connected to a motherboard 1203.

[0415] The motherboard 1203 may be provided with storage devices such as a DRAM 1221 and a flash memory 1222. For example, the DRAM 1221 may be the DOSRAM described in the above embodiment. For example, the flash memory 1222 may be the NOSRAM described in the above embodiment.

[0416] The CPU 1211 preferably has a plurality of CPU cores. The GPU 1212 preferably has a plurality of GPU cores. The CPU 1211 and the GPU 1212 may each have a memory for temporarily storing data. Alternatively, a memory common to the CPU 1211 and the GPU 1212 may be provided in the chip 1200. The memory may be the above-mentioned NOSRAM or DOSRAM. The GPU 1212 is suitable for parallel calculation of a large amount of data, and may be used for image processing and multiplication and accumulation. By providing the GPU 1212 with an image processing circuit or a multiplication and accumulation circuit using the oxide semiconductor of the present invention, it becomes possible to perform image processing and multiplication and accumulation with low power consumption.

[0417] In addition, by providing the CPU 1211 and GPU 1212 on the same chip, the wiring between the CPU 1211 and GPU 1212 can be shortened, and data transfer from the CPU 1211 to the GPU 1212, data transfer between the memories of the CPU 1211 and GPU 1212, and transfer of calculation results from the GPU 1212 to the CPU 1211 after calculation in the GPU 1212 can be performed quickly.

[0418] The analog calculation unit 1213 has one or both of an A / D (analog / digital) conversion circuit and a D / A (digital / analog) conversion circuit. The analog calculation unit 1213 may also be provided with the above-mentioned product-sum calculation circuit.

[0419] The memory controller 1214 has a circuit that functions as a controller for the DRAM 1221 and a circuit that functions as an interface for the flash memory 1222 .

[0420] The interface 1215 has an interface circuit with externally connected devices such as a display device, a speaker, a microphone, a camera, and a controller. The controller includes a mouse, a keyboard, a game controller, etc. As such an interface, a USB (Universal Serial Bus), an HDMI (registered trademark) (High-Definition Multimedia Interface), etc. can be used.

[0421] The network circuit 1216 includes a network circuit such as a LAN (Local Area Network), and may also include a circuit for network security.

[0422] The above circuits (systems) can be formed in the same manufacturing process in the chip 1200. Therefore, even if the number of circuits required for the chip 1200 increases, there is no need to increase the manufacturing process, and the chip 1200 can be manufactured at low cost.

[0423] A PCB 1201 on which a chip 1200 having a GPU 1212 is provided, a motherboard 1203 on which a DRAM 1221 and a flash memory 1222 are provided can be referred to as a GPU module 1204.

[0424] The GPU module 1204 has the chip 1200 using SoC technology, so that its size can be reduced. In addition, since it excels in image processing, it is suitable for use in portable electronic devices such as smartphones, tablet terminals, laptop PCs, and portable (portable) game consoles. In addition, a multiply-and-accumulate circuit using the GPU 1212 can execute operations such as deep neural networks (DNN), convolutional neural networks (CNN), recurrent neural networks (RNN), autoencoders, deep Boltzmann machines (DBM), and deep belief networks (DBN), so that the chip 1200 can be used as an AI chip, and the GPU module 1204 can be used as an AI system module.

[0425] The structures, methods, and the like described in this embodiment mode can be used in appropriate combination with structures, methods, and the like described in other embodiment modes and examples.

[0426] (Embodiment 5) In this embodiment, an application example of a storage device using the semiconductor device described in the previous embodiment will be described. The semiconductor device described in the previous embodiment can be applied to storage devices of various electronic devices (e.g., information terminals, computers, smartphones, electronic book terminals, digital cameras (including video cameras), recording and reproducing devices, navigation systems, and the like). Note that the computer here includes a large computer such as a server system, in addition to tablet computers, notebook computers, and desktop computers. Alternatively, the semiconductor device described in the previous embodiment can be applied to various removable storage devices such as memory cards (e.g., SD cards), USB memories, and SSDs (solid state drives). FIG. 27 shows some configuration examples of removable storage devices. For example, the semiconductor device described in the previous embodiment is processed into a packaged memory chip and used in various storage devices and removable memories.

[0427] 27A is a schematic diagram of a USB memory. The USB memory 1100 has a housing 1101, a cap 1102, a USB connector 1103, and a board 1104. The board 1104 is housed in the housing 1101. For example, a memory chip 1105 and a controller chip 1106 are attached to the board 1104. The semiconductor device described in the above embodiment can be incorporated into the memory chip 1105 of the board 1104.

[0428] FIG. 27B is a schematic diagram of the appearance of an SD card, and FIG. 27C is a schematic diagram of the internal structure of the SD card. The SD card 1110 has a housing 1111, a connector 1112, and a substrate 1113. The substrate 1113 is housed in the housing 1111. For example, a memory chip 1114 and a controller chip 1115 are attached to the substrate 1113. The capacity of the SD card 1110 can be increased by providing a memory chip 1114 on the back side of the substrate 1113 as well. In addition, a wireless chip having a wireless communication function may be provided on the substrate 1113. This makes it possible to read and write data from and to the memory chip 1114 by wireless communication between the host device and the SD card 1110. The semiconductor device shown in the above embodiment can be incorporated into the memory chip 1114 of the substrate 1113 or the like.

[0429] FIG. 27D is a schematic diagram of the appearance of an SSD, and FIG. 27E is a schematic diagram of the internal structure of the SSD. SSD 1150 has a housing 1151, a connector 1152, and a board 1153. Board 1153 is housed in housing 1151. For example, memory chip 1154, memory chip 1155, and controller chip 1156 are attached to board 1153. Memory chip 1155 is a work memory for controller chip 1156, and may be, for example, a DOSRAM chip. By providing memory chip 1154 on the back side of board 1153, the capacity of SSD 1150 can be increased. The semiconductor device shown in the previous embodiment can be incorporated into memory chip 1154 of board 1153.

[0430] The structures, methods, and the like described in this embodiment mode can be used in appropriate combination with structures, methods, and the like described in other embodiment modes and examples.

[0431] (Embodiment 6) In this embodiment, specific examples of electronic devices that can be used with the semiconductor device of one embodiment of the present invention will be described with reference to FIGS.

[0432] More specifically, the semiconductor device according to one embodiment of the present invention can be used in a processor such as a CPU or a GPU, or a chip. A specific example of an electronic device including a processor such as a CPU or a GPU, or a chip according to one embodiment of the present invention is shown in FIG.

[0433] <Electronic equipment and systems> The GPU or chip according to one embodiment of the present invention can be mounted on various electronic devices. Examples of electronic devices include electronic devices with relatively large screens such as television devices, desktop or notebook personal computers, computer monitors, digital signage, large game machines such as pachinko machines, digital cameras, digital video cameras, digital photo frames, mobile phones, portable game machines, personal digital assistants, and audio playback devices. Moreover, by providing an integrated circuit or chip according to one embodiment of the present invention in an electronic device, it is possible to mount artificial intelligence on the electronic device.

[0434] The electronic device of one embodiment of the present invention may have an antenna. By receiving a signal through the antenna, images, information, and the like can be displayed on a display portion. In addition, when the electronic device has an antenna and a secondary battery, the antenna may be used for contactless power transmission.

[0435] An electronic device according to one embodiment of the present invention may have a sensor (including a function of measuring force, displacement, position, velocity, acceleration, angular velocity, rotation speed, distance, light, liquid, magnetism, temperature, chemical substances, sound, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, gradient, vibration, odor, or infrared rays).

[0436] An electronic device according to one embodiment of the present invention can have various functions. For example, it can have a function of displaying various information (still images, videos, text images, etc.) on a display unit, a touch panel function, a function of displaying a calendar, date, or time, a function of executing various software (programs), a wireless communication function, a function of reading out a program or data recorded in a recording medium, etc. An example of an electronic device is shown in FIG. 28.

[0437] [mobile phone] 28A illustrates a mobile phone (smartphone), which is a type of information terminal. An information terminal 5500 has a housing 5510 and a display unit 5511. As an input interface, a touch panel is provided on the display unit 5511, and buttons are provided on the housing 5510.

[0438] By applying the chip of one embodiment of the present invention, the information terminal 5500 can execute applications using artificial intelligence. Examples of applications using artificial intelligence include an application that recognizes a conversation and displays the conversation content on the display unit 5511, an application that recognizes characters, figures, and the like input by a user to a touch panel provided in the display unit 5511 and displays them on the display unit 5511, and an application that performs biometric authentication such as fingerprints and voiceprints.

[0439] [Information terminal 1] 28B shows a desktop information terminal 5300. The desktop information terminal 5300 has a main body 5301 of the information terminal, a display 5302, and a keyboard 5303.

[0440] The desktop information terminal 5300 can execute applications using artificial intelligence by applying a chip according to one embodiment of the present invention, similarly to the above-described information terminal 5500. Examples of applications using artificial intelligence include design support software, text correction software, and automatic menu generation software. In addition, new artificial intelligence can be developed by using the desktop information terminal 5300.

[0441] In the above description, a smartphone and a desktop information terminal are illustrated as examples of electronic devices in Fig. 28A and Fig. 28B, but information terminals other than smartphones and desktop information terminals can also be applied. Examples of information terminals other than smartphones and desktop information terminals include PDAs (Personal Digital Assistants), notebook information terminals, and workstations.

[0442] [electric appliances] 28C shows an example of an electric appliance, an electric refrigerator-freezer 5800. The electric refrigerator-freezer 5800 includes a housing 5801, a refrigerator door 5802, a freezer door 5803, and the like.

[0443] An electric refrigerator-freezer 5800 having artificial intelligence can be realized by applying the chip of one embodiment of the present invention to the electric refrigerator-freezer 5800. By using artificial intelligence, the electric refrigerator-freezer 5800 can have a function of automatically generating a menu based on ingredients stored in the electric refrigerator-freezer 5800 and the expiration dates of the ingredients, a function of automatically adjusting the temperature to match the ingredients stored in the electric refrigerator-freezer 5800, and the like.

[0444] In this example, an electric refrigerator-freezer has been described as an electrical appliance, but other electrical appliances include, for example, vacuum cleaners, microwave ovens, electric ovens, rice cookers, water heaters, induction cookers, water servers, heating and cooling appliances including air conditioners, washing machines, dryers, and audio-visual equipment.

[0445] [Game consoles] 28D shows a portable game machine 5200, which is an example of a game machine. The portable game machine includes a housing 5201, a display portion 5202, buttons 5203, and the like.

[0446] A low-power portable game console 5200 can be realized by applying a GPU or a chip of one embodiment of the present invention to the portable game console 5200. In addition, low power consumption can reduce heat generation from a circuit, and therefore the influence of heat generation on the circuit itself, peripheral circuits, and modules can be reduced.

[0447] Furthermore, by applying a GPU or a chip of one embodiment of the present invention to the portable game console 5200, the portable game console 5200 can be realized with artificial intelligence.

[0448] Originally, the expression of the progress of a game, the behavior of creatures appearing in the game, and phenomena occurring in the game are determined by the program of the game, but by applying artificial intelligence to the portable game device 5200, it becomes possible to express things that are not limited to the game program. For example, it becomes possible to express things such as changes in the questions asked by the player, the progress of the game, the time, and the behavior of people appearing in the game.

[0449] In addition, when playing a game on the portable game console 5200 that requires multiple players, the game players can be personified using artificial intelligence, so that the game can be played by one person by making the opponent a game player based on artificial intelligence.

[0450] 28D illustrates a portable game machine as an example of a game machine, but the game machine to which the GPU or chip of one embodiment of the present invention is applied is not limited to this. Examples of game machines to which the GPU or chip of one embodiment of the present invention is applied include home-use stationary game machines, arcade game machines installed in entertainment facilities (game centers, amusement parks, etc.), and pitching machines for batting practice installed in sports facilities.

[0451] [Mobile object] The GPU or chip according to one embodiment of the present invention can be applied to automobiles, which are moving objects, and to the area around the driver's seat of an automobile.

[0452] Fig. 28E1 shows an automobile 5700 as an example of a moving body, and Fig. 28E2 shows the periphery of the windshield in the interior of the automobile. Fig. 28E2 shows display panel 5701, display panel 5702, and display panel 5703 attached to the dashboard, as well as display panel 5704 attached to a pillar.

[0453] The display panels 5701 to 5703 can provide various information by displaying a speedometer, a tachometer, a mileage, a fuel gauge, a gear state, an air conditioner setting, and the like. In addition, the display items and layouts displayed on the display panels can be changed as appropriate according to the user's preferences, and the design can be improved. The display panels 5701 to 5703 can also be used as lighting devices.

[0454] The display panel 5704 can complement the field of view (blind spot) blocked by the pillar by displaying an image from an imaging device (not shown) provided in the automobile 5700. That is, by displaying an image from an imaging device provided outside the automobile 5700, the blind spot can be complemented and safety can be improved. In addition, by displaying an image that complements the invisible part, safety can be confirmed more naturally and without discomfort. The display panel 5704 can also be used as a lighting device.

[0455] Since the GPU or chip of one embodiment of the present invention can be used as a component of artificial intelligence, the chip can be used, for example, in an automatic driving system for an automobile 5700. The chip can also be used in a system that performs road guidance, risk prediction, etc. The display panels 5701 to 5704 may be configured to display information such as road guidance and risk prediction.

[0456] In the above description, an automobile is described as an example of a moving object, but the moving object is not limited to an automobile. For example, the moving object may be a train, a monorail, a ship, an aircraft (helicopter, unmanned aerial vehicle (drone), airplane, rocket), etc., and the chip of one embodiment of the present invention may be applied to these moving objects to provide a system using artificial intelligence.

[0457] [Broadcasting System] The GPU or chip according to one embodiment of the present invention can be applied to a broadcasting system.

[0458] Fig. 28F shows a schematic diagram of data transmission in a broadcasting system. Specifically, Fig. 28F shows a path that radio waves (broadcast signals) transmitted from a broadcasting station 5680 take to reach a television receiver (TV) 5600 in each home. The TV 5600 includes a receiving device (not shown), and the broadcast signal received by an antenna 5650 is transmitted to the TV 5600 via the receiving device.

[0459] In FIG. 28F, antenna 5650 is shown as a UHF (Ultra High Frequency) antenna, but a BS / 110° CS antenna, a CS antenna, or the like can also be used as antenna 5650.

[0460] Radio waves 5675A and 5675B are broadcast signals for terrestrial broadcasting, and radio tower 5670 amplifies received radio waves 5675A and transmits radio waves 5675B. In each home, radio waves 5675B are received by antenna 5650, allowing viewers to watch terrestrial TV broadcasting on TV 5600. Note that the broadcasting system is not limited to the terrestrial broadcasting shown in Fig. 28F, and may be satellite broadcasting using an artificial satellite, data broadcasting via optical fiber, or the like.

[0461] The above-mentioned broadcasting system may be a broadcasting system using artificial intelligence by applying the chip of one embodiment of the present invention. When broadcasting data is transmitted from the broadcasting station 5680 to the TV 5600 in each home, the broadcasting data is compressed by an encoder, and when the antenna 5650 receives the broadcasting data, the broadcasting data is restored by a decoder of a receiving device included in the TV 5600. By using artificial intelligence, for example, in motion compensation prediction, which is one of the compression methods of the encoder, it is possible to recognize a display pattern included in a display image. In addition, intraframe prediction using artificial intelligence can also be performed. In addition, for example, when low-resolution broadcasting data is received and the broadcasting data is displayed on the TV 5600 with high resolution, image interpolation processing such as up-conversion can be performed in the restoration of the broadcasting data by the decoder.

[0462] The above-mentioned broadcasting system using artificial intelligence is suitable for ultra-high definition television (UHDTV: 4K, 8K) broadcasting, in which the amount of broadcast data is increasing.

[0463] Furthermore, as an application of artificial intelligence on the TV 5600 side, for example, a recording device having artificial intelligence may be provided in the TV 5600. With such a configuration, the recording device can be made to learn user preferences through artificial intelligence, thereby automatically recording programs that match the user's preferences.

[0464] The electronic devices, functions of the electronic devices, application examples of artificial intelligence, and effects thereof described in this embodiment can be appropriately combined with the descriptions of other electronic devices.

[0465] The structures, methods, and the like described in this embodiment mode can be used in appropriate combination with structures, methods, and the like described in other embodiment modes and examples. EXAMPLES

[0466] In this example, samples 1A, 1B, and 1C having the structures shown in FIG. 29 were fabricated, and the results of analyzing these samples will be described.

[0467] The structure shown in FIG. 29 includes a silicon substrate 10, a silicon oxide film 12 on the silicon substrate 10, a silicon oxynitride film 14 on the silicon oxide film 12, a silicon oxynitride film 18 on the silicon oxynitride film 14, and a silicon oxynitride film 20 on the silicon oxynitride film 18. Here, a nitride region 16 is formed in the silicon oxynitride film 14 near the interface with the silicon oxynitride film 18. Also, the silicon oxynitride film 20 contains deuterium D. Note that the nitride region 16 is not formed in the sample 1A. Also, the nitride region 16 is formed in the samples 1B and 1C, but the method of forming the nitride region 16 is different.

[0468] First, the methods for fabricating Samples 1A, 1B, and 1C will be described.

[0469] First, in each of Samples 1A, 1B, and 1C, the silicon substrate 10 was thermally oxidized to form a silicon oxide film 12 on the surface of the silicon substrate 10 with a target thickness of 100 nm.

[0470] Next, a silicon oxynitride film 14 was formed on each of the samples 1A, 1B, and 1C by the PECVD method to a thickness of 150 nm. 4 Gas 5sccm and N 2 The O gas was used at 1000 sccm, the film formation pressure was 133.3 Pa, the film formation power was 45 W (13.56 MHz), the substrate temperature was 325° C., and the electrode distance was 20 mm.

[0471] Next, a microwave processing apparatus was used to perform microwave processing on Sample 1B and Sample 1C. The microwave processing was performed with 1000 sccm of Ar gas and N 2 A gas of 200 sccm was used, the pressure was 12 Pa, the power was 1200 W, and the treatment temperature was 400° C. The treatment time for sample 1B was 300 seconds, and the treatment time for sample 1C was 1800 seconds. As a result, nitrided regions 16 were formed near the surfaces of the silicon oxynitride films 14 of samples 1B and 1C. Note that since microwave treatment was not performed on sample 1A, nitrided regions 16 were not formed.

[0472] Next, a silicon oxynitride film 18 was formed on each of Samples 1A, 1B, and 1C under the same film-forming conditions as those for the silicon oxynitride film 14, aiming for a film thickness of 50 nm.

[0473] Next, a silicon oxynitride film 20 was formed on each of the samples 1A, 1B, and 1C by the PECVD method to a thickness of 50 nm. 4 Gas 2sccm, N 2 O gas 800sccm, and D 2 The dilution gas was 200 sccm, the deposition pressure was 200 Pa, the deposition power was 150 W (60 MHz), the substrate temperature was 160° C., and the electrode distance was 35 mm. 2 The dilution gas is based on Ar gas, and 2 The gas is diluted to 5%.

[0474] For the prepared samples 1A to 1C, cross-sectional STEM images were taken using a Hitachi High-Technologies Corporation HD-2700 at an accelerating voltage of 200 kV, and analysis was performed by energy dispersive X-ray spectroscopy (EDX).

[0475] 30A to 30C show cross-sectional STEM images of the vicinity of the interface between the silicon oxynitride film 14 and the silicon oxynitride film 18 of Sample 1A to Sample 1C. As shown in FIG. 30A, no nitrided region 16 was observed near the interface of the silicon oxynitride film 14 of Sample 1A, which was not subjected to microwave treatment. In contrast, as shown in FIGS. 30B and 30C, nitrided region 16 was observed near the interface of the silicon oxynitride film 14 of Sample 1B and Sample 1C, which were subjected to microwave treatment. The thickness of the nitrided region 16 in Sample 1B was about 1.7 nm, and the thickness of the nitrided region 16 in Sample 1C was about 1.8 nm. In other words, the thickness of the nitrided region 16 was approximately the same regardless of the time of microwave treatment.

[0476] Next, the results of EDX analysis of the silicon oxynitride film 14 (1A-14) of sample 1A, the nitrided region (1B-16) of sample 1B, the silicon oxynitride film 14 (1B-14) of sample 1B, the nitrided region (1C-16) of sample 1C, and the silicon oxynitride film 14 (1C-14) of sample 1C are shown in Fig. 31. Fig. 31 is a bar graph showing the quantitative value [atomic %] of nitrogen.

[0477] In Sample 1B and Sample 1C, the nitrogen concentration in the nitrided region 16 is higher than that in the silicon oxynitride film 14, and it is found that the surface of the silicon oxynitride film 14 is nitrided by the microwave treatment. This tendency is more prominent in Sample 1C, which was subjected to a longer microwave treatment time, than in Sample 1B.

[0478] Next, Samples 1D to 1F were fabricated, which had the same structures as Samples 1A to 1C and were further subjected to a heat treatment at 400° C. for 1 hour in a nitrogen atmosphere.

[0479] The thus-prepared samples 1A to 1F were subjected to SIMS analysis to examine the diffusion state of deuterium D contained in the silicon oxynitride film 20. FIG. 32A shows the concentration [atoms / cm 3 ] of deuterium D in the samples 1A and 1D. 3 ] and the deuterium D concentration [atoms / cm ] of sample 1B and sample 1E in Fig. 32B. 3] and the deuterium D concentration [atoms / cm ] of sample 1C and sample 1F in Fig. 32C. 3 32A to 32C. In addition, the SIMS analysis of Samples 1A to 1F is performed from the silicon substrate 10 side, and an adhesive is formed on the silicon oxynitride film 20. The dashed lines in the SIMS graphs shown in FIGS. 32A to 32C indicate the lower limit of measurement. The quantitative layers are the silicon oxynitride film 14, the silicon oxynitride film 18, and the silicon oxynitride film 20.

[0480] 32A, in samples 1A and 1D, deuterium D diffuses up to the silicon oxynitride film 14, which is particularly noticeable in sample 1D which has been subjected to heat treatment. In contrast, as shown in FIGS. 32B and 32C, in samples 1B, 1C, 1E and 1F, the concentration of deuterium D is significantly reduced at the interface between the silicon oxynitride film 18 and the silicon oxynitride film 14, i.e., at the nitrided region 16. That is, it can be seen that in these samples, deuterium D contained in the silicon oxynitride film 20 is blocked by the nitrided region 16.

[0481] As described above, by forming a nitride region in a silicon oxynitride film by microwave treatment, a layer having a barrier property against hydrogen can be formed. By using such a layer as described in the above embodiment, hydrogen diffusing into an oxide semiconductor can be reduced. By using an oxide semiconductor in which impurities such as hydrogen are sufficiently reduced in this manner for a channel formation region of a transistor, the transistor can have normally-off characteristics, have stable electrical characteristics, and improve reliability. EXAMPLES

[0482] In this example, the results of measuring the resistivity of Samples 2A to 2I in which a tantalum nitride film formed on a silicon substrate was subjected to microwave treatment in an atmosphere containing nitrogen will be described.

[0483] First, the manufacturing methods of Samples 2A to 2I will be described.

[0484] First, in each of Samples 2A to 2I, a silicon substrate was thermally oxidized to form a silicon oxide film with a target thickness of 100 nm on the surface of the silicon substrate.

[0485] Next, a tantalum nitride film was formed on each of Samples 2A to 2I by DC sputtering to a thickness of 20 nm. In forming the tantalum nitride film, a tantalum target was used, and the deposition gases were argon gas at 50 sccm and nitrogen gas at 10 sccm, the deposition pressure was 0.6 Pa, the deposition power was 1000 W, the substrate temperature was room temperature, and the target-substrate distance was 60 mm.

[0486] Next, the samples 2B to 2I were subjected to microwave processing using a microwave processing apparatus. The microwave processing was performed with 1000 sccm of Ar gas and N 2 The gas was 200 sccm, the power was 1200 W, and the treatment temperature was 400° C. Here, the pressure and treatment time of the microwave treatment of Samples 2B to 2I were set under the conditions shown in Table 1 below.

[0487] [Table 1]

[0488] The results of measuring the sheet resistance of the tantalum nitride films of the fabricated samples 2A to 2I are shown in Figures 33A and 33B. Figure 33A is a graph comparing samples 2A to 2F with different pressure conditions with the treatment time fixed at 5 minutes, and Figure 33B is a graph comparing samples 2A, 2G, 2B, 2H, and 2I with different treatment time conditions with the pressure fixed at 12 Pa. In both Figures 33A and 33B, the vertical axis shows resistivity [Ωcm]. In addition, in both Figures 33A and 33B, the resistivity is expressed as 2.0×10 -3 A dotted line is drawn in Ωcm, which is the target value for the resistivity of the source electrode and the drain electrode in the transistor according to the above embodiment.

[0489] As shown in Fig. 33A, the resistivity of Samples 2B to 2F, which were subjected to microwave treatment, was slightly higher than that of Sample 2A, which was not subjected to microwave treatment, but was approximately the same. Furthermore, the resistivity of Samples 2B to 2F did not show any dependence on the pressure of the microwave treatment.

[0490] As shown in FIG. 33B, the resistivity of samples 2G, 2B, 2H, and 2I, which were subjected to microwave treatment, tended to increase with treatment time. However, the resistivity of samples 2G, 2B, 2H, and 2I was 2.0×10 -3 The value was sufficiently low for Ωcm.

[0491] Thus, it was shown that the resistivity of the tantalum nitride used for the source and drain electrodes does not increase significantly even if the source and drain electrodes are exposed to microwave treatment when the nitride regions are formed in the silicon oxynitride film. By using such a conductive film for the source and drain electrodes, it is not necessary to perform special post-treatment on the source and drain electrodes after the nitride regions are formed in the silicon oxynitride film, and therefore the productivity of the semiconductor device can be improved. EXAMPLES

[0492] In this example, Samples 3A to 3H having the structures shown in Fig. 29 in Example 1 were fabricated, and the results of analyzing these samples will be described. Samples 3A to 3H are different from Samples 1A to 1F in the formation conditions of the nitride region 16.

[0493] As in Example 1, the structure shown in FIG. 29 includes a silicon substrate 10, a silicon oxide film 12 on the silicon substrate 10, a silicon oxynitride film 14 on the silicon oxide film 12, a silicon oxynitride film 18 on the silicon oxynitride film 14, and a silicon oxynitride film 20 on the silicon oxynitride film 18. Here, a nitride region 16 is formed in the silicon oxynitride film 14 near the interface with the silicon oxynitride film 18. The silicon oxynitride film 20 contains deuterium D. Note that the nitride region 16 is not formed in Sample 3A and Sample 3E. Note that the nitride region 16 is formed in Sample 3B, Sample 3C, Sample 3D, Sample 3F, Sample 3G, and Sample 3H, but the conditions for forming the nitride region 16 are different.

[0494] First, the manufacturing methods of Samples 3A to 3H will be described.

[0495] First, in each of Samples 3A to 3H, the silicon substrate 10 was thermally oxidized to form a silicon oxide film 12 on the surface of the silicon substrate 10 with a target thickness of 100 nm.

[0496] Next, a silicon oxynitride film 14 was formed on each of the samples 3A to 3H by using a PECVD method to a thickness of 150 nm. 4 Gas 5sccm and N 2 The O gas was used at 1000 sccm, the film formation pressure was 133.3 Pa, the film formation power was 45 W (13.56 MHz), the substrate temperature was 325° C., and the electrode distance was 20 mm.

[0497] Next, a microwave processing apparatus was used to perform microwave processing on Sample 3B, Sample 3C, Sample 3D, Sample 3F, Sample 3G, and Sample 3H. The microwave processing was performed using 1000 sccm of Ar gas and N 2The gas was 200 sccm, the power was 1200 W, the processing temperature was 400° C., and the processing time was 300 seconds. Here, the pressure of Samples 3B and 3F was 12 Pa, the pressure of Samples 3C and 3G was 60 Pa, and the pressure of Samples 3D and 3H was 400 Pa. As a result, nitrided regions 16 were formed near the surfaces of the silicon oxynitride films 14 of Samples 3B, 3C, 3D, 3F, 3G, and 3H. Note that, since microwave processing was not performed on Samples 3A and 3E, nitrided regions 16 were not formed.

[0498] Next, a silicon oxynitride film 18 was formed on each of Samples 3A to 3H under the same film-forming conditions as those for the silicon oxynitride film 14, aiming for a film thickness of 50 nm.

[0499] Next, a silicon oxynitride film 20 was formed on each of the samples 3A to 3H by using a PECVD method to a thickness of 50 nm. 4 Gas 2sccm, N 2 O gas 800sccm, and D 2 The dilution gas was 200 sccm, the deposition pressure was 200 Pa, the deposition power was 150 W (60 MHz), the substrate temperature was 160° C., and the electrode distance was 35 mm. 2 The dilution gas is based on Ar gas, and 2 The gas is diluted to 5%.

[0500] Next, Samples 3E, 3F, 3G, and 3H were subjected to a heat treatment at 400° C. for 8 hours in a nitrogen atmosphere.

[0501] The thus-prepared samples 3A to 3H were subjected to SIMS analysis to examine the diffusion state of deuterium D contained in the silicon oxynitride film 20. FIG. 34A shows the concentration [atoms / cm 3 ] of deuterium D in each of the samples 3A to 3H. 3 ], and the deuterium D concentration [atoms / cm ] of Samples 3E to 3H in FIG. 34B. 334A and 34B. The SIMS analysis of samples 3A to 3H was performed from the silicon substrate 10 side, and an adhesive was formed on the silicon oxynitride film 20. The dashed lines in the SIMS graphs shown in FIGS. 34A and 34B indicate the lower limit of measurement. The quantitative layers are the silicon oxide film 12, the silicon oxynitride film 14, the silicon oxynitride film 18, and the silicon oxynitride film 20.

[0502] As shown in Fig. 34A, in Samples 3B to 3D, which have not been subjected to a long-term high-temperature heat treatment, deuterium D contained in the silicon oxynitride film 20 is blocked by the nitride region 16 regardless of the pressure of the microwave treatment. In contrast, as shown in Fig. 34B, in Samples 3F to 3H, which have been subjected to a long-term high-temperature heat treatment, deuterium D contained in the silicon oxynitride film 20 is blocked by the nitride region 16 more than in Sample 3E, in which the nitride region 16 is not formed, but the hydrogen blocking ability is dependent on the pressure of the microwave treatment. That is, in Sample 3G, which is subjected to a pressure of 60 Pa, the diffusion of deuterium D is suppressed more than in Sample 3H, which is subjected to a pressure of 400 Pa, and in Sample 3F, which is subjected to a pressure of 12 Pa, the diffusion of deuterium D is suppressed more than in Sample 3G, which is subjected to a pressure of 60 Pa.

[0503] As described above, by reducing the pressure during microwave treatment and forming a nitride region in the silicon oxynitride film, the barrier property against hydrogen can be improved. By using such a nitride region as described in the above embodiment, hydrogen diffusing into the oxide semiconductor can be reduced even when high-temperature heat treatment is performed for a long time in the manufacturing process of the semiconductor device. By using an oxide semiconductor in which impurities such as hydrogen are sufficiently reduced in this way for the channel formation region of a transistor, the transistor can have normally-off characteristics, have stable electrical characteristics, and improve reliability. EXAMPLES

[0504] In this example, Sample 4A and Sample 4B having the structure shown in FIG. 35 were fabricated, and the results of analyzing these samples will be described.

[0505] 35 includes a silicon substrate 30, a silicon oxide film 32 on the silicon substrate 30, a silicon oxide film 34 on the silicon oxide film 32, and a silicon nitride film 38 on the silicon oxide film 34. Here, in sample 4B, a nitride region 36 is formed in the silicon oxide film 34 near the interface with the silicon nitride film 38. Note that in sample 4A, the nitride region 36 is not formed.

[0506] First, a method for fabricating Samples 4A and 4B will be described.

[0507] First, in each of Samples 4A and 4B, the silicon substrate 30 was thermally oxidized to form a silicon oxide film 32 on the surface of the silicon substrate 30 with a target thickness of 100 nm.

[0508] Next, a silicon oxide film 34 was formed on each of the samples 4A and 4B by RF sputtering to a thickness of 100 nm. 2 An anhydrous synthetic quartz target was used. 50 sccm of oxygen gas was used as the deposition gas, the deposition pressure was 0.7 Pa (measured with a miniature gauge MG-2 manufactured by Canon Anelva), the deposition power was 1500 W, the substrate temperature was 170° C., and the target-substrate distance was 60 mm.

[0509] Next, the sample 4B was subjected to microwave processing using a microwave processing device. The microwave processing was performed with 1000 sccm of Ar gas and N 2 The gas was 200 sccm, the power was 1200 W, the processing temperature was 400° C., the pressure was 12 Pa, and the processing time was 300 seconds. As a result, a nitrided region 36 was formed near the surface of the silicon oxide film 34 of the sample 4B. Note that the microwave processing was not performed on the sample 4A, so the nitrided region 36 was not formed.

[0510] Next, a silicon nitride film 38 was formed on each of the samples 4A and 4B by the PECVD method to a thickness of 20 nm. 4 Gas 5sccm, and N 2The gas was 2500 sccm, the deposition pressure was 100 Pa, the deposition power was 250 W (13.56 MHz), the substrate temperature was 350° C., and the electrode distance was 20 mm. In this process, Samples 4A and 4B were exposed to a large amount of hydrogen generated in the chamber.

[0511] The thus-prepared samples 4A and 4B were subjected to SIMS analysis to confirm whether hydrogen had diffused into the silicon oxide film 34 during the formation of the silicon nitride film 38. 3 36 shows the SIMS analysis of samples 4A and 4B from the silicon substrate 30 side, and an adhesive is formed on the silicon nitride film 38. The dashed line in the SIMS graph shown in FIG. 36 shows the lower limit of measurement. The quantitative layer is the silicon oxide film 34.

[0512] 36, in sample 4A, hydrogen H diffuses up to the silicon oxide film 34. In contrast to this, in sample 4B, the concentration of hydrogen H is significantly reduced at the interface between the silicon nitride film 38 and the silicon oxide film 34, i.e., in the nitrided region 36. That is, it can be seen that in sample 4B, hydrogen is reduced in the nitrided region 36 during the formation of the silicon nitride film 38.

[0513] As described above, by forming a nitride region by microwave treatment, even if a film formation method in which a large amount of hydrogen is generated in a chamber, such as a PECVD method, is used with the nitride region exposed, hydrogen diffusing inward from the nitride region can be reduced. By using such a nitride region as described in the above embodiment, hydrogen diffusing into an oxide semiconductor can be reduced. By using an oxide semiconductor in which impurities such as hydrogen are sufficiently reduced in this way for a channel formation region of a transistor, a normally-off characteristic can be achieved, and the transistor can have stable electrical characteristics and have improved reliability.

[0514] The structures, methods, and the like described in the above-described embodiment modes can be used in appropriate combination with structures, methods, and the like described in other embodiment modes and examples. [Explanation of symbols]

[0515] 200: transistor, 200_n: transistor, 200_1: transistor, 205: conductor, 205a: conductor, 205b: conductor, 210: insulator, 212: insulator, 214: insulator, 216: insulator, 217: region, 218: conductor, 222: insulator, 224: insulator, 230: oxide, 230a: oxide, 230A: oxide film, 230b: oxide, 230B: oxide film, 230c: oxide, 230C: oxide film, 240: conductor, 240a: conductor, 240b: conductor, 241: region, 241a: region, 241b: region, 241c: region, 242: conductor, 242a: conductor, 242A: conductive film, 242b: conductor, 242B: conductive layer, 243: oxide, 243a: oxide, 243A: oxide film, 243b: oxide, 243B: oxide layer, 244: region, 244a: region, 244b: region, 245: region, 246: conductor, 246a: conductor, 246b: conductor, 250: insulator, 250A: insulating film, 255a: opening, 255b: opening, 260: conductor, 260 a: conductor, 260Aa: conductive film, 260Ab: conductive film, 260b: conductor, 265: sealing portion, 265a: sealing portion, 265b: sealing portion, 272: insulator, 272a: insulator, 272A: insulating film, 272b: insulator, 272B: insulator layer, 274: insulator, 280: insulator, 281: valve, 282: insulator, 283: insulator

Claims

1. A method for manufacturing a semiconductor device having first and second conductors, first to sixth insulators, and first and second oxides, comprising the steps of: depositing the first insulator on a substrate; forming the first conductor on the first insulator; depositing the second insulator on the first conductor; depositing the third insulator on the second insulator; forming the first oxide on the third insulator; depositing the fourth insulator on the first oxide; forming a first opening in the fourth insulator that reaches the first oxide; forming a first oxide film in the first opening so as to be in contact with the first oxide and the fourth insulator; forming a first insulating film on the first oxide film; forming a first conductive film on the first insulating film; removing a portion of the first oxide film, a portion of the first insulating film, and a portion of the first conductive film; forming the second oxide in contact with an upper surface of the fourth insulator; forming a fifth insulator in contact with an upper surface of the second oxide; forming the sixth insulator in contact with an upper surface of the fifth insulator; removing a portion of the sixth insulator, a portion of the fifth insulator, and a portion of the fourth insulator; forming a first region in contact with a side surface of the sixth insulator and a second region in contact with a side surface of the fourth insulator; A method for manufacturing a semiconductor device, wherein the third insulator, the fourth insulator, and the first insulating film are formed using a gas having molecules containing silicon atoms.

2. In claim 1, A method for manufacturing a semiconductor device, wherein the first region and the second region are formed by removing a part of the sixth insulator, a part of the fifth insulator, and a part of the fourth insulator and then performing microwave treatment in an atmosphere containing nitrogen.

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