Photoelectric conversion device, photoelectric conversion system, mobile object

Abstract

To reduce the power consumption of a photoelectric conversion device having an AD converter.SOLUTION: A photoelectric conversion device has a plurality of pixels, a comparator that compares output signals from the pixels with a reference signal, and a K-bit (K is a natural number) counter that operates in parallel with the operation of the comparator, and the photoelectric conversion device converts the output signals from the pixels into digital signals by using output from the comparator and output from the counter. The photoelectric conversion device comprises an addition unit that adds up the plurality of digital signals, and the addition unit has an M-bit (M is a natural number less than K) serial adder.SELECTED DRAWING: Figure 4

Description

[Technical field]

[0001] The present invention relates to a photoelectric conversion device, and a photoelectric conversion system and a mobile object that include the photoelectric conversion device. [Background technology]

[0002] Patent Document 1 discloses a photoelectric conversion device that has an AD converter with an up / down counter for each column, and performs digital addition processing on data sampled a plurality of times. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2018-23025 A Summary of the Invention [Problem to be solved by the invention]

[0004] This digital addition process requires high speed addition of multiple binary data for each pixel, which increases the power consumption of the device. Reducing this power consumption is one of the challenges facing photoelectric conversion devices. [Means for solving the problem]

[0005] One aspect of the present invention is a photoelectric conversion device having a plurality of pixels, a comparator that compares an output signal of the pixel with a reference signal, and a Kbit (K is a natural number) counter that operates in parallel with the operation of the comparator, and converting the output signal of the pixel into a digital signal using an output of the comparator and an output of the counter, the photoelectric conversion device further comprising an adder that adds a plurality of the digital signals, the adder comprising an Mbit (M is a natural number less than K) serial adder and a multi-bit holding unit for holding the signal output from the serial adder.and wherein at least a portion of a period during which the comparator is operating and at least a portion of a period during which the adder is executing an addition process overlap each other. Another aspect of the present invention is a photoelectric conversion device having a plurality of pixels, a comparator that compares an output signal of the pixel with a reference signal, and a K-bit (K is a natural number) counter that operates in parallel with the operation of the comparator, and converts the output signal of the pixel into a digital signal using an output of the comparator and an output of the counter, the photoelectric conversion device further comprising an adder that adds a plurality of the digital signals, the adder comprising an M-bit (M is a natural number less than K) serial adder. and a multi-bit holding unit for holding the signal output from the serial adder. wherein in multi-sampling, the serial adder performs addition and subtraction. Effect of the Invention

[0006] According to the present invention, it is possible to provide a photoelectric conversion device capable of reducing power consumption compared to the conventional device. [Brief description of the drawings]

[0007] [Figure 1] 1 is a block diagram of an imaging apparatus according to a first embodiment. [Diagram 2] 2 is a schematic diagram of a pixel unit and a column AD conversion unit of the imaging device according to the first embodiment. [Diagram 3] 2 is a schematic diagram of a pixel of the imaging device according to the first embodiment. [Figure 4] 2 is a schematic diagram of a column memory of the imaging device according to the first embodiment; [Diagram 5] 4 is a timing chart showing the operation of a column AD conversion unit of the imaging device according to the first embodiment. [Figure 6] 10 is a timing chart showing the operation of a column AD conversion unit of an imaging device according to a second embodiment. [Figure 7] FIG. 13 is a diagram illustrating a configuration of a photoelectric conversion system according to a third embodiment. [Figure 8] 13A to 13C are diagrams illustrating a configuration and an operation of a moving body according to a fourth embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0008] Each embodiment will be described below with reference to the drawings.

[0009] In the following embodiments, an image pickup device will be mainly described as an example of a photoelectric conversion device. However, each embodiment is not limited to an image pickup device, and can be applied to other examples of photoelectric conversion devices. For example, a distance measuring device (a device for measuring distance using focus detection or TOF (Time Of Flight)) or a photometric device (a device for measuring the amount of incident light) may be used.

[0010] First Embodiment (Imaging device) FIG. 1 is a block diagram showing an imaging device according to this embodiment.

[0011] The imaging device 1 shown in FIG. 1 includes a control unit 102, a vertical scanning unit 103, a pixel unit 104, a column AD conversion unit 105, a horizontal transfer unit 106, a data processing unit 107, and a signal output unit .

[0012] The imaging device 1 is controlled by an external CPU 101 .

[0013] An input terminal of the control unit 102 is connected to an output terminal of the CPU 101, and the control unit 102 operates upon receiving a synchronous signal output by communication from the CPU 101. The output of the control unit 102 is input to a vertical scanning unit 103, a column AD conversion unit 105, and a horizontal transfer unit 106.

[0014] An input terminal of the vertical scanning unit 103 is connected to an output terminal of the control unit 102, and the vertical scanning unit 103 operates in response to a control signal from the control unit 102. An output terminal of the vertical scanning unit 103 is connected to the pixel unit 104.

[0015] In the pixel section 104, pixels 201 are arranged in a matrix of n rows and m columns, where n and m are natural numbers.

[0016] The column AD conversion unit 105 receives a control signal output from the control unit 102 and converts the analog signal output from the pixel unit 104 for each column into a digital signal (hereinafter also referred to as AD conversion).

[0017] The horizontal transfer unit 106 receives a control signal output from the control unit 102 and transfers the digital signal (digital data) output from the column AD conversion unit 105 to the data processing unit.

[0018] The data processing unit 107 processes the digital signal transferred from the horizontal transfer unit 106 and outputs it to the signal output unit 108 .

[0019] The signal output unit 108 outputs a signal having a value corresponding to the output of the data processing unit 107 to the outside as an output of the photoelectric conversion device 1 .

[0020] FIG. 2 is a schematic diagram of the pixel unit 104 and the column AD conversion unit 105 according to this embodiment.

[0021] In the pixel section 104, a plurality of pixels 201 are arranged in an array across a plurality of rows and a plurality of columns. Here, a pixel section 104 in which the pixels 201 are arranged across n rows and m columns will be described as an example. The number of pixels 201 constituting the pixel section 104 is not particularly limited.

[0022] The pixels 201 convert incident light into a signal (electric charge) and output a signal (pixel signal) according to the amount of incident light. Vertical signal lines 202 extending in the column direction (vertical direction in FIG. 1) are arranged in each column of the pixel unit 104. The vertical signal lines are respectively connected to the pixels 201 arranged in the column direction and form a common signal line for the pixels 201 arranged in the column direction.

[0023] The vertical signal line 202 is connected to a constant current source (not shown). A pixel signal (also referred to as a signal charge) read out from the pixel 201 is input to the column AD conversion unit 105 via the vertical signal line 202.

[0024] The vertical signal line 202 is connected to a column comparator 203 of the column AD conversion unit 105, and the pixel signal becomes one input signal of the column comparator 203. An output LATCH# (#: 1 to m) of the column comparator 203 is connected to a column memory 204.

[0025] A ramp signal RAMP common to each column is input to the column comparator 203 as a reference signal, which is the other input signal. This ramp signal RAMP is generated by a ramp signal generating unit 205. The ramp signal RAMP may be a signal whose potential decreases continuously over time, or a signal whose potential increases continuously over time, or a signal whose potential changes in a sawtooth pattern. When a signal whose potential changes continuously is used, it is also acceptable for the potential change to be blunted at the rise of the potential.

[0026] A gray code GRAY common to each column is input to the column memory 204. This gray code GRAY is generated by a gray counter 206 and is K bits (K is a natural number; in this embodiment, K=4).

[0027] The Gray counter 206 operates in parallel with the operation of the column comparator 203. By performing Gray code generation and comparison between the pixel signal and the reference signal in parallel, it is possible to store the Gray code GRAY at the timing when the output LATCH# of the column comparator 203 becomes High. The column memory 204 outputs a Kbit digital signal ADCOUT# (#: 1 to m) generated using this Gray code.

[0028] (Pixel circuit) The configuration of the pixel 201 of the imaging device according to this embodiment and the function of each element will be described.

[0029] FIG. 3 is an equivalent circuit diagram of a configuration example of a pixel 201 of the image pickup device according to this embodiment.

[0030] The pixel 201 includes a photoelectric conversion element 311 , a charge transfer unit 312 , a floating diffusion portion FD (hereinafter, referred to as FD), a reset unit 313 , a signal amplification unit 314 , and a row selection unit 315 .

[0031] When light is incident on the photoelectric conversion element 311, an electric charge is generated by photoelectric conversion. The photoelectric conversion element 311 accumulates the generated electric charge as a signal charge.

[0032] The charge transfer means 312 is a transfer transistor for reading out the charge accumulated in the photoelectric conversion element 311, and is connected between the photoelectric conversion element 311 and the FD. Conduction / non-conduction (on / off) is controlled by a pixel transfer signal PTX(1) input to the gate.

[0033] The reset means 313 is a reset transistor for supplying a power supply voltage VDD to the FD to reset the circuit, and is connected between the power supply voltage VDD and the FD. Conduction / non-conduction (on / off) is controlled by a pixel unit reset signal PRES(1) input to the gate.

[0034] The signal amplifier 314 is a source follower transistor that converts the charge accumulated in the FD into a voltage, amplifies it, and outputs it as a voltage signal to the vertical signal line 202. The FD is connected to a gate terminal of the signal amplifier 314, and a power supply voltage VDD and the row selection means 315 are connected to the drain and source terminals.

[0035] The row selection means 315 is a transistor for selecting a row to output a pixel signal, and is connected between the output of the signal amplification means 314 and the vertical signal line 202. Conduction / non-conduction (on / off) is controlled by a row selection signal PSEL(1) input to the gate.

[0036] The following describes a method of reading out noise data (hereinafter also referred to as N data) from pixel 201, reading signal data (hereinafter also referred to as S data), and removing the N data from the S data to obtain valid data.

[0037] First, the FD is reset by the reset means 313, and the charge held in the FD after the reset is released is read out via the signal amplification means 314 and defined as N data. In other words, the reset noise of the FD is read out as N data. After the N data is read out, the charge held in the photoelectric conversion element 311 is transferred to the FD by the charge transfer means 312. The charge held in the FD as a result of this transfer is read out via the signal amplification means 314 and defined as S data. In other words, the sum of the effective signal data based on the charge held in the photoelectric conversion element 311 and the reset noise of the FD is the S data.

[0038] By performing correlated double sampling (CDS) processing to subtract the N data (reset noise) from the S data, valid data for the pixel 201 can be obtained.

[0039] (column circuit) The column circuit configuration according to this embodiment will be described.

[0040] FIG. 4 is a diagram showing an example of the configuration of the column memory 204 in the image pickup device according to this embodiment.

[0041] The column memory 204 includes a write storage unit 401, an adder unit 402, and a read storage unit 403. The output of the write storage unit 401 is input to the adder unit 402. The output of the adder unit 402 is input to the read storage unit 403. This will be described in detail below.

[0042] The write storage unit 401 is a circuit that can store the gray code GRAY when LATCH# goes high.

[0043] The addition unit 402 is a serial binary adder. It mainly includes FFs (DI[3] to DI[0]) (hereinafter referred to as DI) for holding input data, a 1-bit adder, and FFs (DO[3] to DO[0]) (hereinafter referred to as DO) for holding output data. In addition, a Gray-binary conversion circuit 404 is provided between the input terminal of the DI and the output terminal of the write storage unit 401.

[0044] The DI performs a "shift operation" to input the input data to the 1-bit adder in sequence starting from the least significant bit. Also, the DI can switch between "the operation of converting the Gray code stored in the write storage unit 401 into a binary code" and "the shift operation" by the signal SE.

[0045] The 1-bit adder is equipped with a full adder and a carry bit holding FF.

[0046] DO performs a "shift operation" to store the output of the 1-bit adder in order from the least significant bit. In addition, the output of DO[0] can be bit-inverted and input to the 1-bit adder by using the signal INV.

[0047] The signal SE also serves as a clock stop function for the 1-bit adder and DO. The readout storage unit 403 is a circuit that can store the value of DO when the signal P_MTX goes high. The output of the readout storage unit 403 becomes the output ADCOUT# of the column memory 204.

[0048] A method for driving the photoelectric conversion device according to this embodiment will be described below.

[0049] (Drive method: single sampling) FIG. 5 is a timing chart showing an example of the operation of the column AD conversion unit 105 of the image pickup device.

[0050] The upper part of FIG. 5 shows an outline of the operation of the column AD conversion unit 105, and the lower part of FIG. 5 shows the details of the operation of the column memory 204.

[0051] First, an outline of the operation of the column AD conversion unit 105 will be described with reference to the upper part of FIG.

[0052] The operation of AD converting the signals output from the pixels 201 in the first row and outputting the digital data corresponding to the signals as ADCOUT# will be described.

[0053] At time T1, the CPU 101 outputs a horizontal synchronization signal HD to the control unit .

[0054] From time T1n1 to time T1n2, the column AD conversion unit 105 simultaneously AD converts the N data of the pixels 201 in all columns of the first row. Two circuits control the AD conversion. First, the column comparator 203 compares the pixel output Vsig with the ramp signal RAMP and outputs LATCH#. Next, the write storage unit 401 of the column memory 204 stores the gray code GRAY at the timing when LATCH# becomes High. The N data converted into a digital signal by this AD conversion is designated as N.

[0055] From time T1n2, the adder 402 in the column memory 204 operates to perform an addition process of 0 (initial value)+N. Details of this operation will be described later.

[0056] From time T1s1 to time T1s2, the column AD conversion unit 105 simultaneously AD-converts the S data of all columns of pixels 201 in the first row. At this time, the AD conversion process of the S data of the first row starting from time T1s1 and the addition process (0+N) of the N data of the first row are simultaneously executed, and the period during which both processes are performed is overlapped, thereby making it possible to shorten the period of one frame. Note that the AD conversion process period of the S data and the addition process period of the N data may entirely overlap, or one period may entirely overlap with part of the processing period of the other. Part of one processing period may overlap with part of the processing period of the other.

[0057] The AD conversion process of the S data is the same as that of the N data. The S data converted into a digital signal by this AD conversion is denoted as S.

[0058] From time T1s2, the adder 402 of the column memory 204 operates and performs a subtraction process of S-N' (N'=N+1). This operation will be described in detail later. After this subtraction process is completed, the output (S-N') of the adder 402 is transferred to the readout storage unit 403.

[0059] Thereafter, the value of SN' in the readout storage unit 403 is held for a period corresponding to the cycle of the horizontal synchronizing signal HD.

[0060] The held values ​​of SN′ are read out and sequentially output as a digital signal ADCOUT# of the storage unit 403 via the horizontal transfer unit 106 .

[0061] From time T2, AD conversion is similarly performed on the signals output from the pixels 201 in the second row. At this time, the AD conversion process of the N data in the second row starting from time T2n1 and the subtraction process (S-N') in the first row are performed so that their respective periods overlap each other, thereby making it possible to shorten the period of the horizontal synchronization signal HD.

[0062] Next, the operation of the column memory 204 will be described in detail with reference to the lower part of Fig. 5. Here, an example where N data = 3, S data = 13, and S-N' = 9 (N' = N + 1) will be described.

[0063] In the following explanation, Gray code will be represented as GXXXX (X is either 0 or 1), and binary code will be represented as BXXXX (X is either 0 or 1).

[0064] At time T1nb, the write storage unit 401 holds the Gray code (G0010) of N data (3 in this embodiment).

[0065] At the first rising edge of CLK, signal SE is low. DI converts the Gray code (G0010) in the write storage unit 401 to binary code (B0011) and stores it as binary data. DO does not operate because the clock is stopped by signal SE.

[0066] During the second to fifth rising edges of CLK, the signal SE is High and the signal INV is Low. DI (B0011) and DO (B0000) perform shift operations in synchronization with CLK while executing the addition process {DI (3 = B0011) + DO (0 = B0000)}.

[0067] As a result, at time T1ne, DO(3=B0011) is stored.

[0068] The addition process will be described in more detail. As described above, the addition unit 402 has a full adder and a 1-bit adder equipped with a carry bit holding FF. Each digit of DI (3=B0011) is held in DI[3] to DI[0], and each digit of DO (0=B0000) is held in DO[3] to DO[0].

[0069] Therefore, when each digit of DI and DO shifts one place at a time in sync with CLK, the least significant bit of DI (3 = B0011) and the least significant bit of DO (0 = B0000) are input to the full adder and added. The FF that holds the carry bit stores the carry. At the next CLK, the second-to-least significant bit of DI (3 = B0011) and the second-to-least significant bit of DO (0 = B0000) are input to the full adder and added.

[0070] In this way, the input data can be input to the adder in order from the least significant bit by shifting. In this type of adder, K clock cycles are required to perform an addition of K bits.

[0071] At time T1sb, the write storage unit 401 holds the Gray code (G1011) of the S data (13 in this embodiment).

[0072] Next, at the first rising edge of CLK, signal SE is Low. DI converts the Gray code (G1011) in the write storage unit 401 to binary code (B1101) and stores it as binary data. DO does not operate because the clock is stopped by signal SE.

[0073] At the second to fifth rising edges of CLK, the signal SE is High and the signal INV is High. The output of DO[0], i.e., the N data, is bit-inverted and input to the 1-bit adder by the signal INV. DI(B1101) and (B1100), which is the inverted DO(B0011), are added while shifting in synchronization with CLK, thereby executing the subtraction process {DI(13=B1101)-DO(3=B0011)-1}.

[0074] As a result, at time T1se, DO(9=B1001) is saved.

[0075] At time T1se, the subtraction process of S-N' (N'=N+1) is completed.

[0076] The obtained S-N' (N'=N+1) can be corrected to SN in subsequent processing to perform correlated double sampling processing.

[0077] As described above, in this embodiment, a 1-bit adder is used as a circuit for performing SN subtraction processing, thereby suppressing the circuit size. By suppressing the circuit size, it is possible to reduce the power consumed by the circuit. In addition, it is possible to increase the size of the pixels while keeping the overall size of the imaging device constant, thereby improving image quality.

[0078] Furthermore, one frame period is shortened by executing the "AD conversion of N data" and "SN subtraction processing" so that their periods overlap.

[0079] Therefore, in this embodiment, it is possible to provide a column circuit capable of performing addition processing at high speed while suppressing power consumption and circuit scale.

[0080] In addition, by using Gray code, which transitions one bit at a time, it is possible to prevent values ​​in the middle of a transition from being input to memory, and to suppress errors to 1 LSB. In addition to improving image quality by reducing noise, power consumption can be reduced because there are fewer transitions and the maximum frequency is low.

[0081] Although the Gray code is used in the description of this embodiment, the code to be used is not limited to the Gray code. Similar effects can be expected with any code in which the Hamming distance between adjacent count values ​​is 1.

[0082] Second Embodiment In the first embodiment, an example of an imaging device that performs SN (subtraction processing) using a 1-bit adder has been described. In this embodiment, an application example to a multi-sampling operation (N data and S data are each AD converted multiple times and added) using the same imaging device as in the first embodiment will be described with reference to FIG.

[0083] The configuration of the imaging device (FIGS. 1 to 4) is the same as that of the first embodiment. The same reference numerals are used to designate the same elements in FIG. 6 as those in FIG. 5, and therefore the description will be omitted. The description will be focused mainly on the differences from the first embodiment.

[0084] A method for driving the photoelectric conversion device according to the second embodiment will be described below.

[0085] (Drive method: multi-sampling) FIG. 6 is a timing chart showing an example of the operation of the column AD conversion unit 105 of the image pickup device according to the second embodiment.

[0086] 6 shows an outline of the operation of the column AD conversion unit 105, and the lower part of FIG. 6 shows the details of the operation of the column memory 204.

[0087] First, the operation of the column AD conversion unit 105 will be outlined with reference to the upper part of FIG.

[0088] The operation of AD converting the signals output from the pixels 201 in the first row and outputting the digital data corresponding to the signals as ADCOUT# will be described.

[0089] At time T1, the CPU 101 outputs a horizontal synchronization signal HD to the control unit .

[0090] A first AD conversion of N data is performed from time T1n1 to time T1n2. The obtained N data is designated as N1. The operation of the column AD conversion unit 105 is the same as in the first embodiment.

[0091] From time T1n2, the adder 402 of the column memory 204 operates to perform an addition process of 0 (initial value)+N1. This operation will be described in detail later. At the same time, a second AD conversion of N data is performed from time T1n2 to time T1n3. The obtained N data is designated as N2. The operation of the column AD conversion unit 105 is the same as that of the first embodiment.

[0092] From time T1n3, the adder 402 of the column memory 204 operates to perform the addition process of N1+N2. This operation will be described in detail later.

[0093] A first AD conversion of the S data is performed from time T1s1 to time T1s2. The resulting S data is designated as S1. The AD conversion operation of the S data is the same as the AD conversion operation of the N data.

[0094] From time T1s2, the adder 402 of the column memory 204 operates to perform a subtraction process of S1-N' (N'=N1+N2+1). Details of this operation will be described later. At the same time, from time T1s2 to time T1s3, a second AD conversion is performed on the S data. The resulting S data is designated as S2. The operation of the column AD conversion unit 105 is the same as the AD conversion operation of the N data.

[0095] From time T1s3, the adder 402 of the column memory 204 operates to perform the addition process of (S1-N')+S2. Details of this operation will be described later.

[0096] After this addition process is completed, the output S−N′ (S=S 1 +S 2 , N′=N 1 +N 2 +1) of the addition unit 402 is transferred to the read storage unit 403 .

[0097] Thereafter, the value S-N' of the readout storage unit 403 is held for a period corresponding to the cycle of the horizontal synchronizing signal HD.

[0098] The held value SN′ is read out and sequentially output as a digital signal ADCOUT# of the storage unit 403 via the horizontal transfer unit 106 .

[0099] From time T2, AD conversion is similarly performed on the signals output from the pixels 201 in the second row. At this time, the AD conversion process of the N data in the second row, which starts from time T2n1, and the addition process ((S1-N')+S2) in the first row are executed so that their respective processing periods overlap, thereby making it possible to shorten the period of one frame.

[0100] Next, the operation of the column memory 204 will be described in detail with reference to the lower part of Fig. 6. Here, an example will be described in which N1 data = 3, N2 data = 2, S1 data = 9, S2 data = 10, and S-N' = 13 (S = S1 + S2, N' = N1 + N2 + 1).

[0101] In the following description, as in the first embodiment, Gray code is represented as GXXXX (X is 0 or 1), and binary code is represented as BXXXX (X is 0 or 1).

[0102] At time T1n1b, the Gray code (G0010) of N1 data (3 in this embodiment) is held in the write storage unit 401. The process of adding 0 (initial value)+N will be described below.

[0103] At the first rising edge of CLK, signal SE is low. DI converts the Gray code (G0010) in the write storage unit 401 into binary code (B0011) and stores it. DO does not operate because the clock is stopped by signal SE.

[0104] At the second to fifth rising edges of CLK, the signal SE is High and the signal INV is Low. DI (B0011) and DO (B0000) shift in sync with CLK, and are input to the full adder one bit at a time starting from the least significant bit, and the addition process (DI+DO) is performed.

[0105] As a result, at time T1n1e, DO (3=B0011), which is the result of the addition process of 0 (initial value)+N, is stored.

[0106] At time T1n2b, the Gray code (G0011) of N2 data (2 in this embodiment) is held in the write storage unit 401. The addition process of N1+N2 will be described below.

[0107] Next, at the first rising edge of CLK, the signal SE is Low. DI converts the Gray code (G0011) in the write storage unit 401 to a binary code (B0010) and stores it. DO does not operate because the clock is stopped by the signal SE.

[0108] At the second to fifth rising edges of CLK, the signal SE is High and the signal INV is Low. DI (B0010) and DO (B0011) shift in sync with CLK, and are input to the full adder one bit at a time starting from the least significant bit, and the addition process (DI+DO) is performed.

[0109] As a result, at time T1n2e, DO (5=B0101), which is the result of the addition process of N1+N2, is stored.

[0110] At time T1s1b, the Gray code (G1010) of the S1 data (9 in this embodiment) is held in the write storage unit 401. The subtraction process of S1-(N1+N2+1) will be described below.

[0111] Next, at the first rising edge of CLK, the signal SE is Low. DI converts the Gray code (G1010) in the write storage unit 401 to a binary code (B1001) and stores it. DO does not operate because the clock is stopped by the signal SE.

[0112] At the second to fifth rising edges of CLK, the signal SE is High and the signal INV is High. The signal INV causes the output of DO, i.e., the N data, to be bit-inverted and input to the 1-bit adder. The subtraction process (DI-DO-1) is executed by adding DI (B1001) and (B1010), which is the inverted DO (B0101) while shifting in synchronization with CLK.

[0113] As a result, at time T1s1e, DO (3=B0011), which is the subtraction result of S1-(N1+N2+1), is stored.

[0114] At time T1s2b, the Gray code (G1111) of the S2 data (10 in this embodiment) is held in the write storage unit 401. The addition process of {S1-(N1+N2+1)}+S2 will be described below.

[0115] Next, at the first rising edge of CLK, the signal SE is Low. DI converts the Gray code (G1111) in the write storage unit 401 to a binary code (B1010) and stores it. DO does not operate because the clock is stopped by the signal SE.

[0116] At the second to fifth rising edges of CLK, the signal SE is High and the signal INV is Low. DI (B1010) and DO (B0011) shift in sync with CLK, and are input to the full adder one bit at a time starting from the least significant bit, and the addition process (DI+DO) is performed.

[0117] As a result, at time T1s2e, DO(13=B1101) is saved.

[0118] At time T1s2e, the subtraction process of S-N' (S=S1+S2, N'=N1+N2+1) is completed.

[0119] As described above, in this embodiment, a 1-bit adder is used as a circuit for performing addition processing (for example, N1+N2) and subtraction processing of SN in multi-sampling, thereby suppressing the circuit scale and reducing power consumption.

[0120] Furthermore, by suppressing the circuit scale, it is possible to increase the size of the pixels while keeping the overall size of the imaging device constant, thereby improving image quality.

[0121] Furthermore, the period of one frame is shortened by performing the "AD conversion" and the "addition processing" or "subtraction processing" so that their periods overlap.

[0122] Therefore, in this embodiment, it is possible to provide a column circuit capable of high-speed addition and subtraction processing while suppressing power consumption and circuit scale.

[0123] In this embodiment, an example of multi-sampling with two sampling times has been shown, but the number of sampling times is not limited to two, and the same circuit can be applied to three or more sampling times to perform subtraction processing between accumulated signal data and accumulated noise data. However, the number of bits of the adder 402 and readout storage unit 403 needs to be increased depending on the AD conversion range and the number of sampling times.

[0124] Third embodiment The photoelectric conversion system according to this embodiment will be described with reference to Fig. 7. Fig. 7 is a block diagram showing a schematic configuration of the photoelectric conversion system according to this embodiment.

[0125] The photoelectric conversion devices including the imaging device described in the first and second embodiments can be applied to various photoelectric conversion systems. Examples of the applicable photoelectric conversion systems include digital still cameras, digital camcorders, security cameras, copiers, fax machines, mobile phones, car-mounted cameras, and observation satellites. Camera modules equipped with an optical system such as a lens and an imaging device are also included in the photoelectric conversion systems. FIG. 7 illustrates a block diagram of a digital camera as an example of these.

[0126] 7 includes an image pickup device 1004, which is an example of a photoelectric conversion device, and a lens 1002 that forms an optical image of a subject on the image pickup device 1004. It further includes an aperture 1003 for varying the amount of light passing through the lens 1002, and a barrier 1001 for protecting the lens 1002. The lens 1002 and the aperture 1003 form an optical system that focuses light on the image pickup device 1004. The image pickup device 1004 is a photoelectric conversion device according to any one of the above embodiments, and converts the optical image formed by the lens 1002 into an electrical signal.

[0127] The photoelectric conversion system also has a signal processing unit 1007 which is an image generating unit that generates an image by processing an output signal output from the imaging device 1004. The signal processing unit 1007 performs various corrections and compression as necessary to output image data. The signal processing unit 1007 may be formed on the semiconductor substrate on which the imaging device 1004 is provided, or may be formed on a semiconductor substrate separate from the imaging device 1004.

[0128] The photoelectric conversion system further includes a memory unit 1010 for temporarily storing image data, and an external interface unit (external I / F unit) 1013 for communicating with an external computer or the like. The photoelectric conversion system further includes a recording medium 1012 such as a semiconductor memory for recording or reading out imaging data, and a recording medium control interface unit (recording medium control I / F unit) 1011 for recording or reading out data on the recording medium 1012. The recording medium 1012 may be built into the photoelectric conversion system, or may be removable.

[0129] The photoelectric conversion system further includes an overall control / calculation unit 1009 that performs various calculations and controls the entire digital still camera, and a timing generation unit 1008 that outputs various timing signals to the image capture device 1004 and the signal processing unit 1007. Here, the various timing signals may be input from outside, and the photoelectric conversion system only needs to include at least the image capture device 1004 and the signal processing unit 1007 that processes the output signal output from the image capture device 1004.

[0130] The imaging device 1004 outputs an imaging signal to a signal processing unit 1007. The signal processing unit 1007 performs predetermined signal processing on the imaging signal output from the imaging device 1004, and outputs image data. The signal processing unit 1007 generates an image using the imaging signal.

[0131] In this way, according to this embodiment, it is possible to realize a photoelectric conversion system to which the photoelectric conversion device (imaging device) according to any one of the above embodiments is applied.

[0132] (Fourth embodiment) The photoelectric conversion system and the moving object of this embodiment will be described with reference to Fig. 8. Fig. 8 is a diagram showing the configuration of the photoelectric conversion system and the moving object of this embodiment.

[0133] FIG. 8(a) shows an example of a photoelectric conversion system related to an in-vehicle camera. The photoelectric conversion system 300 has an imaging device 310. The imaging device 310 is the photoelectric conversion device described in any of the above embodiments. The photoelectric conversion system 300 has an image processing unit 312 that performs image processing on a plurality of image data acquired by the imaging device 310, and a parallax acquisition unit 314 that calculates parallax (phase difference of parallax images) from the plurality of image data acquired by the photoelectric conversion system 300. The photoelectric conversion system 300 also has a distance acquisition unit 316 that calculates a distance to an object based on the calculated parallax, and a collision determination unit 318 that determines whether or not there is a possibility of a collision based on the calculated distance. Here, the parallax acquisition unit 314 and the distance acquisition unit 316 are examples of distance information acquisition means that acquire distance information to an object. That is, the distance information is information related to the parallax, the defocus amount, the distance to the object, and the like. The collision determination unit 318 may determine the possibility of a collision using any of these distance information. The distance information acquisition means may be realized by dedicated hardware, a software module, a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), or a combination of these.

[0134] The photoelectric conversion system 300 is connected to a vehicle information acquisition device 320, and can acquire vehicle information such as vehicle speed, yaw rate, and steering angle. The photoelectric conversion system 300 is also connected to a control ECU 330, which is a control unit that outputs a control signal to generate a braking force for the vehicle based on the judgment result of the collision judgment unit 318. The photoelectric conversion system 300 is also connected to an alarm device 340 that issues an alarm to the driver based on the judgment result of the collision judgment unit 318. For example, when the judgment result of the collision judgment unit 318 indicates that there is a high possibility of a collision, the control ECU 330 performs vehicle control to avoid a collision and reduce damage by applying the brakes, releasing the accelerator, suppressing engine output, etc. The alarm device 340 warns the user by sounding an alarm, displaying alarm information on the screen of a car navigation system, etc., or vibrating the seat belt or steering wheel.

[0135] In this embodiment, the surroundings of the vehicle, for example, the front or rear, are imaged by the photoelectric conversion system 300. Fig. 8(b) shows the photoelectric conversion system when imaging the area in front of the vehicle (imaging range 350). The vehicle information acquisition device 320 sends instructions to the photoelectric conversion system 300 or the imaging device 310. This configuration can further improve the accuracy of distance measurement.

[0136] Although the above describes an example of control to prevent collision with other vehicles, the present invention can also be applied to control of automatic driving by following other vehicles, control of automatic driving to prevent deviation from lanes, etc. Furthermore, the photoelectric conversion system is not limited to mobile objects (mobile devices) such as automobiles, but can be applied to mobile objects (mobile devices) such as ships, aircraft, and industrial robots. In addition, the present invention can be applied not only to mobile objects, but also to a wide range of devices that use object recognition, such as intelligent transport systems (ITS).

[0137] [Modified embodiment] The present invention is not limited to the above-described embodiment, and various modifications are possible.

[0138] For example, an example in which part of the configuration of any one of the embodiments is added to another embodiment, or an example in which part of the configuration of another embodiment is substituted therefor, is also included in the embodiments of the present invention.

[0139] In the above-described first and second embodiments, a 1-bit adder is used for the adder 402, but this is not limiting. Any adder having a number of bits less than the number of bits of the counter used for AD conversion may be used, and for example, an M-bit adder (M is a natural number less than K) can be used to obtain the effect of reducing the circuit size.

[0140] Therefore, in the first and second embodiments, a 2-bit adder or a 3-bit adder may be used instead of the 1-bit adder.

[0141] Furthermore, in the first and second embodiments, FFs are used in the addition unit 402, but it is also possible to configure the addition unit 402 using other sequential circuits such as a D latch instead of FFs.

[0142] The photoelectric conversion systems shown in the third and fourth embodiments are examples of photoelectric conversion systems to which the photoelectric conversion device of the present invention can be applied, and the photoelectric conversion systems to which the photoelectric conversion device of the present invention can be applied are not limited to the configurations shown in Figures 7 and 8.

[0143] Furthermore, the circuits in each embodiment of the present invention may be formed on one semiconductor substrate, or may be arranged on two or more semiconductor substrates and these substrates may be bonded together to form a laminated structure. For example, a laminated structure consisting of three or more substrates may be formed by dividing the circuit or adding circuits or functions. For example, in the case of a laminated substrate, the pixel section 104 may be provided on an upper substrate, and the other circuits (control section 102, vertical scanning section 103, column AD conversion section 105, horizontal transfer section 106, data processing section 107, signal output section 108) may be provided on a lower substrate.

[0144] It should be noted that the above-mentioned embodiments are merely examples of the implementation of the present invention, and the technical scope of the present invention should not be interpreted as being limited by these embodiments. In other words, the present invention can be implemented in various forms without departing from its technical concept or main features. [Explanation of symbols]

[0145] 104 Pixel section 105 column AD conversion section 204 row memory 401 Write storage 402 Addition section 403 Readout memory unit 404 Gray-to-binary conversion circuit

Claims

1. A plurality of pixels; a comparator for comparing an output signal of the pixel with a reference signal; a Kbit (K is a natural number) counter that operates in parallel with the comparator; a photoelectric conversion device that converts an output signal of the pixel into a digital signal by using an output of the comparator and an output of the counter, an adder unit that adds a plurality of the digital signals; the adder unit has an M-bit (M is a natural number less than K) serial adder and a multi-bit holding unit that holds a signal output from the serial adder, at least a portion of the time during which the comparator is operating; and at least a part of a period during which the adding unit is performing an adding process.

2. A plurality of pixels; a comparator for comparing an output signal of the pixel with a reference signal; a Kbit (K is a natural number) counter that operates in parallel with the comparator; a photoelectric conversion device that converts an output signal of the pixel into a digital signal by using an output of the comparator and an output of the counter, an adder unit that adds a plurality of the digital signals; the adder unit has an M-bit (M is a natural number less than K) serial adder and a multi-bit holding unit that holds a signal output from the serial adder, 11. A photoelectric conversion device according to claim 10, wherein the serial adder performs addition and subtraction in multi-sampling.

3. the serial adder is a 1-bit adder, 3. The photoelectric conversion device according to claim 1, wherein the adder adds the plurality of digital signals by the 1-bit adder.

4. a storage unit that stores each of the plurality of digital signals as binary data; 4. The photoelectric conversion device according to claim 3, wherein the adder adds the values ​​of the respective binary data stored in the storage unit bit by bit, beginning with the least significant bit.

5. at least a portion of the time during which the comparator is operating; 3. The photoelectric conversion device according to claim 2, wherein at least a part of the period during which the addition process is being performed in the adder overlaps with the period during which the addition process is being performed in the adder.

6. converting the noise data as the output signal from an analog signal to a digital signal, and then converting the signal data as the output signal from an analog signal to a digital signal; 6. The photoelectric conversion device according to claim 1, wherein the effective data for the pixel is obtained by subtracting the digital signal of the noise data from the digital signal of the signal data.

7. 7. The photoelectric conversion device according to claim 6, wherein the subtraction is performed by adding the digital signal of the signal data and the inverted digital signal of the noise data using the adder.

8. a photoelectric conversion device that converts noise data as the output signal from an analog signal to a digital signal a plurality of times, and then converts signal data as the output signal from an analog signal to a digital signal a plurality of times, the adding unit calculates cumulative noise data by adding digital signals of the noise data, and calculates cumulative signal data by adding digital signals of the signal data; 8. The photoelectric conversion device according to claim 1, wherein data is calculated by subtracting the accumulated noise data from the accumulated signal data.

9. 9. The photoelectric conversion device according to claim 8, wherein the subtracted data is calculated by adding the cumulative signal data and the cumulative noise data whose bits have been inverted.

10. Further comprising a first storage unit that reads out the signal output from the adding unit, A photoelectric conversion device as described in any one of claims 6 to 9, characterized in that at least a portion of the period during which a read process is being performed in the first memory unit overlaps with at least a portion of the period during which the comparator is operating in response to the noise data and at least a portion of the period during which the comparator is operating in response to the signal data.

11. Further comprising a first storage unit that reads out the signal output from the adding unit, A photoelectric conversion device as described in any one of claims 6 to 9, characterized in that at least a portion of a period during which a readout process is performed in the first memory unit, at least a portion of a period during which an addition process using the noise data is performed in the addition unit, and at least a portion of a period during which an addition process using the signal data is performed in the addition unit overlap with each other.

12. Further comprising a first storage unit that reads out the signal output from the adding unit, 10. The photoelectric conversion device according to claim 1, wherein the holding unit has a plurality of first holding circuits, and the signal output from the serial adder is input to the first memory unit via the plurality of first holding circuits.

13. Further comprising a second memory unit that inputs a signal to the adder unit, 13. The photoelectric conversion device according to claim 1, wherein the holding unit has a plurality of second holding circuits, and the signal output from the second memory unit is input to the serial adder via the plurality of second holding circuits.

14. A photoelectric conversion device described in any one of claims 1 to 13, characterized in that the Kbit is an integer of 2 or more, and the multiple bits are the Kbit.

15. 15. The photoelectric conversion device according to claim 1, wherein the counter generates a code in which a Hamming distance between adjacent count values ​​is 1 in synchronization with an operation of the comparator.

16. 16. The photoelectric conversion device according to claim 15, wherein the code is a Gray code.

17. 17. The photoelectric conversion device according to claim 16, wherein the digital signal is a signal obtained by converting the gray code into a binary code.

18. The photoelectric conversion device according to any one of claims 1 to 17, a signal processing unit that generates an image using a signal output from the photoelectric conversion device.

19. A moving object comprising the photoelectric conversion device according to any one of claims 1 to 17, A moving body comprising: a control unit that controls the movement of the moving body using a signal output from the photoelectric conversion device.

20. A semiconductor substrate laminated with another semiconductor substrate having pixels, a comparator for comparing an output signal of the pixel with a reference signal; a Kbit (K is a natural number) counter that operates in parallel with the comparator; converting an output signal of the pixel into a digital signal using an output of the comparator and an output of the counter; an adder unit that adds a plurality of the digital signals; the adder unit has an M-bit (M is a natural number less than K) serial adder and a multi-bit holding unit that holds a signal output from the serial adder, at least a portion of the time during which the comparator is operating; and at least a part of a period during which the adding process is being performed in the adding section.

21. A semiconductor substrate laminated with another semiconductor substrate having pixels, a comparator for comparing an output signal of the pixel with a reference signal; a Kbit (K is a natural number) counter that operates in parallel with the comparator; converting an output signal of the pixel into a digital signal using an output of the comparator and an output of the counter; an adder unit that adds a plurality of the digital signals; the adder unit has an M-bit (M is a natural number less than K) serial adder and a multi-bit holding unit that holds a signal output from the serial adder, In multi-sampling, the serial adder performs addition and subtraction processing.

22. the serial adder is a 1-bit adder, 22. The semiconductor substrate according to claim 20, wherein the adding section adds a plurality of the digital signals by the 1-bit adder.

Images