Semiconductor memory device and method for manufacturing the same

Abstract

To provide a semiconductor storage device capable of improving electric characteristics, and a method for manufacturing the semiconductor storage device.SOLUTION: A semiconductor storage device of an embodiment comprises a first substrate, a second substrate, a first laminate, and a second laminate. The first laminate is provided between the first substrate and the second substrate, and includes a first wiring, a first pad connected to the first wiring, and a first insulator. The second laminate is provided between the first laminate and the second substrate, and includes a second wiring, a second pad connected to the second wiring, and a second insulator. The first pad includes a plurality of first electrode parts respectively connected to the first wiring. The first insulator is provided between the plurality of first electrode parts. The plurality of first electrode parts are bonded to the second pad.SELECTED DRAWING: Figure 3

Description

[Technical field]

[0001] FIELD Embodiments of the present invention relate to a semiconductor memory device and a method for manufacturing a semiconductor memory device. [Background technology]

[0002] 2. Description of the Related Art Semiconductor memory devices that are manufactured by bonding a plurality of wafers together are known. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2011-49270 A Summary of the Invention [Problem to be solved by the invention]

[0004] An object of the present invention is to provide a semiconductor memory device and a method for manufacturing a semiconductor memory device that can improve electrical characteristics. [Means for solving the problem]

[0005] A semiconductor memory device according to an embodiment has a first substrate, a second substrate, a first stack, and a second stack. The second substrate is separated from the first substrate in a first direction, which is a thickness direction of the first substrate. The first stack is provided between the first substrate and the second substrate, and includes a first wiring, a first pad connected to the first wiring, and a first insulator. The second stack is provided between the first stack and the second substrate, and includes a second wiring, a second pad connected to the second wiring, and a second insulator. The first pad is A frame portion and a support member provided inside the frame portion, The first and second directions are mutually intersecting. and a plurality of first straight line portions each extending linearly in a third direction intersecting the first direction and the second direction and connected to the frame portion, and a plurality of second straight line portions provided inside the frame portion, separated from each other in the third direction, each extending linearly in the second direction, intersecting with the plurality of first straight line portions, and connected to the frame portion. The first insulator is provided between them. The plurality of first straight portions and the plurality of second straight portions is bonded to the second pad. [Brief description of the drawings]

[0006] [Figure 1] 1 is a cross-sectional view showing a configuration of a semiconductor memory device according to an embodiment. [Diagram 2] 2 is a cross-sectional view showing the vicinity of a memory pillar of the memory cell array according to the embodiment. [Diagram 3] 2 is a cross-sectional view of an embodiment of multiple interface pads. [Figure 4] 1 illustrates an embodiment of an interface pad. [Diagram 5] 4 is a cross-sectional view showing a state of an electrode portion of a first laminate and an electrode portion of a second laminate when the first laminate and the second laminate are attached to each other in the embodiment. FIG. [Figure 6] 1A to 1C are cross-sectional views showing a method for manufacturing a semiconductor memory device according to an embodiment. [Figure 7] 1A to 1C are cross-sectional views showing a method for manufacturing a semiconductor memory device according to an embodiment. [Figure 8] 1A to 1C are cross-sectional views showing a method for manufacturing a semiconductor memory device according to an embodiment. [Figure 9] 1A to 1C are cross-sectional views showing a method for manufacturing a semiconductor memory device according to an embodiment. [Figure 10] FIG. 11 is a cross-sectional view showing a semiconductor memory device according to a modified example of the embodiment. [Figure 11] 11 is an enlarged cross-sectional view showing a region surrounded by line F11 shown in FIG. 10. [Figure 12] FIG. 4 is a cross-sectional view showing the shapes of a plurality of electrode parts in the first embodiment. [Figure 13] FIG. 11 is a cross-sectional view showing the shapes of a plurality of electrode portions according to a second embodiment of the present invention. [Figure 14] FIG. 13 is a cross-sectional view showing the shapes of a plurality of electrode parts according to a third example of the embodiment. [Figure 15] FIG. 13 is a cross-sectional view showing the shapes of a plurality of electrode parts in a fourth example of an embodiment. [Figure 16] FIG. 13 is a cross-sectional view showing the shapes of a plurality of electrode parts in a fifth example of an embodiment. [Figure 17] FIG. 13 is a cross-sectional view showing the shapes of a plurality of electrode parts according to a sixth example of an embodiment. [Figure 18] FIG. 13 is a cross-sectional view showing the shapes of a plurality of electrode parts in a seventh example of an embodiment. [Figure 19]FIG. 13 is a cross-sectional view showing the shapes of a plurality of electrode parts according to an eighth embodiment of the present invention. [Figure 20] FIG. 13 is a cross-sectional view showing the shapes of a plurality of electrode parts in a ninth example of an embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0007] The semiconductor memory device of the embodiment will be described below with reference to the drawings. In the following description, components having the same or similar functions are given the same reference numerals. Duplicate descriptions of those components may be omitted. "Connection" is not limited to physical connection, but also includes electrical connection. In other words, "connection" is not limited to direct contact, but also includes the case where another member is interposed. "Annular" is not limited to a circular ring, but also includes a rectangular ring. "Parallel", "orthogonal", and "same" include "approximately parallel", "approximately orthogonal", and "approximately same", respectively.

[0008] First, the X direction, the Y direction, the +Z direction, and the -Z direction are defined. The X direction and the Y direction are directions along the surface 10a of the first substrate 10 (see FIG. 1) described later. The Y direction is a direction intersecting (for example, perpendicular to) the X direction. The +Z direction and the -Z direction are directions intersecting (for example, perpendicular to) the X direction and the Y direction, and are the thickness direction of the first substrate 10. The +Z direction is a direction from the first substrate 10 toward the second substrate 60 (see FIG. 1). The -Z direction is the opposite direction to the +Z direction. When the +Z direction and the -Z direction are not distinguished, they are simply referred to as the "Z direction." In the following description, the "+Z direction" may be referred to as "up" and the "-Z direction" may be referred to as "down." However, these expressions are for convenience and do not define the direction of gravity. The Z direction is an example of the "first direction." Either the X direction or the Y direction is an example of the "second direction." The other of the X direction and the Y direction is an example of a "third direction."

[0009] (Embodiment) <1. Overall configuration of semiconductor memory device> First, a description will be given of the overall configuration of a semiconductor memory device 1 according to the embodiment. The semiconductor memory device 1 is a non-volatile semiconductor memory device, such as a NAND flash memory.

[0010] FIG. 1 is a cross-sectional view showing the configuration of a semiconductor memory device 1. The semiconductor memory device 1 is, for example, a three-dimensional memory in which a circuit chip 2 and an array chip 3 are bonded together at a bonding surface S. The circuit chip 2 is an example of a "first chip." The array chip 3 is an example of a "second chip." The circuit chip 2 includes a control circuit (logic circuit) that controls the operation of the array chip 3. Such a semiconductor memory device 1 will be described in detail below.

[0011] The semiconductor memory device 1 includes a first substrate 10, a stacked body 20, a second substrate 60, and insulating layers 72 and 73, for example.

[0012] The first substrate 10 is a substrate included in the circuit chip 2. The first substrate 10 is, for example, a silicon substrate. The first substrate 10 has a surface 10a on which the laminate 20 is laminated. The first substrate 10 is provided with a source region and a drain region of a transistor 31 (described later) included in the laminate 20.

[0013] The laminate 20 is located between the first substrate 10 and the second substrate 60 in the Z direction. The laminate 20 includes a first laminate 30 and a second laminate 40. The first laminate 30 is provided on the first substrate 10. The first laminate 30 is located between the first substrate 10 and the second laminate 40 in the Z direction. In this embodiment, the first substrate 10 and the first laminate 30 form a circuit chip 2. The first laminate 30 includes a plurality of transistors 31 (only one is shown in FIG. 1 ), a plurality of contact plugs 32, a plurality of wirings 33, a plurality of pads 34, and a first insulator 35.

[0014] The transistor 31 is provided on the first substrate 10. The transistor 31 is connected to a contact plug 32. The transistor 31 is electrically connected to the memory cell array 41 or an external connection pad 71 via contact plugs 32, 42, wirings 33, 43, and pads 34, 44 included in the stacked body 20. The transistor 31 controls, for example, the memory cell array 41.

[0015] The contact plugs 32, the wiring 33, and the pads 34 electrically connect the multiple transistors 31 and the second stack 40. The contact plugs 32, the wiring 33, and the pads 34 are formed of a conductive material such as copper (Cu) or aluminum (Al). The contact plugs 32 extend in the Z direction and are wiring that electrically connects different layers in the first stack 30. The wiring 33 is wiring that extends in the X direction or the Y direction.

[0016] The pads 34 are connection electrodes provided on the first laminate 30. The pads 34 include internal pads provided inside the first laminate 30 and bonding pads 38 exposed on the surface (bonding surface S) of the first laminate 30. The bonding pads 38 are an example of a "first pad." Among the multiple wirings 33, the wiring 37 connected to the bonding pads 38 is an example of a "first wiring." The bonding pads 38 will be described in detail later.

[0017] The first insulator 35 is provided between the contact plugs 32, the wirings 33, and the pads 34, and electrically insulates these elements from one another. The first insulator 35 is made of, for example, TEOS (tetraethyl orthosilicate (Si(OC2H5)4), silicon oxide (SiO2), silicon nitride (SiN), or the like.

[0018] The second stack 40 is provided on the first stack 30. The second stack 40 is located between the first stack 30 and the second substrate 60 in the Z direction. In this embodiment, the second substrate 60 and the second stack 40 configure the array chip 3. The second stack 40 includes a memory cell array 41, a plurality of contact plugs 42, a plurality of wirings 43, a plurality of pads 44, and a second insulator 45.

[0019] The memory cell array 41 is provided below the second substrate 60. The memory cell array 41 is stacked on the second substrate 60 during manufacturing (see FIG. 8). The memory cell array 41 has a plurality of conductive layers 51 and a plurality of memory pillars P. Each of the plurality of conductive layers 51 and the plurality of memory pillars P is connected to a contact plug 42.

[0020] The conductive layers 51 are formed of, for example, tungsten (W) or polysilicon (Poly-Si) doped with impurities. The conductive layers 51 are stacked in the Z direction with an interlayer insulating film 45b (see FIG. 2) included in the second insulator 45 sandwiched therebetween. Of the conductive layers 51, one or two conductive layers 51 on the first stacked body 30 side (−Z direction side) function as drain side selection gate lines SGD. Of the conductive layers 51, one or two conductive layers 51 on the second substrate 60 side (+Z direction side) function as source side selection gate lines SGS. Of the conductive layers 51, the remaining conductive layers 51 located between the drain side selection gate lines SGD and the source side selection gate lines SGS function as word lines WL.

[0021] The memory pillars P extend in the Z direction and penetrate the drain side select gate line SGD, the word lines WL, and the source side select gate line SGS. A memory cell MC is formed at each of the intersections between the word lines WL and the memory pillars P. As a result, the memory cells MC are three-dimensionally arranged at intervals in the X, Y, and Z directions. The memory cells MC will be described in detail later.

[0022] The contact plugs 42, the wiring 43, and the pads 44 electrically connect the memory cell array 41 or external connection pads 71 ​​(described later) to the first stack 30. The contact plugs 42, the wiring 43, and the pads 44 are formed of a conductive material such as copper or aluminum. The contact plugs 42 extend in the Z direction and are wirings that electrically connect different layers in the second stack 40. The wirings 43 extend in the X direction or the Y direction.

[0023] The pads 44 are connection electrodes provided on the second laminate 40. The pads 44 include internal pads provided inside the second laminate 40 and bonding pads 48 exposed on the surface (bonding surface S) of the second laminate 40. In a state in which the first laminate 30 and the second laminate 40 are laminated, the bonding pads 48 of the second laminate 40 are provided on the bonding pads 38 of the first laminate 30 and bonded to the bonding pads 38 of the first laminate 30. The bonding pads 48 are an example of a "second pad." Among the multiple wirings 43, the wiring 47 connected to the bonding pads 48 is an example of a "second wiring." The bonding pads 48 will be described in detail later.

[0024] The second insulator 45 is provided between the contact plugs 42, the wirings 43, and the pads 44, and electrically insulates these elements from one another. The second insulator 45 is formed of, for example, TEOS, silicon oxide, silicon nitride, or the like.

[0025] The second substrate 60 is provided above the second stack 40. The second substrate 60 is located away from the first substrate 10 in the Z direction. The second substrate 60 is a substrate included in the array chip 3. The second substrate 60 is, for example, a silicon substrate. The second substrate 60 is provided with a conductive region that functions as a source line of the memory cell array 41. The second substrate 60 has a first surface 60a facing the memory cell array 41 and a second surface 60b located on the opposite side to the first surface 60a. The second surface 60b is provided with an external connection pad 71. The external connection pad 71 is provided with an external connection terminal (for example, a solder ball) not shown, and is electrically connected to the outside of the semiconductor memory device 1 via the external connection terminal.

[0026] The insulating layer 72 is provided on the second substrate 60. The insulating layer 73 is provided on the insulating layer 72. The insulating layers 72, 73 are passivation films that protect the stacked body 20. The insulating layer 72 is, for example, a silicon oxide film. The insulating layer 73 is, for example, a polyimide film.

[0027] 2 is a cross-sectional view showing the vicinity of a memory pillar P of a memory cell array 41. As shown in FIG. 2, a plurality of word lines WL are stacked in the Z direction with an interlayer insulating film 45b sandwiched therebetween. The plurality of word lines WL extend in the X direction. The memory cell array 41 has a memory hole MH in which a memory pillar P is provided. The memory pillar P extends in the Z direction inside the memory hole MH and penetrates the plurality of word lines WL.

[0028] The memory pillar P has, for example, a circular or elliptical shape when viewed from the Z direction. The memory pillar P has, from the inside, a core insulator 52, a semiconductor body 53, and a memory film 54.

[0029] The core insulator 52 is a columnar body extending in the Z direction. The core insulator 52 includes, for example, silicon oxide. The core insulator 52 is inside the semiconductor body 53.

[0030] The semiconductor body 53 extends in the Z direction and functions as a channel. The semiconductor body 53 is connected to a conductive region of the second substrate 60 that functions as a source line. The semiconductor body 53 covers the outer circumferential surface of the core insulator 52. The semiconductor body 53 includes, for example, silicon. The silicon is, for example, polysilicon obtained by crystallizing amorphous silicon.

[0031] The memory film 54 extends in the Z direction. The memory film 54 covers the outer peripheral surface of the semiconductor body 53. The memory film 54 is located between the inner surface of the memory hole MH and the outer side surface of the semiconductor body 53. The memory film 54 includes, for example, a tunnel insulating film 55 and a charge storage film 56.

[0032] The tunnel insulating film 55 is located between the charge storage film 56 and the semiconductor body 53. The tunnel insulating film 55 includes, for example, silicon oxide or silicon oxide and silicon nitride. The tunnel insulating film 55 is a potential barrier between the semiconductor body 53 and the charge storage film 56.

[0033] The charge storage film 56 is provided between each of the word lines WL and the interlayer insulating film 45b and the tunnel insulating film 55. The charge storage film 56 includes, for example, silicon nitride. The intersections of the charge storage film 56 and the word lines WL function as memory cells MC. The memory cells MC retain data depending on the presence or absence of charge in the intersections (charge storage portions) of the charge storage film 56 and the word lines WL, or the amount of accumulated charge. The charge storage portions are located between the word lines WL and the semiconductor body 53, and are surrounded by an insulating material.

[0034] A block insulating film 57 and a barrier film 58 may be provided between the word line WL and the interlayer insulating film 45b, and between the word line WL and the memory film 54. The block insulating film 57 is an insulating film that suppresses back tunneling. Back tunneling is a phenomenon in which charges return from the word line WL to the memory film 54. The block insulating film 57 is, for example, a silicon oxide film, a metal oxide film, or a laminated structure film in which a plurality of insulating films are laminated. An example of a metal oxide is aluminum oxide. The barrier film 58 is, for example, a titanium nitride film, or a laminated structure film of titanium nitride and titanium.

[0035] A cover insulating film 59 may be provided between the interlayer insulating film 45b and the charge storage film 56. The cover insulating film 59 contains, for example, silicon oxide. The cover insulating film 59 protects the charge storage film 56 from etching during processing. The cover insulating film 59 may be omitted, or a portion of the cover insulating film 59 may be left between the conductive layer 51 and the charge storage film 56 and used as a block insulating film.

[0036] <2. Structure of the bonding pad> Next, the configuration of the bonding pads 38, 48 will be described. FIG. 3 is a cross-sectional view showing a plurality of bonding pads 38, 48. As shown in FIG. 3, the wiring 37 of the first laminate 30 includes wirings 37A, 37B, 37C that are electrically independent from each other. In the X direction and the Y direction, a first insulator 35 is provided between the wirings 37A, 37B, 37C. This electrically insulates the wirings 37A, 37B, 37C from each other. The wirings 37A, 37B, 37C can be at different potentials from each other. In the following, when the wirings 37A, 37B, 37C are not distinguished from each other, they are referred to as "wirings 37."

[0037] The bonding pads 38 of the first laminate 30 include a bonding pad 38B connected to the wiring 37A, a bonding pad 38C connected to the wiring 37C. A first insulator 35 is provided between the bonding pads 38A, 38B, and 38C in the X and Y directions. The bonding pads 38A, 38B, and 38C can be at different potentials. Hereinafter, when the bonding pads 38A, 38B, and 38C are not to be distinguished from one another, they will be referred to as "bonding pads 38."

[0038] In this embodiment, each of the bond pads 38A, 38B, and 38C has a plurality of electrode portions 81 spaced apart from each other in at least one of the X and Y directions. In the example described here, each of the bond pads 38A, 38B, and 38C has a plurality of electrode portions 81 spaced apart from each other in each of the X and Y directions (see FIG. 4). A first insulator 35 is provided between the plurality of electrode portions 81 in the X and Y directions. In other words, when viewed in the Z direction, a first insulator 35 is provided between the plurality of electrode portions 81 on the bonding surface S. The electrode portion 81 is an example of a "first electrode portion."

[0039] The multiple electrode portions 81 are connected to the wiring 37 independently of one another. That is, the multiple electrode portions 81 included in the same bond pad 38 are connected to the same wiring 37. The multiple electrode portions 81 included in the same bond pad 38 have the same potential. In the example shown in FIG. 3, the multiple electrode portions 81 included in bond pad 38A are connected to wiring 37A. The multiple electrode portions 81 included in bond pad 38B are connected to wiring 37B. The multiple electrode portions 81 included in bond pad 38C are connected to wiring 37C.

[0040] Similarly, the wiring 47 of the second laminate 40 includes wirings 47A, 47B, and 47C that are electrically independent from each other. In the X direction and the Y direction, a second insulator 45 is provided between the wirings 47A, 47B, and 47C. This electrically insulates the wirings 47A, 47B, and 47C from each other. The wirings 47A, 47B, and 47C can be at different potentials from each other. Hereinafter, when the wirings 47A, 47B, and 47C are not to be distinguished from each other, they will be referred to as "wirings 47."

[0041] The bonding pads 48 of the second laminate 40 include a bonding pad 48A connected to the wiring 47A, a bonding pad 48B connected to the wiring 47B, and a bonding pad 48C connected to the wiring 47C. A second insulator 45 is provided between the bonding pads 48A, 48B, and 48C in the X and Y directions. The bonding pads 48A, 48B, and 48C can be at different potentials. Hereinafter, when the bonding pads 48A, 48B, and 48C are not to be distinguished from one another, they will be referred to as "bonding pads 48."

[0042] In this embodiment, each of the bond pads 48A, 48B, 48C has a plurality of electrode parts 82 spaced apart from each other in at least one of the X direction and the Y direction, similar to the bond pads 38A, 38B, 38C of the first laminate 30. In the example described here, each of the bond pads 48A, 48B, 48C has a plurality of electrode parts 82 spaced apart from each other in each of the X direction and the Y direction. In the X direction and the Y direction, a second insulator 45 is provided between the plurality of electrode parts 82. In other words, when viewed in the Z direction, a second insulator 45 is provided between the plurality of electrode parts 82 on the bonding surface S. The electrode part 82 is an example of a "second electrode part."

[0043] The multiple electrode portions 82 are connected to the wiring 47 independently of one another. That is, the multiple electrode portions 82 included in the same bonding pad 48 are connected to the same wiring 47. The multiple electrode portions 82 included in the same bonding pad 48 are at the same potential. In the example shown in FIG. 3, the multiple electrode portions 82 included in bonding pad 48A are connected to wiring 47A. The multiple electrode portions 82 included in bonding pad 48B are connected to wiring 47B. The multiple electrode portions 82 included in bonding pad 48C are connected to wiring 47C.

[0044] The electrode portions 81 of the bonding pad 38 of the first laminate 30 and the electrode portions 82 of the bonding pad 48 of the second laminate 40 are bonded to each other at the bonding surface S. As a result, the bonding pad 38 of the first laminate 30 and the bonding pad 48 of the second laminate 40 are bonded to each other. In the example shown in FIG. 3, the electrode portions 81 of the bonding pad 38 of the first laminate 30 and the electrode portions 82 of the bonding pad 48 of the second laminate 40 are provided in the same manner. "In the same manner" means that the shapes of the electrode portions 81, 82 are the same. In this case, the electrode portions 81 of the bonding pad 38 of the first laminate 30 and the electrode portions 82 of the bonding pad 48 of the second laminate 40 are bonded to each other in a one-to-one correspondence relationship.

[0045] In this embodiment, the wiring 37A and the wiring 47A are electrically connected by bonding the electrode portions 81 of the bonding pad 38A of the first laminate 30 and the electrode portions 82 of the bonding pad 48A of the second laminate 40 to each other. Similarly, the wiring 37B and the wiring 47B are electrically connected by bonding the electrode portions 81 of the bonding pad 38B of the first laminate 30 and the electrode portions 82 of the bonding pad 48B of the second laminate 40 to each other. The wiring 37C and the wiring 47C are electrically connected by bonding the electrode portions 81 of the bonding pad 38C of the first laminate 30 and the electrode portions 82 of the bonding pad 48C of the second laminate 40 to each other.

[0046] In this embodiment, the bond pads 38A, 38B, 38C, 48A, 48B, and 48C have the same shape as each other. Therefore, the following will describe in detail one bond pad 38 of the first stack 30. The bond pad 48 of the second stack 40 has the same structure as described below.

[0047] 4 is a diagram showing the bonding pad 38. FIG. 4 shows the bonding pad 38 in a state before the first laminate 30 and the second laminate 40 are bonded together. In this embodiment, the plurality of electrode parts 81 includes, for example, nine electrode parts 81 arranged in a 3×3 matrix shape divided in the X direction and the Y direction. That is, the plurality of electrode parts 81 includes a plurality of electrode parts 81 spaced apart from each other and arranged at equal intervals in the X direction. Similarly, the plurality of electrode parts 81 includes a plurality of electrode parts 81 spaced apart from each other and arranged at equal intervals in the Y direction. However, the number and arrangement of the electrode parts 81 are not limited to the above example.

[0048] The electrode portion 81 has, for example, a rectangular shape along the X direction and the Y direction. In the example shown in Fig. 4, the width W1 of the electrode portion 81 in the X direction is the same as the distance L1 between two adjacent electrode portions 81 in the X direction. Similarly, the width W2 of the electrode portion 81 in the Y direction is the same as the distance L2 between two adjacent electrode portions 81 in the Y direction. The distances L1, L2 between two adjacent electrode portions 81 are smaller than the distance L3 (see Fig. 3) between two adjacent bond pads 38.

[0049] When viewed from the Z direction, the inner region of an imaginary line IL that surrounds the multiple electrode portions 81 along the edges of the multiple electrode portions 81A that are located at the outermost positions with respect to the center of the bonding pad 38 among the multiple electrode portions 81 included in one bonding pad 38 is defined as a "pad region R," the total area of ​​the multiple electrode portions 81 in the pad region R is smaller than the area of ​​the first insulator 35 in the pad region R. In other words, the multiple electrode portions 81 are arranged apart from each other at a relatively large pitch.

[0050] In this embodiment, each electrode portion 81 has an electrode body 91 and a connection portion 92. The electrode body 91 is exposed on the bonding surface S (see FIG. 3) and is bonded to the bonding pad 48 of the second laminate 40. The connection portion 92 is located between the electrode body 91 and the wiring 37 and connects the electrode body 91 and the wiring 37. The connection portion 92 is thinner than the electrode body 91. For example, the width W4 of the connection portion 92 in the X direction is smaller than the width W3 of the electrode body 91 in the X direction. Similarly, the width of the connection portion 92 in the Y direction is smaller than the width of the electrode body 91 in the Y direction. The electrode body 91 of each electrode portion 81 is connected to the wiring 37 via the corresponding connection portion 92.

[0051] From another perspective, each electrode portion 81 has a conductive portion body 95 and a barrier metal layer 96. The conductive portion body 95 forms a main portion of each electrode portion 81. The barrier metal layer 96 is provided between the conductive portion body 95 and the first insulator 35 in the X direction and the Y direction. The barrier metal layer 96 is a metal layer that suppresses the conductive material (e.g., copper or aluminum) contained in the conductive portion body 95 from diffusing into the first insulator 35. The conductive portion body 95 and the barrier metal layer 96 are each provided in both the electrode body 91 and the connection portion 92.

[0052] 4, before the first laminate 30 and the second laminate 40 are bonded together, the end E of each electrode portion 81 protrudes in the +Z direction with respect to the surface 35a on the +Z direction side of the first insulator 35. The end E of each electrode portion 81 has a bowl-shaped recess RS in the -Z direction.

[0053] The above describes the bonding pads 38 of the first laminate 30. For the bonding pads 48 of the second laminate 40, in the above description, "bonding pads 38" can be read as "bonding pads 48," "wiring 37" can be read as "wiring 47," "+Z direction" can be read as "-Z direction," and "-Z direction" can be read as "+Z direction."

[0054] 5 is a cross-sectional view showing the state of the electrode portion 81 of the first laminate 30 and the electrode portion 82 of the second laminate 40 when the first laminate 30 and the second laminate 40 are bonded together. In this embodiment, when the first laminate 30 and the second laminate 40 are bonded together, the first laminate 30 and the second laminate 40 are heated, and the second laminate 40 is pressed toward the first laminate 30. That is, the second laminate 40 is pressed toward the first laminate 30 in a state in which the electrode portion 81 of the first laminate 30 and the electrode portion 82 of the second laminate 40 are in contact with each other.

[0055] As a result, the electrode portion 81 of the first laminate 30 and the electrode portion 82 of the second laminate 40 are each deformed. That is, the electrode portion 81 of the first laminate 30 is deformed so that it does not protrude from the surface 35a of the first insulator 35. Furthermore, the recess RS of the end portion E of the electrode portion 81 of the first laminate 30 is filled and disappears (or becomes smaller). Similarly, the electrode portion 82 of the second laminate 40 is deformed so that it does not protrude from the surface 45a of the second insulator 45. Furthermore, the recess RS of the end portion of the electrode portion 82 of the second laminate 40 is filled and disappears (or becomes smaller).

[0056] <3. Manufacturing method of semiconductor memory device> Next, a method for manufacturing the semiconductor memory device 1 will be described. 6 to 9 are cross-sectional views showing a manufacturing method of the semiconductor memory device 1.

[0057] FIG. 6 shows the manufacturing stages of the circuit chip 2. The circuit chip 2 is manufactured as a part of the circuit wafer CW. The circuit wafer CW includes a plurality of circuit chips 2. The circuit wafer CW is obtained by forming a first laminate 30 on a first substrate 10. The first laminate 30 includes a transistor 31, a contact plug 32, a wiring 33, a pad 34, and a first insulator 35. These are formed for each layer. The circuit wafer CW is formed by repeating the film formation of each of these layers and processing by photolithography or the like. The film formation method and processing method other than the bonding pad 38 can be a publicly known method. A plurality of bonding pads 38 are exposed on the bonding surface S1 of the circuit wafer CW opposite to the first substrate 10. This completes the circuit wafer CW.

[0058] The method of forming bond pads 38 will now be described in detail. Fig. 7 shows details of a manufacturing stage of the bond pad 38. First, as shown in (a) of Fig. 7, a part of the first insulator 35 is provided on the wiring 37. The first insulator 35 provided on the wiring 37 is formed of, for example, silicon oxide (SiO2).

[0059] Next, the protective layer 101 is provided on the first insulator 35. The protective layer 101 is formed of a material different from that of the first insulator 35. The protective layer 101 is formed of, for example, silicon nitride (SiN). The thickness T1 of the protective layer 101 is set to be larger than, for example, the recess amount K of the recess RS caused by dishing in chemical mechanical polishing (see (c) in FIG. 7). For example, the thickness T1 of the protective layer 101 (for example, the thickness in the Z direction) is larger than the thickness T2 of the barrier metal layer 96 (for example, the thickness in the X direction).

[0060] 7(b), a resist pattern is formed by a photo engraving process (PEP), and the protective layer 101 and the first insulator 35 are etched by reactive ion etching (RIE). As a result, a plurality of holes 102 are formed at positions where a plurality of electrode portions 81 will be provided in a later process.

[0061] 7(c), a conductive layer 103a that will become the barrier metal layer 96 is formed on the inner surface of the hole 102. Thereafter, a conductive material (e.g., a metal material such as copper or aluminum) is embedded inside the hole 102 to form a conductive portion 103b that will become the conductive portion main body 95. This forms the conductive portion 103 that fills the hole 102. The conductive portion 103 is a conductive portion that will become the plurality of electrode portions 81.

[0062] Next, the conductive portion 103 is planarized by chemical mechanical polishing (CMP) using the protective layer 101 as a stop layer. The CMP is performed, for example, in an endpoint mode in which polishing is terminated by detecting the surface of the protective layer 101. As a result, a plurality of electrode portions 81 are formed from the conductive portion 103. At this time, recesses RS are formed on the surface of the upper end of each electrode portion 81 by dishing.

[0063] Next, as shown in (d) of FIG. 7, the protective layer 101 is removed. When the protective layer 101 is made of silicon nitride, the protective layer 101 is removed by using, for example, phosphoric acid. This exposes the surface 35a of the first insulator 35. The surface 35a of the first insulator 35 forms a bonding surface S1 to be bonded to the array chip 3. Ends E, which are the upper ends of the electrode portions 81, protrude upward from the surface 35a (bonding surface S1) of the first insulator 35. This completes the bonding pads 38.

[0064] 8 shows a manufacturing stage of the array chip 3. The array chip 3 is manufactured as a part of an array wafer AW. The array wafer AW includes a plurality of array chips 3. The array wafer AW shown in FIG. 8 is in a state before being bonded to the circuit wafer CW, and is upside down with respect to the array chip 3 shown in FIG.

[0065] The array wafer AW is obtained by forming the second laminate 40 on the second substrate 60. The second laminate 40 includes a memory cell array 41, contact plugs 42, wiring 43, pads 44, and a second insulator 45. These are formed for each layer. The array wafer AW is formed by repeating the film formation of each of these layers and processing by photolithography or the like. The film formation method and processing method other than the bonding pads 48 can be known methods. A plurality of bonding pads 48 are exposed on the bonding surface S2 of the array wafer AW opposite to the second substrate 60. The method of forming the bonding pads 48 is the same as the method of forming the bonding pads 38 described with reference to FIG. 7, for example. In this way, the circuit wafer CW is completed.

[0066] 9 shows the step of bonding the circuit wafer CW and the array wafer AW. Specifically, the circuit wafer CW and the array wafer AW are heated, and the bonding surface S1 of the circuit wafer CW and the bonding surface S2 of the array wafer AW are placed face to face (i.e., the bonding pads 38 of the first laminate 30 and the bonding pads 48 of the second laminate 40 are placed face to face), and the circuit wafer CW and the array wafer AW are bonded together by mechanical pressure. This bonds the first insulator 35 and the second insulator 45 together.

[0067] 5, the bonding pads 38 of the circuit wafer CW and the bonding pads 48 of the array wafer AW abut against each other in a state in which the end E of the electrode portion 81 of the bonding pad 38 protrudes from the surface 35a of the first insulator 35 and the end E of the electrode portion 82 of the bonding pad 48 protrudes from the surface 45a of the second insulator 45. Then, due to mechanical pressure, the electrode portions 81 and 82 of the bonding pads 38 and 48, which are in abutting against each other, are deformed, and the recesses RS formed in the electrode portions 81 and 82 by dishing in the previous process are filled in and disappear (or become smaller).

[0068] Next, the array wafer AW and the circuit wafer CW are annealed at 400° C. This bonds the electrode portion 81 of the bonding pad 38 to the electrode portion 82 of the bonding pad 48. This forms a bonded body 111 in which the circuit wafer CW and the array wafer AW are bonded together.

[0069] Next, the second substrate 60 is thinned. The second substrate 60 is thinned by, for example, CMP. Next, the external connection pads 71 ​​and the insulating layers 72 and 73 are provided on the second substrate 60 by a known method. Then, the bonded body 111 is cut along dicing lines (not shown). As a result, the bonded body 111 is divided into a plurality of chips (semiconductor memory devices 1). As a result, the semiconductor memory device 1 is obtained.

[0070] <4. Advantages> For comparison, consider a case where the bond pad is configured with one relatively large electrode portion. In such a comparative example configuration, if large dishing occurs at the edge of the bond pad due to CMP or other reasons, a space may remain between the two bond pads that are bonded together. In this case, a void is formed at the bonding surface of the two bond pads. In this case, the electrical resistance of the bond pad becomes high.

[0071] Furthermore, these voids may move (aggregate) to the connection between the bond pad and the wiring due to stress migration at room temperature. In this case, there is a possibility that the connection between the bond pad and the wiring may become disconnected. On the other hand, if the annealing temperature is increased to increase the thermal expansion in order to bond the two bond pads more securely, the metal contained in the barrier metal layer may diffuse into the insulator, which may reduce the barrier properties of the barrier metal layer.

[0072] On the other hand, in this embodiment, the bonding pad 38 includes a plurality of electrode parts 81 that are spaced apart from each other in the X direction and each connected to the wiring 37. The first insulator 35 is provided between the plurality of electrode parts 81. With this configuration, the bonding pad 38 is divided into a plurality of small electrode parts 81, so that large dishing is unlikely to occur in each electrode part 81, and the depression amount K of the recess RS is small. Therefore, a space is unlikely to remain between the two bonding pads 38, 48 that are bonded together, and a void is unlikely to occur on the bonding surface of the two bonding pads. As a result, the electrical resistance of the bonding pads 38, 48 is unlikely to be high. This can improve the electrical characteristics of the semiconductor memory device 1.

[0073] Moreover, in this embodiment, the multiple electrode portions 81 are connected independently to the wiring 37. With this configuration, the stress acting on the bonding pad 38 can be dispersed among the multiple electrode portions 81. This can reduce the probability of disconnection due to stress migration.

[0074] In this embodiment, during the manufacture of the semiconductor memory device 1, a protective layer 101 is provided on the first insulator 35. After that, chemical mechanical polishing is performed using the protective layer 101 as a stop layer to form the plurality of electrode portions 81. Then, the protective layer 101 is removed. As a result, the ends E of the plurality of electrode portions 81 are protruded from the first insulator 35. Then, the plurality of electrode portions 81 of the bonding pad 38 are abutted against the bonding pad 48 in a state in which the ends E of the plurality of electrode portions 81 protrude from the first insulator 35. According to this configuration, the two bonding pads 38, 48 are bonded in a state in which the ends E of the electrode portions 81 protrude from the first insulator 35, so that the recesses RS formed by dishing are filled by the ends E of the electrode portions 81 protruding from the first insulator 35. For this reason, a space is unlikely to remain between the two bonding pads 38, 48 that are bonded together, and voids are unlikely to occur on the bonding surfaces of the two bonding pads 38, 48. This can improve the electrical characteristics of the semiconductor memory device 1.

[0075] Furthermore, when chemical mechanical polishing is performed using the protective layer 101 as a stop layer, the dishing-induced recesses RS are formed at a higher position relative to the surface 35a of the first insulator 35 than when the protective layer 101 is not provided. That is, the electrode parts 81 are formed with the interface where the dishing is formed raised. Therefore, when viewed from the surface 35a of the first insulator 35 as a reference, large dishing is unlikely to occur in the electrode parts 81, and the recess amount K of the recesses RS is small. For this reason, a space is unlikely to remain between the two bond pads 38, 48 that are bonded together, and voids are unlikely to occur on the bonded surfaces of the two bond pads 38, 48. This can improve the electrical characteristics of the semiconductor memory device 1.

[0076] In this embodiment, when the region surrounding the plurality of electrode portions 81 along the edge of the plurality of electrode portions 81A located at the outermost position with respect to the center of the bonding pad 38 among the plurality of electrode portions 81 as viewed from the Z direction is defined as the pad region R, the total area of ​​the plurality of electrode portions 81 in the pad region R is smaller than the area of ​​the first insulator 35 in the pad region R. With this configuration, the bonding pad 38 is divided into a plurality of smaller electrode portions 81, so that it is even more difficult for large dishing to occur in each electrode portion 81. This can improve the electrical characteristics of the semiconductor memory device 1.

[0077] In this embodiment, the multiple electrode portions 81 include multiple electrode portions 81 spaced apart in the X direction and multiple electrode portions 81 spaced apart in the Y direction. With this configuration, the bond pad 38 is divided into small electrode portions 81 in multiple directions, making it even more difficult for large dishing to occur in each electrode portion 81. This can improve the electrical characteristics of the semiconductor memory device 1.

[0078] In this embodiment, each of the multiple electrode portions 81 has an electrode body 91 and a connection portion 92 located between the electrode body 91 and the wiring 37. A width W4 of the connection portion 92 in the X direction is smaller than a width W3 of the electrode body 91 in the X direction. With this configuration, even in a configuration in which the connection portion 92 is narrow and therefore prone to breakage due to stress migration, the multiple electrode portions 81 are connected to the wiring 37 independently of one another, so that the probability of breakage due to stress migration can be reduced.

[0079] <5. Modifications> The following describes a modified example. The configuration of this modified example is the same as that of the above-described embodiment except for the configuration described below.

[0080] FIG. 10 is a cross-sectional view showing a semiconductor memory device 1 of a modified example. FIG. 11 is a cross-sectional view showing an enlarged view of a region surrounded by line F11 shown in FIG. 10. In this modified example, the width W1A of each electrode portion 81 of the bonding pad 38 of the first laminate 30 in the X direction is larger than the distance L1B between two adjacent electrode portions 82 of the bonding pad 48 of the second laminate 40 in the X direction. Similarly, the width W1B of each electrode portion 82 of the bonding pad 48 of the second laminate 40 in the X direction is larger than the distance L1A between two adjacent electrode portions 81 of the bonding pad 38 of the first laminate 30 in the X direction. This is also true for the Y direction.

[0081] In this modification, even if the bonding pads 48 of the second laminate 40 are misaligned with respect to the bonding pads 38 of the first laminate 30, a part of the electrode portion 81 of the bonding pad 38 and a part of the electrode portion 82 of the bonding pad 48 reliably face each other in the Z direction, and the electrode portion 81 of the bonding pad 38 and the electrode portion 82 of the bonding pad 48 are reliably connected to each other. This improves the electrical characteristics of the semiconductor memory device 1.

[0082] <6. Examples> Below, several examples of the shapes of the electrode portions 81, 82 of the bonding pads 38, 48 will be described. Below, the shape of the electrode portion 81 of the bonding pad 38 of the first laminate 30 will be described as a representative. The shape of the electrode portion 82 of the bonding pad 48 of the second laminate 40 is similar. Note that the shapes of the electrode portions 81, 82 are not limited to the contents of the examples described below.

[0083] <6.1 First Example> Fig. 12 is a cross-sectional view showing the shape of a plurality of electrode parts 81 in the first embodiment. In the first embodiment, the plurality of electrode parts 81 are arranged in a matrix shape spaced apart from each other in the X direction and the Y direction. In the example shown in Fig. 12, 8 x 8 = 64 electrode parts 81 are provided.

[0084] <6.2 Second Example> FIG. 13 is a cross-sectional view of the shape of the plurality of electrode portions 81 of the second embodiment. In the second embodiment, the bonding pad 38 includes a frame portion 121, a plurality of first straight portions 122, and a plurality of second straight portions 123. The plurality of first straight portions 122 and the plurality of second straight portions 123 are provided inside the frame portion 121. The plurality of first straight portions 122 are spaced apart from each other in the X direction and each extend in the Y direction. A first insulator 35 is provided between the plurality of first straight portions 122 in the X direction. On the other hand, the plurality of second straight portions 123 are spaced apart from each other in the Y direction and each extend in the X direction. A first insulator 35 is provided between the plurality of second straight portions 123 in the Y direction. The plurality of first straight portions 122 and the plurality of second straight portions 123 intersect with each other.

[0085] In this embodiment, a plurality of electrode portions 81 spaced apart from one another in the X direction are formed by a plurality of first straight portions 122. Similarly, a plurality of electrode portions 81 spaced apart from one another in the Y direction are formed by a plurality of second straight portions 123. In this specification, "spaced apart from one another" is not limited to being completely independent as in the first embodiment, but also includes being connected to one another via another portion (for example, frame portion 121).

[0086] In the second embodiment, the first linear portion 122 has a length that spans (straddles) at least two or more of the multiple second linear portions 123 in the extension direction (Y direction) of the first linear portion 122. With this configuration, even if a positional deviation occurs between the bond pad 38 and the bond pad 48 in the Y direction, the bond pad 38 and the bond pad 48 can be more reliably connected to each other. Similarly, the second linear portion 123 has a length that spans (straddles) at least two or more of the multiple first linear portions 122 in the extension direction (X direction) of the second linear portion 123. With this configuration, even if a positional deviation occurs between the bond pad 38 and the bond pad 48 in the X direction, the bond pad 38 and the bond pad 48 can be more reliably connected to each other.

[0087] <6.3 Third Example> 14 is a cross-sectional view of the shape of the plurality of electrode portions 81 in the third embodiment. In the third embodiment, the bonding pad 38 includes a plurality of straight portions 131. The plurality of straight portions 131 are spaced apart from each other in the Y direction and extend in the X direction. A first insulator 35 is provided between the plurality of straight portions 131 in the Y direction. In this embodiment, the plurality of straight portions 131 form a plurality of electrode portions 81 spaced apart from each other in the Y direction. With this configuration, even if a positional deviation occurs between the bonding pad 38 and the bonding pad 48 in the X direction, the bonding pad 38 and the bonding pad 48 can be more reliably connected to each other.

[0088] <6.4 Fourth Example> 15 is a cross-sectional view of the shape of the plurality of electrode portions 81 in the fourth embodiment. In the third embodiment, the bonding pad 38 includes a plurality of straight portions 141. The plurality of straight portions 141 are spaced apart from each other in the X direction and extend in the Y direction. A first insulator 35 is provided between the plurality of straight portions 141 in the X direction. In this embodiment, the plurality of straight portions 141 form a plurality of electrode portions 81 that are spaced apart from each other in the X direction. With this configuration, even if a positional deviation occurs between the bonding pad 38 and the bonding pad 48 in the Y direction, the bonding pad 38 and the bonding pad 48 can be more reliably connected to each other.

[0089] <6.5 Fifth Example> 16 is a cross-sectional view of the shape of the multiple electrode portions 81 of the fifth embodiment. In the fifth embodiment, the bonding pad 38 includes a frame portion 151 and multiple straight portions 152. The multiple straight portions 152 are provided inside the frame portion 151. The multiple straight portions 152 are spaced apart from each other in the Y direction and each extend in the X direction. A first insulator 35 is provided between the multiple straight portions 152 in the Y direction. In this embodiment, the multiple straight portions 152 form multiple electrode portions 81 that are spaced apart from each other in the Y direction.

[0090] <6.6 Sixth Example> 17 is a cross-sectional view of the shape of the multiple electrode portions 81 of the sixth embodiment. In the sixth embodiment, the bonding pad 38 includes a frame portion 161 and multiple straight portions 162. The multiple straight portions 162 are provided inside the frame portion 161. The multiple straight portions 162 are spaced apart from each other in the X direction and extend in the Y direction. A first insulator 35 is provided between the multiple straight portions 162 in the X direction. In this embodiment, the multiple straight portions 162 form multiple electrode portions 81 that are spaced apart from each other in the X direction.

[0091] <6.7 Seventh Example> FIG. 18 is a cross-sectional view of the shape of the plurality of electrode parts 81 in the seventh embodiment. In the seventh embodiment, the bonding pad 38 includes a plurality of frame parts 171. The plurality of frame parts 171 are annular in shape with different sizes and are arranged concentrically. A first insulator 35 is provided between the plurality of frame parts 171 in the X direction and the Y direction. In this embodiment, the plurality of annular electrode parts 81 are formed by the plurality of frame parts 171. From another perspective, the plurality of electrode parts 81 are formed by the linear parts 171a along the Y direction included in the plurality of frame parts 171, which are spaced apart from each other in the X direction. Similarly, the plurality of electrode parts 81 are formed by the linear parts 171b along the X direction included in the plurality of frame parts 171, which are spaced apart from each other in the Y direction. When the bonding pad 38 includes both a portion extending in the Y direction and a portion extending in the X direction, the bonding pad 38 and the bonding pad 48 are more likely to be connected reliably even if a positional deviation occurs between the bonding pad 38 and the bonding pad 48 in either the X direction or the Y direction.

[0092] <6.8 Eighth Example> Fig. 19 is a cross-sectional view showing the shapes of the multiple electrode portions 81, 82 of the eighth embodiment. (a) in Fig. 19 shows the multiple electrode portions 81 of the bonding pad 38 of the first stack 30. (b) in Fig. 19 shows the multiple electrode portions 82 of the bonding pad 48 of the second stack 40.

[0093] In this embodiment, the multiple electrode portions 81 of the bonding pad 38 of the first laminate 30 are provided in a first mode. The first mode of this embodiment is, for example, the same mode as the third embodiment (FIG. 14). On the other hand, the multiple electrode portions 82 of the bonding pad 48 of the second laminate 40 are provided in a second mode different from the above-mentioned first mode. "Different mode" means that the shapes of the multiple electrode portions 81, 82 are different. The second mode of this embodiment is, for example, the same mode as the fourth embodiment (FIG. 15).

[0094] 19(c) shows a state in which the multiple electrode portions 81 of the bonding pad 38 and the multiple electrode portions 82 of the bonding pad 48 are overlapped (bonded together). In the example shown in Fig. 19, the direction in which the multiple electrode portions 81 of the bonding pad 38 move away from each other (Y direction) is different from the direction in which the multiple electrode portions 82 of the bonding pad 48 move away from each other (X direction).

[0095] At least a portion of each electrode portion 81 of the bonding pad 38 extends linearly across (straddling) two or more electrode portions 82 in the direction (X direction) in which the electrode portions 82 of the bonding pad 48 move away from one another. On the other hand, at least a portion of each electrode portion 82 of the bonding pad 48 extends linearly across (straddling) two or more electrode portions 81 in the direction (Y direction) in which the electrode portions 81 of the bonding pad 38 move away from one another. With this configuration, even if a positional deviation occurs between the bonding pad 38 and the bonding pad 48 in either the X direction or the Y direction, the bonding pad 38 and the bonding pad 48 are more reliably connected to each other.

[0096] <6.9 Ninth Example> Fig. 20 is a cross-sectional view showing the shapes of the multiple electrode portions 81, 82 of the ninth embodiment. (a) in Fig. 20 shows the multiple electrode portions 81 of the bonding pad 38 of the first stack 30. (b) in Fig. 20 shows the multiple electrode portions 82 of the bonding pad 48 of the second stack 40.

[0097] In this embodiment, the multiple electrode portions 81 of the bonding pads 38 of the first laminate 30 are provided in a first manner. The first manner of this embodiment is, for example, the same as the first embodiment (FIG. 12). On the other hand, the multiple electrode portions 82 of the bonding pads 48 of the second laminate 40 are provided in a second manner different from the above-mentioned first manner. The second manner of this embodiment is, for example, the same as the seventh embodiment (FIG. 18).

[0098] 20(c) shows a state in which the electrode portions 81 of the bonding pad 38 and the electrode portions 82 of the bonding pad 48 are overlapped (attached). In the example shown in FIG. 20, the electrode portions 81 of the bonding pad 38 are spaced apart from each other in the X direction and the Y direction. On the other hand, at least a portion (e.g., linear portion 171b) of each electrode portion 82 of the bonding pad 48 extends linearly across (straddling) two or more electrode portions 81 in the direction (X direction) in which the electrode portions 81 of the bonding pad 38 are spaced apart from each other. At least a portion (e.g., linear portion 171a) of each electrode portion 82 of the bonding pad 48 extends linearly across (straddling) two or more electrode portions 81 in the direction (Y direction) in which the electrode portions 81 of the bonding pad 38 are spaced apart from each other. With this configuration, even if a positional deviation occurs between bond pad 38 and bond pad 48 in either the X direction or the Y direction, bond pad 38 and bond pad 48 can be more reliably connected to each other.

[0099] The above describes the embodiments, modifications, and some examples. However, the embodiments, modifications, and examples are not limited to the above examples. For example, the electrode portion 81 of the bond pad 38 of any one of the first to seventh examples may be bonded to the electrode portion 82 of the bond pad 48 of any other one of the first to seventh examples. In all the above descriptions, the shapes of the bond pad 38 and the bond pad 48 may be reversed. In the above embodiment, the bond pad 38 is divided into a plurality of electrode portions 81, and the bond pad 48 is divided into a plurality of electrode portions 82. Instead of this, the bond pad 38 may be divided into a plurality of electrode portions 81, and the bond pad 48 may be one large pad, or the bond pad 48 may be divided into a plurality of electrode portions 82, and the bond pad 38 may be one large pad.

[0100] According to at least one of the embodiments described above, the semiconductor memory device has a first laminate and a second laminate. The first laminate includes a first wiring, a first pad connected to the first wiring, and a first insulator. The second laminate includes a second wiring, a second pad connected to the second wiring, and a second insulator. The first pad includes a plurality of first electrode parts spaced apart from each other and connected to the first wiring. A first insulator is provided between the plurality of first electrode parts. The plurality of first electrode parts are joined to the second pad. According to this configuration, it is possible to provide a semiconductor memory device and a method for manufacturing a semiconductor memory device that can improve electrical characteristics.

[0101] Although some embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These embodiments can be implemented in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included in the scope of the invention and its equivalents described in the claims, as well as in the scope and spirit of the invention. [Explanation of symbols]

[0102] 1...semiconductor memory device, 10...first substrate, 30...first laminate, 35...first insulator, 37...wiring (first wiring), 38...bonding pad (first pad), 40...second laminate, 45...second insulator, 47...wiring (second wiring), 48...bonding pad (second pad), 81...electrode portion (first electrode portion), 82...electrode portion (second electrode portion), 101...protective layer, R...pad area.

Claims

1. A first substrate; a second substrate spaced apart from the first substrate in a first direction, which is a thickness direction of the first substrate; a first laminate provided between the first substrate and the second substrate, the first laminate including a first wiring, a first pad connected to the first wiring, and a first insulator; a second laminate provided between the first laminate and the second substrate, the second laminate including a second wiring, a second pad connected to the second wiring, and a second insulator; Equipped with The first pad is A frame portion and a plurality of first straight line portions provided inside the frame portion, spaced apart from each other in a second direction intersecting with the first direction, each extending linearly in a third direction intersecting with the first direction and the second direction and connected to the frame portion; a plurality of second straight line portions provided inside the frame portion, spaced apart from one another in the third direction, each extending linearly in the second direction, intersecting with the plurality of first straight line portions, and connected to the frame portion; Including, the first insulator is provided between the plurality of first straight portions and between the plurality of second straight portions; the plurality of first linear portions and the plurality of second linear portions are joined to the second pad; Semiconductor memory device.

2. the second pad includes a plurality of second electrode portions spaced apart from each other in the second direction or the third direction and each connected to the second wiring, The second insulator is provided between the second electrode portions, The second electrode portions are joined to the first linear portions and the second linear portions.

2. The semiconductor memory device according to claim 1.

3. When a region surrounding the frame portion along the frame portion as viewed from the first direction is defined as a pad region, a total area of ​​the spaces between the plurality of first straight line portions and the plurality of second straight line portions in the pad region is smaller than an area of ​​the first insulator in the pad region.

3. The semiconductor memory device according to claim 1.

4. The second pad includes a plurality of electrode portions spaced apart from each other in the second direction and the third direction; the first linear portions and the second linear portions of the first pad are joined to the electrode portions of the second pad; 4. The semiconductor memory device according to claim 1, wherein the first and second memory cells are connected to each other.

5. The second pad includes a plurality of electrode portions each having a concentric ring shape, the first linear portions and the second linear portions of the first pad are joined to the electrode portions of the second pad; 4. The semiconductor memory device according to claim 1, wherein the first and second memory cells are connected to each other.

6. forming a first laminate on a first substrate, the first laminate including a first wiring, a first pad connected to the first wiring, and a first insulator; forming a second laminate on a second substrate, the second laminate including a second wiring, a second pad connected to the second wiring, and a second insulator; the first laminate and the second laminate are attached to each other with the first pad and the second pad facing each other, and the first pad and the second pad are joined together; The first pad is A frame portion and a plurality of first linear portions provided inside the frame portion, spaced apart from each other in a second direction intersecting a first direction that is a thickness direction of the first substrate, and each extending linearly in a third direction intersecting the first direction and the second direction and connected to the frame portion; a plurality of second straight line portions provided inside the frame portion, spaced apart from one another in the third direction, each extending linearly in the second direction, intersecting with the plurality of first straight line portions, and connected to the frame portion; Including, the first insulator is provided between the plurality of first straight portions and between the plurality of second straight portions; the first linear portions and the second linear portions are joined to the second pad; A method for manufacturing a semiconductor memory device.

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