Semiconductor Device

Abstract

To provide a technique which can reduce load of software diagnosis.SOLUTION: A semiconductor device according to the present invention has a syndrome generator circuit configured to generate data and a syndrome code based on an error correction code for the data, an error determination circuit configured to determine a bit error based on the syndrome code to output a bit error determination signal indicative of detection of a single bit error, and a multibit error detection circuit configured to determine, based on the bit error determination signal, an address of the data with the single bit error and the syndrome code generated upon detection of the bit error, whether or not the single bit error is a multibit error.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present disclosure relates to a semiconductor device and is applicable to, for example, a semiconductor device including an error detection circuit that detects multiple-bit errors in a memory. [Background technology]

[0002] One type of error correction code (ECC) is the single-bit error correction and double-bit error detection code (SEC-DED Code). It is known that this ECC has characteristics that it cannot detect all even-bit errors of 4 or more bits, and that it may misidentify odd-bit errors of 3 or more bits as 1-bit errors and erroneously correct normal bits (Non-Patent Document 1).

[0003] In response to this, Patent Document 1 discloses a technique for increasing the probability of detecting multiple bit errors by providing an encoder unit that generates two sets of ECCs.

[0004] When an error detection and correction circuit using ECC that can correct 1-bit errors and 2-bit errors is used in equipment that requires functional safety, it is necessary to detect when a 1-bit error occurs to ensure that the error is not an error of 3 or more bits (multi-bit error). An example of an equipment that requires functional safety is an equipment that must comply with functional safety standards such as ISO26262. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] JP 2019-109806 A [Non-patent literature]

[0006] [Non-Patent Document 1] MY Hsiao, “A Class of Optimal Minimum Odd-weight-column SECDED Codes”, IBM Journal of Research and Development, Volume 14, Issue 4, published by IBM, July 1970. Summary of the Invention [Problem to be solved by the invention]

[0007] The technology disclosed in Patent Document 1 may not be able to detect multiple bit errors. Therefore, from the viewpoint of functional safety, software diagnosis is required every time an error is detected. When an address of data containing a single bit error is repeatedly accessed, software diagnosis is required each time, which increases the load of the software diagnosis.

[0008] Other objects and novel features will become apparent from the description of this specification and the accompanying drawings. [Means for solving the problem]

[0009] A representative aspect of the present disclosure can be briefly outlined as follows: A semiconductor device includes a syndrome generation circuit configured to generate a syndrome code based on data and an error correction code for the data, an error determination circuit configured to determine a bit error based on the syndrome code and output a bit error determination signal indicating that a single bit error has been detected, and a multiple bit error detection circuit configured to determine whether the single bit error is a multiple bit error or not based on the bit error determination signal, an address of the data in which the bit error has been detected, and the syndrome code when the bit error was detected. Effect of the Invention

[0010] According to the semiconductor device, the load of software diagnosis can be reduced. [Brief description of the drawings]

[0011] [Figure 1] FIG. 1 is a block diagram showing a configuration of a semiconductor device according to an embodiment. [Diagram 2] FIG. 2 is a block diagram showing an example of the configuration of the multi-bit error detection circuit shown in FIG. [Diagram 3] FIG. 3 is a block diagram showing an example of the configuration of a semiconductor device according to the first embodiment. [Figure 4] FIG. 4 is a diagram for explaining cases in which an error is detected during reading from a memory. [Diagram 5] FIG. 5 is a block diagram showing an example of the configuration of a semiconductor device according to the second embodiment. [Figure 6] FIG. 6 is a block diagram showing an example of the configuration of a semiconductor device according to the third embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0012] Hereinafter, the embodiments and modifications will be described with reference to the drawings. In the following description, the same components are designated by the same reference numerals, and repeated description may be omitted.

[0013] As described above, when an error detection and correction circuit using ECC capable of single-bit error correction and double-bit error detection is used in a device requiring functional safety, it is necessary to detect when a single-bit error occurs that the error is not a 3-bit or greater error (that it is a true single-bit error). Prior to this disclosure, the present inventors considered diagnosing a true single-bit error by software. However, when repeatedly accessing an address of data containing a single-bit error to read the data, software diagnosis is required each time, which increases the load of the software diagnosis.

[0014] [Embodiment] An embodiment for solving the above-mentioned problems will be described with reference to Fig. 1. Fig. 1 is a block diagram showing the configuration of a semiconductor device in the embodiment.

[0015] The error detection and correction circuit (ED&C) as the semiconductor device in the embodiment includes a syndrome generation circuit (SYGN), an error determination circuit (EJDG), and a multi-bit error detection circuit (MBED). Here, the syndrome generation circuit (SYGN) generates a syndrome code (SYC) based on data stored in the memory and an ECC added to the data. The ECC may be a code capable of correcting a single bit error, or may be a code capable of correcting a single bit error and detecting two bit errors. The error determination circuit (EJDG) determines a single bit error based on the syndrome code (SYC), and outputs a bit error determination signal (1EJ) indicating that a bit error has been detected. The multi-bit error detection circuit (MBED) determines whether a single bit error is a multi-bit error or not based on the bit error determination signal (1EJ), the address (ADR) of the data in which the bit error has been detected, and the syndrome code (SYC) when the error was detected.

[0016] When the multi-bit error detection circuit (MBED) detects a single-bit error for the first time at a given address, it notifies the CPU. This is so that the CPU can diagnose in software whether that single-bit error is actually a multi-bit error. When the multi-bit error detection circuit (MBED) repeatedly reads data containing that single-bit error from memory, it checks whether the syndrome code from the first read matches the syndrome code from the second or subsequent reads. If the syndrome codes do not match, the multi-bit error detection circuit (MBED) notifies the CPU that the single-bit error is a multi-bit error. If the syndrome codes match, the multi-bit error detection circuit (MBED) does not notify the CPU that it is a single-bit error.

[0017] Next, the multi-bit error detection circuit (MBED) will be described with reference to Fig. 2. Fig. 2 is a block diagram showing an example of the configuration of the multi-bit error detection circuit shown in Fig. 1.

[0018] The multiple-bit error detection circuit (MBED) has a first address register (ATR) and a second address register (APR) for capturing an address (ADR) of data in which a bit error has occurred, and a first syndrome register (STR) and a second syndrome register (SPR) for capturing a syndrome code (SYC) in which a bit error has occurred.

[0019] The multi-bit error detection circuit (MBED) also has an address comparison circuit (ACM) for comparing the first address register (ATR) with the second address register (APR), and a syndrome comparison circuit (SCM) for comparing the first syndrome register (STR) with the second syndrome register (SPR).

[0020] In addition, the multi-bit error detection circuit (MBED) has a multi-bit error judgment circuit (MEJD) that detects the case where the values ​​of the first address register (ATR) and the second address register (APR) match when a bit error occurs, and the values ​​of the first syndrome register (STR) and the second syndrome register (SPR) do not match.

[0021] The multi-bit error detection circuit (MBED) also has a control circuit (CCNT) that controls the first address register (ATR), the second address register (APR), the first syndrome register (STR) and the second syndrome register (SPR).

[0022] Furthermore, the multi-bit error detection circuit (MBED) has a CPU interface circuit (CPU I / F) that notifies the CPU of single-bit error and multi-bit error information. The CPU interface circuit (CPU I / F) receives address match information (AMT) from the control circuit (CCNT), multi-bit error information (MEJ) from the multi-bit error decision circuit (MEJD), and information that a single bit error has been detected (1EJ).

[0023] In the semiconductor device of the embodiment, only when a single bit error is detected for the first time at a corresponding address, the CPU performs software diagnosis to determine whether the single bit error is a multiple bit error. However, when data containing the single bit error is repeatedly read from the memory, the second and subsequent reads check to see if the syndrome code from the first read matches the syndrome code from the current read. This eliminates the need for software diagnosis when reading from the second and subsequent reads, making it possible to reduce the load on the CPU due to software.

[0024] Furthermore, the embodiment does not require two sets of ECCs as in Patent Document 1, and can reliably detect multi-bit errors, and does not cause the problem of an increase in memory capacity due to the second set of ECCs.

[0025] Furthermore, the embodiment can replace the double-bit error detection function as in Patent Document 1, eliminating the need for double-bit error detection as in Patent Document 1. This also makes it possible to reduce the memory capacity by reducing the number of ECC bits. EXAMPLES

[0026] FIG. 3 is a block diagram showing an example of the configuration of a semiconductor device according to the first embodiment.

[0027] The semiconductor device 100 includes a CPU 1, a memory 2, an error detection and correction circuit (ED&C) 3, and an internal bus 4. The semiconductor device 100 is configured as, for example, a microcontroller and formed on one semiconductor chip. The memory 2 is, for example, a flash memory. The memory 2 stores programs executed by the CPU 1 and data handled by the programs. The CPU 1, the memory 2, and the error detection and correction circuit (ED&C) 3 may be formed on different semiconductor chips. Alternatively, the CPU 1 and the error detection and correction circuit (ED&C) 3 may be formed on the same semiconductor chip, and the memory 2 may be formed on a different semiconductor chip. Alternatively, the memory 2 and the error detection and correction circuit (ED&C) 3 may be formed on the same semiconductor chip, and the CPU 1 may be formed on a different semiconductor chip.

[0028] The error detection and correction circuit (ED&C) 3 includes an ECC encoder (ECCE) 5, a syndrome generation circuit (SYGN) 6, an error judgment circuit (EJDG) 7, and an error correction circuit (SDEC) 8.

[0029] The error detection and correction circuit (ED&C) 3 includes a first address register (ATR) 9, three second address registers (APR) 10a, 10b, 10c, and three address comparison circuits (ACM) 13a, 13b, 13c. The error detection and correction circuit (ED&C) 3 includes a first syndrome register (STR) 11, three second syndrome registers (SPR) 12a, 12b, 12c, and three syndrome comparison circuits (SCM) 14a, 14b, 14c. The error detection and correction circuit (ED&C) 3 includes a multi-bit error determination circuit (MEJD) 15 and a control circuit (CCNT) 16.

[0030] The error detection and correction circuit (ED&C) 3 includes an error flag mask circuit 17, an error flag register 18, and an interrupt control circuit (INTC) 36. The error flag mask circuit 17, the error flag register 18, and the interrupt control circuit (INTC) 36 configure a CPU interface circuit (CPU I / F) in this embodiment.

[0031] The ECC encoder (ECCE) 5 generates an ECC capable of correcting one-bit errors and detecting two-bit errors based on write data (WD) written to the memory 2 from the CPU 1 or from outside the semiconductor device 100. For example, if the write data (WD) is 32 bits, the ECC is 7 bits. The ECC encoder (ECCE) 5 outputs the generated ECC to the memory 2. The write data (WD) transferred via the write data bus 19 and the ECC output from the ECC encoder (ECCE) 5 are stored in the memory 2.

[0032] The syndrome generation circuit (SYGN) 6 generates a syndrome code (SYC) based on the data (FRD) and ECC read from the memory 2. The syndrome generation circuit (SYGN) 6 generates a 7-bit syndrome code (SYC) from, for example, 32-bit data (FRD) and 7-bit ECC. The syndrome generation circuit (SYGN) 6 outputs the generated syndrome code (SYC) to the error determination circuit (EJDG) 7, the error correction circuit (SDEC) 8, and the first syndrome register (STR) 11.

[0033] The error determination circuit (EJDG) 7 generates a 1-bit error determination signal (1EJ) and a 2-bit error determination signal (2EJ) based on the syndrome code (SYC). When the error determination circuit (EJDG) 7 detects a 1-bit error, it activates the 1-bit error determination signal (1EJ) and outputs it to the control circuit (CCNT) 16 and the error flag mask circuit 17. When the error determination circuit (EJDG) 7 detects a 2-bit error, it activates the 2-bit error determination signal (2EJ) and outputs it to the error flag register 18.

[0034] The data (FRD), syndrome code (SYC), and 1-bit error determination signal (1EJ) are input to the error correction circuit (SDEC) 8. Then, the error correction circuit (SDEC) 8 outputs read data (RD) to the CPU 1 via a read data bus 39. If there is a 1-bit error, the error correction circuit (SDEC) 8 corrects the error in the data (FRD) and outputs it as read data (RD). If no 1-bit error is detected, the error correction circuit (SDEC) 8 outputs the data (FRD) as read data (RD).

[0035] The control circuit (CCNT) 16 receives the 1-bit error judgment signal (1EJ) and the address comparison signals (ACa, ACb, ACc) output from the address comparison circuits (ACM) 13a, 13b, 13c. The control circuit (CCNT) 16 outputs a first address control signal (AT) to the first address register (ATR) 9, and outputs a second address control signal (APa, APb, APc) to the second address registers (APR) 10a, 10b, 10c. The control circuit (CCNT) 16 outputs a first syndrome control signal (ST) to the first syndrome register (STR) 11, and outputs a second syndrome control signal (SPa, SPb, SPc) to the second syndrome registers (SPR) 12a, 12b, 12c. The control circuit (CCNT) 16 takes the OR logic of the address comparison signals (ACa, ACb, ACc) and outputs them to the error flag mask circuit 17 as an address match signal (AMT).

[0036] The address comparison circuits (ACM) 13a, 13b, 13c are circuits that compare the address stored in the first address register (ATR) 9 with the address stored in the second address register (APR) 10a, 10b, 10c, respectively. The address comparison circuits (ACM) 13a, 13b, 13c output address comparison signals (ACa, ACb, ACc) to the control circuit (CCNT) 16 and the multi-bit error determination circuit (MEJD) 15. When any of the addresses stored in the first address register (ATR) 9 and the second address registers (APR) 10a, 10b, 10c match, the address comparison circuits (ACM) 13a, 13b, 13c activate the corresponding address comparison signals (ACa, ACb, ACc).

[0037] The syndrome comparison circuits (SCM) 14a, 14b, 14c are circuits that compare the syndrome code stored in the first syndrome register (STR) 11 with the syndrome code stored in the second syndrome registers (SPR) 12a, 12b, 12c. The syndrome comparison circuits (SCM) 14a, 14b, 14c output syndrome comparison signals (SCa, SCb, SCc) to the multi-bit error determination circuit 15. When any of the syndrome codes in the first syndrome register (STR) 11 and the second syndrome registers (SPR) 12a, 12b, 12c match, the syndrome comparison circuits (SCM) 14a, 14b, 14c activate the corresponding syndrome comparison signals (SCa, SCb, SCc).

[0038] The multi-bit error determination circuit (MEJD) 15 generates a multi-bit error determination signal (MEJ) based on the address comparison signals (ACa, ACb, ACc) and the syndrome comparison signals (SCa, SCb, SCc), and outputs the multi-bit error determination signal (MEJ) to the error flag register 18 and the interrupt control circuit (INTC) 36. When the address comparison signals (ACa, ACb, ACc) are active and the syndrome comparison signals (SCa, SCb, SCc) are inactive, the multi-bit error determination circuit (MEJD) 15 activates the multi-bit error determination signal (MEJ).

[0039] The error flag mask circuit 17 generates a 1-bit error confirmed signal (1ED) based on the 1-bit error judgment signal (1EJ) and the address match signal (AMT). When the 1-bit error judgment signal (1EJ) is active and the address match signal (AMT) is inactive, the error flag mask circuit 17 activates the 1-bit error confirmed signal (1ED).

[0040] The error flag register 18 receives a 1-bit error determination signal (1ED), a 2-bit error determination signal (2EJ), a multiple-bit error determination signal (MEJ), and an address overflow signal (AOF). When the 1-bit error determination signal (1ED) is active, the 1-bit error flag (1E) is set. When the 2-bit error determination signal (2EJ) is active, the 2-bit error flag (2E) is set. When the multiple-bit error determination signal (MEJ) is active, the multiple-bit error flag (ME) is set. When the address overflow signal (AOF) is active 1, the over flag (OV) is set.

[0041] The interrupt control circuit (INTC) 36 generates an interrupt signal (IRQ) based on the one-bit error determination signal (1ED), the two-bit error determination signal (2EJ), and the multiple-bit error determination signal (MEJ), and outputs it to the CPU 1. The interrupt control circuit (INTC) 36 activates the interrupt signal (IRQ) when any of the one-bit error determination signal (1ED), the two-bit error determination signal (2EJ), and the multiple-bit error determination signal (MEJ) is active.

[0042] Next, the operation of the semiconductor device 100 will be described with reference to Figures 3 and 4. Figure 4 is a diagram for explaining cases in which an error is detected during reading from a memory.

[0043] The memory 2 is a memory that stores a program executed by the CPU 1. The ECC encoder (ECCE) 5 generates an ECC based on program data provided from outside the semiconductor device 100. The program data is written into the memory 2 together with the ECC.

[0044] The CPU 1 sends an address (ADR) to the memory 2 via the address bus 24, and instructs it to read data corresponding to the address (ADR) (step S1).

[0045] The memory 2 reads out the read data (FRD) and the corresponding ECC based on the address (ADR) and outputs them to the syndrome generation circuit (SYGN) 6. If the data (FRD) read from the memory 2 contains a 1-bit error, the error determination circuit (EJDG) 7 performs error determination based on the syndrome code (SYC) generated by the syndrome generation circuit (SYGN) 6 (step S2). If the error determination circuit (EJDG) 7 detects a 1-bit error, the error determination circuit (EJDG) 7 activates the 1-bit error determination signal (1EJ) (1EJ=1).

[0046] If the error determination circuit (EJDG) 7 detects a one-bit error, the error correction circuit (SDEC) 8 and the control circuit (CCNT) 16 carry out the following (step S3).

[0047] The error correction circuit (SDEC) 8 decodes the syndrome code (SYC) and determines the bit position of the 1-bit error. Then, upon receiving the active 1-bit error determination signal (1EJ), the error correction circuit (SDEC) 8 corrects the read data (FRD) by inverting the data of the erroneous bit based on the bit position of the determined 1-bit error.

[0048] Furthermore, upon receiving the 1-bit error determination signal (1EJ), the control circuit (CCNT) 16 controls so that the address of the data in which a bit error has been detected is captured from the address bus 24 to the first address register (ATR) 9. In parallel with this, the control circuit (CCNT) 16 controls so that the syndrome code of the data in which a bit error has been detected is captured from the syndrome generation circuit (SYGN) 6 to the first syndrome register (STR) 11. Hereinafter, the address of the data in which a bit error has been detected is referred to as the "error address (EAD)". Hereinafter, the syndrome code of the data in which a bit error has been detected is referred to as the "error syndrome code (ESC)".

[0049] The address comparison circuits (ACM) 13a, 13b, 13c compare the address captured in the first address register (ATR) 9 with the addresses in the second address registers (APR) 10a, 10b, 10c (step S4). The second address registers (APR) 10a, 10b, 10c store addresses corresponding to data in which a single-bit error has been detected in the past. Therefore, by address comparison, it is possible to determine whether the address captured in the first address register (ATR) 9 is an address in which a single-bit data error has already been detected. If the address captured in the first address register (ATR) 9 does not match any of the addresses in the second address registers (APR) 10a, 10b, 10c (AC=0), the operation of case 1 is performed thereafter. Note that if an error address has not yet been captured in the first address register (ATR), an address outside the address space of the memory 2 is set in the second address registers (APR) 10a, 10b, 10c.

[0050] (1) Case 1 Case 1 is the case where a one-bit error is detected for the first time (first time) in data corresponding to an address provided by the CPU 1. The operation of case 1 will be described below.

[0051] (1-1) Operation of the error detection and correction circuit (ED&C) 3 The address comparison circuits (ACM) 13a, 13b, and 13c transmit the address comparison signals (ACa, ACb, and ACc) that are the comparison results to the control circuit (CCNT) 16. In case 1, the data corresponding to the address of the first address register (ATR) 9 is data in which a one-bit error has been detected for the first time, so the address comparison signals (ACa, ACb, and ACc) indicate that the address of the first address register (ATR) 9 does not match any of the addresses of the second address registers (APR) 10a, 10b, and 10c. Based on such address comparison signals (ACa, ACb, and ACc), the control circuit (CCNT) 16 controls the address captured in the first address register (ATR) 9 to be copied to any one of the second address registers (APR) 10a, 10b, and 10c. The control circuit (CCNT) 16 holds information on whether the error address (EAD) has already been captured in the second address registers (APR) 10a, 10b, and 10c. The control circuit (CCNT) 16 controls to copy the error address in the first address register (ATR) 9 to the registers that have not captured the error address (EAD).

[0052] In this embodiment, the control circuit (CCNT) 16 controls the second address registers (APR) 10a, 10b, and 10c to capture the error address (EAD) in this order.

[0053] When no error address (EAD) is captured in the second address registers (APR) 10a, 10b, and 10c, the control circuit (CCNT) 16 activates the second address control signal (APa) and copies the contents of the first address register (ATR) 9 to the second address register (APR) 10a. In response to the selection of the second address register (APR) 10a, the control circuit (CCNT) 16 activates the second syndrome control signal (SPa) and copies the error syndrome code (ESC) stored in the first syndrome register (STR) 11 to the second syndrome register (SPR) 12a. As a result, the error address (EAD) is stored in the second address register (APR) 10a, and the error syndrome code (ESC) is stored in the second syndrome register (SPR) 12a.

[0054] If second address registers (APR) 10a, 10b have already captured another error address (EAD), control circuit (CCNT) 16 activates second address control signal (APc) to copy the contents of first address register (ATR) 9 to second address register (APR) 10c. In this case, in response to the selection of second address register (APR) 10c, control circuit (CCNT) 16 activates second syndrome control signal (SPc) to copy the contents of first syndrome register (STR) 11 to second syndrome register (SPR) 12c.

[0055] If all of the second address registers (APR) 10a, 10b, and 10c have already captured another error address (EAD), the control circuit (CCNT) 16 does not copy to the second address registers (APR) 10a, 10b, and 10c and the second syndrome registers (SPR) 12a, 12b, and 12c. Then, the control circuit (CCNT) 16 determines that an address overflow has occurred and activates the address overflow signal (AOF).

[0056] In case 1, the address captured in the first address register (ATR) 9 does not match any of the addresses in the second address registers (APR) 10a, 10b, and 10c. That is, all of the address comparison signals (ACa, ACb, and ACc) are inactive, indicating a mismatch. Therefore, the multi-bit error determination circuit (MEJD) 15 makes the multi-bit error determination signal (MEJ) inactive. Also, the control circuit (CCNT) 16 makes the address match signal (AMT), which indicates whether the address in the first address register (ATR) 9 matches any of the addresses in the second address registers (APR) 10a, 10b, and 10c, inactive. As a result, the error flag mask circuit 17 makes the 1-bit error determination signal (1ED) active. As a result, the 1-bit error flag (1E) in the error flag register 18 is set. Also, the interrupt control circuit (INTC) 36 makes the interrupt signal (IRQ) active.

[0057] (1-2) Software diagnosis The operation of CPU 1 will be described below when a single bit error is detected for the first time in data corresponding to an address provided by CPU 1, that is, when a single bit error is detected but the error address (EAD) stored in first address register (ATR) 9 does not match the address stored in second address registers (APR) 10a, 10b, 10c and no address overflow occurs.

[0058] After detecting a single bit error, the CPU 1 receives an interrupt signal (IRQ) and reads the error flag register 18. This allows the CPU 1 to confirm that the cause of the interrupt is a single bit error, and then diagnoses in the interrupt routine whether this single bit error is a true single bit error.

[0059] As mentioned above, there are cases where an odd-numbered bit error of 3 or more bits is mistakenly recognized as a 1-bit error, and the normal bits are incorrectly corrected. If the incorrectly corrected data is used, it may lead to a security violation, so if there is a multi-bit error, the device must transition to a secure state.

[0060] Whether or not it was a true single-bit error can be diagnosed by software stored in memory 2 by adding a checksum or cyclic redundancy check (CRC) data to the data in memory 2. ECC is added in units of words (e.g., 32 bits) and stored in memory 2. Meanwhile, checksum and CRC data is generally calculated from the data of multiple words for each multiple words and stored in memory 2 so as not to increase memory capacity. The data also includes the object code of the program.

[0061] Therefore, when diagnosing data in which a single bit error has been detected, the CPU 1 reads out the address area in which the multiple words of data including the data in which a single bit error has been detected are stored all at once. The read out multiple words of data are subjected to error correction using the ECC corresponding to each word. The CPU 1 then calculates data for a checksum or CRC from the multiple words of data after the error correction, and compares it with the checksum or CRC data stored in the memory 2. The data for the checksum or CRC calculated from the read out multiple words of data may be calculated by a dedicated arithmetic device. This makes it possible to confirm that there is no error in the data after the error correction of the read out multiple words of data, and to determine whether the single bit error correction of the address was correct. In other words, it can be confirmed that the single bit error was a true single bit error. In this way, the CPU 1 is used to diagnose whether or not there is a single bit error, so that the CPU load for performing the diagnosis is applied when the first single bit error is detected.

[0062] If the diagnosis confirms that the error is a true single-bit error, the CPU 1 continues operation using the error-corrected data. If the diagnosis determines that the error is not a true single-bit error but a multiple-bit error, the CPU 1 transitions the semiconductor device 100 to a safe state. If an address overflow occurs, the CPU 1 also transitions the semiconductor device 100 to a safe state, for example.

[0063] The following describes the case where any of the addresses captured in the second address registers (APR) 10a, 10b, and 10c matches the address captured in the first address register (ATR) 9 (AC=1). When data containing a single bit error from the same address is repeatedly read, the bit error is detected the second or subsequent time the data is read.

[0064] The syndrome comparison circuits (SCM) 14a, 14b, 14c compare the syndrome code (SYC) captured in the first syndrome register (STR) 11 with the syndrome code (SYC) captured in the second syndrome registers (SPR) 12a, 12b, 12c (step S5).

[0065] When the syndrome code (SYC) captured in the first syndrome register (STR) 11 matches any of the syndrome codes captured in the second syndrome registers (SPR) 12a, 12b, and 12c (SC=1), the operation of Case 2 is performed thereafter.

[0066] (2) Case 2 In case 2, the error syndrome code (ESC) captured in the first syndrome register (STR) 11 matches the error syndrome code (ESC) captured in any one of the second syndrome registers (SPR) 12a, 12b, and 12c. In other words, the read data corresponding to the syndrome code captured in the first syndrome register (STR) 11 matches the read data corresponding to the syndrome code (SYC) stored in any one of the second syndrome registers (SPR) 12a, 12b, and 12c.

[0067] In case 2, the newly detected single bit error can be considered to be the same as the previously detected single bit error. It has already been confirmed by the software diagnosis in case 1 that the read data corresponding to the error syndrome code (ESC) stored in any one of the second syndrome registers (SPR) 12a, 12b, and 12c is a true single bit error. Therefore, there is no need for software diagnosis to confirm that the currently detected single bit error is a true single bit error.

[0068] Based on the address comparison signals (ACa, ACb, ACc), the control circuit (CCNT) 16 determines that the address captured in the first address register (ATR) is already stored in the second address register (APR) 10a, 10b, 10c. Therefore, the control circuit (CCNT) 16 does not copy the error address (EAD) captured in the first address register (ATR) to the second address register (APR) 10c. In addition, the control circuit (CCNT) 16 does not copy the error syndrome code (ESC) captured in the first syndrome register (STR) 11 to the second syndrome register (SPR) 12c.

[0069] The multi-bit error determination circuit (MEJD) 15 outputs a multi-bit error determination signal (MEJ) based on the syndrome comparison signals (SCa, SCb, SCc) which are the comparison results of the syndrome comparison circuits 14a, 14b, 14c corresponding to the second address register (APR) with a matching address.

[0070] For example, when the address of the second address register (APR) 10b matches the address of the first address register (ATR) 9, the multi-bit error determination circuit (MEJD) 15 outputs the multi-bit error determination signal (MEJ) based on the syndrome comparison signal (SCb). When the syndrome code of the first syndrome register (STR) 11 matches the syndrome code of the second syndrome register (SPR) 12b, the multi-bit error determination circuit (MEJD) 15 makes the multi-bit error determination signal (MEJ) inactive.

[0071] As described above, in case 2, one of the error addresses (EAD) captured in the second address registers (APR) 10a, 10b, and 10c matches the newly detected error address (EAD) of a single bit error captured in the first address register (ATR) 9. Therefore, one of the address comparison signals (ACa, ACb, and ACc) becomes active.

[0072] Therefore, the control circuit (CCNT) 16 activates the address match signal (AMT) based on the address comparison signals (ACa, ACb, ACc). This causes the error flag mask circuit 17 to mask the 1-bit judgment signal (1EJ), and the 1-bit error determination signal (1ED) becomes inactive. As a result, the 1-bit error flag (1E) in the error flag register 18 is not set. Also, the interrupt control circuit (INTC) 36 makes the interrupt signal (IRQ) inactive. As a result, no interrupt occurs and the 1-bit error flag (1E) in the error flag register 18 is not set, so the CPU 1 does not perform unnecessary software diagnostic processing.

[0073] (3) Case 3 If the address of the first address register (ATR) 9 matches any of the addresses of the second address registers (APR) 10a, 10b, and 10c, but the syndrome code of the first syndrome register (STR) 11 does not match any of the syndrome codes of the second syndrome registers (SPR) 12a, 12b, and 12c (SC=0), then the operation of Case 3 is performed.

[0074] Case 3 shows that the error syndrome code (ESC) newly captured in the first syndrome register (STR) 11 does not match any of the error syndrome codes (ESC) captured in the second syndrome registers (SPR) 12a, 12b, and 12c. This means that the content of the bit error has changed, that is, data containing a single bit error has changed to data containing multiple bit errors (three or more errors have occurred), and furthermore, the multiple bit error has been erroneously determined to be a single bit error.

[0075] At this time, the control circuit (CCNT) 16 determines, based on the address comparison signals (ACa, ACb, ACc), that the address newly captured in the first address register (ATR) is already stored in the second address register (APR) 10a, 10b, 10c, similar to case 2. Therefore, similar to case 2, the control circuit (CCNT) 16 does not copy the error address (EAD) newly captured in the first address register (ATR) to the second address register (APR) 10c. In addition, the control circuit (CCNT) 16 does not copy the error syndrome code (ESC) newly captured in the first syndrome register (STR) 11 to the second syndrome register (SPR) 12c.

[0076] Since the error syndrome code (ESC) newly captured in the first syndrome register (STR) 11 does not match any of the error syndrome codes (ESC) captured in the second syndrome registers (SPR) 12a, 12b, and 12c, all of the syndrome comparison signals (SCa, SCb, and SCc) become inactive. Therefore, the multi-bit error determination circuit 15 activates the multi-bit error determination signal (MEJ).

[0077] As described above, in case 3, one of the erroneous addresses (EAD) captured in the second address registers (APR) 10a, 10b, and 10c matches the newly generated erroneous address (EAD) captured in the first address register (ATR) 9. Therefore, one of the address comparison signals (ACa, ACb, and ACc) becomes active.

[0078] Therefore, the control circuit (CCNT) 16 activates the address match signal (AMT). As a result, the error flag mask circuit 17 masks the setting of the 1-bit error flag (1E) in the error flag register 18 by the 1-bit error determination signal (1EJ). However, since the multi-bit error determination signal (MEJ) is active, the multi-bit error flag (ME) is set. Also, since the multi-bit error determination signal (MEJ) is active, the interrupt control circuit (INTC) 36 activates the interrupt signal (IRQ) as a multi-bit error and notifies the CPU 1. Note that the error correction circuit (SDEC) 8 performs error correction, but this is a miscorrection.

[0079] The CPU 1 receives an interrupt signal (IRQ) and, in the interrupt processing routine, can confirm detection of a multi-bit error by reading the error flag register 18. When the CPU 1 confirms detection of a multi-bit error, it transitions the semiconductor device 100 to a safe state.

[0080] (4) Case 4 If there is a 2-bit error in the data read from the memory 2, the error determination circuit (EJDG) 7 performs error determination based on the syndrome code (SYC) generated by the syndrome generation circuit (SYGN) 6 (step S2). The error determination circuit (EJDG) 7 detects the 2-bit error and activates the 2-bit error determination signal (2EJ) (2EJ=1). After that, the operation of Case 4 is performed.

[0081] In case 4, the interrupt control circuit (INTC) 36 receives the 2-bit error judgment signal (2EJ) and outputs an interrupt signal (IRQ) to the CPU 1. Upon receiving the interrupt signal (IRQ), the CPU 1 reads the error flag register 18. If it confirms that there is a 2-bit error, the data read from the memory 2 is not corrected and is erroneous, and therefore the semiconductor device 100 transitions to a safe state.

[0082] Retention failures of memories and the like are generally bit-related failures, and as bit failures accumulate, one bit error becomes two bit errors, and then three bit errors. In this embodiment, when a one bit error transitions to a two bit error, it is detected by the two bit error detection function of the error determination circuit (EJDG) 7. However, the error determination circuit (EJDG) 7 is not only unable to detect a three bit error, but may erroneously determine it as a one bit error. In this embodiment, when it is determined that there is a one bit error, it is possible to detect whether or not it is a multi-bit error. In addition, memory failures are not limited to bit-related failures, and may also result in sudden multi-bit errors, such as address decoder failures. These errors can be detected in this embodiment.

[0083] As described above, the semiconductor device in this embodiment includes an error detection and correction circuit having the functions of single-bit error correction and double-bit error detection, and a multi-bit error detection circuit.

[0084] The multi-bit error detection circuit has the following functions.

[0085] (a) A function that receives a 1-bit error detection signal, captures the error address (EAD) in the first address register (ATR), and simultaneously captures the syndrome code (ESC) in which the error occurred in the first syndrome register (STR).

[0086] (b) A function to compare the first address register (ATR) and the second address register (APR), and if there is no matching second address register, to copy the value of the first address register (ATR) to the second address register (APR) as a new address, and to copy the value of the first syndrome register (STR) to the second syndrome register (SPR).

[0087] (c) A function for comparing the first address register (ATR) with the second address register (APR) and, if they match, comparing the value of the first syndrome register (STR) with the value of the second syndrome register (SPR) corresponding to the matching second address register (APR).

[0088] (d) In (c) above, a function to mask the notification to the CPU of the occurrence of a single bit error (correctable bit error) when the values ​​of the first syndrome register (STR) and the second syndrome register (SPR) match.

[0089] (e) In the above (c), if the values ​​of the first syndrome register and the second syndrome register do not match, a function of outputting an interrupt as a multi-bit error and setting a multi-bit error flag.

[0090] The semiconductor device in this embodiment has the function (d) above, so that it can prevent repeated interrupts from occurring due to the same single bit error at the same address that has already been confirmed by software diagnosis to be not a multi-bit error. This makes it possible to reduce the CPU load by performing software diagnosis to determine whether or not a single bit error is a true single bit error, which is required every time a single bit error is detected, only at the first detection of the single bit error.

[0091] The semiconductor device of this embodiment has the function (e) above, which allows the CPU to recognize a multi-bit error, thereby enabling the semiconductor device to transition to a safe state.

[0092] When the first single-bit error is detected, software diagnosis is used to check whether it is a multi-bit error, and if a single-bit error is detected for the second or subsequent time for the same address, the functions of this embodiment make it possible to reliably detect multi-bit errors.

[0093] Furthermore, the semiconductor device in this embodiment does not need to have two sets of ECCs as in Patent Document 1, and can reliably detect multi-bit errors, and does not have the problem of an increased memory capacity due to the second set of ECCs. EXAMPLES

[0094] FIG. 5 is a diagram showing an example of the configuration of a semiconductor device according to the second embodiment.

[0095] The semiconductor device 100 in the second embodiment differs from the first embodiment in that the error judgment circuit (EJDG) 7 does not have a double-bit error judgment function, an interrupt is generated due to a double-bit error, and there is no double-bit error flag in the error flag register 18. Other configurations of the semiconductor device 100 in the second embodiment are the same as those in the first embodiment.

[0096] The operation of the semiconductor device 100 in the second embodiment is the same as that in the first embodiment, except that there is no double-bit error detection.

[0097] Since the syndrome code (SYC) for one bit error and the syndrome code (SYC) for two bit errors are different, the multi-bit error judgment signal (MEJ) can also detect two bit errors. Therefore, it is not necessary for the error judgment circuit (EJDG) 7 to detect two bit errors.

[0098] When the 2-bit error detection function of the first embodiment is present, that is, the advantage of the first embodiment is that, for example, a 2-bit error is not the result of an accumulation of 1-bit errors, and even if 2-bit retention failures occur simultaneously, although the occurrence probability is low, there is no need to perform software diagnosis. In contrast, in the second embodiment, a 2-bit error is also judged as a 1-bit error, and cannot be distinguished. Therefore, when the first 1-bit error is detected, it is necessary to judge by software diagnosis whether it is a true 1-bit error or a multi-bit error of 2 or more bits.

[0099] However, in the error detection and correction circuit (ED&C) 3 in the embodiment, it is assumed that software diagnosis is performed when the first one-bit error is detected at a specific address, so there is no need to have the double-bit error detection function of the first embodiment. In other words, in both the first and second embodiments, software diagnosis is performed when the first one-bit error is detected at the address, so the CPU load caused by this is the same in both the first and second embodiments.

[0100] On the other hand, if the error is a two-bit error caused by an accumulation of retention failures, in the second embodiment it is determined to be a multi-bit error, an interrupt is generated, and a multi-bit error flag is raised, so that the device can be transitioned directly to a safe state without the need for software diagnosis after the error occurs.

[0101] The number of ECC bits for 1-bit error correction and 2-bit error detection in the first embodiment requires 7 bits when the data width is 32 bits, for example. Since this embodiment does not have the 2-bit error detection function of the first embodiment and uses 1-bit error correction, the number of ECC bits can be 6 bits, which is a reduction of 1 bit. In other words, the memory capacity can be reduced by 2.56%.

[0102] As described above, the second embodiment shows that it is not necessary to have the 2-bit detection function of the first embodiment, and this makes it possible to reduce the number of ECC bits, thereby reducing the area of ​​the memory cell array region of the memory 2. The effect becomes greater as the memory capacity becomes larger. EXAMPLES

[0103] FIG. 6 is a block diagram showing an example of the configuration of a semiconductor device according to the third embodiment.

[0104] The third embodiment further comprises a CRC calculation circuit (FCRC) 40 and an address selector (ASLC) 41 in addition to the components of the second embodiment.

[0105] The CRC calculation circuit (FCRC) 40 is connected to the CPU 1 via the internal bus 4. Then, the read data (RD) on the read bus 39 is input to the CRC calculation circuit (FCRC) 40. Then, the CRC calculation circuit (FCRC) 40 outputs a CRC diagnostic address (CAD) to an address selector (ASLC) 41, and outputs a CRC calculation completion signal (CCE) to the CPU 1.

[0106] The CRC diagnostic address (CAD) and the address (ADR) on the address bus 24 are input to the address selector (ASLC) 41. Then, the address selector (ASLC) 41 selects either the address (ADR) or the CRC diagnostic address (CAD) and outputs the address (FAD) to the memory 2.

[0107] Next, the operation of the semiconductor device according to the third embodiment will be described.

[0108] In general, semiconductor devices are initialized by a reset and start operating when the reset is released. In semiconductor devices that comply with functional safety standards, it is strongly recommended to perform diagnostic tests on various circuits immediately after the reset is released.

[0109] For example, this embodiment is provided with a CRC calculation circuit 40 that can diagnose the entire area of ​​the memory 2 at high speed without using the CPU 1. After reset release, the CRC calculation circuit 40 continuously reads the entire area of ​​the memory 2 and performs CRC calculation according to a predetermined polynomial.

[0110] In the CRC diagnosis after reset release, the address selector (ASLC) 41 selects the CRC diagnosis address (CAD) for the address (FAD) of memory 2. Then, the CRC calculation circuit (FCRC) 40 automatically increments the addresses of all areas of memory 2, reads the data of all areas of memory 2, and calculates the CRC value. Data of all areas of memory 2 is read for this CRC calculation, but the CPU 1 is in a halt state, so it ignores the read data and does not operate. After reading of data of all areas of memory 2 is completed and the CRC value is calculated, the CRC calculation circuit (FCRC) 40 activates and sends the CRC calculation completion signal (CCE) to the CPU 1.

[0111] Upon receiving the CRC calculation completion signal (CCE), the CPU 1 transitions from a halt state to a normal state, and reads the calculation result from the CRC calculation circuit (FCRC) 40 via the internal bus 4. The CPU 1 then reads the CRC value stored in the memory 2 from the read data bus 39. The CPU 1 then compares the two CRC values ​​read from the CRC calculation circuit (FCRC) 40 and the memory 2 to confirm that the data written to the memory 2 is free of errors.

[0112] The error detection and correction circuit (ED&C) 3 is functioning even when the CRC calculation circuit (FCRC) 40 reads the entire area of ​​the memory 2, and corrects the data if there is a single-bit error. Therefore, if the defect in the memory 2 is only a true single-bit error, the error correction is performed correctly, and the CRC diagnosis result is a pass judgment. On the other hand, if there are two or more errors, the error correction is not possible, and the CRC diagnosis result is a fail judgment. Also, since the error detection and correction circuit (ED&C) 3 is functioning during the period in which the CRC diagnosis is being performed, if there is a single-bit error, the capture of the error address (EAD) and the capture of the error syndrome code (ESC) are performed as described in the first embodiment. By software diagnosis, it becomes possible to capture the error address (EAD) having true single-bit error information from the entire area of ​​the memory 2 in the second address register (APR), and the error syndrome code (ESC) in that case in the second syndrome register (SPR).

[0113] By using such a startup method, even in a system where the power supply of the semiconductor device is cut off, the error address (EAD) and error syndrome code (ESC) once captured can be captured again at each startup even if they are not stored in a non-volatile memory. This can significantly reduce the probability that a single bit error will be detected again for the first time during normal operation and software diagnosis must be performed. This is because the error address (EAD) and error syndrome code (ESC) captured as a single bit error before the power supply is cut off can be detected during the CRC diagnosis period after the next power supply is turned on. Therefore, by combining with a CRC calculation circuit capable of checking the entire area of ​​memory 2, the load due to software diagnosis during normal operation can be further reduced.

[0114] In a system with ample startup time after power cut, the CPU 1 may read instructions from a RAM (not shown) and perform a CRC diagnosis of the entire area of ​​the memory 2 by software, without providing a CRC calculation circuit made up of hardware. Here, the software to be diagnosed is expanded from the memory 2 to the RAM and stored therein. This makes it possible to obtain the same effect as providing a CRC calculation circuit, and is not limited to the implementation of a CRC calculation circuit made up of hardware.

[0115] The disclosure made by the present disclosure has been specifically described above based on embodiments and examples. However, the present disclosure is not limited to the above embodiments and examples, and it goes without saying that various modifications can be made without departing from the spirit of the present disclosure.

[0116] For example, in the embodiment, an example has been described in which three second address registers, three second syndrome registers, three address comparison circuits, and three syndrome comparison circuits are provided, but at least one of each may be provided.

[0117] In addition, in the embodiment, an error detection and correction circuit for 1-bit error correction and 2-bit error detection has been described, but this is not limited to this and the present invention can also be applied to error detection and correction circuits for 1-bit and 2-bit error correction and 3-bit error detection, etc. [Explanation of symbols]

[0118] 3. Error detection and correction circuits (ED&C, semiconductor devices) 6 Syndrome Generator (SYGN) 7 Error Detection Circuit (EJDG)

Claims

1. a syndrome generation circuit configured to generate a syndrome code based on the data and an error correction code for the data; an error determination circuit configured to determine a bit error based on the syndrome code and output a bit error determination signal indicating that a single bit error has been detected; a first address register for capturing an address corresponding to the data when the bit error determination signal is output from the error determination circuit, a first syndrome register for capturing a syndrome code corresponding to the data when the bit error determination signal is output from the error determination circuit, a second address register for storing an address corresponding to the data already confirmed to be a single bit error, a second syndrome register for storing a syndrome code corresponding to the data already confirmed to be a single bit error, an address comparison circuit for comparing values ​​of the first address register and the second address register in response to the bit error determination signal, and a syndrome comparison circuit for comparing values ​​of the first syndrome register and the second syndrome register in response to the bit error determination signal, and a multi-bit error detection circuit configured to determine whether or not the data when the bit error determination signal is output from the error determination circuit is a multi-bit error based on a comparison result of the address comparison circuit and a comparison result of the syndrome comparison circuit; A semiconductor device comprising:

2. 2. The semiconductor device according to claim 1, The semiconductor device further includes a control circuit configured to notify a detected bit error as a single bit error when the bit error determination signal indicates a bit error and the value of the first address register and the value of the second address register do not match.

3. 3. The semiconductor device according to claim 2, When the bit error determination signal indicates a bit error, and when the value of the first address register and the value of the second address register do not match, configured to copy a value in the first address register to the second address register; A semiconductor device configured to copy a value of the first syndrome register to the second syndrome register.

4. 2. The semiconductor device according to claim 1, The multi-bit error detection circuit is a semiconductor device configured to determine that a multi-bit error has occurred and notify of a multi-bit error when the bit error judgment signal indicates a bit error, when the value of the first address register and the value of the second address register match, and when the value of the second syndrome register that is paired with the second address register for which a match has been confirmed does not match the value of the first syndrome register.

5. 5. The semiconductor device according to claim 4, The semiconductor device is configured such that, when the multiple-bit error detection circuit determines that a detected bit error is a multiple-bit error, it does not notify the detected bit error as a single-bit error.

6. 2. The semiconductor device according to claim 1, The semiconductor device includes an equal number of each of the second address register, the second syndrome register, the address comparison circuit, and the syndrome comparison circuit.

7. 2. The semiconductor device according to claim 1, The semiconductor device further includes a control circuit configured to notify the detected bit error as a one-bit error when the bit error determination signal indicates a bit error and there is no second address register that matches the value of the first address register.

8. 3. The semiconductor device according to claim 2, When the second address register is empty and an erroneous address has not yet been captured, the control circuit configured to copy the value of the first address register into an empty second address register; A semiconductor device configured to copy a value of the first syndrome register to the second syndrome register that is paired with the empty second address register.

9. 9. The semiconductor device according to claim 1, The error correction code is a code capable of correcting one bit error and detecting two bit errors.

10. 9. The semiconductor device according to claim 1, The error correcting code is a code that can correct a single bit error but cannot detect a double bit error.

11. The semiconductor device according to any one of claims 1 to 8, further comprising: A CPU, a memory in which the data and the error correction code for the data are stored; an error correction circuit configured to correct the data based on the bit error determination signal and the syndrome code; a CPU interface circuit configured to notify the CPU of the single bit error and the multi-bit error; A semiconductor device comprising:

12. 12. The semiconductor device of claim 11, The semiconductor device further includes a CRC calculation circuit configured to generate addresses for the entire area of ​​the memory, read data from the entire area of ​​the memory, and calculate data for a cyclic redundancy check of the data output from the error correction circuit.

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