Semiconductor Device

Abstract

Provided is a semiconductor device with good electrical properties. A transistor, comprising a gate electrode, a source electrode, and a drain electrode, a first insulator, a second insulator over the first insulator, a third insulator over the second insulator, a first electrode that abuts an upper surface of the source electrode, and a second electrode that abuts an upper surface of the drain electrode are provided. The second insulator comprises a first opening section that overlaps the source electrode and a second opening section that overlaps the drain electrode. The third insulator abuts the first opening section, a side surface of the second insulator on the inner side of the second opening section, and an upper surface of the first insulator. The first electrode passes through the first opening section, and the second electrode passes through the second opening section.

Description

[Technical field]

[0001] 1. Field of the Invention An embodiment of the present invention relates to a transistor, a semiconductor device, and an electronic device. Another embodiment of the present invention relates to a manufacturing method of a semiconductor device. Another embodiment of the present invention relates to a semiconductor wafer and a module.

[0002] In this specification and the like, a semiconductor device refers to any device that can function by utilizing semiconductor characteristics. Semiconductor elements such as transistors, semiconductor circuits, arithmetic devices, and memory devices are all embodiments of semiconductor devices. Display devices (such as liquid crystal display devices and light-emitting display devices), projection devices, lighting devices, electro-optical devices, power storage devices, memory devices, semiconductor circuits, imaging devices, electronic devices, and the like may be considered to include semiconductor devices.

[0003] Note that one aspect of the present invention is not limited to the above technical field. One aspect of the invention disclosed in the present specification etc. relates to an object, a method, or a manufacturing method. Another aspect of the present invention relates to a process, a machine, a manufacture, or a composition of matter. [Background technology]

[0004] In recent years, the development of semiconductor devices has progressed, particularly in LSIs, CPUs, and memories. A CPU is a collection of semiconductor elements having semiconductor integrated circuits (at least transistors and memories) separated from a semiconductor wafer and on which electrodes serving as connection terminals are formed.

[0005] Semiconductor circuits (IC chips) such as LSIs, CPUs, and memories are mounted on circuit boards, such as printed wiring boards, and used as one of the components of various electronic devices.

[0006] In addition, a technology for constructing a transistor using a semiconductor thin film formed on a substrate having an insulating surface is attracting attention. Such transistors are widely used in electronic devices such as integrated circuits (ICs) and image display devices (also simply referred to as display devices). Silicon-based semiconductor materials are widely known as semiconductor thin films that can be used in transistors, but oxide semiconductors are also attracting attention as other materials.

[0007] It is also known that a transistor using an oxide semiconductor has an extremely low leakage current in a non-conducting state. For example, a low-power consumption CPU that utilizes the low leakage current characteristic of a transistor using an oxide semiconductor has been disclosed (see Patent Document 1). In addition, a memory device that can retain stored data for a long period of time by utilizing the low leakage current characteristic of a transistor using an oxide semiconductor has been disclosed (see Patent Document 2).

[0008] Furthermore, in recent years, with the trend toward smaller and lighter electronic devices, there is an increasing demand for higher density integrated circuits, and there is also a demand for improved productivity in the manufacture of semiconductor devices including integrated circuits. [Prior art documents] [Patent documents]

[0009] [Patent Document 1] JP 2012-257187 A [Patent Document 2] JP 2011-151383 A Summary of the Invention [Problem to be solved by the invention]

[0010] An object of one embodiment of the present invention is to provide a semiconductor device having favorable electrical characteristics. Another object of one embodiment of the present invention is to provide a semiconductor device with favorable reliability. Another object of one embodiment of the present invention is to provide a semiconductor device with high on-state current. Another object of one embodiment of the present invention is to provide a semiconductor device with little variation in transistor characteristics. Another object of one embodiment of the present invention is to provide a semiconductor device that can be miniaturized or highly integrated. Another object of one embodiment of the present invention is to provide a semiconductor device with low power consumption. Another object of one embodiment of the present invention is to provide a method for manufacturing a semiconductor device with high productivity.

[0011] Note that the description of these problems does not preclude the existence of other problems. Note that one embodiment of the present invention does not necessarily solve all of these problems. Note that problems other than these will become apparent from the description of the specification, drawings, claims, etc., and it is possible to extract problems other than these from the description of the specification, drawings, claims, etc. [Means for solving the problem]

[0012] One embodiment of the present invention is a semiconductor device including a transistor having a gate electrode, a gate insulating film, a source electrode, and a drain electrode, a first insulator on the transistor, a second insulator on the first insulator, a third insulator on the second insulator, a first electrode in contact with an upper surface of the source electrode, and a second electrode in contact with an upper surface of the drain electrode, the second insulator has a first opening overlapping with the source electrode and a second opening overlapping with the drain electrode, the third insulator is in contact with a side surface of the second insulator and an upper surface of the first insulator inside the first opening and the second opening, the first electrode is disposed through the first opening, and the second electrode is disposed through the second opening.

[0013] In the above, it is preferable that the first insulator has a first groove overlapping the first opening, and a second groove overlapping the second opening.

[0014] In the above, the side surface of the first electrode may be in contact with the third insulator at the first opening and the first groove, and the side surface of the second electrode may be in contact with the third insulator at the second opening and the second groove.

[0015] In the above, it is preferable to have a fourth insulator provided in contact with a side surface of the first electrode and a fifth insulator provided in contact with a side surface of the second electrode, and the side surface of the fourth insulator contacts the third insulator at the first opening and the first groove, and the side surface of the fifth insulator contacts the third insulator at the second opening and the second groove.

[0016] In the above, the second insulator preferably contains aluminum oxide. In the above, the first insulator preferably contains silicon oxide, and the third insulator preferably contains silicon nitride. In the above, the transistor preferably includes an oxide semiconductor layer, and the oxide semiconductor layer preferably includes one or more selected from the group consisting of In, Ga, and Zn.

[0017] In the above, it is preferable that a gate insulating film, a source electrode, and a drain electrode are provided on the oxide semiconductor layer, a gate electrode is provided on the gate insulating film, the first insulator overlaps a region between the source electrode and the drain electrode, an opening is formed in the first insulator, and the gate insulating film and the gate electrode are disposed in the opening.

[0018] In the above, it is preferable that the semiconductor device further includes a sixth insulator covering the oxide semiconductor layer, the source electrode, and the drain electrode, the sixth insulator has an opening formed therein overlapping with a region between the source electrode and the drain electrode, and the first insulator is provided on the sixth insulator. In the above, it is preferable that the sixth insulator contains silicon nitride.

[0019] In the above, it is preferable that the first insulator and the second insulator are formed in an island shape, and the third insulator covers the first insulator and the second insulator.

[0020] In addition, in the above, the second insulator may have a third opening in a region that does not overlap with the gate electrode, the source electrode, and the drain electrode, and the third insulator may be configured to contact a side surface of the second insulator and an upper surface of the first insulator inside the third opening.

[0021] Another embodiment of the present invention is a method for manufacturing a semiconductor device, comprising: forming a transistor having a source electrode and a drain electrode; and a first insulator above the source electrode and the drain electrode; depositing a second insulator containing aluminum oxide over the first insulator; forming, in the second insulator, a first opening overlapping with the source electrode and a second opening overlapping with the drain electrode; depositing a third insulator over the first insulator and the second insulator; forming a fourth insulator to fill a region on the third insulator that overlaps with the first opening and the second opening; forming, in the first insulator, a third opening reaching the source electrode and a fourth opening reaching the drain electrode, in the first insulator, the third insulator, and the fourth insulator; the third opening is located inside the first opening in a top view and the fourth opening is located inside the second opening in a top view; and forming a first electrode in the third opening and a second electrode in the fourth opening.

[0022] In the above, it is preferable that the first insulator and the fourth insulator contain silicon oxide, and the third insulator contains silicon nitride.

[0023] In the above, the third opening and the fourth opening are preferably formed by dry etching using a gas containing fluorine.

[0024] Another embodiment of the present invention is a method for manufacturing a semiconductor device, comprising the steps of: forming a second insulator over a first insulator; forming an oxide semiconductor layer containing one or more elements selected from In, Ga, and Zn over the second insulator; processing the oxide semiconductor layer into an island shape by dry etching using a gas containing CH4; and processing the second insulator into an island shape by dry etching using a gas containing a halogen; and exposing a top surface of the first insulator.

[0025] In the above, it is preferable that the first insulator contains hafnium oxide and the second insulator contains silicon oxide.

[0026] In the above, it is preferable that after the second insulator is processed into an island shape, a third insulator is formed to cover the first insulator, the second insulator, and the oxide semiconductor layer, and the third insulator contains silicon nitride.

[0027] In the above, a hard mask containing tungsten is preferably formed over the oxide semiconductor layer and the oxide semiconductor layer is processed into an island shape using the hard mask. Effect of the Invention

[0028] According to one embodiment of the present invention, a semiconductor device having favorable electrical characteristics can be provided. According to one embodiment of the present invention, a semiconductor device with favorable reliability can be provided. According to one embodiment of the present invention, a semiconductor device with large on-state current can be provided. According to one embodiment of the present invention, a semiconductor device with less variation in transistor characteristics can be provided. According to one embodiment of the present invention, a semiconductor device that can be miniaturized or highly integrated can be provided. According to one embodiment of the present invention, a semiconductor device with low power consumption can be provided. According to one embodiment of the present invention, a method for manufacturing a semiconductor device with high productivity can be provided.

[0029] Note that the description of these effects does not preclude the existence of other effects. Note that one embodiment of the present invention does not need to have all of these effects. Note that effects other than these will become apparent from the description in the specification, drawings, claims, etc., and it is possible to extract effects other than these from the description in the specification, drawings, claims, etc. [Brief description of the drawings]

[0030] Fig. 1A is a top view of a semiconductor device according to one embodiment of the present invention, and Figs. 1B to 1D are cross-sectional views of the semiconductor device according to one embodiment of the present invention. 2A to 2D are cross-sectional views of a semiconductor device according to one embodiment of the present invention. FIG. 3 is a cross-sectional view of a semiconductor device according to an embodiment of the present invention. Figure 4A is a diagram explaining the classification of IGZO crystal structures, Figure 4B is a diagram explaining the XRD spectrum of a CAAC-IGZO film, and Figure 4C is a diagram explaining the ultrafine electron beam diffraction pattern of a CAAC-IGZO film. 5A is a top view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention, and FIGS. 5B to 5D are cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. 6A is a top view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention, and FIGS. 6B to 6D are cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. 7A is a top view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention, and FIGS. 7B to 7D are cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. 8A is a top view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention, and FIGS. 8B to 8D are cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. 9A is a top view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention, and FIGS. 9B to 9D are cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. 10A is a top view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention, and FIGS. 10B to 10D are cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. 11A is a top view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention, and FIGS. 11B to 11D are cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. 12A is a top view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention, and FIGS. 12B to 12D are cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. 13A is a top view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention, and FIGS. 13B to 13D are cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. 14A is a top view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention, and FIGS. 14B to 14D are cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. 15A is a top view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention, and FIGS. 15B to 15D are cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. 16A is a top view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention, and FIGS. 16B to 16D are cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. 17A is a top view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention, and FIGS. 17B to 17D are cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. 18A is a top view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention, and FIGS. 18B to 18D are cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. 19A is a top view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention, and FIGS. 19B to 19D are cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. 20A is a top view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention, and FIGS. 20B to 20D are cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. 21A is a top view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention, and FIGS. 21B to 21D are cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. 22A is a top view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention, and FIGS. 22B to 22D are cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. 23A is a top view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention, and FIGS. 23B to 23D are cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. 24A is a top view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention, and FIGS. 24B to 24D are cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. FIG. 25 is a schematic diagram showing a model of a dry etching process for an In-Ga-Zn oxide. FIG. 26 is a top view illustrating a microwave processing apparatus according to one embodiment of the present invention. FIG. 27 is a cross-sectional view illustrating a microwave processing apparatus according to one embodiment of the present invention. FIG. 28 is a cross-sectional view illustrating a microwave processing apparatus according to one embodiment of the present invention. FIG. 29 is a cross-sectional view illustrating a microwave processing apparatus according to one embodiment of the present invention. 30A and 30B are a top view and a cross-sectional view of a semiconductor device according to one embodiment of the present invention. Fig. 31A is a top view of a semiconductor device according to one embodiment of the present invention, and Fig. 31B is a cross-sectional view of the semiconductor device according to one embodiment of the present invention. 32A and 32B are a top view and a cross-sectional view of a semiconductor device according to one embodiment of the present invention. Fig. 33A is a top view of a semiconductor device according to one embodiment of the present invention, and Fig. 33B and Fig. 33C are cross-sectional views of the semiconductor device according to one embodiment of the present invention. FIG. 34 is a cross-sectional view illustrating a configuration of a memory device according to one embodiment of the present invention. FIG. 35 is a cross-sectional view illustrating a configuration of a memory device according to one embodiment of the present invention. FIG. 36 is a cross-sectional view of a semiconductor device according to one embodiment of the present invention. 37A and 37B are cross-sectional views of a semiconductor device according to one embodiment of the present invention. FIG. 38 is a cross-sectional view of a semiconductor device according to one embodiment of the present invention. 39A and 39B are block diagrams illustrating a configuration example of a storage device according to one embodiment of the present invention. 40A to 40H are circuit diagrams illustrating configuration examples of a memory device according to one embodiment of the present invention. Fig. 41A is a block diagram of a semiconductor device according to one embodiment of the present invention, and Fig. 41B is a schematic diagram of the semiconductor device according to one embodiment of the present invention. 42A and 42B are diagrams illustrating an example of an electronic component according to one embodiment of the present invention. 43A to 43E are schematic diagrams of a memory device according to one embodiment of the present invention. 44A to 44H are diagrams showing electronic devices according to one embodiment of the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0031] Hereinafter, the embodiments will be described with reference to the drawings. However, it will be easily understood by those skilled in the art that the embodiments can be implemented in many different ways, and that the modes and details can be changed in various ways without departing from the spirit and scope of the present invention. Therefore, the present invention should not be interpreted as being limited to the description of the following embodiments.

[0032] In addition, in the drawings, the size, thickness of the layer, or the area may be exaggerated for clarity. Therefore, it is not necessarily limited to the scale. In addition, the drawings are schematic illustrations of ideal examples, and are not limited to the shapes or values ​​shown in the drawings. For example, in the actual manufacturing process, layers or resist masks may be unintentionally thinned by etching or other processes, but this may not be reflected in the drawings to facilitate understanding. In addition, in the drawings, the same reference numerals are used in common between different drawings for the same parts or parts having similar functions, and repeated explanations may be omitted. In addition, when referring to similar functions, the same hatch pattern may be used and no particular reference numeral may be attached.

[0033] In order to facilitate understanding of the invention, particularly in top views (also called "plan views") or perspective views, some components may be omitted from the drawings. Also, some hidden lines may be omitted from the drawings.

[0034] In addition, in this specification, ordinal numbers such as first, second, etc. are used for convenience and do not indicate the order of steps or stacking. Therefore, for example, "first" can be appropriately replaced with "second" or "third" for explanation. In addition, the ordinal numbers described in this specification and the like may not match the ordinal numbers used to specify one embodiment of the present invention.

[0035] In addition, in this specification, the terms "above" and "below" indicating the arrangement are used for convenience in order to explain the positional relationship between the components with reference to the drawings. In addition, the positional relationship between the components changes as appropriate depending on the direction in which each component is depicted. Therefore, the terms are not limited to those described in the specification, and can be rephrased appropriately depending on the situation.

[0036] In addition, when it is explicitly stated in this specification that X and Y are connected, the case where X and Y are electrically connected, the case where X and Y are functionally connected, and the case where X and Y are directly connected are considered to be disclosed in this specification. Therefore, it is not limited to a specific connection relationship, for example, a connection relationship shown in a figure or text, and a connection relationship other than that shown in a figure or text is also considered to be disclosed in the figure or text. Here, X and Y are objects (for example, a device, an element, a circuit, wiring, an electrode, a terminal, a conductive film, a layer, etc.).

[0037] In this specification, a transistor is an element having at least three terminals including a gate, a drain, and a source. A region where a channel is formed between the drain (drain terminal, drain region, or drain electrode) and the source (source terminal, source region, or source electrode) (hereinafter, also referred to as a channel formation region) is provided, and a current can flow between the source and the drain through the channel formation region. In this specification, a channel formation region refers to a region through which a current mainly flows.

[0038] In addition, when a transistor with a polarity different from that described in the specification or drawings is used, or when the direction of current changes during circuit operation, the functions of the source and drain may be interchanged. For this reason, in this specification and the like, the terms source and drain may be used interchangeably depending on the situation.

[0039] The channel length refers to, for example, a region where the semiconductor (or a portion in the semiconductor through which current flows when the transistor is on) and the gate electrode overlap in a top view of a transistor, or a distance between the source (source region or source electrode) and the drain (drain region or drain electrode) in a channel formation region. Note that the channel length of one transistor does not necessarily have the same value in all regions. That is, the channel length of one transistor may not be fixed to one value. Therefore, in this specification, the channel length is defined as any one value, maximum value, minimum value, or average value in the channel formation region.

[0040] The channel width refers to, for example, the length of a channel formation region in a vertical direction based on the channel length direction in a region where a semiconductor (or a portion in the semiconductor through which current flows when the transistor is on) and a gate electrode overlap in a top view of a transistor, or in a channel formation region. Note that the channel width does not necessarily have the same value in all regions in one transistor. In other words, the channel width of one transistor may not be determined to a single value. Therefore, in this specification, the channel width is defined as any one value, maximum value, minimum value, or average value in the channel formation region.

[0041] In this specification and the like, depending on the structure of a transistor, the channel width in a region where a channel is actually formed (hereinafter also referred to as an "effective channel width") may differ from the channel width shown in a top view of the transistor (hereinafter also referred to as an "apparent channel width"). For example, when a gate electrode covers a side surface of a semiconductor, the effective channel width may be larger than the apparent channel width, and the influence of this may not be negligible. For example, in a fine transistor in which a gate electrode covers a side surface of a semiconductor, the proportion of a channel formation region formed on the side surface of the semiconductor may be large. In that case, the effective channel width is larger than the apparent channel width.

[0042] In such a case, it may be difficult to estimate the effective channel width by actual measurement. For example, in order to estimate the effective channel width from the design value, it is necessary to assume that the shape of the semiconductor is known. Therefore, if the shape of the semiconductor is not precisely known, it is difficult to accurately measure the effective channel width.

[0043] In this specification, when simply described as a channel width, it may refer to an apparent channel width. Alternatively, when simply described as a channel width, it may refer to an effective channel width. Note that the values ​​of the channel length, channel width, effective channel width, apparent channel width, etc. can be determined by analyzing a cross-sectional TEM image, etc.

[0044] Note that impurities in a semiconductor refer to, for example, anything other than the main components constituting the semiconductor. For example, an element with a concentration of less than 0.1 atomic % can be said to be an impurity. The inclusion of impurities can, for example, increase the density of defect states in the semiconductor or reduce the crystallinity. When the semiconductor is an oxide semiconductor, impurities that change the characteristics of the semiconductor include, for example, Group 1 elements, Group 2 elements, Group 13 elements, Group 14 elements, Group 15 elements, and transition metals other than the main components of the oxide semiconductor, such as hydrogen, lithium, sodium, silicon, boron, phosphorus, carbon, and nitrogen. Note that water can also function as an impurity. For example, the inclusion of impurities can cause oxygen deficiencies (V O :oxygen vacancy) may be formed.

[0045] In this specification and the like, an oxynitride is a material whose composition contains more oxygen than nitrogen. For example, a silicon oxynitride is a material whose composition contains more oxygen than nitrogen. A nitride oxide is a material whose composition contains more nitrogen than oxygen. For example, a silicon nitride oxide is a material whose composition contains more nitrogen than oxygen.

[0046] In this specification and the like, the term "insulator" can be replaced with an insulating film or an insulating layer, the term "conductor" can be replaced with a conductive film or a conductive layer, and the term "semiconductor" can be replaced with a semiconductor film or a semiconductor layer.

[0047] In addition, in this specification, "parallel" refers to a state in which two straight lines are arranged at an angle of -10 degrees or more and 10 degrees or less. Therefore, it also includes the case of -5 degrees or more and 5 degrees or less. "Approximately parallel" refers to a state in which two straight lines are arranged at an angle of -30 degrees or more and 30 degrees or less. "Perpendicular" refers to a state in which two straight lines are arranged at an angle of 80 degrees or more and 100 degrees or less. Therefore, it also includes the case of 85 degrees or more and 95 degrees or less. "Approximately perpendicular" refers to a state in which two straight lines are arranged at an angle of 60 degrees or more and 120 degrees or less.

[0048] In this specification and the like, the term "metal oxide" refers to an oxide of a metal in a broad sense. Metal oxides are classified into oxide insulators, oxide conductors (including transparent oxide conductors), oxide semiconductors (also referred to as oxide semiconductors or simply OS), and the like. For example, when a metal oxide is used for a semiconductor layer of a transistor, the metal oxide may be referred to as an oxide semiconductor. In other words, an OS transistor can be rephrased as a transistor having a metal oxide or an oxide semiconductor.

[0049] In this specification and the like, normally off means that when no potential is applied to the gate or when a ground potential is applied to the gate, the drain current flowing through the transistor per 1 μm of channel width is 1×10 -20 A or less, 1×10 at 85℃ -18 A or less, or 1×10 at 125°C -16 This means that it is A or lower.

[0050] (Embodiment 1) In this embodiment, an example of a semiconductor device according to one embodiment of the present invention and a manufacturing method thereof will be described with reference to FIGS.

[0051] One embodiment of the present invention can provide, for example, a semiconductor device including a plurality of transistors each having an oxide semiconductor layer. When impurities and oxygen vacancies are present in a region in which a channel is formed in the oxide semiconductor layer, the electrical characteristics of a transistor using the oxide semiconductor layer are likely to fluctuate and the reliability may be reduced. In addition, hydrogen near the oxygen vacancies may be introduced into the oxygen vacancies (hereinafter, referred to as V O H) and generate electrons that serve as carriers. For this reason, if oxygen vacancies are present in a region in the oxide semiconductor layer where a channel is formed, the transistor is likely to have normally-on characteristics (a channel exists even when no voltage is applied to the gate electrode, and a current flows through the transistor). Therefore, in the region in the oxide semiconductor layer where a channel is formed, impurities, oxygen vacancies, and V O It is preferable that H is reduced as much as possible. In other words, it is preferable that a region in the oxide semiconductor layer where a channel is formed has a reduced carrier concentration and is i-type (intrinsic) or substantially i-type.

[0052] In response to this, an insulator containing oxygen that is released by heating (hereinafter may be referred to as excess oxygen) is provided near the oxide semiconductor layer and heat treatment is performed. In this way, oxygen is supplied from the insulator to the oxide semiconductor layer, and oxygen vacancies and V O H can be reduced.

[0053] However, when an excessive amount of oxygen is supplied to the channel formation region of the oxide semiconductor layer or its vicinity (for example, the interface between the channel formation region and the gate insulating film), the electrical characteristics may deteriorate (for example, the transistor may become excessively normally off) or the reliability may deteriorate. Furthermore, when an excessive amount of oxygen is supplied to the source region or the drain region, the on-current or the field-effect mobility of the transistor may decrease. Furthermore, the amount of oxygen supplied may vary within the substrate surface, which may cause the electrical characteristics of the transistor to vary.

[0054] Therefore, in the oxide semiconductor layer, a sufficient amount of oxygen is preferably supplied to a region that functions as a channel formation region and its vicinity, but an excessive amount of oxygen is preferably not supplied.

[0055] In view of this, the semiconductor device described in this embodiment has a structure in which oxygen is diffused from an insulator containing oxygen that is released by heating to an oxide semiconductor layer and at the same time, oxygen is diffused outward from the insulator, whereby a sufficient amount of oxygen can be supplied from the insulator containing oxygen that is released by heating to a region in the oxide semiconductor layer that functions as a channel formation region and its vicinity, and an excessive amount of oxygen can be prevented from being supplied.

[0056] <Example of semiconductor device configuration> A configuration example of a semiconductor device having a transistor 200 will be described with reference to FIGS. 1A to 1D. FIG. 1A is a top view of the semiconductor device. FIGS. 1B to 1D are cross-sectional views of the semiconductor device. FIG. 1B is a cross-sectional view of a portion indicated by a dashed line A1-A2 in FIG. 1A, and is also a cross-sectional view of the transistor 200 in the channel length direction. FIG. 1C is a cross-sectional view of a portion indicated by a dashed line A3-A4 in FIG. 1A, and is also a cross-sectional view of the transistor 200 in the channel width direction. FIG. 1D is a cross-sectional view of a portion indicated by a dashed line A5-A6 in FIG. 1A, and is also a cross-sectional view of the transistor 200 in the channel width direction. Note that some elements are omitted in the top view of FIG. 1A for clarity.

[0057] A semiconductor device of one embodiment of the present invention includes an insulator 212 over a substrate (not shown), an insulator 214 over the insulator 212, a transistor 200 over the insulator 214, an insulator 280 over the transistor 200, an insulator 282 (insulator 282a and insulator 282b) over the insulator 280, an insulator 283 over the insulator 282, an insulator 286 over the insulator 283, and an insulator 274 over the sealing portion 265. The insulators 212, 214, 280, 282, 283, 286, and 274 function as interlayer films. The insulator 280 is an insulator containing oxygen that is released by heating as described above, and can supply oxygen to an oxide semiconductor layer included in the transistor 200. The encapsulating portion 265 is provided to surround the multiple transistors 200, the insulators 216, 280, and 282. In the encapsulating portion 265, the insulator 283 is in contact with the upper surface of the insulator 214.

[0058] [Aperture area 400] A semiconductor device according to one embodiment of the present invention includes a conductor 240a electrically connected to a conductor 242a of the transistor 200 and functioning as a plug, and a conductor 240b electrically connected to a conductor 242b of the transistor 200 and functioning as a plug. An opening region 400a is provided in the insulator 280 and the insulator 282 near the conductor 240a functioning as a plug, and similarly, an opening region 400b is provided in the insulator 280 and the insulator 282 near the conductor 240b. As shown in FIG. 1B and other drawings, the opening region 400a overlaps with the conductor 242a, and the opening region 400b overlaps with the conductor 242b. An insulator 241a is provided in contact with a side surface of the conductor 240a functioning as a plug, and similarly, an insulator 241b is provided in contact with a side surface of the conductor 240b. Moreover, a conductor 246a electrically connected to the conductor 240a and functioning as wiring is provided on the insulator 286 and the conductor 240a, and similarly, a conductor 246b electrically connected to the conductor 240b and functioning as wiring is provided on the insulator 286 and the conductor 240b. Moreover, an insulator 271a is provided in contact with the upper surface of the conductor 242a, and an insulator 271b is provided in contact with the upper surface of the conductor 242b. Moreover, an insulator 272 is provided so as to cover the conductor 242a, the conductor 242b, the insulator 271a, and the insulator 271b.

[0059] In the following, the conductor 242a and the conductor 242b may be collectively referred to as the conductor 242. The conductor 240a and the conductor 240b may be collectively referred to as the conductor 240. The opening region 400a and the opening region 400b may be collectively referred to as the opening region 400. The insulator 241a and the insulator 241b may be collectively referred to as the insulator 241. The conductor 246a and the conductor 246b may be collectively referred to as the conductor 246. The insulator 271a and the insulator 271b may be collectively referred to as the insulator 271.

[0060] At least one of the insulators 212, 214, 271, 272, 282, and 283 preferably functions as a barrier insulating film that suppresses diffusion of impurities such as water and hydrogen from the substrate side or from above the transistor 200 to the transistor 200. Therefore, at least one of the insulators 212, 214, 271, 272, 282, and 283 is preferably made of an insulating material that has a function of suppressing diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (N2O, NO, NO2, etc.), and copper atoms (through which the above impurities are difficult to permeate). Alternatively, it is preferable to use an insulating material that has a function of suppressing diffusion of oxygen (for example, at least one of oxygen atoms, oxygen molecules, etc.) (through which the above oxygen is difficult to permeate).

[0061] In this specification, a barrier insulating film refers to an insulating film having barrier properties. In this specification, the barrier properties refer to a function of suppressing diffusion of a corresponding substance (also referred to as low permeability). Alternatively, the barrier properties refer to a function of capturing and fixing (also referred to as gettering) a corresponding substance. For example, it is preferable to use insulating films having a high function of suppressing diffusion of hydrogen as the insulators 212, 272, and 283. It is also preferable to use insulating films having a high function of capturing and fixing hydrogen as the insulators 214, 271, and 282.

[0062] Here, Fig. 2A shows an enlarged cross-sectional view of the vicinity of conductor 240 shown in Fig. 1B etc. Fig. 2B shows an enlarged cross-sectional view of the configuration shown in Fig. 2A in a state before conductor 240 is formed. Note that Figs. 2A and 2B are drawings corresponding to both conductor 240a and conductor 240b.

[0063] 2B, insulator 282 has an opening in opening region 400. In addition, insulator 280 may have a groove overlapping the opening of insulator 282 in opening region 400. The depth of the groove in insulator 280 may be at most deep enough to expose the top surface of insulator 272, and may be, for example, about ¼ to ½ of the maximum film thickness of insulator 280.

[0064] By performing heat treatment in a state where such an opening region 400 is formed and the insulator 280 is exposed through the opening of the insulator 282, part of the oxygen contained in the insulator 280 can be diffused outward from the opening region 400 while oxygen is supplied to the oxide semiconductor layer of the transistor 200. In this manner, sufficient oxygen can be supplied from the insulator 280 containing oxygen released by heating to a region in the oxide semiconductor layer that functions as a channel formation region and its vicinity, while preventing an excessive amount of oxygen from being supplied.

[0065] At this time, hydrogen contained in the insulator 280 can be bonded to oxygen and released to the outside through the opening region 400. The hydrogen bonded to oxygen is released as water. Thus, the amount of hydrogen contained in the insulator 280 can be reduced, and the amount of hydrogen contained in the insulator 280 that enters the oxide semiconductor layer of the transistor 200 can be reduced.

[0066] 1A, the opening regions 400a and 400b are disposed on the conductors 242a and 242b, respectively, and are disposed approximately symmetrically with respect to the gate of the transistor 200. Thus, approximately equal amounts of oxygen can be supplied to the oxide semiconductor layer of the transistor 200 from the source side and the drain side. This can prevent a large imbalance in the amount of oxygen vacancies between the source side and the drain side in the channel formation region of the transistor 200.

[0067] As shown in Fig. 2B etc., insulator 283 contacts the side of insulator 282, the side of insulator 280, and the top surface of insulator 280 inside opening region 400. Also, as shown in Fig. 2B, before conductor 240 is formed, a part of insulator 274 may be formed in opening region 400 so as to fill a recess formed in insulator 283. At this time, as shown in Fig. 2B, the top surface of insulator 274 and the top surface of insulator 283 may roughly coincide with each other.

[0068] As shown in FIG. 2A and other figures, the conductor 240 is disposed so as to penetrate the opening region 400. In other words, the conductor 240 is disposed through the opening of the insulator 282, and is further provided so as to penetrate the bottom of the groove of the insulator 280. As shown in FIG. 2A, if the width of the opening region 400 is not sufficiently larger than the width of the conductor 240, the insulator 274 will be almost entirely removed when forming the opening into which the conductor 240 is embedded. In this case, in the opening region 400, the side surface of the insulator 241 will be in contact with the insulator 283.

[0069] In this manner, by forming the opening region 400 and the conductor 240 functioning as a plug to overlap each other when viewed from above, the opening region 400 can be provided without significantly increasing the area occupied by the transistor 200. As a result, even in a design in which a plurality of transistors 200 are densely arranged, the opening region 400 can be provided without changing the arrangement of the transistors 200 to provide extra space. With such a configuration, a semiconductor device that can be miniaturized or highly integrated can be provided.

[0070] In the above, the configuration in which the insulator 241 is provided in contact with the side surface of the conductor 240 has been described, but the present invention is not limited to this. For example, as shown in FIG. 2C, the configuration may be such that the insulator 241 is not provided on the side surface of the conductor 240. In this case, it is preferable that the excessive amount of impurities such as oxygen or hydrogen contained in the insulator 280 is sufficiently reduced. Here, the side surface of the conductor 240 contacts the insulator 283 in the opening region 400 (which may also be referred to as the opening of the insulator 282 and the groove portion of the insulator 280). With this configuration, most of the side surface of the conductor 240 is covered with the insulator 283, and the excessive amount of impurities such as oxygen or hydrogen in the insulator 280 is sufficiently reduced, so that impurities such as oxygen or hydrogen can be prevented from being mixed into the conductor 240.

[0071] In the above, a configuration in which the insulator 283 is provided in contact with the side surface of the insulator 241 has been described, but the present invention is not limited to this. For example, as shown in FIG. 2D, there is a case in which the insulator 274 remains in the opening region 400 and contacts the side surface of the insulator 241. In this case, the width of the opening region 400 (which may be rephrased as the width of the opening of the insulator 282 and the width of the groove portion of the insulator 280) is sufficiently larger than the width of the conductor 240. By providing the opening region 400 in this manner, a sufficient margin can be provided for the opening into which the conductor 240 is embedded.

[0072] 1A, the shape of the opening region 400a and the opening region 400b in a top view is substantially square, but the present invention is not limited to this. For example, the shape of the opening region 400a and the opening region 400b in a top view may be rectangular, elliptical, circular, rhombic, or a combination of these. The size of the opening region 400a and the opening region 400b can be appropriately set according to the design of the semiconductor device including the transistor 200.

[0073] [Transistor 200] As shown in FIGS. 1A to 1D , the transistor 200 includes an insulator 216 on an insulator 214, a conductor 205 (conductor 205a, conductor 205b, and conductor 205c) disposed so as to be embedded in the insulator 216, an insulator 222 on the insulator 216 and on the conductor 205, an insulator 224 on the insulator 222, an oxide 230a on the insulator 224, an oxide 230b on the oxide 230a, an oxide 243 (oxide 243a and oxide 243b) on the oxide 230b, a conductor 242a on the oxide 243a, and an insulator 271 on the conductor 242a. a, a conductor 242b on the oxide 243b, an insulator 271b on the conductor 242b, an insulator 250a on the oxide 230b, an insulator 250b on the insulator 250a, a conductor 260 (conductor 260a and conductor 260b) located on the insulator 250b and overlapping a part of the oxide 230b, and an insulator 272 arranged to cover the insulator 224, the oxide 230 (oxide 230a and oxide 230b), the oxide 243, the conductor 242 (conductor 242a and conductor 242b), and the insulator 271 (insulator 271a and insulator 271b). Here, as shown in FIG. 1B to FIG. 1D, the insulator 272 has an area in contact with a part of the upper surface of the insulator 222. Moreover, the upper surface of the conductor 260 is disposed so as to substantially coincide with the uppermost surface of the insulator 250 and the upper surface of the insulator 280. Moreover, the insulator 282 contacts the upper surfaces of the conductor 260, the insulator 250, and the insulator 280.

[0074] In the following, the oxide 230a and the oxide 230b may be collectively referred to as the oxide 230. Furthermore, the insulator 250a and the insulator 250b may be collectively referred to as the insulator 250.

[0075] The insulator 280 and the insulator 272 have openings that reach the oxide 230b. The insulator 250 and the conductor 260 are disposed in the openings. In addition, in the channel length direction of the transistor 200, the conductor 260 and the insulator 250 are provided between the insulator 271a, the conductor 242a, and the oxide 243a and the insulator 271b, the conductor 242b, and the oxide 243b. The insulator 250 contacts the side surface of the conductor 260 and the bottom surface of the conductor 260.

[0076] The conductor 260 functions as a first gate (also referred to as a top gate) electrode, and the conductor 205 functions as a second gate (also referred to as a back gate) electrode. The insulator 250 functions as a first gate insulating film, and the insulators 222 and 224 function as second gate insulating films. The conductor 242a functions as one of a source electrode or a drain electrode, and the conductor 242b functions as the other of the source electrode or the drain electrode. At least a part of a region of the oxide 230 overlapping with the conductor 260 functions as a channel formation region.

[0077] In the transistor 200, it is preferable to use a metal oxide that functions as a semiconductor (hereinafter also referred to as an oxide semiconductor) for the oxide 230 (the oxide 230a and the oxide 230b) including a channel formation region.

[0078] In addition, the metal oxide functioning as a semiconductor preferably has a band gap of 2 eV or more, more preferably 2.5 eV or more. By using a metal oxide having a wide band gap in this way, the off-state current of a transistor can be reduced.

[0079] As the oxide 230, for example, a metal oxide such as an In-M-Zn oxide having indium, an element M, and zinc (the element M is one or more selected from aluminum, gallium, yttrium, tin, copper, vanadium, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, etc.) may be used. Alternatively, as the oxide 230, an In-Ga oxide, an In-Zn oxide, or an indium oxide may be used.

[0080] Here, it is preferable that the atomic ratio of In to element M in the metal oxide used for oxide 230b is greater than the atomic ratio of In to element M in the metal oxide used for oxide 230a.

[0081] In this manner, by disposing the oxide 230a below the oxide 230b, it is possible to suppress the diffusion of impurities and oxygen from structures formed below the oxide 230a into the oxide 230b.

[0082] In addition, the oxide 230a and the oxide 230b have a common element other than oxygen (as a main component), so that the defect state density at the interface between the oxide 230a and the oxide 230b can be reduced. Since the defect state density at the interface between the oxide 230a and the oxide 230b can be reduced, the effect of interface scattering on carrier conduction is small, and a high on-current can be obtained.

[0083] Moreover, the oxide 230b preferably has crystallinity. In particular, it is preferable to use c-axis aligned crystalline oxide semiconductor (CAAC-OS) as the oxide 230b.

[0084] CAAC-OS has a highly crystalline and dense structure and is free of impurities or defects (e.g., oxygen vacancies (V O) is a metal oxide having a small amount of impurities. In particular, by performing heat treatment at a temperature at which the metal oxide does not become polycrystallized (for example, 400° C. or higher and 600° C. or lower) after the formation of the metal oxide, the CAAC-OS can have a dense structure with higher crystallinity. In this way, the density of the CAAC-OS can be increased, and the diffusion of impurities or oxygen in the CAAC-OS can be reduced.

[0085] On the other hand, it is difficult to identify clear grain boundaries in CAAC-OS, so it is unlikely that the electron mobility will decrease due to grain boundaries. Therefore, metal oxides with CAAC-OS have stable physical properties. Therefore, metal oxides with CAAC-OS are resistant to heat and highly reliable.

[0086] In addition, since a crystalline oxide such as CAAC-OS has few impurities or defects (such as oxygen vacancies) and a dense structure with high crystallinity, it is possible to suppress the extraction of oxygen from the oxide 230b by the source or drain electrode. As a result, even if a heat treatment is performed, the extraction of oxygen from the oxide 230b can be reduced, and the transistor 200 is stable against high temperatures (so-called thermal budget) in the manufacturing process.

[0087] Next, FIG. 3 shows an enlarged view of the vicinity of the channel formation region in FIG. 1B. As shown in FIG. 3, the oxide 230b has a region 230bc that functions as a channel formation region of the transistor 200, and regions 230ba and 230bb that are provided on either side of the region 230bc and function as a source region or a drain region. At least a portion of the region 230bc overlaps with the conductor 260. In other words, the region 230bc is provided in a region between the conductor 242a and the conductor 242b. The region 230ba is provided overlapping with the conductor 242a, and the region 230bb is provided overlapping with the conductor 242b.

[0088] The region 230bc functioning as a channel formation region has fewer oxygen vacancies or a lower impurity concentration than the regions 230ba and 230bb, and is therefore a high-resistance region with a low carrier concentration. The regions 230ba and 230bb functioning as a source region or drain region have many oxygen vacancies or a high concentration of impurities such as hydrogen, nitrogen, or metal elements, and therefore have an increased carrier concentration and low resistance. In other words, the regions 230ba and 230bb have a higher carrier concentration and lower resistance than the region 230bc.

[0089] Here, the carrier concentration of the region 230bc functioning as a channel forming region is 1×10 18 cm -3 It is preferable that the value is less than 1×10 17 cm -3 More preferably, it is less than 1×10 16 cm -3 More preferably, it is less than 1×10 13 cm -3 More preferably, it is less than 1×10 12 cm -3 The lower limit of the carrier concentration of the region 230bc that functions as a channel formation region is not particularly limited, but is, for example, 1×10 -9 cm -3 It can be said that:

[0090] In the present embodiment, as described above, it is possible to supply sufficient oxygen to the region 230bc and its vicinity from the insulator 280 containing oxygen that is desorbed by heating, without supplying an excessive amount of oxygen. In addition, at this time, it is possible to suppress the intrusion of hydrogen into the region 230bc. As a result, oxygen vacancies and V O By removing H, the region 230bc can be made i-type or substantially i-type. This can suppress fluctuations in the electrical characteristics of the transistor 200 and improve reliability. In addition, variation in the electrical characteristics of the transistor 200 within the substrate surface can be suppressed.

[0091] By adopting the above-mentioned configuration, it is possible to provide a semiconductor device having good electrical characteristics, a highly reliable semiconductor device, and a semiconductor device with less variation in transistor characteristics.

[0092] In addition, a region having a carrier concentration equal to or lower than that of the region 230ba and the region 230bb, and equal to or higher than that of the region 230bc, may be formed between the region 230bc and the region 230ba or the region 230bb. That is, the region functions as a junction region between the region 230bc and the region 230ba or the region 230bb. The junction region may have a hydrogen concentration equal to or lower than that of the region 230ba and the region 230bb, and equal to or higher than that of the region 230bc. The junction region may have an oxygen vacancy equal to or less than that of the region 230ba and the region 230bb, and equal to or more than that of the region 230bc.

[0093] 3 shows an example in which the regions 230ba, 230bb, and 230bc are formed in the oxide 230b, but the present invention is not limited to this. For example, each of the above regions may be formed not only in the oxide 230b but also in the oxide 230a.

[0094] In addition, it may be difficult to clearly detect the boundaries between the regions in the oxide 230. The concentrations of metal elements, hydrogen, nitrogen, and other impurity elements detected in each region may not only vary stepwise from region to region, but may also vary continuously within each region. In other words, it is sufficient that the concentrations of metal elements, hydrogen, nitrogen, and other impurity elements decrease in the region closer to the channel formation region.

[0095] In addition, as shown in FIG. 3, in a cross-sectional view of the transistor in the channel length direction, a groove may be formed in a region of the oxide 230b that overlaps with the insulator 250, and a part of the insulator 250 may be embedded in the groove. In this case, the insulator 250 is formed in contact with the sidewall and bottom surface of the groove. In this case, it is preferable that the film thickness of the insulator 250 is approximately the same as the depth of the groove. With this configuration, even if a damaged region is formed on the surface of the oxide 230b that is the bottom of the opening when forming an opening for embedding the conductor 260 or the like, the damaged region can be removed. This makes it possible to suppress defects in the electrical characteristics of the transistor 200 caused by the damaged region.

[0096] In FIG. 3 and other figures, the side of the opening in which the conductor 260 and the like are embedded is approximately perpendicular to the surface on which the oxide 230b is formed, including the groove of the oxide 230b, but this embodiment is not limited to this. For example, the bottom of the opening may be U-shaped with a gentle curve. Also, for example, the side of the opening may be inclined with respect to the surface on which the oxide 230b is formed.

[0097] 1C, in a cross-sectional view in the channel width direction of the transistor 200, a curved surface may be formed between the side surface of the oxide 230b and the top surface of the oxide 230b. In other words, the end of the side surface and the end of the top surface may be curved (also referred to as rounded).

[0098] The radius of curvature of the curved surface is preferably greater than 0 nm and smaller than the film thickness of the oxide 230b in the region overlapping with the conductor 242, or smaller than half the length of the region not having the curved surface. Specifically, the radius of curvature of the curved surface is greater than 0 nm and less than 20 nm, preferably greater than 1 nm and less than 15 nm, and more preferably greater than 2 nm and less than 10 nm. By forming the curved surface in this manner, the coverage of the oxide 230b by the insulator 250 and the conductor 260 can be improved.

[0099] The oxide 230 preferably has a laminated structure of a plurality of oxide layers with different chemical compositions. Specifically, in the metal oxide used for the oxide 230a, the atomic ratio of element M to the metal element that is the main component is preferably greater than the atomic ratio of element M to the metal element that is the main component in the metal oxide used for the oxide 230b. In addition, in the metal oxide used for the oxide 230a, the atomic ratio of element M to In is preferably greater than the atomic ratio of element M to In in the metal oxide used for the oxide 230b. In addition, in the metal oxide used for the oxide 230b, the atomic ratio of In to element M is preferably greater than the atomic ratio of In to element M in the metal oxide used for the oxide 230a.

[0100] Here, the conduction band minimum changes gradually at the junction between the oxide 230a and the oxide 230b. In other words, the conduction band minimum at the junction between the oxide 230a and the oxide 230b can be said to change continuously or to be a continuous junction. To achieve this, it is preferable to reduce the defect level density of the mixed layer formed at the interface between the oxide 230a and the oxide 230b.

[0101] Specifically, the oxide 230a and the oxide 230b have a common element other than oxygen as a main component, so that a mixed layer with a low density of defect states can be formed. For example, when the oxide 230b is an In-M-Zn oxide, the oxide 230a may be an In-M-Zn oxide, an M-Zn oxide, an oxide of element M, an In-Zn oxide, an indium oxide, or the like.

[0102] Specifically, the oxide 230a may be a metal oxide having a composition of In:M:Zn=1:3:4 [atomic ratio] or a composition close thereto, or In:M:Zn=1:1:0.5 [atomic ratio] or a composition close thereto. The oxide 230b may be a metal oxide having a composition of In:M:Zn=1:1:1 [atomic ratio] or a composition close thereto, or In:M:Zn=4:2:3 [atomic ratio] or a composition close thereto, or In:M:Zn=5:1:3 [atomic ratio] or a composition close thereto. The composition close thereto includes a range of ±30% of the desired atomic ratio. It is preferable to use gallium as the element M.

[0103] In addition, when a metal oxide film is formed by a sputtering method, the above atomic ratio is not limited to the atomic ratio of the formed metal oxide film, but may be the atomic ratio of a sputtering target used to form the metal oxide film.

[0104] By configuring the oxide 230a and the oxide 230b as described above, the defect state density at the interface between the oxide 230a and the oxide 230b can be reduced, so that the effect of interface scattering on carrier conduction is reduced, and the transistor 200 can obtain a large on-current and high frequency characteristics.

[0105] In the transistor 200, the oxide 230 has a two-layer structure of the oxide 230a and the oxide 230b, but the present invention is not limited to this. For example, the oxide 230b may have a single layer or a stacked structure of three or more layers. The oxide 230a and the oxide 230b may each have a stacked structure. When the oxide 230 has a stacked structure of three or more layers, a part of the stacked structure of the oxide 230 may be formed in the openings formed in the insulator 280 and the insulator 272, as in the case of the insulator 250.

[0106] For the insulators 212, 214, 271, 272, 282, and 283, it is preferable to use insulators having a function of suppressing the diffusion of impurities such as water and hydrogen, and oxygen. For example, aluminum oxide, magnesium oxide, hafnium oxide, gallium oxide, indium gallium zinc oxide, silicon nitride, or silicon nitride oxide can be used. For example, it is preferable to use silicon nitride, which has a higher hydrogen barrier property, for the insulators 212, 272, and 283. Also, for example, it is preferable to use aluminum oxide or magnesium oxide, which has a high function of capturing and fixing hydrogen, for the insulators 214, 271, and 282. This can suppress the diffusion of impurities such as water and hydrogen from the substrate side to the transistor 200 side through the insulators 212 and 214. Alternatively, it can suppress the diffusion of impurities such as water and hydrogen from an interlayer insulating film arranged outside the insulator 283 to the transistor 200 side. Alternatively, oxygen contained in the insulator 224 or the like can be suppressed from diffusing toward the substrate side through the insulator 212 and the insulator 214. Alternatively, oxygen contained in the insulator 280 or the like can be suppressed from diffusing upward from the transistor 200 through the insulator 282 or the like. In this manner, it is preferable to have a structure in which the transistor 200 is surrounded by the insulators 212, 214, 271, 272, 282, and 283, which have the function of suppressing the diffusion of impurities such as water and hydrogen, and oxygen.

[0107] Here, an oxide having an amorphous structure may be used as the insulator 212, the insulator 214, the insulator 271, the insulator 272, the insulator 282, and the insulator 283. In particular, it is preferable to use an oxide having an amorphous structure as the insulator 214, the insulator 271, and the insulator 282. For example, AlO x (x is any number greater than 0), or MgO yIt is preferable to use a metal oxide such as y (y is any number greater than 0). In such a metal oxide having an amorphous structure, oxygen atoms have dangling bonds, and the dangling bonds may have the property of capturing or fixing hydrogen. By using such a metal oxide having an amorphous structure as a component of the transistor 200 or providing it around the transistor 200, hydrogen contained in the transistor 200 or hydrogen present around the transistor 200 can be captured or fixed. In particular, it is preferable to capture or fix hydrogen contained in the channel formation region of the transistor 200. By using a metal oxide having an amorphous structure as a component of the transistor 200 or providing it around the transistor 200, a transistor 200 and a semiconductor device having good characteristics and high reliability can be manufactured.

[0108] The insulators 212, 214, 271, 272, 282, and 283 may be made of oxides having an amorphous structure, but may have a polycrystalline region formed in a portion thereof. The insulators 212, 214, 271, 272, 282, and 283 may have a multilayer structure in which a layer having an amorphous structure and a layer having a polycrystalline structure are stacked. For example, they may have a stacked structure in which a layer having a polycrystalline structure is formed on a layer having an amorphous structure.

[0109] The insulators 212, 214, 216, 271, 272, 280, 282, 283, and 286 may be formed by, for example, a sputtering method. Since the sputtering method does not require the use of hydrogen as a film formation gas, the hydrogen concentration of the insulators 212, 214, 216, 271, 272, 280, 282, 283, and 286 can be reduced. Note that the film formation method is not limited to the sputtering method, and a chemical vapor deposition (CVD) method, a molecular beam epitaxy (MBE) method, a pulsed laser deposition (PLD) method, an atomic layer deposition (ALD) method, or the like may be used as appropriate.

[0110] In addition, it may be preferable to reduce the resistivity of the insulator 212 and the insulator 283. For example, it is preferable to reduce the resistivity of the insulator 212 and the insulator 283 to approximately 1×10 13 By setting the resistivity at Ωcm, the insulator 212 and the insulator 283 may be able to reduce charge-up of the conductor 205, the conductor 242, the conductor 260, or the conductor 246 in a process using plasma or the like in a semiconductor device manufacturing process. The resistivity of the insulator 212 and the insulator 283 is preferably 1×10 10 Ωcm or more 1×10 15 Ωcm or less.

[0111] Furthermore, the insulators 216, 274, 280, and 286 preferably have a lower dielectric constant than the insulator 214. By using a material with a low dielectric constant as an interlayer film, the parasitic capacitance generated between wirings can be reduced. For example, silicon oxide, silicon oxynitride, silicon oxide to which fluorine has been added, silicon oxide to which carbon has been added, silicon oxide to which carbon and nitrogen have been added, silicon oxide having vacancies, or the like may be used as appropriate for the insulators 216, 274, 280, and 286.

[0112] The conductor 205 is disposed so as to overlap the oxide 230 and the conductor 260. Here, the conductor 205 is preferably provided by being embedded in an opening formed in the insulator 216. Note that a part of the conductor 205 may be embedded in the insulator 214.

[0113] The conductor 205 includes conductor 205a, conductor 205b, and conductor 205c. The conductor 205a is provided in contact with the bottom surface and side wall of the opening. The conductor 205b is provided so as to be embedded in a recess formed in the conductor 205a. Here, the upper surface of the conductor 205b is lower than the upper surface of the conductor 205a and the upper surface of the insulator 216. The conductor 205c is provided in contact with the upper surface of the conductor 205b and the side surface of the conductor 205a. Here, the height of the upper surface of the conductor 205c is approximately the same as the height of the top of the conductor 205a and the height of the upper surface of the insulator 216. In other words, the conductor 205b is configured to be wrapped in the conductor 205a and the conductor 205c.

[0114] Here, the conductor 205a and the conductor 205c are preferably made of a conductive material having a function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (NO, NO, NO, etc.), copper atoms, etc. Alternatively, it is preferable to use a conductive material having a function of suppressing the diffusion of oxygen (for example, at least one of oxygen atoms, oxygen molecules, etc.).

[0115] By using a conductive material having a function of reducing hydrogen diffusion for the conductor 205a and the conductor 205c, it is possible to prevent impurities such as hydrogen contained in the conductor 205b from diffusing into the oxide 230 via the insulator 224 and the like. In addition, by using a conductive material having a function of suppressing oxygen diffusion for the conductor 205a and the conductor 205c, it is possible to suppress the conductor 205b from being oxidized and its conductivity from decreasing. As the conductive material having a function of suppressing oxygen diffusion, it is preferable to use, for example, titanium, titanium nitride, tantalum, tantalum nitride, ruthenium, ruthenium oxide, or the like. Therefore, the conductor 205a may be a single layer or a multilayer of the above conductive material. For example, the conductor 205a may be made of titanium nitride.

[0116] The conductor 205b is preferably made of a conductive material containing tungsten, copper, or aluminum as a main component, for example, tungsten.

[0117] The conductor 205 may function as a second gate electrode. In this case, the threshold voltage (Vth) of the transistor 200 can be controlled by changing the potential applied to the conductor 205 independently of the potential applied to the conductor 260. In particular, applying a negative potential to the conductor 205 can increase the Vth of the transistor 200 and reduce the off-current. Therefore, applying a negative potential to the conductor 205 can reduce the drain current when the potential applied to the conductor 260 is 0 V, compared to not applying a negative potential.

[0118] The electrical resistivity of the conductor 205 is designed in consideration of the potential applied to the conductor 205, and the film thickness of the conductor 205 is set according to the electrical resistivity. The film thickness of the insulator 216 is approximately the same as that of the conductor 205. Here, it is preferable to make the film thicknesses of the conductor 205 and the insulator 216 thin within the range permitted by the design of the conductor 205. By making the film thickness of the insulator 216 thin, the absolute amount of impurities such as hydrogen contained in the insulator 216 can be reduced, and therefore the diffusion of the impurities into the oxide 230 can be reduced.

[0119] As shown in FIG. 1A, the conductor 205 is preferably provided larger than the size of the region of the oxide 230 that does not overlap with the conductor 242a and the conductor 242b. In particular, as shown in FIG. 1C, the conductor 205 preferably extends to the region outside the end of the oxide 230a and the oxide 230b in the channel width direction. In other words, outside the side surface of the oxide 230 in the channel width direction, the conductor 205 and the conductor 260 preferably overlap with each other via an insulator. With this configuration, the channel formation region of the oxide 230 can be electrically surrounded by the electric field of the conductor 260 functioning as the first gate electrode and the electric field of the conductor 205 functioning as the second gate electrode. In this specification, a structure of a transistor in which the channel formation region is electrically surrounded by the electric fields of the first gate and the second gate is called a surrounded channel (S-channel) structure.

[0120] In this specification and the like, a transistor with an S-channel structure refers to a transistor structure in which a channel formation region is electrically surrounded by the electric fields of one and the other of a pair of gate electrodes. The S-channel structure disclosed in this specification and the like is different from a fin type structure and a planar type structure. By adopting the S-channel structure, it is possible to improve resistance to the short channel effect, in other words, to make a transistor in which the short channel effect is unlikely to occur.

[0121] 1C, the conductor 205 is extended to function as wiring. However, the present invention is not limited to this, and a conductor functioning as wiring may be provided below the conductor 205. Also, it is not necessary to provide one conductor 205 for each transistor. For example, the conductor 205 may be shared by multiple transistors.

[0122] Note that, in the transistor 200, the conductor 205 has a stacked structure of the conductor 205a, the conductor 205b, and the conductor 205c, but the present invention is not limited to this. For example, the conductor 205 may have a single layer, a two-layer structure, or a stacked structure of four or more layers. For example, the conductor 205 may have a two-layer structure of the conductor 205a and the conductor 205b.

[0123] Insulator 222 and insulator 224 function as gate insulators.

[0124] The insulator 222 preferably has a function of suppressing the diffusion of hydrogen (e.g., at least one of hydrogen atoms, hydrogen molecules, etc.). The insulator 222 preferably has a function of suppressing the diffusion of oxygen (e.g., at least one of oxygen atoms, oxygen molecules, etc.). For example, the insulator 222 preferably has a function of suppressing the diffusion of one or both of hydrogen and oxygen more than the insulator 224.

[0125] The insulator 222 may be an insulator containing an oxide of one or both of aluminum and hafnium, which are insulating materials. As the insulator, it is preferable to use aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), or the like. When the insulator 222 is formed using such a material, the insulator 222 functions as a layer that suppresses the release of oxygen from the oxide 230 to the substrate side and the diffusion of impurities such as hydrogen from the periphery of the transistor 200 to the oxide 230. Thus, by providing the insulator 222, it is possible to suppress the diffusion of impurities such as hydrogen into the inside of the transistor 200 and to suppress the generation of oxygen vacancies in the oxide 230. In addition, it is possible to suppress the reaction of the conductor 205 with oxygen contained in the insulator 224 or the oxide 230.

[0126] Alternatively, for example, aluminum oxide, bismuth oxide, germanium oxide, niobium oxide, silicon oxide, titanium oxide, tungsten oxide, yttrium oxide, or zirconium oxide may be added to the insulator. Alternatively, these insulators may be nitrided. The insulator 222 may be formed by stacking silicon oxide, silicon oxynitride, or silicon nitride on these insulators.

[0127] The insulator 222 may be a single layer or a multilayer of insulators containing so-called high-k materials, such as aluminum oxide, hafnium oxide, tantalum oxide, zirconium oxide, lead zirconate titanate (PZT), strontium titanate (SrTiO3), (Ba,Sr)TiO3 (BST), etc. As transistors become smaller and more highly integrated, problems such as leakage current may occur due to the thinning of the gate insulator. By using a high-k material for the insulator that functions as the gate insulator, it is possible to reduce the gate potential during transistor operation while maintaining the physical film thickness.

[0128] The insulator 224 in contact with the oxide 230 may be made of, for example, silicon oxide, silicon oxynitride, or the like. The insulator 224 is preferably processed into an island shape so as to overlap with the oxide 230a. In this case, the insulator 272 is configured to be in contact with the side surface of the insulator 224 and the upper surface of the insulator 222. With this configuration, the volume of the insulator 224 can be significantly reduced, and the insulator 224 and the insulator 280 can be separated by the insulator 272. Therefore, the oxygen contained in the insulator 280 can be diffused into the insulator 224, and the oxygen in the insulator 224 can be prevented from becoming excessive.

[0129] The insulator 222 and the insulator 224 may have a laminated structure of two or more layers. In that case, the laminated structure is not limited to being made of the same material, and may be made of different materials. Although FIG. 1B and other figures show a configuration in which the insulator 224 is formed in an island shape by overlapping with the oxide 230a, the present invention is not limited to this. If the amount of oxygen contained in the insulator 224 can be appropriately adjusted, the insulator 224 may be configured not to be patterned, similar to the insulator 222.

[0130] An oxide 243a and an oxide 243b are provided on the oxide 230b. The oxide 243a and the oxide 243b are provided apart from each other with the conductor 260 therebetween.

[0131] The oxide 243 (oxide 243a and oxide 243b) preferably has a function of suppressing oxygen permeation. By disposing the oxide 243 having a function of suppressing oxygen permeation between the conductor 242 functioning as a source electrode or drain electrode and the oxide 230b, the electrical resistance between the conductor 242 and the oxide 230b is reduced, which is preferable. With such a structure, the electrical characteristics and reliability of the transistor 200 can be improved. Note that if the electrical resistance between the conductor 242 and the oxide 230b can be sufficiently reduced, the oxide 243 may not be provided.

[0132] A metal oxide having element M may be used as the oxide 243. In particular, aluminum, gallium, yttrium, or tin may be used as the element M. It is preferable that the oxide 243 has a higher concentration of element M than the oxide 230b. Gallium oxide may be used as the oxide 243. A metal oxide such as In-M-Zn oxide may be used as the oxide 243. Specifically, in the metal oxide used for the oxide 243, the atomic ratio of element M to In is preferably greater than the atomic ratio of element M to In in the metal oxide used for the oxide 230b. The film thickness of the oxide 243 is preferably 0.5 nm or more and 5 nm or less, more preferably 1 nm or more and 3 nm or less, and even more preferably 1 nm or more and 2 nm or less. It is preferable that the oxide 243 has crystallinity. When the oxide 243 has crystallinity, the release of oxygen in the oxide 230 can be suitably suppressed. For example, if the oxide 243 has a crystal structure such as a hexagonal crystal structure, the release of oxygen in the oxide 230 may be suppressed.

[0133] It is preferable that the conductor 242a be provided in contact with an upper surface of the oxide 243a, and the conductor 242b be provided in contact with an upper surface of the oxide 243b. The conductor 242a and the conductor 242b function as a source electrode and a drain electrode of the transistor 200, respectively.

[0134] As the conductor 242 (conductor 242a and conductor 242b), for example, a nitride containing tantalum, a nitride containing titanium, a nitride containing molybdenum, a nitride containing tungsten, a nitride containing tantalum and aluminum, a nitride containing titanium and aluminum, or the like is preferably used. In one embodiment of the present invention, a nitride containing tantalum is particularly preferable. Also, for example, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, an oxide containing lanthanum and nickel, or the like may be used. These materials are preferable because they are conductive materials that are difficult to oxidize, or materials that maintain their conductivity even when they absorb oxygen.

[0135] Note that hydrogen contained in the oxide 230b etc. may diffuse into the conductor 242a or the conductor 242b. In particular, by using a nitride containing tantalum for the conductor 242a and the conductor 242b, hydrogen contained in the oxide 230b etc. is likely to diffuse into the conductor 242a or the conductor 242b, and the diffused hydrogen may bond with nitrogen contained in the conductor 242a or the conductor 242b. In other words, hydrogen contained in the oxide 230b etc. may be absorbed by the conductor 242a or the conductor 242b.

[0136] It is preferable that no curved surface be formed between the side surface of the conductor 242 and the top surface of the conductor 242. The conductor 242 having no curved surface can increase the cross-sectional area of ​​the conductor 242 in the cross section in the channel width direction. This can increase the conductivity of the conductor 242 and the on-state current of the transistor 200.

[0137] The insulator 271a is provided in contact with the upper surface of the conductor 242a, and the insulator 271b is provided in contact with the upper surface of the conductor 242b. The upper surface of the insulator 271a is preferably in contact with the insulator 272, and a side surface of the insulator 271a is preferably in contact with the insulator 250. The upper surface of the insulator 271b is preferably in contact with the insulator 272, and a side surface of the insulator 271b is preferably in contact with the insulator 250. The insulator 271 preferably functions as a barrier insulating film against oxygen. Therefore, the insulator 271 preferably has a function of suppressing the diffusion of oxygen. For example, the insulator 271 preferably has a function of suppressing the diffusion of oxygen more than the insulator 280. As the insulator 271, for example, a nitride containing silicon such as silicon nitride may be used. The insulator 271 preferably has a function of capturing impurities such as hydrogen. In this case, an insulator such as a metal oxide having an amorphous structure, for example, aluminum oxide or magnesium oxide, may be used as the insulator 271. In particular, it is preferable to use aluminum oxide having an amorphous structure or aluminum oxide having an amorphous structure as the insulator 271 because hydrogen can be captured or fixed more effectively in some cases. This makes it possible to manufacture a transistor 200 and a semiconductor device having favorable characteristics and high reliability.

[0138] The insulator 272 is provided to cover the insulator 224, the oxide 230a, the oxide 230b, the oxide 243, the conductor 242, and the insulator 271. It is preferable that the insulator 272 has a function of suppressing the diffusion of hydrogen. In that case, it is preferable that the insulator 272 includes an insulator such as silicon nitride. Alternatively, the insulator 272 may have a function of capturing hydrogen and fixing hydrogen. In that case, it is preferable that the insulator 272 includes an insulator such as a metal oxide having an amorphous structure, for example, aluminum oxide or magnesium oxide.

[0139] The insulator 272 may have a layered structure. For example, the insulator 272 may have a layered structure of aluminum oxide and silicon nitride formed over the aluminum oxide. Such a layered structure is preferable because it can improve the barrier property more than a single layer of aluminum oxide or a single layer of silicon nitride.

[0140] By providing the insulators 271 and 272 as described above, the conductor 242 can be wrapped in an insulator having a barrier property against oxygen. In other words, it is possible to prevent the oxygen contained in the insulators 224 and 280 from diffusing into the conductor 242. This makes it possible to suppress a situation in which the conductor 242 is directly oxidized by the oxygen contained in the insulators 224 and 280, causing an increase in resistivity and a decrease in on-current.

[0141] The insulator 250 functions as a gate insulator. The insulator 250 is preferably disposed in contact with the upper surface of the oxide 230b. The insulator 250 can be made of silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide with added fluorine, silicon oxide having vacancies, or the like. Silicon oxide and silicon oxynitride are particularly preferred because they are stable against heat. Note that the insulator 250 preferably has a low carbon content in the film.

[0142] However, one embodiment of the present invention is not limited thereto, and the insulator 250 may contain carbon. For example, the carbon concentration of the insulator 250 is preferably 1×10 18 atoms / cm 3 5×10 or more 20 atoms / cm 3 Less than or equal to 5×10 18 atoms / cm 3 More than 1×10 20 atoms / cm 3 The carbon concentration in the film of the insulator 250 can be measured by SIMS analysis or the like.

[0143] The insulator 250 preferably has a reduced concentration of impurities such as water and hydrogen in the insulator 250, similar to the insulator 224. The thickness of the insulator 250 is preferably 1 nm or more and 20 nm or less.

[0144] As shown in FIG. 1B and FIG. 1C, when the insulator 250 has a two-layer laminate structure, it is preferable that the lower insulator 250a is formed using an insulator that easily transmits oxygen, and the upper insulator 250b is formed using an insulator that has a function of suppressing the diffusion of oxygen. With such a configuration, it is possible to suppress the diffusion of oxygen contained in the insulator 250a to the conductor 260. In other words, it is possible to suppress the decrease in the amount of oxygen supplied to the oxide 230. In addition, it is possible to suppress the oxidation of the conductor 260 due to the oxygen contained in the insulator 250a. For example, the insulator 250a is provided using a material that can be used for the insulator 250 described above, and the insulator 250b is preferably an insulator containing one or both of oxides of aluminum and hafnium. It is preferable to use aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), or the like as the insulator. The thickness of the insulator 250b is 0.5 nm or more and 3.0 nm or less, and preferably 1.0 nm or more and 1.5 nm or less.

[0145] When silicon oxide or silicon oxynitride is used for the lower layer of the insulator 250, the upper layer of the insulator 250 may be made of an insulating material that is a high-k material with a high dielectric constant. By forming the gate insulator into a laminated structure of the insulator 250a and the insulator 250b, it is possible to obtain a laminated structure that is stable against heat and has a high dielectric constant. Therefore, it is possible to reduce the gate potential applied during transistor operation while maintaining the physical thickness of the gate insulator. In addition, it is possible to reduce the equivalent oxide thickness (EOT) of the insulator that functions as the gate insulator.

[0146] Furthermore, a metal oxide may be provided between the insulator 250 and the conductor 260. The metal oxide preferably suppresses the diffusion of oxygen from the insulator 250 to the conductor 260. By providing a metal oxide that suppresses the diffusion of oxygen, the diffusion of oxygen from the insulator 250 to the conductor 260 is suppressed. In other words, a decrease in the amount of oxygen supplied to the oxide 230 can be suppressed. Furthermore, oxidation of the conductor 260 due to oxygen from the insulator 250 can be suppressed.

[0147] The metal oxide may be configured to function as a part of the first gate electrode. For example, the metal oxide that can be used as the oxide 230 may be used as the metal oxide. In this case, the electric resistance value of the metal oxide can be reduced to make it a conductor by forming the conductor 260a by a sputtering method. This can be called an OC (Oxide Conductor) electrode.

[0148] By including the metal oxide, the on-current of the transistor 200 can be improved without weakening the effect of the electric field from the conductor 260. Furthermore, by maintaining a distance between the conductor 260 and the oxide 230 due to the physical thickness of the insulator 250 and the metal oxide, it is possible to suppress leakage current between the conductor 260 and the oxide 230. Furthermore, by providing a stacked structure of the insulator 250 and the metal oxide, it is possible to easily and appropriately adjust the physical distance between the conductor 260 and the oxide 230 and the electric field strength applied from the conductor 260 to the oxide 230.

[0149] The conductor 260 functions as a first gate electrode of the transistor 200. The conductor 260 preferably includes a conductor 260a and a conductor 260b disposed on the conductor 260a. For example, the conductor 260a is preferably disposed so as to surround the bottom and side surfaces of the conductor 260b. As shown in FIG. 1B and FIG. 1C, the top surface of the conductor 260 is substantially aligned with the top surface of the insulator 250. Note that, although the conductor 260 is shown as a two-layer structure of the conductor 260a and the conductor 260b in FIG. 1B and FIG. 1C, the conductor 260 may be a single-layer structure or a stacked structure of three or more layers.

[0150] The conductor 260a is preferably made of a conductive material having a function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules, copper atoms, etc. Alternatively, it is preferably made of a conductive material having a function of suppressing the diffusion of oxygen (for example, at least one of oxygen atoms, oxygen molecules, etc.).

[0151] Furthermore, since the conductor 260a has a function of suppressing oxygen diffusion, it is possible to suppress a decrease in conductivity due to oxidation of the conductor 260b caused by oxygen contained in the insulator 250. As a conductive material having a function of suppressing oxygen diffusion, it is preferable to use, for example, titanium, titanium nitride, tantalum, tantalum nitride, ruthenium, ruthenium oxide, or the like.

[0152] In addition, since the conductor 260 also functions as wiring, it is preferable to use a conductor with high conductivity. For example, the conductor 260b can be a conductive material mainly composed of tungsten, copper, or aluminum. The conductor 260b may also have a laminated structure, for example, a laminated structure of titanium or titanium nitride and the above-mentioned conductive material.

[0153] Moreover, in the transistor 200, the conductor 260 is formed in a self-aligned manner so as to fill an opening formed in the insulator 280 or the like. By forming the conductor 260 in this manner, the conductor 260 can be reliably disposed in the region between the conductor 242a and the conductor 242b without alignment.

[0154] As shown in FIG. 1C, in the channel width direction of the transistor 200, the height of the bottom surface of the conductor 260 in the region where the conductor 260 and the oxide 230b do not overlap is preferably lower than the height of the bottom surface of the oxide 230b when the bottom surface of the insulator 222 is used as a reference. The conductor 260, which functions as a gate electrode, is configured to cover the side and upper surface of the channel formation region of the oxide 230b via the insulator 250 or the like, so that the electric field of the conductor 260 can be easily applied to the entire channel formation region of the oxide 230b. This makes it possible to increase the on-current of the transistor 200 and improve the frequency characteristics. When the bottom surface of the insulator 222 is used as a reference, the difference between the height of the bottom surface of the conductor 260 in the region where the oxide 230a and the oxide 230b do not overlap with the conductor 260 and the height of the bottom surface of the oxide 230b is 0 nm or more and 100 nm or less, preferably 3 nm or more and 50 nm or less, and more preferably 5 nm or more and 20 nm or less.

[0155] The insulator 280 is provided on the insulator 272, and has openings formed in the areas where the insulator 250 and the conductor 260 are provided. The upper surface of the insulator 280 may be flattened.

[0156] The insulator 280 that functions as an interlayer film preferably has a low dielectric constant. By using a material with a low dielectric constant as the interlayer film, the parasitic capacitance that occurs between wirings can be reduced. The insulator 280 is preferably formed using, for example, the same material as the insulator 216. In particular, silicon oxide and silicon oxynitride are preferable because they are thermally stable. In particular, materials such as silicon oxide, silicon oxynitride, and silicon oxide having vacancies are preferable because they can easily form a region containing oxygen that is desorbed by heating.

[0157] It is preferable to reduce the concentration of impurities such as water and hydrogen in the insulator 280. Therefore, for example, the insulator 280 may be made of an oxide containing silicon, such as silicon oxide or silicon oxynitride, as appropriate.

[0158] The insulator 282 preferably functions as a barrier insulating film that suppresses the diffusion of impurities such as water and hydrogen from above into the insulator 280, and preferably has a function of capturing impurities such as hydrogen. The insulator 282 preferably functions as a barrier insulating film that suppresses the transmission of oxygen. The insulator 282 may be an insulator such as a metal oxide having an amorphous structure, for example, aluminum oxide. By providing the insulator 282, which is in contact with the insulator 280 and has a function of capturing impurities such as hydrogen, in the region sandwiched between the insulator 212 and the insulator 283, the impurities such as hydrogen contained in the insulator 280 can be captured, and the amount of hydrogen in the region can be made constant. In particular, it is preferable to use aluminum oxide having an amorphous structure or aluminum oxide having an amorphous structure as the insulator 282, because hydrogen can be more effectively captured or fixed. This makes it possible to manufacture a transistor 200 and a semiconductor device having excellent characteristics and high reliability.

[0159] The insulator 282a and the insulator 282b on the insulator 282a can be deposited by sputtering in an atmosphere containing oxygen, thereby adding oxygen to the insulator 280. It is preferable that the insulator 282a has less oxygen added to the insulator 280 than the insulator 282b. For example, the RF power during deposition of the insulator 282a may be smaller than the RF power during deposition of the insulator 282b. This can prevent an excessive amount of oxygen from being added to the insulator 280. Note that in the insulator 282, it may be difficult to clearly detect the boundary between the insulator 282a and the insulator 282b.

[0160] In the above, an example has been shown in which the insulator 282 has a laminated structure of the insulator 282a and the insulator 282b, but the present invention is not limited to this. If the amount of oxygen added to the insulator 280 can be suitably adjusted, a configuration in which only one of the insulator 282a or the insulator 282b is provided may be used.

[0161] The insulator 283 functions as a barrier insulating film that suppresses the diffusion of impurities such as water and hydrogen from above into the insulator 280. The insulator 283 is disposed on the insulator 282. As the insulator 283, it is preferable to use a nitride containing silicon, such as silicon nitride or silicon nitride oxide. For example, the insulator 283 may be silicon nitride formed by a sputtering method. By forming the insulator 283 by a sputtering method, a silicon nitride film that is high in density and unlikely to form voids can be formed. Furthermore, as the insulator 283, silicon nitride formed by an ALD method may be stacked on silicon nitride formed by a sputtering method. With such a structure, even if defects, such as voids, occur in the silicon nitride formed by the sputtering method, the voids can be filled by the silicon nitride formed by the ALD method, which has good coverage, and thus the sealing performance can be improved.

[0162] The insulator 286 is provided on the insulator 283 and the insulator 274. Note that the region of the insulator 286 that overlaps with the conductor 246 may have a higher upper surface height than other regions of the insulator 286.

[0163] The insulator 241a is provided in contact with the inner wall of the opening formed in the insulator 280, the insulator 283, and the insulator 286 in which the conductor 240a is embedded, the first conductor of the conductor 240a is provided in contact with the side surface of the insulator 241a, and the second conductor of the conductor 240a is provided further inward. The insulator 241b is provided in contact with the inner wall of the opening formed in the insulator 280, the insulator 283, and the insulator 286 in which the conductor 240b is embedded, the first conductor of the conductor 240b is provided in contact with the side surface of the insulator 241b, and the second conductor of the conductor 240b is provided further inward. Here, it is preferable that the conductor 240a, the conductor 240b, the insulator 241a, and the insulator 241b are configured not to be in contact with the insulator 282. Furthermore, the height of the top surface of the conductor 240 and the height of the top surface of the insulator 286 in the area overlapping with the conductor 246 can be made approximately the same.

[0164] In the above, the first conductor of the conductor 240 and the second conductor of the conductor 240 are stacked, but the present invention is not limited to this. For example, the conductor 240 may be configured to have a single layer or a stacked structure of three or more layers. When the structure has a stacked structure, ordinal numbers may be given in the order of formation to distinguish them.

[0165] The conductor 240a and the conductor 240b are preferably made of a conductive material mainly composed of tungsten, copper, or aluminum. For example, the second conductor of the conductor 240a and the conductor 240b may be made of a conductive material mainly composed of tungsten, copper, or aluminum.

[0166] In addition, it is preferable to use a conductive material having a function of suppressing the permeation of impurities such as water and hydrogen for the first conductor. For example, it is preferable to use tantalum, tantalum nitride, titanium, titanium nitride, ruthenium, ruthenium oxide, etc. In addition, the conductive material having a function of suppressing the permeation of impurities such as water and hydrogen may be used in a single layer or a multilayer structure. In addition, it is possible to suppress impurities such as water and hydrogen contained in layers above the insulator 283 from being mixed into the oxide 230 through the conductor 240a and the conductor 240b.

[0167] 1A, the conductors 240a and 240b are circular in top view, but are not limited thereto. For example, the conductors 240a and 240b may be substantially circular, such as elliptical, polygonal, such as rectangular, or polygonal, such as rectangular, with rounded corners, in top view.

[0168] The insulator 241a and the insulator 241b may be, for example, an insulator such as silicon nitride, aluminum oxide, or silicon nitride oxide. The insulator 241 may have a laminated structure. For example, a silicon nitride layer may be provided in contact with the conductor 240, and an aluminum oxide layer may be provided outside the silicon nitride layer. The insulators 241a and 241b are provided in contact with the insulators 286, 283, 280, 272, and 271, so that impurities such as water and hydrogen contained in the insulator 280 and the like can be prevented from being mixed into the oxide 230 through the conductors 240a and 240b. In particular, silicon nitride is preferable because it has high barrier properties against hydrogen. In addition, it can prevent oxygen contained in the insulator 280 from being absorbed by the conductors 240a and 240b.

[0169] Conductors 246 (conductors 246a and 246b) may be disposed in contact with the upper surface of conductor 240a and the upper surface of conductor 240b to function as wiring. Conductor 246 is preferably made of a conductive material containing tungsten, copper, or aluminum as a main component. The conductor may have a laminated structure, for example, a laminate of titanium or titanium nitride and the above-mentioned conductive material. The conductor may be formed so as to be embedded in an opening provided in an insulator.

[0170] <Materials for semiconductor devices> The following describes constituent materials that can be used in the semiconductor device.

[0171] <<Substrate>> The substrate on which the transistor 200 is formed may be, for example, an insulating substrate, a semiconductor substrate, or a conductive substrate. Examples of insulating substrates include a glass substrate, a quartz substrate, a sapphire substrate, a stabilized zirconia substrate (such as an yttria stabilized zirconia substrate), and a resin substrate. Examples of semiconductor substrates include a semiconductor substrate made of silicon or germanium, or a compound semiconductor substrate made of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, and gallium oxide. Examples of semiconductor substrates include a semiconductor substrate having an insulating region inside the semiconductor substrate, such as an SOI (Silicon On Insulator) substrate. Examples of conductive substrates include a graphite substrate, a metal substrate, an alloy substrate, and a conductive resin substrate. Examples of substrates include a substrate having a metal nitride, a substrate having a metal oxide, and the like. Examples of substrates include a substrate having a conductor or semiconductor provided on an insulating substrate, a substrate having a conductor or insulator provided on a semiconductor substrate, and a substrate having a semiconductor or insulator provided on a conductive substrate. Alternatively, a substrate having elements provided thereon may be used. The elements provided on the substrate include a capacitor element, a resistor element, a switch element, a light-emitting element, a memory element, and the like.

[0172] <<Insulators>> Examples of the insulator include oxides, nitrides, oxynitrides, nitride oxides, metal oxides, metal oxynitrides, and metal nitride oxides, each of which has insulating properties.

[0173] For example, as transistors become smaller and more highly integrated, problems such as leakage current can occur due to thinner gate insulators. By using a high-k material for the insulator that functions as the gate insulator, it is possible to reduce the voltage required for transistor operation while maintaining the physical film thickness. On the other hand, by using a material with a low dielectric constant for the insulator that functions as the interlayer film, it is possible to reduce the parasitic capacitance that occurs between wiring. Therefore, it is best to select materials according to the function of the insulator.

[0174] Further, examples of insulators with a high relative dielectric constant include gallium oxide, hafnium oxide, zirconium oxide, oxides having aluminum and hafnium, oxynitrides having aluminum and hafnium, oxides having silicon and hafnium, oxynitrides having silicon and hafnium, and nitrides having silicon and hafnium.

[0175] Examples of insulators with a low dielectric constant include silicon oxide, silicon oxynitride, silicon oxide doped with fluorine, silicon oxide doped with carbon, silicon oxide doped with carbon and nitrogen, silicon oxide having voids, and resin.

[0176] In addition, the transistor using metal oxide can have stable electrical characteristics by being surrounded by an insulator having a function of suppressing the permeation of impurities such as hydrogen and oxygen. As the insulator having a function of suppressing the permeation of impurities such as hydrogen and oxygen, for example, an insulator containing boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, or tantalum may be used in a single layer or a stacked layer. Specifically, as the insulator having a function of suppressing the permeation of impurities such as hydrogen and oxygen, metal oxides such as aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide, and metal nitrides such as aluminum nitride, silicon nitride oxide, and silicon nitride can be used.

[0177] The insulator that functions as the gate insulator is preferably an insulator having a region containing oxygen that is released by heating. For example, by using a structure in which silicon oxide or silicon oxynitride having a region containing oxygen that is released by heating is in contact with the oxide 230, oxygen vacancies in the oxide 230 can be compensated for.

[0178] <<Conductors>> As the conductor, it is preferable to use a metal element selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, lanthanum, etc., or an alloy containing the above-mentioned metal elements as a component, or an alloy combining the above-mentioned metal elements. For example, it is preferable to use tantalum nitride, titanium nitride, tungsten, nitride containing titanium and aluminum, nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxide containing strontium and ruthenium, oxide containing lanthanum and nickel, etc. In addition, tantalum nitride, titanium nitride, nitride containing titanium and aluminum, nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxide containing strontium and ruthenium, oxide containing lanthanum and nickel are conductive materials that are difficult to oxidize, or materials that maintain conductivity even when oxygen is absorbed, so they are preferable. Furthermore, a semiconductor having high electrical conductivity, typified by polycrystalline silicon containing an impurity element such as phosphorus, or a silicide such as nickel silicide may be used.

[0179] A plurality of conductive layers formed of the above-mentioned materials may be stacked. For example, a stacked structure may be formed by combining the above-mentioned material containing a metal element and a conductive material containing oxygen. A stacked structure may be formed by combining the above-mentioned material containing a metal element and a conductive material containing nitrogen. A stacked structure may be formed by combining the above-mentioned material containing a metal element, a conductive material containing oxygen, and a conductive material containing nitrogen.

[0180] In addition, when an oxide is used for the channel formation region of a transistor, a conductor functioning as a gate electrode preferably has a stacked structure in which a material containing a metal element and a conductive material containing oxygen are combined. In this case, the conductive material containing oxygen is preferably provided on the channel formation region side. By providing the conductive material containing oxygen on the channel formation region side, oxygen released from the conductive material is easily supplied to the channel formation region.

[0181] In particular, it is preferable to use a conductive material containing oxygen and a metal element contained in the metal oxide in which the channel is formed as a conductor functioning as a gate electrode. A conductive material containing the above-mentioned metal element and nitrogen may also be used. For example, a conductive material containing nitrogen, such as titanium nitride or tantalum nitride, may also be used. Indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, and indium tin oxide to which silicon is added may also be used. Indium gallium zinc oxide containing nitrogen may also be used. By using such a material, hydrogen contained in the metal oxide in which the channel is formed may be captured. Alternatively, hydrogen mixed in from an external insulator may be captured.

[0182] <<Metal oxides>> It is preferable to use a metal oxide that functions as a semiconductor (oxide semiconductor) as the oxide 230. Hereinafter, a metal oxide that can be used as the oxide 230 and the oxide 243 according to the present invention will be described.

[0183] The metal oxide preferably contains at least indium or zinc. In particular, it is preferable that the metal oxide contains indium and zinc. In addition to these, it is preferable that the metal oxide contains aluminum, gallium, yttrium, tin, etc. In addition, it may contain one or more elements selected from boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, cobalt, etc.

[0184] Here, the case where the metal oxide is an In-M-Zn oxide having indium, element M, and zinc is considered. The element M is aluminum, gallium, yttrium, or tin. Other elements applicable to the element M include boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, and cobalt. However, there are cases where the element M may be a combination of multiple elements mentioned above.

[0185] In this specification and the like, metal oxides containing nitrogen may also be collectively referred to as metal oxides. Furthermore, metal oxides containing nitrogen may also be referred to as metal oxynitrides.

[0186] <Classification of crystal structures> First, classification of crystal structures in oxide semiconductors will be described with reference to Fig. 4A. Fig. 4A is a diagram for explaining classification of crystal structures of oxide semiconductors, typically IGZO (metal oxide containing In, Ga, and Zn).

[0187] As shown in FIG. 4A, oxide semiconductors are broadly classified into "Amorphous", "Crystalline", and "Crystal". "Amorphous" includes completely amorphous. "Crystalline" includes c-axis-aligned crystalline (CAAC), nanocrystalline (nc), and cloud-aligned composite (CAC) (excluding single crystal and poly crystal). "Crystalline" excludes single crystal, poly crystal, and completely amorphous. "Crystal" includes single crystal and poly crystal.

[0188] The structure in the bold frame shown in Fig. 4A is an intermediate state between "Amorphous" and "Crystal" and belongs to a new boundary region (New crystalline phase). In other words, this structure is completely different from the energetically unstable "Amorphous" or "Crystal".

[0189] The crystal structure of the film or substrate can be evaluated using X-ray diffraction (XRD) spectrum. Figure 4B shows the XRD spectrum obtained by GIXD (Grazing-Incidence XRD) measurement of the CAAC-IGZO film classified as "Crystalline". The GIXD method is also called the thin film method or the Seemann-Bohlin method. Hereinafter, the XRD spectrum obtained by the GIXD measurement shown in Figure 4B will be simply referred to as the XRD spectrum. The composition of the CAAC-IGZO film shown in Figure 4B is in the vicinity of In:Ga:Zn=4:2:3 [atomic ratio]. The thickness of the CAAC-IGZO film shown in Figure 4B is 500 nm.

[0190] As shown in Figure 4B, a peak indicating clear crystallinity is detected in the XRD spectrum of the CAAC-IGZO film. Specifically, a peak indicating c-axis orientation is detected near 2θ=31° in the XRD spectrum of the CAAC-IGZO film. Note that, as shown in Figure 4B, the peak near 2θ=31° is asymmetric with respect to the angle at which the peak intensity is detected.

[0191] The crystal structure of the film or substrate can be evaluated by a diffraction pattern (also called a nanobeam electron diffraction pattern) observed by nanobeam electron diffraction (NBED). The diffraction pattern of the CAAC-IGZO film is shown in Figure 4C. Figure 4C shows a diffraction pattern observed by NBED, which causes an electron beam to be incident parallel to the substrate. The composition of the CAAC-IGZO film shown in Figure 4C is approximately In:Ga:Zn=4:2:3 [atomic ratio]. In the nanobeam electron diffraction method, electron diffraction is performed with a probe diameter of 1 nm.

[0192] As shown in Figure 4C, multiple spots indicating c-axis orientation are observed in the diffraction pattern of the CAAC-IGZO film.

[0193] <<Structure of oxide semiconductor>> In addition, when focusing on the crystal structure, oxide semiconductors may be classified differently from that shown in FIG. 4A. For example, oxide semiconductors are divided into single-crystal oxide semiconductors and other non-single-crystal oxide semiconductors. Examples of non-single-crystal oxide semiconductors include the above-mentioned CAAC-OS and nc-OS. In addition, non-single-crystal oxide semiconductors include polycrystalline oxide semiconductors, pseudo-amorphous-like oxide semiconductors (a-like OS), amorphous oxide semiconductors, and the like.

[0194] Here, the above-mentioned CAAC-OS, nc-OS, and a-like OS will be described in detail.

[0195] [CAAC-OS] CAAC-OS is an oxide semiconductor having a plurality of crystalline regions, each of which has a c-axis aligned in a specific direction. The specific direction is the thickness direction of the CAAC-OS film, the normal direction of the surface on which the CAAC-OS film is formed, or the normal direction of the surface of the CAAC-OS film. The crystalline region is a region having periodic atomic arrangement. If the atomic arrangement is considered as a lattice arrangement, the crystalline region is also a region with a uniform lattice arrangement. CAAC-OS has a region in which a plurality of crystalline regions are connected in the ab-plane direction, and the region may have distortion. The distortion refers to a portion in which the direction of the lattice arrangement changes between a region with a uniform lattice arrangement and another region with a uniform lattice arrangement in the region in which the plurality of crystalline regions are connected. In other words, CAAC-OS is an oxide semiconductor having a c-axis aligned and no clear orientation in the ab-plane direction.

[0196] Each of the multiple crystalline regions is composed of one or more minute crystals (crystals with a maximum diameter of less than 10 nm). When a crystalline region is composed of one minute crystal, the maximum diameter of the crystalline region is less than 10 nm. When a crystalline region is composed of many minute crystals, the size of the crystalline region may be about several tens of nm.

[0197] In addition, in an In-M-Zn oxide (wherein element M is one or more elements selected from aluminum, gallium, yttrium, tin, titanium, etc.), the CAAC-OS tends to have a layered crystal structure (also referred to as a layered structure) in which a layer containing indium (In) and oxygen (hereinafter, In layer) and a layer containing element M, zinc (Zn), and oxygen (hereinafter, (M, Zn) layer) are stacked. Note that indium and element M are mutually substituted. Thus, the (M, Zn) layer may contain indium. Also, the In layer may contain element M. Note that the In layer may contain Zn. The layered structure is observed as a lattice image in a high-resolution TEM image, for example.

[0198] When the CAAC-OS film is subjected to structural analysis using, for example, an XRD device, a peak indicating c-axis orientation is detected at or near 2θ=31° in out-of-plane XRD measurement using θ / 2θ scan. Note that the position of the peak indicating c-axis orientation (2θ value) may vary depending on the type and composition of the metal elements constituting the CAAC-OS.

[0199] For example, a plurality of bright points (spots) are observed in the electron diffraction pattern of the CAAC-OS film, and the two spots are observed at positions symmetrical to each other with respect to the spot of the incident electron beam that has passed through the sample (also called the direct spot).

[0200] When the crystal region is observed from the specific direction, the lattice arrangement in the crystal region is based on a hexagonal lattice, but the unit cell is not necessarily a regular hexagon and may be a non-regular hexagon. The above distortion may have a lattice arrangement such as a pentagon or heptagon. In addition, in the CAAC-OS, no clear grain boundary can be confirmed even in the vicinity of the distortion. That is, it can be seen that the formation of grain boundaries is suppressed by the distortion of the lattice arrangement. This is thought to be because the CAAC-OS can tolerate distortion due to the fact that the arrangement of oxygen atoms is not dense in the ab-plane direction or the bond distance between atoms changes due to the substitution of metal atoms.

[0201] A crystal structure in which clear grain boundaries are observed is called a polycrystal. The grain boundaries are likely to become recombination centers, trap carriers, and cause a decrease in the on-current of a transistor and a decrease in field effect mobility. Therefore, CAAC-OS in which clear grain boundaries are not observed is one of the crystalline oxides having a crystal structure suitable for a semiconductor layer of a transistor. In order to form a CAAC-OS, a structure containing Zn is preferable. For example, In-Zn oxide and In-Ga-Zn oxide are suitable because they can suppress the occurrence of grain boundaries more than In oxide.

[0202] The CAAC-OS is an oxide semiconductor with high crystallinity and no clear crystal grain boundaries. Therefore, it can be said that the CAAC-OS is less susceptible to a decrease in electron mobility due to crystal grain boundaries. In addition, since the crystallinity of an oxide semiconductor can be decreased by the inclusion of impurities or the generation of defects, the CAAC-OS can be said to be an oxide semiconductor with few impurities or defects (such as oxygen vacancies). Therefore, the physical properties of an oxide semiconductor having the CAAC-OS are stable. Therefore, an oxide semiconductor having the CAAC-OS is resistant to heat and has high reliability. In addition, the CAAC-OS is stable against high temperatures (so-called thermal budget) in the manufacturing process. Therefore, the use of the CAAC-OS in an OS transistor can increase the degree of freedom in the manufacturing process.

[0203] [nc-OS] The nc-OS has periodic atomic arrangement in a minute region (for example, a region of 1 nm to 10 nm, particularly a region of 1 nm to 3 nm). In other words, the nc-OS has minute crystals. Note that the size of the minute crystals is, for example, 1 nm to 10 nm, particularly 1 nm to 3 nm, and therefore the minute crystals are also called nanocrystals. In addition, the nc-OS does not show regularity in the crystal orientation between different nanocrystals. Therefore, no orientation is seen in the entire film. Therefore, depending on the analysis method, the nc-OS may be indistinguishable from an a-like OS or an amorphous oxide semiconductor. For example, when a structure analysis is performed on an nc-OS film using an XRD device, no peak indicating crystallinity is detected in out-of-plane XRD measurement using θ / 2θ scan. In addition, when an nc-OS film is subjected to electron diffraction (also called selected area electron diffraction) using an electron beam with a probe diameter larger than that of nanocrystals (for example, 50 nm or more), a diffraction pattern like a halo pattern is observed. On the other hand, when electron diffraction (also called nanobeam electron diffraction) is performed on an nc-OS film using an electron beam with a probe diameter (e.g., 1 nm to 30 nm) that is close to the size of a nanocrystal or smaller than the nanocrystal, an electron diffraction pattern in which multiple spots are observed within a ring-shaped region centered on the direct spot may be obtained.

[0204] [a-like OS] The a-like OS is an oxide semiconductor having a structure between the nc-OS and an amorphous oxide semiconductor. The a-like OS has a void or low-density region. That is, the a-like OS has lower crystallinity than the nc-OS and CAAC-OS. Moreover, the a-like OS has a higher hydrogen concentration in the film than the nc-OS and CAAC-OS.

[0205] <<Oxide semiconductor structure>> Next, the above-mentioned CAC-OS will be described in detail, with reference to its material composition.

[0206] [CAC-OS] CAC-OS is, for example, a material configuration in which elements constituting a metal oxide are unevenly distributed in a size range of 0.5 nm to 10 nm, preferably 1 nm to 3 nm, or in the vicinity thereof. In the following, a state in which one or more metal elements are unevenly distributed in a metal oxide and the regions having the metal elements are mixed in a size range of 0.5 nm to 10 nm, preferably 1 nm to 3 nm, or in the vicinity thereof, is also referred to as a mosaic or patch state.

[0207] Furthermore, CAC-OS is a composite metal oxide in which the material is separated into a first region and a second region, forming a mosaic structure, and the first region is distributed throughout the film (also called a cloud structure). In other words, CAC-OS is a composite metal oxide in which the first region and the second region are mixed together.

[0208] Here, the atomic ratios of In, Ga, and Zn to the metal elements constituting the CAC-OS in the In-Ga-Zn oxide are represented as [In], [Ga], and [Zn], respectively. For example, in the CAC-OS in the In-Ga-Zn oxide, the first region is a region where [In] is larger than [In] in the composition of the CAC-OS film. Also, the second region is a region where [Ga] is larger than [Ga] in the composition of the CAC-OS film. Alternatively, for example, the first region is a region where [In] is larger than [In] in the second region and [Ga] is smaller than [Ga] in the second region. Also, the second region is a region where [Ga] is larger than [Ga] in the first region and [In] is smaller than [In] in the first region.

[0209] Specifically, the first region is a region mainly composed of indium oxide, indium zinc oxide, etc., and the second region is a region mainly composed of gallium oxide, gallium zinc oxide, etc. In other words, the first region can be rephrased as a region mainly composed of In, and the second region can be rephrased as a region mainly composed of Ga.

[0210] In addition, there are cases where a clear boundary between the first region and the second region cannot be observed.

[0211] For example, in the case of a CAC-OS of an In-Ga-Zn oxide, EDX mapping obtained using EDX (Energy Dispersive X-ray spectroscopy) has confirmed that the CAC-OS has a structure in which a region mainly composed of In (first region) and a region mainly composed of Ga (second region) are unevenly distributed and mixed.

[0212] When CAC-OS is used in a transistor, the conductivity due to the first region and the insulating property due to the second region act in a complementary manner, giving the CAC-OS a switching function (On / Off function). In other words, CAC-OS has a conductive function in part of the material and an insulating function in other parts of the material, and the material as a whole functions as a semiconductor. By separating the conductive function from the insulating function, it is possible to maximize both functions. Therefore, by using CAC-OS in a transistor, it is possible to achieve a high on-current (I on ), high field effect mobility (μ), and good switching behavior can be achieved.

[0213] Oxide semiconductors have a variety of structures and each structure has different characteristics. The oxide semiconductor of one embodiment of the present invention may include two or more of an amorphous oxide semiconductor, a polycrystalline oxide semiconductor, an a-like OS, a CAC-OS, an nc-OS, and a CAAC-OS.

[0214] <Transistor Having Oxide Semiconductor> Next, the case where the oxide semiconductor is used for a transistor will be described.

[0215] By using the oxide semiconductor for a transistor, a transistor with high field-effect mobility and high reliability can be realized.

[0216] For the channel formation region of the transistor, an oxide semiconductor with a low carrier concentration is preferably used. For example, the carrier concentration of the channel formation region of the oxide semiconductor is 1×10 17 cm -3 Less than or equal to 1×10 15 cm -3 Less than 1×10, more preferably 13 cm -3 Less than or equal to 1×10 11 cm -3 Less than 1×10, more preferably 10 cm -3Less than 1 x 10 -9 cm -3 The above is the case. Note that in order to reduce the carrier concentration of an oxide semiconductor film, the impurity concentration in the oxide semiconductor film may be reduced to reduce the density of defect states. In this specification and the like, an oxide semiconductor having a low impurity concentration and a low density of defect states is referred to as a high-purity intrinsic or substantially high-purity intrinsic oxide semiconductor. Note that an oxide semiconductor having a low carrier concentration may be referred to as a high-purity intrinsic or substantially high-purity intrinsic oxide semiconductor.

[0217] Furthermore, a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor film has a low density of defect states, and therefore the density of trap states might also be low.

[0218] In addition, charges trapped in the trap states of an oxide semiconductor take a long time to disappear and may behave as if they are fixed charges. Therefore, a transistor in which a channel formation region is formed in an oxide semiconductor with a high density of trap states may have unstable electrical characteristics.

[0219] Therefore, in order to stabilize the electrical characteristics of a transistor, it is effective to reduce the impurity concentration in the oxide semiconductor. In order to reduce the impurity concentration in the oxide semiconductor, it is preferable to also reduce the impurity concentration in a nearby film. Examples of impurities include hydrogen, nitrogen, alkali metals, alkaline earth metals, iron, nickel, silicon, and the like.

[0220] <Impurities> Here, the influence of each impurity in an oxide semiconductor will be described.

[0221] When an oxide semiconductor contains silicon or carbon, which is one of the Group 14 elements, defect levels are formed in the oxide semiconductor. For this reason, the concentration of silicon or carbon in the channel formation region of the oxide semiconductor and the concentration of silicon or carbon in the interface between the insulator and the channel formation region of the oxide semiconductor and in the vicinity of the interface (concentration obtained by secondary ion mass spectrometry (SIMS)) are set to 2×10 18 atoms / cm 3 Less than or equal to 2×10 17 atoms / cm 3 The following applies.

[0222] In addition, when an oxide semiconductor contains an alkali metal or an alkaline earth metal, defect levels are formed and carriers are generated in some cases. Therefore, a transistor using an oxide semiconductor containing an alkali metal or an alkaline earth metal is likely to have normally-on characteristics. For this reason, when the concentration of the alkali metal or the alkaline earth metal in the channel formation region of the oxide semiconductor obtained by SIMS is set to 1×10 18 atoms / cm 3 Less than or equal to 2×10 16 atoms / cm 3 To the following:

[0223] Furthermore, when nitrogen is contained in an oxide semiconductor, electrons serving as carriers are generated, the carrier concentration increases, and the semiconductor is likely to become n-type. As a result, a transistor using an oxide semiconductor containing nitrogen as a semiconductor is likely to have normally-on characteristics. Alternatively, when nitrogen is contained in an oxide semiconductor, trap states may be formed. As a result, the electrical characteristics of the transistor may become unstable. For this reason, the nitrogen concentration in the channel formation region of the oxide semiconductor obtained by SIMS is set to 5×10 19 atoms / cm 3 Less than 5 x 10 18 atoms / cm 3 Less than or equal to 1×10 18 atoms / cm 3 Less than 5×10, more preferably17 atoms / cm 3 To the following:

[0224] Furthermore, hydrogen contained in the oxide semiconductor reacts with oxygen bonded to a metal atom to form water, which may form an oxygen vacancy. When hydrogen enters the oxygen vacancy, electrons serving as carriers may be generated. In addition, some of the hydrogen may bond with oxygen bonded to a metal atom to generate electrons serving as carriers. Therefore, a transistor using an oxide semiconductor containing hydrogen is likely to have normally-on characteristics. For this reason, it is preferable to reduce hydrogen in the channel formation region of the oxide semiconductor as much as possible. Specifically, the hydrogen concentration measured by SIMS in the channel formation region of the oxide semiconductor is 1×10 20 atoms / cm 3 Less than 5 x 10 19 atoms / cm 3 less than 1×10 19 atoms / cm 3 less than 5×10 18 atoms / cm 3 less than 1×10 18 atoms / cm 3 Make it less than.

[0225] When an oxide semiconductor in which impurities are sufficiently reduced is used for a channel formation region of a transistor, stable electrical characteristics can be obtained.

[0226] <<Other semiconductor materials>> The semiconductor material that can be used for the oxide 230 is not limited to the above-mentioned metal oxides. A semiconductor material having a band gap (a semiconductor material that is not a zero-gap semiconductor) may be used for the oxide 230. For example, a semiconductor of a single element such as silicon, a compound semiconductor such as gallium arsenide, or a layered material (also called an atomic layer material, a two-dimensional material, etc.) that functions as a semiconductor is preferably used for the semiconductor material. In particular, it is preferable to use a layered material that functions as a semiconductor for the semiconductor material.

[0227] Here, in this specification and the like, the layered material is a general term for a group of materials having a layered crystal structure. The layered crystal structure is a structure in which layers formed by covalent bonds or ionic bonds are stacked via bonds weaker than covalent bonds or ionic bonds, such as van der Waals forces. The layered material has high electrical conductivity within a unit layer, that is, high two-dimensional electrical conductivity. By using a material that functions as a semiconductor and has high two-dimensional electrical conductivity in the channel formation region, a transistor with a large on-current can be provided.

[0228] Layered materials include graphene, silicene, and chalcogenides. Chalcogenides are compounds that contain chalcogen. Chalcogen is a general term for elements in group 16, including oxygen, sulfur, selenium, tellurium, polonium, and livermorium. Chalcogenides include transition metal chalcogenides and group 13 chalcogenides.

[0229] It is preferable to use, for example, a transition metal chalcogenide that functions as a semiconductor as the oxide 230. Specific examples of transition metal chalcogenides that can be used as the oxide 230 include molybdenum sulfide (representatively MoS2), molybdenum selenide (representatively MoSe2), molybdenum tellurium (representatively MoTe2), tungsten sulfide (representatively WS2), tungsten selenide (representatively WSe2), tungsten tellurium (representatively WTe2), hafnium sulfide (representatively HfS2), hafnium selenide (representatively HfSe2), zirconium sulfide (representatively ZrS2), and zirconium selenide (representatively ZrSe2).

[0230] <Method for manufacturing semiconductor device> Next, a manufacturing method of the semiconductor device of one embodiment of the present invention shown in FIGS. 1A to 1D will be described with reference to FIGS. 5A to 24D.

[0231] 5A to 24D, A in each figure shows a top view. B in each figure is a cross-sectional view corresponding to a portion indicated by a dashed line A1-A2 in A in each figure, and is also a cross-sectional view in the channel length direction of the transistor 200. C in each figure is a cross-sectional view corresponding to a portion indicated by a dashed line A3-A4 in A in each figure, and is also a cross-sectional view in the channel width direction of the transistor 200. D in each figure is a cross-sectional view corresponding to a portion indicated by a dashed line A5-A6 in A in each figure, and is also a cross-sectional view in the channel width direction of the transistor 200. Note that in the top view of A in each figure, some elements are omitted for clarity.

[0232] In the following, insulating materials for forming insulators, conductive materials for forming conductors, or oxide materials for forming oxides can be formed as films using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like, as appropriate.

[0233] There are three types of sputtering: RF sputtering, which uses a high-frequency power source for the sputtering power supply, DC sputtering, which uses a direct current power source, and pulsed DC sputtering, which changes the voltage applied to the electrode in a pulsed manner. RF sputtering is mainly used when depositing insulating films, while DC sputtering is mainly used when depositing metal conductive films. Pulsed DC sputtering is mainly used when depositing compounds such as oxides, nitrides, and carbides using reactive sputtering.

[0234] CVD methods can be classified into plasma enhanced CVD (PECVD), which uses plasma, thermal CVD (TCVD), which uses heat, photo CVD (Photo CVD), etc. They can also be further divided into metal CVD (MCVD) and metal organic CVD (MOCVD), depending on the source gas used.

[0235] The plasma CVD method can obtain a high-quality film at a relatively low temperature. Moreover, the thermal CVD method is a film formation method that can reduce plasma damage to the object to be processed because it does not use plasma. For example, wiring, electrodes, elements (transistors, capacitive elements, etc.) included in a semiconductor device may be charged up by receiving electric charge from plasma. At this time, the wiring, electrodes, elements, etc. included in the semiconductor device may be destroyed by the accumulated electric charge. On the other hand, in the case of the thermal CVD method that does not use plasma, such plasma damage does not occur, so the yield of the semiconductor device can be increased. Furthermore, in the thermal CVD method, plasma damage does not occur during film formation, so a film with few defects can be obtained.

[0236] As the ALD method, a thermal ALD method in which a reaction between a precursor and a reactant is carried out using only thermal energy, a plasma enhanced ALD method in which a plasma excited reactant is used, or the like can be used.

[0237] In addition, the ALD method utilizes the self-regulating nature of atoms to deposit atoms one layer at a time, and thus has the following advantages: extremely thin films can be formed; films can be formed on structures with high aspect ratios; films can be formed with fewer defects such as pinholes; films can be formed with excellent coverage; and films can be formed at low temperatures. In the PEALD method, the use of plasma can be preferable because it allows films to be formed at lower temperatures. Note that some precursors used in the ALD method contain impurities such as carbon. For this reason, films formed by the ALD method may contain more impurities such as carbon than films formed by other film formation methods. Note that the amount of impurities can be quantified using X-ray photoelectron spectroscopy (XPS).

[0238] The CVD method and the ALD method are different from the film formation method in which particles emitted from a target or the like are deposited, and are film formation methods in which a film is formed by a reaction on the surface of a workpiece. Therefore, they are film formation methods that are not easily affected by the shape of the workpiece and have good step coverage. In particular, the ALD method has excellent step coverage and excellent thickness uniformity, so it is suitable for coating the surface of an opening with a high aspect ratio. However, since the ALD method has a relatively slow film formation speed, it may be preferable to use it in combination with other film formation methods such as the CVD method, which has a fast film formation speed.

[0239] In the CVD method and the ALD method, the composition of the film obtained can be controlled by the flow rate ratio of the raw material gas. For example, in the CVD method and the ALD method, a film of any composition can be formed by changing the flow rate ratio of the raw material gas. In addition, for example, in the CVD method and the ALD method, a film whose composition changes continuously can be formed by changing the flow rate ratio of the raw material gas while forming the film. When forming a film while changing the flow rate ratio of the raw material gas, the time required for film formation can be shortened compared to the case of forming a film using multiple film formation chambers because no time is required for transportation or pressure adjustment. Therefore, the productivity of semiconductor devices can be increased in some cases.

[0240] First, a substrate (not shown) is prepared, and the insulator 212 is formed on the substrate (see FIGS. 5A to 5D). The insulator 212 is preferably formed by a sputtering method. By using a sputtering method that does not require hydrogen as a deposition gas, the hydrogen concentration in the insulator 212 can be reduced. However, the method for forming the insulator 212 is not limited to the sputtering method, and a CVD method, an MBE method, a PLD method, an ALD method, or the like may be used as appropriate.

[0241] In this embodiment, a silicon nitride film is formed as the insulator 212 by pulsed DC sputtering using a silicon target in an atmosphere containing nitrogen gas. By using pulsed DC sputtering, the generation of particles due to arcing on the target surface can be suppressed, making the film thickness distribution more uniform. In addition, by using a pulsed voltage, the rise and fall of the discharge can be made steeper than with a high-frequency voltage. This allows power to be supplied to the electrodes more efficiently, improving the sputtering rate and film quality.

[0242] By using an insulator such as silicon nitride through which impurities such as water and hydrogen do not easily permeate, it is possible to suppress the diffusion of impurities such as water and hydrogen contained in layers below the insulator 212. Furthermore, by using an insulator such as silicon nitride through which copper does not easily permeate as the insulator 212, even if a metal that easily diffuses, such as copper, is used for a conductor in a layer (not shown) below the insulator 212, it is possible to suppress the diffusion of the metal upward through the insulator 212.

[0243] Next, the insulator 214 is deposited on the insulator 212 (see FIGS. 5A to 5D). The insulator 214 is preferably deposited by a sputtering method. By using a sputtering method that does not require hydrogen as a deposition gas, the hydrogen concentration in the insulator 214 can be reduced. However, the deposition of the insulator 214 is not limited to the sputtering method, and a CVD method, an MBE method, a PLD method, an ALD method, or the like may also be used as appropriate.

[0244] In this embodiment, an aluminum oxide film is formed as the insulator 214 by pulsed DC sputtering using an aluminum target in an atmosphere containing oxygen gas. By using the pulsed DC sputtering method, the film thickness distribution can be made more uniform, and the sputtering rate and film quality can be improved. Here, RF (Radio Frequency) power may be applied to the substrate. The amount of oxygen injected into the layer below the insulator 214 can be controlled by the magnitude of the RF power applied to the substrate. The RF power is set to 0 W / cm. 2Above 1.86W / cm 2 The following is set forth. In other words, the amount of oxygen suitable for the transistor characteristics can be changed and injected by adjusting the RF power when forming the insulator 214. Therefore, it is possible to inject an amount of oxygen suitable for improving the reliability of the transistor. In addition, the RF frequency is preferably 10 MHz or higher. Typically, it is 13.56 MHz. The higher the RF frequency, the less damage can be caused to the substrate.

[0245] It is preferable to use a metal oxide having an amorphous structure, such as aluminum oxide, which has a high function of trapping and fixing hydrogen, as the insulator 214. This makes it possible to trap or fix hydrogen contained in the insulator 216 and the like and prevent the hydrogen from diffusing into the oxide 230. In particular, it is preferable to use aluminum oxide having an amorphous structure or aluminum oxide having an amorphous structure as the insulator 214, because hydrogen can be more effectively trapped or fixed. This makes it possible to manufacture a transistor 200 and a semiconductor device having excellent characteristics and high reliability.

[0246] Next, the insulator 216 is formed on the insulator 214 (see FIGS. 5A to 5D). The insulator 216 is preferably formed by a sputtering method. By using a sputtering method that does not require hydrogen as a deposition gas, the hydrogen concentration in the insulator 216 can be reduced. However, the method for forming the insulator 216 is not limited to the sputtering method, and a CVD method, an MBE method, a PLD method, an ALD method, or the like may also be used as appropriate.

[0247] In this embodiment, a silicon oxide film is formed by pulsed DC sputtering using a silicon target in an atmosphere containing oxygen gas as the insulator 216. By using the pulsed DC sputtering method, the film thickness distribution can be made more uniform, and the sputtering rate and film quality can be improved.

[0248] It is preferable that the insulators 212, 214, and 216 are successively formed without exposure to the air. For example, a multi-chamber film formation apparatus can be used. This allows the insulators 212, 214, and 216 to be formed with reduced hydrogen in the films, and further reduces the incorporation of hydrogen into the films between each film formation process.

[0249] Next, an opening is formed in the insulator 216, reaching the insulator 214 (see FIG. 5A to FIG. 5D). The opening includes, for example, a groove and a slit. The opening may be referred to as an opening. The opening may be formed by wet etching, but dry etching is preferable for fine processing. A dry etching apparatus, which will be described later, may be used for the dry etching. For the insulator 214, it is preferable to select an insulator that functions as an etching stopper film when etching the insulator 216 to form a groove. For example, when silicon oxide or silicon oxynitride is used for the insulator 216 that forms the groove, the insulator 214 may be silicon nitride, aluminum oxide, or hafnium oxide. A recess may be formed in the insulator 214 so as to overlap the opening of the insulator 216.

[0250] After the openings are formed, the conductive film 205A is formed (see FIGS. 5A to 5D). The conductive film 205A desirably includes a conductor having a function of suppressing oxygen transmission. For example, tantalum nitride, tungsten nitride, titanium nitride, or the like can be used. Alternatively, the conductive film 205A may be a stacked film of a conductor having a function of suppressing oxygen transmission and tantalum, tungsten, titanium, molybdenum, aluminum, copper, or a molybdenum-tungsten alloy. The conductive film 205A can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

[0251] In this embodiment, titanium nitride is formed as the conductive film 205A. By using such a metal nitride as the lower layer of the conductor 205b, it is possible to prevent the conductor 205b from being oxidized by the insulator 216 or the like. Even if a metal that easily diffuses, such as copper, is used as the conductor 205b, it is possible to prevent the metal from diffusing out of the conductor 205a.

[0252] Next, a conductive film 205B is formed (see FIGS. 5A to 5D). As the conductive film 205B, tantalum, tungsten, titanium, molybdenum, aluminum, copper, a molybdenum-tungsten alloy, or the like can be used. The conductive film can be formed by a plating method, a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. In this embodiment, tungsten is formed as the conductive film 205B.

[0253] Next, a CMP process is performed to remove a portion of the conductive film 205A and the conductive film 205B, thereby exposing the insulator 216 (see FIGS. 6A to 6D). As a result, the conductor 205a and the conductor 205b remain only in the openings. Note that the CMP process may remove a portion of the insulator 216.

[0254] Next, the upper portion of the conductor 205b is removed by etching (see FIGS. 7A to 7D). As a result, the upper surface of the conductor 205b becomes lower than the upper surfaces of the conductor 205a and the insulator 216. The conductor 205b can be etched by dry etching or wet etching, but dry etching is preferable for fine processing.

[0255] Next, the conductive film 205C is formed over the insulator 216, the conductor 205a, and the conductor 205b (see FIGS. 8A to 8D). The conductive film 205C preferably contains a conductor having a function of suppressing oxygen permeation, similar to the conductive film 205A.

[0256] In this embodiment, titanium nitride is formed as the conductive film 205C. By using such a metal nitride as the upper layer of the conductor 205b, it is possible to prevent the conductor 205b from being oxidized by the insulator 222 or the like. Even if a metal that easily diffuses, such as copper, is used as the conductor 205b, it is possible to prevent the metal from diffusing out of the conductor 205c.

[0257] Next, a part of the conductive film 205C is removed by performing CMP processing to expose the insulator 216 (see FIG. 9A to FIG. 9D). As a result, the conductor 205a, the conductor 205b, and the conductor 205c remain only in the opening. This allows the conductor 205 to be formed with a flat upper surface. Furthermore, the conductor 205b is configured to be surrounded by the conductor 205a and the conductor 205c. This prevents impurities such as hydrogen from the conductor 205b from diffusing out of the conductor 205a and the conductor 205c, and prevents oxygen from entering from outside the conductor 205a and the conductor 205c and oxidizing the conductor 205b. Note that the CMP processing may remove a part of the insulator 216.

[0258] Next, the insulator 222 is formed on the insulator 216 and the conductor 205 (see FIGS. 10A to 10D). As the insulator 222, an insulator containing one or both of an oxide of aluminum and hafnium may be formed. Note that as the insulator containing one or both of an oxide of aluminum and hafnium, it is preferable to use aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), or the like. An insulator containing one or both of an oxide of aluminum and hafnium has a barrier property against oxygen, hydrogen, and water. When the insulator 222 has a barrier property against hydrogen and water, the hydrogen and water contained in the structure provided around the transistor 200 are prevented from diffusing into the inside of the transistor 200 through the insulator 222, and the generation of oxygen vacancies in the oxide 230 can be suppressed.

[0259] The insulator 222 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, etc. In this embodiment, hafnium oxide is formed as the insulator 222 by an ALD method.

[0260] It is preferable to carry out a heat treatment subsequently. The heat treatment may be carried out at 250°C or higher and 650°C or lower, preferably 300°C or higher and 500°C or lower, and more preferably 320°C or higher and 450°C or lower. The heat treatment may be carried out in an atmosphere of nitrogen gas or an inert gas, or an atmosphere containing 10 ppm or higher, 1% or higher, or 10% or higher of an oxidizing gas. For example, when the heat treatment is carried out in a mixed atmosphere of nitrogen gas and oxygen gas, the oxygen gas may be about 20%. The heat treatment may be carried out under reduced pressure. Alternatively, the heat treatment may be carried out in an atmosphere of nitrogen gas or an inert gas, and then in an atmosphere containing 10 ppm or higher, 1% or higher, or 10% or higher of an oxidizing gas to compensate for the desorbed oxygen.

[0261] In addition, it is preferable that the gas used in the heat treatment is highly purified. For example, the amount of moisture contained in the gas used in the heat treatment is 1 ppb or less, preferably 0.1 ppb or less, and more preferably 0.05 ppb or less. By performing the heat treatment using a highly purified gas, it is possible to prevent moisture and the like from being taken into the insulator 222 as much as possible.

[0262] In this embodiment, after the insulator 222 is formed, heat treatment is performed at a flow rate ratio of nitrogen gas and oxygen gas of 4 slm:1 slm at a temperature of 400° C. for one hour. The heat treatment can remove impurities such as water and hydrogen contained in the insulator 222. When an oxide containing hafnium is used as the insulator 222, the heat treatment may cause part of the insulator 222 to crystallize. The heat treatment can also be performed at a timing such as after the insulator 224 is formed.

[0263] Next, the insulator 224 is formed on the insulator 222 (see FIGS. 10A to 10D). The insulator 224 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. In this embodiment, a silicon oxide film is formed as the insulator 224 by a sputtering method. By using a sputtering method that does not require hydrogen as a deposition gas, the hydrogen concentration in the insulator 224 can be reduced. Because the insulator 224 comes into contact with the oxide 230a in a later process, it is preferable that the hydrogen concentration be reduced in this manner.

[0264] Next, oxide films 230A and 230B are formed in this order on insulator 224 (see FIGS. 10A to 10D). Note that it is preferable to form oxide films 230A and 230B successively without exposing them to the atmospheric environment. By forming the films without exposing them to the atmosphere, it is possible to prevent impurities or moisture from the atmospheric environment from adhering to oxide films 230A and 230B, and it is possible to keep the vicinity of the interface between oxide films 230A and 230B clean.

[0265] The oxide film 230A and the oxide film 230B can be formed by using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

[0266] For example, when the oxide film 230A and the oxide film 230B are formed by sputtering, oxygen or a mixed gas of oxygen and a rare gas is used as the sputtering gas. By increasing the ratio of oxygen contained in the sputtering gas, the excess oxygen in the oxide film to be formed can be increased. In addition, when the oxide film is formed by sputtering, the above-mentioned In-M-Zn oxide target can be used.

[0267] In particular, during the formation of the oxide film 230A, a portion of the oxygen contained in the sputtering gas may be supplied to the insulator 224. Therefore, the ratio of oxygen contained in the sputtering gas may be 70% or more, preferably 80% or more, and more preferably 100%.

[0268] When the oxide film 230B is formed by a sputtering method, an oxygen-excessive oxide semiconductor is formed when the ratio of oxygen contained in the sputtering gas is more than 30% and less than or equal to 100%, preferably 70% to 100%. A transistor using an oxygen-excessive oxide semiconductor for a channel formation region can have relatively high reliability. However, one embodiment of the present invention is not limited thereto. When the oxide film 230B is formed by a sputtering method, an oxygen-deficient oxide semiconductor is formed when the ratio of oxygen contained in the sputtering gas is more than or equal to 1% and less than or equal to 30%, preferably 5% to 20%,. A transistor using an oxygen-deficient oxide semiconductor for a channel formation region can have relatively high field-effect mobility. When the oxide film is formed while the substrate is heated, the crystallinity of the oxide film can be improved.

[0269] In this embodiment, the oxide film 230A is formed by sputtering using an oxide target with an atomic ratio of In:Ga:Zn=1:3:4. The oxide film 230B is formed by sputtering using an oxide target with an atomic ratio of In:Ga:Zn=4:2:4.1. Each oxide film may be formed according to the characteristics required for the oxide 230a and the oxide 230b by appropriately selecting the film formation conditions and atomic ratio.

[0270] Next, the oxide film 243A is formed on the oxide film 230B (see FIGS. 10A to 10D). The oxide film 243A can be formed by sputtering, CVD, MBE, PLD, ALD, or the like. The atomic ratio of Ga to In in the oxide film 243A is preferably greater than the atomic ratio of Ga to In in the oxide film 230B. In this embodiment, the oxide film 243A is formed by sputtering using an oxide target with an atomic ratio of In:Ga:Zn=1:3:4.

[0271] It is preferable to form the insulator 222, the insulator 224, the oxide film 230A, the oxide film 230B, and the oxide film 243A by a sputtering method without exposing them to the atmosphere. For example, a multi-chamber film forming apparatus may be used. This allows the insulator 222, the insulator 224, the oxide film 230A, the oxide film 230B, and the oxide film 243A to be formed with reduced hydrogen in the films, and further reduces the inclusion of hydrogen in the films between each film forming process.

[0272] Next, it is preferable to carry out a heat treatment. The heat treatment may be carried out in a temperature range in which the oxide film 230A, the oxide film 230B, and the oxide film 243A are not polycrystallized, and may be carried out at a temperature of 250°C to 650°C, and preferably 400°C to 600°C. The heat treatment is carried out in an atmosphere of nitrogen gas or an inert gas, or an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas. For example, when the heat treatment is carried out in an atmosphere containing a mixture of nitrogen gas and oxygen gas, the oxygen gas may be about 20%. This supplies oxygen to the oxide 230, thereby reducing the oxygen deficiency (V O ) can be reduced. The heat treatment may be performed under reduced pressure. Alternatively, the heat treatment may be performed in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas in order to compensate for the desorbed oxygen after the heat treatment in an atmosphere of nitrogen gas or an inert gas.

[0273] In addition, the gas used in the heat treatment is preferably highly purified. For example, the amount of moisture contained in the gas used in the heat treatment may be 1 ppb or less, preferably 0.1 ppb or less, and more preferably 0.05 ppb or less. By using a highly purified gas to perform the heat treatment, it is possible to prevent moisture and the like from being taken into the oxide film 230A, the oxide film 230B, and the oxide film 243A as much as possible.

[0274] In this embodiment, the heat treatment is performed in a nitrogen atmosphere at 400°C for 1 hour, followed by another heat treatment in an oxygen atmosphere at 400°C for 1 hour. This heat treatment can remove impurities such as water and hydrogen from the oxide film 230A, the oxide film 230B, and the oxide film 243A. Furthermore, this heat treatment can improve the crystallinity of the oxide film 230B, resulting in a denser and more compact structure. This can reduce the diffusion of oxygen or impurities in the oxide film 230B.

[0275] In this way, by performing the oxygen supplying process on the oxide film 230A, the oxide film 230B, and the oxide film 243A, the oxygen vacancies in the oxide film 230A, the oxide film 230B, and the oxide film 243A are repaired by the supplied oxygen. In other words, O +O→null reaction can be promoted. Furthermore, the supplied oxygen reacts with the hydrogen remaining in the oxide film 230A, the oxide film 230B, and the oxide film 243A, and the hydrogen can be removed as H2O (dehydrated). As a result, the hydrogen remaining in the oxide 230 recombines with the oxygen vacancies to form V O The formation of H can be suppressed.

[0276] Next, the conductive film 242A is formed on the oxide film 243A (see FIGS. 10A to 10D). The conductive film 242A can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. For example, tantalum nitride may be formed as the conductive film 242A by a sputtering method. Note that a heat treatment may be performed before the conductive film 242A is formed. The heat treatment may be performed under reduced pressure, and the conductive film 242A may be formed continuously without exposure to the air. By performing such a treatment, moisture and hydrogen adsorbed on the surface of the oxide film 243A and the like can be removed, and the moisture concentration and hydrogen concentration in the oxide film 230A, the oxide film 230B, and the oxide film 243A can be further reduced. The temperature of the heat treatment is preferably 100° C. or higher and 400° C. or lower. In this embodiment, the temperature of the heat treatment is set to 200° C.

[0277] Next, the insulating film 271A is formed over the conductive film 242A (see FIGS. 10A to 10D). The insulating film 271A can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. The insulating film 271A is preferably an insulating film having a function of suppressing oxygen permeation. For example, the insulating film 271A may be formed of aluminum oxide by a sputtering method.

[0278] In this embodiment, the insulating film 271A is formed by pulse DC sputtering using an aluminum target in an atmosphere containing oxygen gas. The RF power applied to the substrate is 0.62 W / cm. 2 Less than or equal to 0 W / cm 2 More than 0.31W / cm 2 By reducing the RF power, the amount of oxygen implanted into the conductive film 242A can be suppressed, and oxidation of the conductive film 242A can be prevented.

[0279] Note that the conductive film 242A and the insulating film 271A are preferably formed by a sputtering method without exposure to the air. For example, a multi-chamber film formation apparatus may be used. This can reduce hydrogen in the conductive film 242A and the insulating film 271A and can also reduce hydrogen from entering the films between film formation steps.

[0280] Next, a hard mask layer 275A is formed on the insulating film 271A. (See FIG. 11A to FIG. 11D.) The hard mask layer 275A can be formed by sputtering, CVD, MBE, PLD, ALD, or the like. The hard mask layer 275A is a film that functions as a hard mask for forming the oxide 230b or the like in a later step. The hard mask layer 275A may be made of a metal material or an inorganic insulating material. For example, the hard mask layer 275A may be made of tungsten by sputtering. Alternatively, the hard mask layer 275A may be formed continuously after the insulating film 271A is formed without exposure to the air.

[0281] Next, an organic coating film 276A is formed on the hard mask layer 275A. (See FIG. 11A to FIG. 11D.) The organic coating film 276A may have a function of improving adhesion between a hard mask and a resist mask, which will be described later. The organic coating film 276A may be formed by, for example, a spin coating method. A non-photosensitive organic resin may be used as the organic coating film 276A. For example, a SOG (Spin On Glass) film or a SOC (Spin On Carbon) film may be formed as the organic coating film 276A. Also, for example, a laminated film in which an SOC film and an SOG film are formed thereon may be used as the organic coating film 276A. The organic coating film 276A may be provided as necessary, and if only a resist mask, which will be described later, is sufficient, the organic coating film 276A may not be provided.

[0282] Next, a resist mask 277 is formed on the organic coating film 276A using a lithography method. (See FIGS. 11A to 11D.) A photosensitive organic resin also called a photoresist may be used as the resist mask 277. For example, a positive photoresist or a negative photoresist may be used. The photoresist that becomes the resist mask 277 can be formed to a uniform thickness by forming a film using, for example, a spin coating method.

[0283] In the lithography method, first, a photoresist is exposed through a mask. Next, the exposed area is removed or left using a developer to form a resist mask 277. For example, the resist may be exposed using KrF excimer laser light, ArF excimer laser light, EUV (Extreme Ultraviolet) light, or the like to form the resist mask 277. Also, a liquid immersion technique may be used in which a liquid (e.g., water) is filled between the substrate and the projection lens for exposure. Also, an electron beam or an ion beam may be used instead of the light described above. When an electron beam or an ion beam is used, a mask is not required.

[0284] Next, using a resist mask 277, the conductive film 242A, the insulating film 271A, the hard mask layer 275A and the organic coating film 276A are processed into island shapes to form a conductive layer 242B, an insulating layer 271B, a hard mask 275 and an organic coating film 276 (see Figures 12A to 12D).

[0285] This processing can be performed by a dry etching method or a wet etching method. Since the processing by the dry etching method is suitable for fine processing, it is preferable to use the dry etching method. As the etching gas, a halogen-based etching gas containing one or more of fluorine, chlorine, and bromine can be used. In addition, oxygen gas, nitrogen gas, helium gas, argon gas, hydrogen gas, or the like can be appropriately added to the etching gas containing halogen. In addition, the etching conditions can be appropriately changed according to the objects to be etched (the conductive film 242A, the insulating film 271A, the hard mask layer 275A, and the organic coating film 276A).

[0286] As the dry etching apparatus, a capacitively coupled plasma (CCP) etching apparatus having parallel plate electrodes can be used. The capacitively coupled plasma etching apparatus having parallel plate electrodes can be configured to apply a high frequency voltage to one of the parallel plate electrodes. Alternatively, it can be configured to apply a plurality of different high frequency voltages to one of the parallel plate electrodes. Alternatively, it can be configured to apply a high frequency voltage of the same frequency to each of the parallel plate electrodes. Alternatively, it can be configured to apply high frequency voltages of different frequencies to each of the parallel plate electrodes. Alternatively, a dry etching apparatus having a high density plasma source can be used. As the dry etching apparatus having a high density plasma source, for example, an inductively coupled plasma (ICP) etching apparatus or the like can be used.

[0287] Next, the oxide film 230A, the oxide film 230B, and the oxide film 243A are processed into island shapes using a hard mask 275 to form an oxide 230a, an oxide 230b, and an oxide layer 243B (see FIGS. 13A to 13D).

[0288] This processing can be performed by using a dry etching method or a wet etching method. Since the dry etching method is suitable for fine processing, it is preferable to use the dry etching method. As the etching gas, it is preferable to use an etching gas containing a hydrocarbon such as methane (CH4) gas. Examples of the hydrocarbon used in the etching gas include methane (CH4), ethane (C2H6), propane (C3H8), and butane (C4H 10 ), ethylene (C2H4), propylene (C3H6), acetylene (C2H2), and propyne (C3H4) can be used. Note that oxygen gas, nitrogen gas, helium gas, argon gas, hydrogen gas, or the like can be added appropriately to the etching gas containing a hydrocarbon. In addition, the above-mentioned dry etching apparatus can be used in the etching process.

[0289] In this embodiment, the case where methane (CH4) is used as the etching gas is illustrated. When oxides containing one or more selected from In, Ga, and Zn are used as the oxide films 230A, 230B, and 243A, etching can be performed relatively easily by using methane (CH4) gas.

[0290] Here, an example of a model in which an oxide film 230B made of In-Ga-Zn oxide is etched using a mixed gas of CH4 gas and Ar gas will be described with reference to Fig. 25. In Fig. 25, In, Ga, and Zn are collectively referred to as metal atoms M e It is expressed as:

[0291] The Ar gas is ionized in the plasma to generate Ar ions. As shown in FIG. 25, the Ar ions are accelerated by a bias voltage applied to the electrode on the substrate side and collide with the surface of the oxide film 230B. Here, oxygen atoms in the oxide film 230B are converted into metal atoms M e Since it is lighter than the oxygen atom, it is relatively easily desorbed by the collision of an Ar ion. When an oxygen atom is desorbed, the metal atom M adjacent to the oxygen atom is desorbed. e The bond with the oxygen atom is broken, and the site where the oxygen atom was located is filled with an oxygen vacancy V O In this manner, oxygen atoms are removed from the oxide film 230B.

[0292] In addition, the CH4 gas is decomposed in the plasma to generate CH3 radicals 295. Here, the metal atom M e Therefore, as shown in FIG. 25, the generated CH3 radical 295 reacts with the metal atom M e It can be coordinated relatively easily to

[0293] Metal atom M coordinated with CH3 radical 295 e Further oxygen atom elimination proceeds around the metal atom M with the CH3 radical 295 coordinated. e and the metal atom M e The bond between the metal atom M and the adjacent oxygen atom is broken. e By repeating this cycle, the metal atom M e is sublimated as a metal complex 296. In this manner, the metal complex 296 is formed, and the metal atom M e is removed.

[0294] Here, for example, In(CH3)3, Ga(CH3)3, Zn(CH3)2, etc. are formed as the metal complex 296. All of these metal complexes have a boiling point of 70°C or less and are relatively volatile. Therefore, even if the substrate temperature is relatively low, the reaction of the model shown in FIG. 25 can proceed. In this way, by using a mixed gas of CH4 gas and Ar gas, it is possible to easily process In-Ga-Zn oxide, which is a material that is difficult to etch.

[0295] Although the etching model for the oxide film 230B has been described above, the oxide film 230A and the oxide film 243A can also be etched according to a similar model.

[0296] As described above, when dry etching is performed using CH4 gas or the like, by-products may be formed on the sides of the organic coating film 276 and the resist mask 277. Therefore, it is preferable to remove the organic coating film 276 and the resist mask 277 during the etching process shown in Fig. 12 or at an early stage of the etching process shown in Fig. 13, and perform the etching process using the hard mask 275 as a mask.

[0297] Furthermore, during dry etching using CH4 gas or the like, the organic coating film 276 and the resist mask 277 may disappear. For this reason, it is preferable to provide a hard mask 275 under the resist mask 277, which will not disappear during the etching process.

[0298] Furthermore, when the hard mask 275 contains tungsten and the insulator 224 contains silicon oxide, it is preferable to use methane (CH4) gas to etch the oxide film 230A, the oxide film 230B, and the oxide film 243A. By performing etching in this manner, the etching selectivity of the oxide film 230A, the oxide film 230B, and the oxide film 243A can be significantly larger than that of the hard mask 275 and the insulator 224. Therefore, in this process, the oxide film 230A, the oxide film 230B, and the oxide film 243A can be formed in an island shape while the insulator 224 is kept flat. As a result, in the process of forming the insulator 224 in an island shape described later, the region of the insulator 224 that does not overlap with the oxide 230a can be completely removed, and the insulator 222 can be prevented from being over-etched.

[0299] In addition, if the resist mask 277 and the organic coating film 276 remain after the process shown in FIG. 13, they may be removed by performing a dry etching process such as ashing, a wet etching process, a dry etching process followed by a wet etching process, or a dry etching process followed by a wet etching process.

[0300] Next, an etching process is performed to process the insulator 224 into an island shape by overlapping it with the oxide 230a (see FIGS. 14A to 14D). The etching process can be performed using a dry etching method or a wet etching method. Dry etching is suitable for fine processing, so it is preferable to use the dry etching method. As the etching gas, a halogen-based etching gas containing one or more of fluorine, chlorine, and bromine can be used. In addition, oxygen gas, nitrogen gas, helium gas, argon gas, hydrogen gas, or the like can be appropriately added to the etching gas containing halogen. In addition, the above-mentioned dry etching apparatus can be used in the etching process.

[0301] Here, it is preferable that the insulator 222 is not over-etched during processing of the insulator 224. Therefore, it is preferable to perform etching under conditions where the etching selectivity to the insulator 222 is large. For example, when the insulator 224 contains silicon oxide and etching is performed with a gas containing fluorine, it is preferable that the insulator 222 contains hafnium oxide. By performing etching in this manner, the insulator 272 can be provided in contact with the side surface of the insulator 224 and the upper surface of the insulator 222 in a process described later. That is, the insulator 224 can be separated from the insulator 280 by the insulator 272. With such a configuration, it is possible to prevent impurities such as an excessive amount of oxygen or hydrogen from being mixed into the oxide 230 from the insulator 280 via the insulator 224.

[0302] As described above, it is preferable to perform this etching step while keeping the insulator 224 flat, that is, while the variation in the thickness of the insulator 224 is small within the substrate surface. This reduces the variation in the time until the insulator 224 is removed within the substrate surface, so that it is possible to prevent the insulator 222 from being over-etched and losing a part of the insulator 222. Alternatively, it is possible to prevent a part of the insulator 224 from remaining on the insulator 222.

[0303] In addition, the hard mask 275 may be removed in this etching step (see FIGS. 14A to 14D). The hard mask 275 can be removed by a dry etching method or a wet etching method. However, if the material of the hard mask 275 does not affect a later step or can be used in a later step, it is not necessarily necessary to remove the hard mask 275.

[0304] In addition, in the process of removing the hard mask 275, the insulating layer 271B functions as a mask for the conductive layer 242B, so that the conductive layer 242B does not have a curved surface between the side surface and the top surface, as shown in FIG. 14B and FIG. 14C. As a result, the conductor 242a and the conductor 242b shown in FIG. 1B have angular ends where the side surface and the top surface intersect. The angular end where the side surface and the top surface of the conductor 242 intersect increases the cross-sectional area of ​​the conductor 242 compared to when the end has a curved surface. This reduces the resistance of the conductor 242, so that the on-current of the transistor 200 can be increased.

[0305] In addition, when the insulating layer 271B functions as a mask for the conductive layer 242B, the hard mask 275 may be removed before processing the insulator 224 into an island shape. In addition, the hard mask 275 may be removed in parallel with processing the insulator 224 into an island shape.

[0306] 12 to 14 may be performed continuously without exposure to the outside air. For example, the etching steps may be performed continuously in the same chamber, or a multi-chamber etching apparatus may be used to perform the etching steps without exposure to the outside air.

[0307] 12 to 14, the insulator 224, the oxide 230a, the oxide 230b, the oxide layer 243B, the conductive layer 242B, and the insulating layer 271B are formed so as to at least partially overlap with the conductor 205. It is preferable that the side surfaces of the insulator 224, the oxide 230a, the oxide 230b, the oxide layer 243B, the conductive layer 242B, and the insulating layer 271B are approximately perpendicular to the upper surface of the insulator 222. When the side surfaces of the insulator 224, the oxide 230a, the oxide 230b, the oxide layer 243B, the conductive layer 242B, and the insulating layer 271B are approximately perpendicular to the upper surface of the insulator 222, a reduction in area and a high density can be achieved when providing a plurality of transistors 200. Alternatively, the angles formed by the side surfaces of the insulator 224, the oxide 230a, the oxide 230b, the oxide layer 243B, the conductive layer 242B, and the insulating layer 271B and the upper surface of the insulator 222 may be low. In this case, the angles formed by the side surfaces of the insulator 224, the oxide 230a, the oxide 230b, the oxide layer 243B, the conductive layer 242B, and the insulating layer 271B and the upper surface of the insulator 222 are preferably 60 degrees or more and less than 70 degrees. By adopting such a shape, the coverage of the insulator 272 and the like can be improved in the subsequent steps, and defects such as porosity can be reduced.

[0308] 12 to 14 may be formed in layers on the side surfaces of the insulator 224, the oxide 230a, the oxide 230b, the oxide layer 243B, the conductive layer 242B, and the insulating layer 271B. In this case, the layered by-products are formed in the insulator 224, the oxide 230a, the oxide 230b, the oxide 243, the conductor 242, and between the insulators 271 and 272. If the transistor 200 is manufactured by proceeding with the process in a state in which the layered by-products are formed, the reliability of the transistor 200 may be deteriorated. Therefore, it is preferable to remove the layered by-products.

[0309] Next, the insulator 272 is formed on the insulator 222, the insulator 224, the oxide 230a, the oxide 230b, the oxide layer 243B, the conductive layer 242B, and the insulating layer 271B (see FIGS. 15A to 15D). The insulator 272 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. In this embodiment, the insulator 272 is formed by forming an aluminum oxide film by a pulse DC sputtering method using an aluminum target in an atmosphere containing oxygen gas. Alternatively, the insulator 272 may be formed by forming a silicon nitride film by a sputtering method. Also, the insulator 272 is in close contact with a part of the upper surface of the insulator 222.

[0310] The insulator 272 may have a multilayer structure. For example, an aluminum oxide film may be formed by sputtering, and a silicon nitride film may be formed on the aluminum oxide by sputtering. By forming the insulator 272 into such a multilayer structure, the function of suppressing the diffusion of impurities such as water and hydrogen, and oxygen may be improved.

[0311] In this manner, the oxide 230a, the oxide 230b, the oxide layer 243B, and the conductive layer 242B can be covered with the insulator 272 and the insulating layer 271B, which have a function of suppressing the diffusion of oxygen. This can reduce the diffusion of oxygen into the oxide 230a, the oxide 230b, the oxide layer 243B, and the conductive layer 242B in a later process.

[0312] Next, an insulating film to be the insulator 280 is formed on the insulator 272. The insulating film can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. For example, a silicon oxide film may be formed by a sputtering method as the insulating film. The insulating film to be the insulator 280 can be formed by a sputtering method in an atmosphere containing oxygen, thereby forming the insulator 280 containing excess oxygen. In addition, the hydrogen concentration in the insulator 280 can be reduced by using a sputtering method that does not require hydrogen as a deposition gas. Note that a heat treatment may be performed before the insulating film is formed. The heat treatment may be performed under reduced pressure, and the insulating film may be formed continuously without exposure to the atmosphere. By performing such a treatment, moisture and hydrogen adsorbed on the surface of the insulator 272 and the like can be removed, and the moisture concentration and hydrogen concentration in the oxide 230a, the oxide 230b, the oxide layer 243B, and the insulator 224 can be further reduced. The heat treatment conditions described above can be used for the heat treatment.

[0313] Next, the insulating film that becomes the insulator 280 is subjected to CMP processing to form the insulator 280 with a flat upper surface (see FIGS. 15A to 15D). Note that a silicon nitride film may be formed on the insulator 280 by, for example, a sputtering method, and the CMP processing may be performed until the silicon nitride reaches the insulator 280.

[0314] Next, a part of the insulator 280, a part of the insulator 272, a part of the insulating layer 271B, a part of the conductive layer 242B, and a part of the oxide layer 243B are processed to form an opening that reaches the oxide 230b. The opening is preferably formed so as to overlap the conductor 205. By forming the opening, the insulator 271a, the insulator 271b, the conductor 242a, the conductor 242b, the oxide 243a, and the oxide 243b are formed (see FIGS. 16A to 16D).

[0315] When forming the opening, the upper part of the oxide 230b may be removed. By removing a part of the oxide 230b, a groove portion is formed in the oxide 230b. Depending on the depth of the groove portion, the groove portion may be formed in the process of forming the opening, or may be formed in a process different from the process of forming the opening.

[0316] Furthermore, a part of the insulator 280, a part of the insulator 272, a part of the insulating layer 271B, a part of the conductive layer 242B, and the oxide layer 243B can be processed by dry etching or wet etching. Processing by the dry etching method is suitable for fine processing. Moreover, the processing may be performed under different conditions. For example, a part of the insulator 280 may be processed by dry etching, a part of the insulator 272 and a part of the insulating layer 271B may be processed by wet etching, and a part of the conductive layer 242B and a part of the oxide layer 243B may be processed by dry etching. Moreover, a part of the conductive layer 242B and a part of the oxide layer 243B may be processed under different conditions.

[0317] Here, impurities may adhere to the side of the oxide 230a, the top and side of the oxide 230b, the side of the conductor 242, the side of the insulator 280, etc., or may diffuse into these. A step of removing such impurities may be performed. In addition, a damaged area may be formed on the surface of the oxide 230b by the dry etching. Such a damaged area may be removed. The impurities may be due to components contained in the insulator 280, the insulator 272, a part of the insulating layer 271B, the conductive layer 242B, and the insulator 222, components contained in the members used in the device used to form the opening, and components contained in the gas or liquid used in the etching. The impurities may be, for example, hafnium, aluminum, silicon, tantalum, fluorine, chlorine, etc.

[0318] In particular, impurities such as aluminum or silicon inhibit the oxide 230b from becoming a CAAC-OS. Therefore, it is preferable that impurity elements such as aluminum or silicon that inhibit the CAAC-OS formation are reduced or removed. For example, the concentration of aluminum atoms in the oxide 230b and its vicinity may be 5.0 atomic % or less, preferably 2.0 atomic % or less, more preferably 1.5 atomic % or less, even more preferably 1.0 atomic % or less, and even more preferably less than 0.3 atomic %.

[0319] In addition, the region of the metal oxide in which the CAAC-OS formation is inhibited by impurities such as aluminum or silicon and which becomes an amorphous-like oxide semiconductor (a-like OS) is sometimes called a non-CAAC region. In the non-CAAC region, the density of the crystal structure is reduced, so the V O A large amount of H is formed, which makes the transistor more likely to be normally on. Therefore, it is preferable that the non-CAAC region of the oxide 230b is reduced or removed.

[0320] In contrast, it is preferable that the oxide 230b has a layered CAAC structure. In particular, it is preferable that the oxide 230b has the CAAC structure up to the lower end of the drain. Here, in the transistor 200, the conductor 242a or the conductor 242b and its vicinity function as the drain. In other words, it is preferable that the oxide 230b near the lower end of the conductor 242a (conductor 242b) has the CAAC structure. In this way, even at the drain end, which significantly affects the drain breakdown voltage, the damaged region of the oxide 230b is removed, and by having the CAAC structure, the fluctuation in the electrical characteristics of the transistor 200 can be further suppressed. In addition, the reliability of the transistor 200 can be improved.

[0321] In order to remove the above-mentioned impurities, a cleaning process is performed. The cleaning method includes wet cleaning using a cleaning solution, plasma processing using plasma, cleaning by heat treatment, and the like, and the above cleaning methods may be combined appropriately. Note that the above-mentioned grooves may become deeper due to the cleaning process.

[0322] For wet cleaning, a cleaning process may be performed using an aqueous solution of ammonia water, oxalic acid, phosphoric acid, hydrofluoric acid, or the like diluted with carbonated water or pure water, pure water, carbonated water, or the like. Alternatively, ultrasonic cleaning may be performed using these aqueous solutions, pure water, or carbonated water. Alternatively, these cleaning methods may be combined as appropriate.

[0323] In this specification, an aqueous solution obtained by diluting commercially available hydrofluoric acid with pure water may be called diluted hydrofluoric acid, and an aqueous solution obtained by diluting commercially available ammonia water with pure water may be called diluted ammonia water. The concentration and temperature of the aqueous solution may be appropriately adjusted depending on the impurities to be removed and the configuration of the semiconductor device to be cleaned. The ammonia concentration of the diluted ammonia water may be 0.01% or more and 5% or less, preferably 0.1% or more and 0.5% or less. The hydrogen fluoride concentration of the diluted hydrofluoric acid may be 0.01 ppm or more and 100 ppm or less, preferably 0.1 ppm or more and 10 ppm or less.

[0324] In addition, it is preferable to use a frequency of 200 kHz or more, and more preferably 900 kHz or more, for ultrasonic cleaning. By using such a frequency, damage to the oxide 230b and the like can be reduced.

[0325] The above cleaning process may be performed multiple times, and the cleaning solution may be changed for each cleaning process. For example, a first cleaning process may be performed using diluted hydrofluoric acid or diluted ammonia water, and a second cleaning process may be performed using pure water or carbonated water.

[0326] In the present embodiment, as the cleaning process, wet cleaning is performed using diluted hydrofluoric acid, followed by wet cleaning using pure water or carbonated water. By performing this cleaning process, impurities attached to the surfaces of the oxide 230a, the oxide 230b, etc. or diffused inside can be removed. Furthermore, the crystallinity of the oxide 230b can be improved.

[0327] In addition, if the above-mentioned impurities are not removed before forming the insulating film 250A described later, the impurities may remain between the oxide 230a, the oxide 230b, the conductor 242, the insulator 280, etc. and the insulator 250a.

[0328] After the etching or cleaning, a heat treatment may be performed. The heat treatment may be performed at a temperature of 100° C. to 450° C., preferably 350° C. to 400° C. The heat treatment is performed in an atmosphere of nitrogen gas or an inert gas, or an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas. For example, the heat treatment is preferably performed in an oxygen atmosphere. This supplies oxygen to the oxide 230a and the oxide 230b, thereby reducing the oxygen vacancy V. O In addition, by performing such a heat treatment, the crystallinity of the oxide 230b can be improved. The heat treatment may be performed under reduced pressure. Alternatively, after the heat treatment in an oxygen atmosphere, the heat treatment may be performed in a nitrogen atmosphere without exposure to the air.

[0329] Next, the insulating film 250A that becomes the insulator 250a is formed (see FIGS. 17A to 17D). A heat treatment may be performed before the formation of the insulating film 250A, and the heat treatment may be performed under reduced pressure, and the insulating film 250A may be formed continuously without exposure to the atmosphere. The heat treatment is preferably performed in an atmosphere containing oxygen. By performing such a treatment, moisture and hydrogen adsorbed on the surface of the oxide 230b can be removed, and the moisture concentration and hydrogen concentration in the oxide 230a and the oxide 230b can be further reduced. The temperature of the heat treatment is preferably 100° C. or higher and 400° C. or lower.

[0330] The insulating film 250A can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. The insulating film 250A is preferably formed by a film formation method using a gas in which hydrogen atoms are reduced or removed. This allows the hydrogen concentration of the insulating film 250A to be reduced. Since the insulating film 250A becomes the insulator 250a that contacts the oxide 230b in a later process, it is preferable that the hydrogen concentration is reduced in this manner.

[0331] In addition, it is preferable to form the insulating film 250A by using the ALD method. The thickness of the insulator 250 functioning as the gate insulating film of the miniaturized transistor 200 must be extremely thin (for example, about 5 nm to 30 nm) and have small variations. In contrast, the ALD method is a film formation method in which a precursor and a reactant (oxidizer) are alternately introduced, and the film thickness can be adjusted by the number of times this cycle is repeated, so that precise film thickness adjustment is possible. Therefore, the precision of the gate insulating film required by the miniaturized transistor 200 can be achieved. In addition, as shown in FIG. 17B and FIG. 17C, the insulating film 250A must be formed with good coverage on the bottom and side surfaces of the opening formed by the insulator 280 and the like. Since layers of atoms can be deposited one by one on the bottom and side surfaces of the opening, the insulating film 250A can be formed with good coverage on the opening.

[0332] In addition, for example, when the insulating film 250A is formed by using the PECVD method, the film formation gas containing hydrogen is decomposed in the plasma, and a large amount of hydrogen radicals is generated. The oxygen in the oxide 230b is extracted by the reduction reaction of the hydrogen radicals, and V O When H is formed, the hydrogen concentration in the oxide 230b increases. However, when the insulating film 250A is formed using the ALD method, the generation of hydrogen radicals can be suppressed both when the precursor and the reactant are introduced. Therefore, by forming the insulating film 250A using the ALD method, the hydrogen concentration in the oxide 230b can be prevented from increasing.

[0333] Next, a microwave treatment may be performed in an atmosphere containing oxygen (see Figs. 17A to 17D). Here, the microwave treatment refers to a treatment using a device having a power source that generates high density plasma using microwaves, for example. The dotted lines in Figs. 17B to 17D indicate microwaves, high frequency such as RF, oxygen plasma, or oxygen radicals. For the microwave treatment, it is preferable to use a microwave treatment device having a power source that generates high density plasma using microwaves, for example. The microwave treatment device may also have a power source that applies RF to the substrate side. By using high density plasma, high density oxygen radicals can be generated. Furthermore, by applying RF to the substrate side, oxygen ions generated by high density plasma can be efficiently introduced into the oxide 230b. Moreover, the microwave treatment is preferably performed under reduced pressure, and the pressure may be 60 Pa or more, preferably 133 Pa or more, more preferably 200 Pa or more, and even more preferably 400 Pa or more and 700 Pa or less. Moreover, it is preferable to perform the treatment at an oxygen flow rate ratio (O2 / O2+Ar) of 50% or less, preferably 10% or more and 30% or less. The treatment temperature may be 750° C. or less, preferably 500° C. or less, for example, about 400° C. After the oxygen plasma treatment, a heat treatment may be performed continuously without exposure to the outside air.

[0334] As shown in Figures 17B to 17D, by performing microwave processing in an atmosphere containing oxygen, oxygen gas can be turned into plasma using microwaves or high frequency waves such as RF, and the oxygen plasma can be applied to the region between the conductors 242a and 242b of the oxide 230b. At this time, microwaves or high frequency waves such as RF can also be irradiated to the region 230bc. In other words, microwaves, high frequency waves such as RF, oxygen plasma, etc. can be applied to the region 230bc shown in Figure 3. The action of the plasma, microwaves, etc. increases the V of the region 230bc. O H can be split off and hydrogen H can be removed from the region 230bc. O H→H+V O" occurs, and the hydrogen concentration in the region 230bc can be reduced. Therefore, the oxygen vacancies and V O By supplying oxygen radicals generated by the oxygen plasma or oxygen contained in the insulator 250 to the oxygen vacancies formed in the region 230bc, the oxygen vacancies in the region 230bc can be further reduced, and the carrier concentration can be reduced.

[0335] On the other hand, conductors 242a and 242b are provided on the regions 230ba and 230bb shown in Fig. 3. As shown in Fig. 17B to Fig. 17D, the conductors 242a and 242b block the effects of microwaves, high frequency waves such as RF, oxygen plasma, and the like, so that these effects do not reach the regions 230ba and 230bb. As a result, the microwave treatment causes a V O Since there is no reduction in H and no excessive supply of oxygen, a decrease in the carrier concentration can be prevented.

[0336] In this manner, oxygen vacancies and V are selectively formed in the oxide semiconductor region 230bc. O By removing H, the region 230bc can be made i-type or substantially i-type. Furthermore, the supply of excess oxygen to the regions 230ba and 230bb that function as source and drain regions can be suppressed, and the n-type can be maintained. This suppresses fluctuations in the electrical characteristics of the transistor 200, and suppresses variations in the electrical characteristics of the transistor 200 within the substrate surface.

[0337] Therefore, it is possible to provide a semiconductor device with less variation in transistor characteristics, a highly reliable semiconductor device, and a semiconductor device having good electrical characteristics.

[0338] In the microwave treatment, thermal energy may be directly transferred to the oxide 230b due to electromagnetic interaction between the microwaves and the molecules in the oxide 230b. The oxide 230b may be heated by this thermal energy. Such a heating treatment may be called microwave annealing. By performing the microwave treatment in an atmosphere containing oxygen, an effect equivalent to that of oxygen annealing may be obtained. In addition, if the oxide 230b contains hydrogen, it is considered that the thermal energy is transferred to the hydrogen in the oxide 230b, and thus the activated hydrogen is released from the oxide 230b.

[0339] Next, the insulating film 250B that becomes the insulator 250b is formed (see FIG. 18A to FIG. 18D). The insulating film 250B can be formed by sputtering, CVD, MBE, PLD, ALD, or the like. The insulating film 250B is preferably formed by using an insulator that has a function of suppressing the diffusion of oxygen. With such a configuration, it is possible to suppress the diffusion of oxygen contained in the insulator 250a to the conductor 260. That is, it is possible to suppress the decrease in the amount of oxygen supplied to the oxide 230. In addition, it is possible to suppress the oxidation of the conductor 260 due to the oxygen contained in the insulator 250a. For example, the insulating film 250A can be provided by using a material that can be used for the insulator 250 described above, and the insulating film 250B can be provided by using a material similar to that of the insulator 222.

[0340] Specifically, the insulating film 250B may be a metal oxide containing one or more of hafnium, aluminum, gallium, yttrium, zirconium, tungsten, titanium, tantalum, nickel, germanium, magnesium, etc., or a metal oxide that can be used as the oxide 230. In particular, it is preferable to use an insulator containing an oxide of one or both of aluminum and hafnium.

[0341] In this embodiment, the insulating film 250A is formed of silicon oxynitride by a CVD method, and the insulating film 250B is formed of hafnium oxide by a thermal ALD method.

[0342] A microwave treatment may be performed after the formation of the insulating film 250B. The microwave treatment may be performed under the conditions of the microwave treatment performed after the formation of the insulating film 250A described above. Alternatively, the microwave treatment may be performed after the formation of the insulating film 250B without performing the microwave treatment after the formation of the insulating film 250A.

[0343] Also, after the formation of the insulating film 250A and after the formation of the insulating film 250B, a heating treatment may be performed while maintaining the reduced pressure state. By performing such a treatment, hydrogen in the insulating film 250A, the insulating film 250B, the oxide 230b, and the oxide 230a can be efficiently removed. Also, some of the hydrogen may be gettered to the conductor 242 (the conductor 242a and the conductor 242b). Alternatively, a step of performing a heating treatment may be repeated multiple times while maintaining the reduced pressure state after the microwave treatment. By repeatedly performing the heating treatment, hydrogen in the insulating film 250A, the oxide 230b, and the oxide 230a can be more efficiently removed. The heating treatment temperature is preferably 300° C. or more and 500° C. or less. Also, the microwave treatment, i.e., microwave annealing, may serve as the heating treatment. If the oxide 230b, etc. is sufficiently heated by the microwave annealing, the heating treatment may not be performed.

[0344] Furthermore, by modifying the film quality of the insulating film 250A and the insulating film 250B by microwave processing, it is possible to suppress the diffusion of hydrogen, water, impurities, etc. Therefore, it is possible to suppress the diffusion of hydrogen, water, impurities, etc. into the oxide 230b, the oxide 230a, etc. through the insulator 250 by a post-process such as film formation of a conductive film that becomes the conductor 260, or a post-process such as heat treatment.

[0345] Next, a conductive film that becomes the conductor 260a and a conductive film that becomes the conductor 260b are formed in this order. The conductive film that becomes the conductor 260a and the conductive film that becomes the conductor 260b can be formed by sputtering, CVD, MBE, PLD, ALD, or the like. In this embodiment, titanium nitride is formed by ALD as the conductive film that becomes the conductor 260a, and tungsten is formed by CVD as the conductive film that becomes the conductor 260b.

[0346] Next, the insulating film 250A, the insulating film 250B, the conductive film to be the conductor 260a, and the conductive film to be the conductor 260b are polished by CMP until the insulator 280 is exposed, thereby forming the insulator 250a, the insulator 250b, the conductor 260a, and the conductor 260b (see FIGS. 19A to 19D). As a result, the insulator 250 is disposed so as to cover the opening that reaches the oxide 230b and the inner wall (side wall and bottom surface) of the groove of the oxide 230b. The conductor 260a and the conductor 260b are disposed so as to fill the opening and the groove through the insulator 250.

[0347] Next, heat treatment may be performed under the same conditions as the above heat treatment. In this embodiment, the treatment is performed in a nitrogen atmosphere at a temperature of 400° C. for 1 hour. The heat treatment can reduce the moisture and hydrogen concentrations in the insulators 250 and 280. Note that after the heat treatment, the insulator 282 may be formed without exposure to the air.

[0348] Next, the insulator 282a and the insulator 282b are successively formed over the insulator 250, the conductor 260, and the insulator 280 (see FIGS. 20A to 20D). The insulator 282a and the insulator 282b can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. The insulator 282a and the insulator 282b are preferably formed by a sputtering method. By using a sputtering method that does not require hydrogen as a deposition gas, the hydrogen concentration in the insulator 282a and the insulator 282b can be reduced.

[0349] In this embodiment, aluminum oxide films are formed as the insulators 282a and 282b by pulse DC sputtering using an aluminum target in an atmosphere containing oxygen gas. At this time, oxygen can be added to the insulator 280. Furthermore, by using the pulse DC sputtering method, the film thickness distribution can be made more uniform, and the sputtering rate and film quality can be improved. The RF power applied to the substrate is 1.86 W / cm. 2 Less than or equal to 0 W / cm 2 More than 0.31W / cm 2 By reducing the RF power, the amount of oxygen injected into the insulator 280 can be reduced. In this embodiment, the insulator 282a is formed by applying an RF power of 0 W / cm2 to the substrate. 2 The insulator 282b is formed as follows: RF power applied to the substrate is 0.31 W / cm 2 A film is formed as follows.

[0350] Next, a part of the insulator 282a and a part of the insulator 282b are processed to form the opening region 400a and the opening region 400b (see FIG. 21A to FIG. 21D). The opening region 400a overlaps at least a part of the conductor 242a, and the opening region 400b overlaps at least a part of the conductor 242b. Also, a groove may be formed in the insulator 280 by overlapping with the opening of the insulator 282 in the opening region 400. The part of the insulator 282a, the part of the insulator 282b, and the part of the insulator 280 may be processed by wet etching, but dry etching is preferable for fine processing. Also, the depth of the groove in the insulator 280 may be at most until the top surface of the insulator 272 is exposed, and may be, for example, about ¼ to ½ of the maximum film thickness of the insulator 280.

[0351] Next, the insulators 282a, 282b, 280, 272, 222, and 216 are processed until they reach the top surface of the insulator 214 (see FIGS. 22A to 22D). This processing may be performed by wet etching, but dry etching is preferable for fine processing.

[0352] Next, it is preferable to perform a heat treatment. The heat treatment may be performed at a temperature of 250° C. or more and 650° C. or less, preferably 400° C. or more and 600° C. or less. The heat treatment is preferably performed at a temperature lower than the heat treatment temperature performed after the formation of the oxide film 243A. The heat treatment is performed in a nitrogen gas or inert gas atmosphere. By performing the heat treatment, oxygen contained in the insulator 280 and hydrogen bonded to the oxygen can be released to the outside through the opening region 400. At the same time, oxygen contained in the insulator 280 and hydrogen bonded to the oxygen can be released to the outside from the side surface of the insulator 280 formed by processing the insulators 282a, 282b, 280, 272, 222, and 216. The hydrogen bonded to the oxygen is released as water. Therefore, unnecessary oxygen and hydrogen contained in the insulator 280 can be reduced. Note that the heat treatment may be performed after the opening region 400 is formed, and further after the insulators 282a, 282b, 280, 272, 222, and 216 are processed.

[0353] In this way, it is possible to supply sufficient oxygen to the region 230bc and its vicinity from the insulator 280 containing oxygen that is desorbed by heating, without supplying an excessive amount of oxygen. In addition, it is possible to suppress the intrusion of hydrogen into the region 230bc. This prevents oxygen vacancies and V O By removing H, the region 230bc can be made i-type or substantially i-type. This can suppress fluctuations in the electrical characteristics of the transistor 200 and improve reliability. In addition, variation in the electrical characteristics of the transistor 200 within the substrate surface can be suppressed.

[0354] Next, the insulator 283 is formed on the insulator 214, the insulator 282b, etc. (see FIGS. 23A to 23D). The insulator 283 is preferably in contact with the insulator 280 in the opening region 400a and the opening region 400b. The insulator 283 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, etc. The insulator 283 is preferably formed by a sputtering method. By using a sputtering method that does not require hydrogen as a film formation gas, the hydrogen concentration in the insulator 283 can be reduced. The insulator 283 may have a multi-layer structure. For example, a silicon nitride film may be formed by a sputtering method, and a silicon nitride film may be formed on the silicon nitride by an ALD method.

[0355] Here, the insulator 283 is provided to cover the island-shaped insulators 216, 222, 272, 280, 282a, and 282b. Therefore, by enclosing the transistor 200 with the insulators 283 and 214, which have high barrier properties, it is possible to prevent moisture and hydrogen from entering from the outside.

[0356] Note that, although the above describes a configuration in which the transistor 200 is enclosed by the insulator 283 and the insulator 214, the present invention is not limited to this. For example, in the steps shown in Figures 22A to 22D, the insulator 214 may also be processed into an island shape, the upper surface of the insulator 212 may be exposed, and the transistor 200 may be enclosed by the insulators 283 and 212. In this case, in the sealing portion 265, the upper surface of the insulator 283 contacts the upper surface of the insulator 212.

[0357] Next, an insulating film to be the insulator 274 is formed on the insulator 283 (see FIGS. 24A to 24D). The insulating film to be the insulator 274 can be formed by sputtering, CVD, MBE, PLD, ALD, or the like. In this embodiment, silicon oxide is formed by CVD as the insulating film to be the insulator 274.

[0358] Next, the insulator 274 is polished by CMP until the insulator 283 is exposed, thereby forming the insulator 274 so as to be embedded in the sealing portion 265, the opening region 400a, and the opening region 400b. (See FIGS. 23A to 23D.) Here, the upper surface of the insulator 274 is flattened, and the height of the upper surface of the insulator 274 and the height of the upper surface of the insulator 283 are approximately the same. The CMP process may remove a part of the upper surface of the insulator 283. Also, the insulator 274 may be formed so as to fill the recesses formed in the insulator 283 in the opening region 400a and the opening region 400b.

[0359] Next, the insulator 286 is formed over the insulator 274 and the insulator 283 (see FIGS. 24A to 24D). The insulator 286 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. In this embodiment, a silicon oxide film is formed as the insulator 286 by a sputtering method.

[0360] Next, an opening that penetrates the opening region 400a to reach the conductor 242a and an opening that penetrates the opening region 400b to reach the conductor 242b are formed (see FIGS. 24A to 24D). Here, it is preferable that the opening that reaches the conductor 242a is located inside the opening of the insulator 282 in the opening region 400a in top view, and the opening that reaches the conductor 242b is located inside the opening of the insulator 282 in the opening region 400b in top view.

[0361] The opening reaching the conductor 242 can be formed by forming a mask using lithography and removing the insulators 286, 274, 283, 280, 272, and 271 by anisotropic etching. The opening reaching the conductor 242 has a high aspect ratio, so it is preferable to use a dry etching method. In addition, the above-mentioned dry etching apparatus can be used in the etching process.

[0362] Here, in the case where the opening region 400 and the conductor 240 do not overlap, in order to form an opening reaching the conductor 242, it is necessary to open the insulators 286, 283, 282, and 280 as a thick interlayer insulating film. The insulators 286 and 280 are mainly composed of silicon oxide, the insulator 283 is mainly composed of silicon nitride, and the insulator 282 is mainly composed of aluminum oxide. Therefore, when the above openings are formed collectively using an etching gas containing fluorine, the openings can be formed relatively easily in the insulators 286, 280, and 283, but it is difficult to form an opening in the insulator 282.

[0363] When the insulator 282 is removed using an etching gas containing fluorine, it is preferable that the kinetic energy of ions incident on the insulator 282 is large, so that a high-power bias is applied to the substrate to perform dry etching. At this time, if the pattern of the opening that reaches the conductor 242 is formed only with a resist mask, the resist mask may be destroyed during the dry etching. Therefore, a hard mask made of tungsten or the like must be formed separately from the resist mask. In addition, when the insulator 282 is removed using an etching gas containing fluorine, the cross-sectional shape of the opening in the insulator 282 may be significantly tapered compared to the cross-sectional shape of the opening in the insulator 280.

[0364] 21A to 21D, insulator 282 in opening region 400 is removed, and therefore, in forming an opening reaching conductor 242, there is no need to remove insulator 282. Therefore, in this embodiment, since there is no need to remove insulator 282 under the strict conditions described above, an opening reaching conductor 242 can be formed more easily and in a shape closer to vertical. In this way, by using the method shown in this embodiment, semiconductor devices can be manufactured with good productivity.

[0365] When aluminum oxide is used for the insulators 271 and 272, they also need to be etched to form an opening that reaches the conductor 242. However, since the insulators 271 and 272 have a smaller thickness than the insulator 282, the insulators 271 and 272 can be easily removed by using a dry etching method.

[0366] Next, an insulating film that will become the insulator 241 is formed, and the insulating film is anisotropically etched to form the insulator 241 in the opening that reaches the conductor 242. The insulating film that will become the insulator 241 can be formed by sputtering, CVD, MBE, PLD, ALD, or the like. As the insulating film that will become the insulator 241, it is preferable to use an insulating film that has a function of suppressing oxygen permeation. For example, it is preferable to form an aluminum oxide film by the ALD method. Alternatively, it is preferable to form a silicon nitride film by the PEALD method. Silicon nitride is preferable because it has high barrier properties against hydrogen.

[0367] Moreover, for example, a dry etching method may be used as the anisotropic etching of the insulating film that becomes the insulator 241. By providing the insulator 241 on the sidewall of the opening, it is possible to suppress the permeation of oxygen from the outside and prevent the oxidation of the conductor 240a and the conductor 240b that will be formed next. Also, it is possible to prevent impurities such as water and hydrogen from being mixed into the oxide 230 through the conductor 240a and the conductor 240b.

[0368] Next, a conductive film that will become the conductor 240a and the conductor 240b is formed in the opening that reaches the conductor 242. The conductive film that will become the conductor 240a and the conductor 240b is preferably a laminated structure including a conductor that has a function of suppressing the permeation of impurities such as water and hydrogen. For example, it can be a laminated structure of tantalum nitride, titanium nitride, or the like, and tungsten, molybdenum, copper, or the like. The conductive film that will become the conductor 240 can be formed by using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

[0369] Next, a CMP process is performed to remove a portion of the conductive film that will become the conductor 240a and the conductor 240b, exposing the upper surface of the insulator 286. As a result, the conductive film remains only in the opening that reaches the conductor 242, and the conductor 240a and the conductor 240b can be formed with flat upper surfaces (see FIGS. 1A to 1D). In this way, when the insulator 241 and the conductor 240 are formed inside the opening region 400, the insulator 241 and the conductor 240 are not in contact with the insulator 282. Also, the CMP process may remove a portion of the upper surface of the insulator 286.

[0370] In this manner, by forming the opening region 400 and the conductor 240 functioning as a plug to overlap each other when viewed from above, the opening region 400 can be provided without significantly increasing the area occupied by the transistor 200. As a result, even in a design in which a plurality of transistors 200 are densely arranged, the opening region 400 can be provided without changing the arrangement of the transistors 200 to provide extra space. With such a configuration, a semiconductor device that can be miniaturized or highly integrated can be provided.

[0371] Next, a conductive film is formed to become the conductor 246. The conductive film to become the conductor 246 can be formed by sputtering, CVD, MBE, PLD, ALD, or the like.

[0372] Next, the conductive film that becomes the conductor 246 is processed by lithography to form the conductor 246a in contact with the upper surface of the conductor 240a and the conductor 246b in contact with the upper surface of the conductor 240b. Although not shown, at this time, a part of the insulator 286 in the region where the conductor 246a and the conductor 246b do not overlap with the insulator 286 may be removed.

[0373] Note that dicing lines (which may be called scribe lines, division lines, or cutting lines) may be provided overlapping the sealing portion 265. The substrate on which the semiconductor device is formed is divided along the dicing lines, so that a group of transistors surrounded by the sealing portion 265 is taken out as one chip.

[0374] 1A to 1D can be manufactured. As shown in FIGS. 1A to 1D and 5A to 24D, the transistor 200 can be manufactured with high productivity by using the manufacturing method of a semiconductor device described in this embodiment.

[0375] <Microwave processing equipment> A microwave processing apparatus that can be used in the above-described method for manufacturing a semiconductor device will be described below.

[0376] First, the configuration of a manufacturing apparatus that reduces the inclusion of impurities during the manufacture of semiconductor devices and the like will be described with reference to FIGS. 26, 27 and 28. FIG.

[0377] 26 is a schematic top view of a single-wafer multi-chamber manufacturing apparatus 2700. The manufacturing apparatus 2700 includes an atmosphere-side substrate supply chamber 2701 having a cassette port 2761 for accommodating a substrate and an alignment port 2762 for aligning the substrate, an atmosphere-side substrate transfer chamber 2702 for transferring the substrate from the atmosphere-side substrate supply chamber 2701, a load lock chamber 2703a for loading the substrate and for reducing the pressure in the chamber from atmospheric pressure or from reduced pressure to atmospheric pressure, an unload lock chamber 2703b for unloading the substrate and for switching the pressure in the chamber from reduced pressure to atmospheric pressure or from atmospheric pressure to reduced pressure, a transfer chamber 2704 for transferring the substrate in a vacuum, a chamber 2706a, a chamber 2706b, a chamber 2706c, and a chamber 2706d.

[0378] The atmospheric side substrate transfer chamber 2702 is connected to a load lock chamber 2703a and an unload lock chamber 2703b, the load lock chamber 2703a and the unload lock chamber 2703b are connected to a transfer chamber 2704, and the transfer chamber 2704 is connected to a chamber 2706a, a chamber 2706b, a chamber 2706c, and a chamber 2706d.

[0379] A gate valve GV is provided at the connection between each chamber, and each chamber can be independently maintained in a vacuum state, except for the atmosphere side substrate supply chamber 2701 and the atmosphere side substrate transfer chamber 2702. A transfer robot 2763a is provided in the atmosphere side substrate transfer chamber 2702, and a transfer robot 2763b is provided in the transfer chamber 2704. Substrates can be transferred within the manufacturing apparatus 2700 by the transfer robot 2763a and the transfer robot 2763b.

[0380] The back pressure (total pressure) of the transfer chamber 2704 and each chamber is, for example, 1×10 -4 Pa or less, preferably 3×10 -5 Pa or less, more preferably 1×10 -5 The partial pressure of gas molecules (atoms) with a mass-to-charge ratio (m / z) of 18 in the transfer chamber 2704 and each chamber is, for example, 3×10 -5 Pa or less, preferably 1×10 -5 Pa or less, more preferably 3×10 -6 The partial pressure of gas molecules (atoms) with m / z of 28 in the transfer chamber 2704 and each chamber is, for example, 3×10 -5 Pa or less, preferably 1×10 -5 Pa or less, more preferably 3×10 -6 The partial pressure of gas molecules (atoms) with m / z of 44 in the transfer chamber 2704 and each chamber is, for example, 3×10 -5 Pa or less, preferably 1×10 -5 Pa or less, more preferably 3×10 -6 Pa or less.

[0381] The total pressure and partial pressure in the transfer chamber 2704 and each chamber can be measured using a mass spectrometer. For example, a quadrupole mass spectrometer (also called Q-mass) Qulee CGM-051 manufactured by ULVAC, Inc. may be used.

[0382] In addition, it is desirable that the transfer chamber 2704 and each chamber have a configuration with little external or internal leakage. For example, the leak rate of the transfer chamber 2704 and each chamber is 3×10 -6 Pa·m 3 / s or less, preferably 1×10 -6 Pa·m 3 / s or less. For example, the leak rate of a gas molecule (atom) with m / z of 18 is 1×10 -7 Pa·m 3 / s or less, preferably 3×10 -8 Pa·m 3 / s or less. For example, the leak rate of a gas molecule (atom) with m / z of 28 is 1×10 -5 Pa·m 3 / s or less, preferably 1×10 -6 Pa·m 3 / s or less. For example, the leak rate of a gas molecule (atom) with m / z of 44 is 3×10 -6 Pa·m 3 / s or less, preferably 1×10 -6 Pa·m 3 / s or less.

[0383] The leak rate can be derived from the total pressure and partial pressure measured using the mass spectrometer mentioned above. The leak rate depends on external and internal leaks. External leaks are caused by gas flowing in from outside the vacuum system due to tiny holes or poor sealing. Internal leaks are caused by leakage from partitions such as valves in the vacuum system or gas released from internal components. To keep the leak rate below the above values, measures must be taken from both the external and internal leaks perspective.

[0384] For example, the opening and closing parts of the transfer chamber 2704 and each chamber may be sealed with a metal gasket. The metal gasket is preferably made of a metal coated with iron fluoride, aluminum oxide, or chromium oxide. Metal gaskets have higher adhesion than O-rings and can reduce external leakage. In addition, by using a passivated metal coated with iron fluoride, aluminum oxide, chromium oxide, or the like, the release of gas containing impurities from the metal gasket is suppressed, and internal leakage can be reduced.

[0385] In addition, aluminum, chromium, titanium, zirconium, nickel, or vanadium, which emits less gas containing impurities, is used as a member constituting the manufacturing apparatus 2700. In addition, the above-mentioned metals which emit less gas containing impurities may be used by coating an alloy containing iron, chromium, nickel, etc. Alloys containing iron, chromium, nickel, etc. are rigid, heat-resistant, and suitable for processing. Here, if the surface irregularities of the members are reduced by polishing or the like in order to reduce the surface area, the amount of emitted gas can be reduced.

[0386] Alternatively, the components of the manufacturing apparatus 2700 described above may be coated with iron fluoride, aluminum oxide, chromium oxide, or the like.

[0387] It is preferable that the components of the manufacturing apparatus 2700 are constructed solely from metal as much as possible. For example, even if a viewing window made of quartz or the like is installed, it is advisable to thinly coat the surface with iron fluoride, aluminum oxide, chromium oxide, or the like to suppress outgassing.

[0388] The adsorbed matter present in the transfer chamber 2704 and each chamber does not affect the pressure of the transfer chamber 2704 and each chamber because it is adsorbed to the inner walls, but it causes gas emission when the transfer chamber 2704 and each chamber are evacuated. Therefore, although there is no correlation between the leak rate and the exhaust speed, it is important to use a pump with high exhaust capacity to desorb as much of the adsorbed matter present in the transfer chamber 2704 and each chamber and evacuate them in advance. In addition, the transfer chamber 2704 and each chamber may be baked to promote the desorption of the adsorbed matter. By baking, the desorption speed of the adsorbed matter can be increased by about 10 times. Baking may be performed at 100°C or higher and 450°C or lower. At this time, if the adsorbed matter is removed while introducing an inert gas into the transfer chamber 2704 and each chamber, the desorption speed of water and the like that is difficult to desorb by only exhausting can be further increased. In addition, the desorption speed of the adsorbed matter can be further increased by heating the inert gas introduced to the same temperature as the baking temperature. Here, it is preferable to use a rare gas as the inert gas.

[0389] Alternatively, it is preferable to increase the pressure in the transfer chamber 2704 and each chamber by introducing an inert gas such as a heated rare gas or oxygen, and then evacuate the transfer chamber 2704 and each chamber again after a certain time has passed. By introducing a heated gas, it is possible to desorb adsorbed substances in the transfer chamber 2704 and each chamber, and it is possible to reduce impurities present in the transfer chamber 2704 and each chamber. It is effective to repeat this process 2 to 30 times, preferably 5 to 15 times. Specifically, by introducing an inert gas or oxygen having a temperature of 40° C. to 400° C., preferably 50° C. to 200° C., the pressure in the transfer chamber 2704 and each chamber is set to 0.1 Pa to 10 kPa, preferably 1 Pa to 1 kPa, and more preferably 5 Pa to 100 Pa, and the period for maintaining the pressure is 1 minute to 300 minutes, preferably 5 minutes to 120 minutes. Thereafter, the transfer chamber 2704 and each chamber are evacuated for a period of 5 to 300 minutes, preferably 10 to 120 minutes.

[0390] Next, chamber 2706b and chamber 2706c will be described with reference to the schematic cross-sectional view shown in FIG.

[0391] The chamber 2706b and the chamber 2706c are chambers capable of performing microwave processing on an object to be processed, for example. The chamber 2706b and the chamber 2706c differ only in the atmosphere during microwave processing. Since the other configurations are common, they will be described together below.

[0392] The chamber 2706b and the chamber 2706c have a slot antenna plate 2808, a dielectric plate 2809, a substrate holder 2812, and an exhaust port 2819. In addition, outside the chamber 2706b and the chamber 2706c, a gas supply source 2801, a valve 2802, a high frequency generator 2803, a waveguide 2804, a mode converter 2805, a gas pipe 2806, a waveguide 2807, a matching box 2815, a high frequency power supply 2816, a vacuum pump 2817, and a valve 2818 are provided.

[0393] The high frequency generator 2803 is connected to the mode converter 2805 via a waveguide 2804. The mode converter 2805 is connected to a slot antenna plate 2808 via a waveguide 2807. The slot antenna plate 2808 is disposed in contact with a dielectric plate 2809. The gas supply source 2801 is connected to the mode converter 2805 via a valve 2802. Gas is sent to the chambers 2706b and 2706c through a gas pipe 2806 passing through the mode converter 2805, the waveguide 2807, and the dielectric plate 2809. The vacuum pump 2817 has a function of exhausting gas and the like from the chambers 2706b and 2706c via a valve 2818 and an exhaust port 2819. The high frequency power supply 2816 is connected to the substrate holder 2812 via a matching box 2815.

[0394] The substrate holder 2812 has a function of holding the substrate 2811. For example, the substrate holder 2812 has a function of electrostatically or mechanically chucking the substrate 2811. The substrate holder 2812 also has a function as an electrode to which power is supplied from a high frequency power supply 2816. The substrate holder 2812 also has an internal heating mechanism 2813 and has a function of heating the substrate 2811.

[0395] For example, a dry pump, a mechanical booster pump, an ion pump, a titanium sublimation pump, a cryopump, or a turbo molecular pump can be used as the vacuum pump 2817. A cryotrap may be used in addition to the vacuum pump 2817. The use of a cryopump and a cryotrap is particularly preferable because water can be efficiently exhausted.

[0396] The heating mechanism 2813 may be, for example, a heating mechanism that uses a resistance heating element or the like for heating. Alternatively, it may be a heating mechanism that uses heat conduction or heat radiation from a medium such as a heated gas for heating. For example, RTA (Rapid Thermal Annealing) such as GRTA (Gas Rapid Thermal Annealing) or LRTA (Lamp Rapid Thermal Annealing) can be used. GRTA performs heating processing using high-temperature gas. An inert gas is used as the gas.

[0397] The gas supply source 2801 may be connected to a refiner via a mass flow controller. It is preferable to use a gas with a dew point of -80° C. or less, preferably -100° C. or less. For example, oxygen gas, nitrogen gas, and rare gas (such as argon gas) may be used.

[0398] The dielectric plate 2809 may be made of, for example, silicon oxide (quartz), aluminum oxide (alumina), or yttrium oxide (yttria). A separate protective layer may be formed on the surface of the dielectric plate 2809. The protective layer may be made of magnesium oxide, titanium oxide, chromium oxide, zirconium oxide, hafnium oxide, tantalum oxide, silicon oxide, aluminum oxide, or yttrium oxide. The dielectric plate 2809 is exposed to a particularly high-density region of the high-density plasma 2810 described later, and thus damage to the dielectric plate 2809 can be mitigated by providing a protective layer. As a result, an increase in particles during processing can be suppressed.

[0399] The high frequency generator 2803 has a function of generating microwaves of, for example, 0.3 GHz to 3.0 GHz, 0.7 GHz to 1.1 GHz, or 2.2 GHz to 2.8 GHz. The microwaves generated by the high frequency generator 2803 are transmitted to the mode converter 2805 via the waveguide 2804. In the mode converter 2805, the microwaves transmitted as TE mode are converted to TEM mode. Then, the microwaves are transmitted to the slot antenna plate 2808 via the waveguide 2807. The slot antenna plate 2808 is provided with a plurality of slot holes, and the microwaves pass through the slot holes and the dielectric plate 2809. Then, an electric field is generated below the dielectric plate 2809, and a high density plasma 2810 can be generated. In the high density plasma 2810, ions and radicals according to the gas species supplied from the gas supply source 2801 exist. For example, oxygen radicals and the like exist.

[0400] At this time, the film on the substrate 2811 can be modified by the ions and radicals generated by the high density plasma 2810. It may be preferable to apply a bias to the substrate 2811 side using a high frequency power supply 2816. For the high frequency power supply 2816, an RF (Radio Frequency) power supply with a frequency of, for example, 13.56 MHz or 27.12 MHz may be used. By applying a bias to the substrate side, the ions in the high density plasma 2810 can be efficiently delivered to the depths of the openings of the film on the substrate 2811.

[0401] For example, oxygen can be introduced from a gas supply source 2801 into the chamber 2706b or the chamber 2706c to perform oxygen radical treatment using a high density plasma 2810.

[0402] Next, chamber 2706a and chamber 2706d will be described with reference to the schematic cross-sectional view shown in FIG.

[0403] The chamber 2706a and the chamber 2706d are chambers capable of irradiating the object to be treated with electromagnetic waves, for example. The only difference between the chamber 2706a and the chamber 2706d is the type of electromagnetic waves. As the other configurations are largely common, they will be described together below.

[0404] The chamber 2706a and the chamber 2706d each have one or more lamps 2820, a substrate holder 2825, a gas inlet 2823, and an exhaust port 2830. In addition, a gas supply source 2821, a valve 2822, a vacuum pump 2828, and a valve 2829 are provided outside the chamber 2706a and the chamber 2706d.

[0405] The gas supply source 2821 is connected to a gas inlet 2823 via a valve 2822. The vacuum pump 2828 is connected to an exhaust port 2830 via a valve 2829. The lamp 2820 is disposed facing a substrate holder 2825. The substrate holder 2825 has a function of holding a substrate 2824. The substrate holder 2825 also has an internal heating mechanism 2826 and has a function of heating the substrate 2824.

[0406] A light source having a function of emitting electromagnetic waves such as visible light or ultraviolet light may be used as the lamp 2820. For example, a light source having a function of emitting electromagnetic waves having a peak wavelength of 10 nm to 2500 nm, 500 nm to 2000 nm, or 40 nm to 340 nm may be used.

[0407] For example, lamp 2820 may be a light source such as a halogen lamp, a metal halide lamp, a xenon arc lamp, a carbon arc lamp, a high pressure sodium lamp, or a high pressure mercury lamp.

[0408] For example, the electromagnetic waves emitted from the lamps 2820 can be absorbed in part or in whole by the substrate 2824 to modify a film on the substrate 2824. For example, defects can be generated or reduced, or impurities can be removed. If the process is performed while the substrate 2824 is heated, defects can be generated or reduced, or impurities can be removed efficiently.

[0409] Alternatively, for example, the substrate holder 2825 may be heated by electromagnetic waves emitted from the lamps 2820, thereby heating the substrate 2824. In that case, the substrate holder 2825 does not need to have the heating mechanism 2826 inside.

[0410] For the vacuum pump 2828, refer to the description of the vacuum pump 2817. For the heating mechanism 2826, refer to the description of the heating mechanism 2813. For the gas supply source 2821, refer to the description of the gas supply source 2801.

[0411] The microwave processing device that can be used in this embodiment is not limited to the above. A microwave processing device 2900 shown in FIG. 29 can be used. The microwave processing device 2900 has a quartz tube 2901, a gas supply source 2801, a valve 2802, a high frequency generator 2803, a waveguide 2804, a gas pipe 2806, a vacuum pump 2817, a valve 2818, and an exhaust port 2819. The microwave processing device 2900 also has a substrate holder 2902 that holds a plurality of substrates 2811 (2811_1 to 2811_n, n is an integer of 2 or more) in the quartz tube 2901. The microwave processing device 2900 may also have a heating means 2903 on the outside of the quartz tube 2901.

[0412] Microwaves generated by a high frequency generator 2803 are irradiated to a substrate provided in a quartz tube 2901 through a waveguide 2804. A vacuum pump 2817 is connected to an exhaust port 2819 through a valve 2818, and can adjust the pressure inside the quartz tube 2901. A gas supply source 2801 is connected to a gas pipe 2806 through a valve 2802, and can introduce a desired gas into the quartz tube 2901. A heating means 2903 can heat a substrate 2811 in the quartz tube 2901 to a desired temperature. Alternatively, the heating means 2903 may heat a gas supplied from the gas supply source 2801. The microwave processing device 2900 can simultaneously perform a heat treatment and a microwave treatment on the substrate 2811. Also, a microwave treatment can be performed after the substrate 2811 is heated. Also, a heat treatment can be performed on the substrate 2811 after the microwave treatment.

[0413] The substrates 2811_1 to 2811_n may all be processing substrates for forming semiconductor devices or memory devices, or some of the substrates may be dummy substrates. For example, the substrates 2811_1 and 2811_n may be dummy substrates, and the substrates 2811_2 to 2811_n-1 may be processing substrates. Also, the substrates 2811_1, 2811_2, 2811_n-1, and 2811_n may be dummy substrates, and the substrates 2811_3 to 2811_n-2 may be processing substrates. By using a dummy substrate, a plurality of processing substrates are uniformly processed during microwave processing or heat processing, and the variation between the processing substrates can be reduced, which is preferable. For example, by arranging a dummy substrate on the processing substrate closest to the high frequency generator 2803 and the waveguide 2804, the processing substrate can be prevented from being directly exposed to microwaves, which is preferable.

[0414] By using the above manufacturing apparatus, it is possible to modify the film while suppressing the inclusion of impurities in the processed object.

[0415] <Modifications of the semiconductor device> An example of a semiconductor device which is one embodiment of the present invention will be described below with reference to FIGS.

[0416] <Modification 1 of the semiconductor device> An example of a semiconductor device which is one embodiment of the present invention will be described below with reference to FIG.

[0417] Fig. 30A shows a top view of the semiconductor device. Fig. 30B shows a cross-sectional view corresponding to the portion indicated by the dashed line A3-A4 in Fig. 30A. Note that for a cross-sectional view corresponding to the portion indicated by the dashed line A1-A2 in Fig. 30A, refer to transistor 200 shown in Fig. 1B. Note that some elements are omitted from the top view of Fig. 30A for clarity.

[0418] In the semiconductor device shown in Fig. 30, the same reference numerals are attached to structures having the same functions as the structures constituting the semiconductor device shown in <Configuration example of semiconductor device>. In this section, the materials described in detail in <Configuration example of semiconductor device> can be used as the materials constituting the semiconductor device.

[0419] The semiconductor device illustrated in Fig. 30 is a modified example of the semiconductor device illustrated in Fig. 1. In the semiconductor device illustrated in Fig. 30, a transistor 200 has a configuration including n oxides 230 (oxides 230_1 to 230_n: n is a natural number), which is different from the semiconductor device illustrated in Fig. 1. Each of the oxides 230_1 to 230_n has a channel formation region.

[0420] 30, a conductor 260 is provided on the upper surfaces and side surfaces of multiple channel formation regions via an insulator 250. The conductor 246 (conductor 246a and conductor 246b) extends in the A3-A4 direction and is electrically connected to the oxides 230_1 to 230_n via the conductor 240. Similarly to the semiconductor device shown in FIG. 1, the conductor 240a is provided penetrating the opening region 400a, and the conductor 240b is provided penetrating the opening region 400b.

[0421] That is, in the semiconductor device shown in FIG. 30, the transistor 200 has multiple channel formation regions for one gate electrode. The transistor 200 shown in FIG. 30 can obtain a large on-current by having multiple channel formation regions. In addition, since each channel formation region has a structure covered with a gate electrode, that is, an s-channel structure, a large on-current can be obtained in each channel formation region. Alternatively, in the channel width direction of the transistor 200, the height of the bottom surface of the conductor 260 in a region where the conductor 260 and the oxide 230b do not overlap is lower than the height of the interface between the top surface of the oxide 230b and the insulator 250 when the bottom surface of the insulator 222 is used as a reference, so that a large on-current can be obtained in each channel formation region.

[0422] Note that for other configurations, the configuration of the semiconductor device in FIG. 1 can be referred to.

[0423] <Modification 2 of Semiconductor Device> An example of a semiconductor device which is one embodiment of the present invention will be described below with reference to FIG.

[0424] Fig. 31A shows a top view of the semiconductor device. Fig. 31B shows a cross-sectional view corresponding to the portion indicated by the dashed line A3-A4 in Fig. 31A. Note that for a cross-sectional view corresponding to the portion indicated by the dashed line A1-A2 in Fig. 31A, refer to transistor 200 shown in Fig. 1B. Note that some elements are omitted from the top view of Fig. 31A for clarity.

[0425] In the semiconductor device shown in Fig. 31, the same reference numerals are attached to structures having the same functions as the structures constituting the semiconductor device shown in <Configuration example of semiconductor device>. In this section, the materials described in detail in <Configuration example of semiconductor device> can be used as the materials constituting the semiconductor device.

[0426] The semiconductor device illustrated in Fig. 31 is a modified example of the semiconductor device illustrated in Fig. 30. In the semiconductor device illustrated in Fig. 31, the transistor 200 has n oxides 230 (oxides 230_1 to 230_n: n is a natural number). Each of the oxides 230_1 to 230_n has a channel formation region.

[0427] 31, a conductor 260 is provided on the upper surfaces and side surfaces of multiple channel formation regions via an insulator 250. The conductor 246 (conductor 246a and conductor 246b) extends in the A3-A4 direction and is electrically connected to the oxides 230_1 to 230_n via the conductor 240. Similarly to the semiconductor device shown in FIG. 1, the conductor 240a is provided penetrating the opening region 400a, and the conductor 240b is provided penetrating the opening region 400b.

[0428] 31, a transistor 200 having a plurality of channel formation regions is arranged adjacent to an oxide 230_1 arranged at an end of the transistor 200, and a transistor 200D having at least an oxide 230D is arranged adjacent to an oxide 230_n arranged at an end of the transistor 200. Similarly, a transistor 200D is arranged adjacent to an oxide 230_n arranged at an end of the transistor 200.

[0429] That is, the semiconductor device shown in FIG. 31 differs from the semiconductor device shown in FIG. 30 in that a transistor 200D is provided at one or both ends in the direction in which a plurality of channel formation regions of the transistor 200 are arranged in parallel.

[0430] Here, the transistor 200D may not be electrically connected to any one or all of the gate wiring, source wiring, and drain wiring. That is, the transistor 200D may be provided in a state where it does not function as a transistor. Therefore, the transistor 200D may be referred to as a dummy transistor (sacrificial transistor).

[0431] In addition, it is preferable that the shortest distance between the oxide 230_D and the oxide 230_1 and the shortest distance between the oxide 230_1 and the oxide 230_2 are approximately equal. Similarly, it is preferable that the shortest distance between the oxide 230_D and the oxide 230_n and the shortest distance between the oxide 230_n-1 and the oxide 230_n are approximately equal. Note that, when n is 1, it is preferable that the shortest distance between one oxide 230_D and the oxide 230_1 and the shortest distance between the other oxide 230_D and the oxide 230_1 are approximately equal.

[0432] In addition, the shortest distance between the conductor 242a and the conductor 242b in the oxide 230_D may be approximately equal to or greater than the shortest distance between the conductor 242a and the conductor 242b in the oxide 230_1. Similarly, the shortest distance between the conductor 242a and the conductor 242b in the oxide 230_D may be approximately equal to or greater than the shortest distance between the conductor 242a and the conductor 242b in the oxide 230_n.

[0433] When multiple oxides 230 are formed in parallel, the oxides 230 located at the ends are likely to have variations in shape due to processing. In addition, in the process of removing a part of the insulator 280 and the stacked structure on the channel formation region of the oxide 230 to provide an opening and expose a part of the top surface of the oxide 230, the area of ​​the exposed top surface of the oxide 230 may vary due to the influence of the shape of the end of the region to be removed (also called the opening) or the distance between the oxide 230 and the end of the opening.

[0434] Therefore, by providing transistor 200D as shown in FIG. 31, even if a shape defect occurs in oxide 230_D of transistor 200D or in the opening on oxide 230_D, the shape of oxide 230 formed in the region sandwiched between transistors 200D becomes uniform.

[0435] Therefore, by disposing the transistor 200D adjacent to the transistor 200, when a plurality of transistors 200 are provided, the variation in characteristics among the plurality of transistors 200 can be reduced.

[0436] Furthermore, when multiple oxides 230 are provided at equal intervals in a certain region, the circuit design can be easily performed by changing the wiring layout.

[0437] In the semiconductor device shown in FIG. 31, the transistor 200 has a plurality of channel formation regions for one gate electrode. The transistor 200 shown in FIG. 31 can obtain a large on-current by having a plurality of channel formation regions. In addition, since each channel formation region has a structure covered with a gate electrode, that is, an s-channel structure, a large on-current can be obtained in each channel formation region. Alternatively, in the channel width direction of the transistor 200, the height of the bottom surface of the conductor 260 in a region where the conductor 260 and the oxide 230b do not overlap is lower than the height of the interface between the top surface of the oxide 230b and the insulator 250 when the bottom surface of the insulator 222 is used as a reference, so that a large on-current can be obtained in each channel formation region.

[0438] Note that for other configurations, the configuration of the semiconductor device in FIG. 1 can be referred to.

[0439] <Modification 3 of the semiconductor device> An example of a semiconductor device which is one embodiment of the present invention will be described below with reference to FIG.

[0440] Fig. 32A shows a top view of the semiconductor device. Fig. 32B shows a cross-sectional view corresponding to the portion indicated by the dashed line A3-A4 in Fig. 32A. Note that for a cross-sectional view corresponding to the portion indicated by the dashed line A1-A2 in Fig. 32A, refer to transistor 200 shown in Fig. 1B. Note that some elements are omitted from the top view of Fig. 32A for clarity.

[0441] In the semiconductor device shown in Fig. 32, the same reference numerals are attached to structures having the same functions as the structures constituting the semiconductor device shown in <Configuration example of semiconductor device>. In this section, the materials described in detail in <Configuration example of semiconductor device> can be used as the materials constituting the semiconductor device.

[0442] The semiconductor device described in this section is a modified example of the semiconductor device shown in Fig. 31. Therefore, the transistor 200 differs from the semiconductor device shown in Fig. 31 in that it has an oxide 230 having n channel formation regions (note that the n channel formation regions are channel formation regions 235_1 to 235_n: n is a natural number). In addition, a conductor 260 is provided on the upper surface and side surface of the multiple channel formation regions with an insulator 250 interposed therebetween.

[0443] Moreover, the conductor 242 (conductor 242a and conductor 242b) extends in the A3-A4 direction and is electrically connected to the conductor 246 (conductor 246a and conductor 246b) via the conductor 240 (conductor 240a and conductor 240b). Similarly to the semiconductor device shown in FIG. 1, the conductor 240a is provided penetrating the opening region 400a, and the conductor 240b is provided penetrating the opening region 400b.

[0444] 32, for ease of explanation, the case where n = 2 is shown. Therefore, the transistor 200 has an oxide 230 having two channel formation regions (a channel formation region 235_1 and a channel formation region 235_2).

[0445] In the oxide 230, the source region and the drain region are electrically connected to the conductor 242a or the conductor 242b. Therefore, for example, the conductor 242a and the conductor 246a are electrically connected to each other via at least one or more conductors 240a, so that a voltage can be applied to a plurality of channel formation regions (channel formation regions 235_1 to 235_n).

[0446] In other words, it is not necessary to provide n conductors 240 for a transistor 200 having n channel formation regions 235. For a transistor having n channel formation regions 235, it is preferable that the number of conductors 240 is one or more, preferably one or more and less than n.

[0447] In addition, as transistors become smaller, the size of the plug that electrically connects the transistor to the conductor that functions as wiring also needs to be smaller. In addition, the contact area between the conductor that functions as a plug and the conductor that functions as wiring becomes smaller, which tends to increase the wiring resistance.

[0448] In the semiconductor device described in this section, since a number of plugs less than n is provided for a transistor 200 having n channel formation regions, the size of each of the conductors 240 functioning as plugs can be made larger than, for example, the conductor 240 described in the semiconductor device shown in Figure 31, thereby reducing power consumption.

[0449] 32, a transistor 200 having a plurality of channel formation regions is arranged adjacent to an oxide 230_1 arranged at an end of the transistor 200, and a transistor 200D having at least an oxide 230D is arranged adjacent to an oxide 230_n arranged at an end of the transistor 200. Similarly, a transistor 200D is arranged adjacent to an oxide 230_n arranged at an end of the transistor 200.

[0450] 32, a conductor 260 is provided on the upper surfaces and side surfaces of a plurality of channel formation regions via an insulator 250. In addition, the conductor 246a and the conductor 246b extend in the A3-A4 direction and are electrically connected to the oxide 230_n.

[0451] 32, a transistor 200 having a plurality of channel formation regions is arranged adjacent to a channel formation region 235_1 arranged at an end of the transistor 200, and a transistor 200D having at least an oxide 230D is arranged adjacent to a channel formation region 235_n arranged at an end of the transistor 200. Similarly, a transistor 200D is arranged adjacent to a channel formation region 235_n arranged at an end of the transistor 200.

[0452] That is, the transistor 200D is provided at one end or both ends in the direction in which a plurality of channel formation regions of the transistor 200 are arranged in parallel.

[0453] Here, the transistor 200D may not be electrically connected to any one or all of the gate wiring, source wiring, and drain wiring. That is, the transistor 200D may be provided in a state where it does not function as a transistor. Therefore, the transistor 200D may be referred to as a dummy transistor (sacrificial transistor).

[0454] In addition, it is preferable that the shortest distance between the oxide 230_D and the oxide 230_1 and the shortest distance between the oxide 230_1 and the oxide 230_2 are approximately equal. Similarly, it is preferable that the shortest distance between the oxide 230_D and the oxide 230_n and the shortest distance between the oxide 230_n-1 and the oxide 230_n are approximately equal. Note that, when n is 1, it is preferable that the shortest distance between one oxide 230_D and the oxide 230_1 and the shortest distance between the other oxide 230_D and the oxide 230_1 are approximately equal.

[0455] In addition, the shortest distance between the conductor 242a and the conductor 242b in the oxide 230_D may be approximately equal to or greater than the shortest distance between the conductor 242a and the conductor 242b in the oxide 230_1. Similarly, the shortest distance between the conductor 242a and the conductor 242b in the oxide 230_D may be approximately equal to or greater than the shortest distance between the conductor 242a and the conductor 242b in the oxide 230_n.

[0456] In addition, the difference between the shortest distance between conductor 242a and conductor 242b in oxide 230_D and the shortest distance between conductor 242a and conductor 242b in oxide 230_1 may be larger than the difference between the shortest distance between conductor 242a and conductor 242b in oxide 230_1 and the shortest distance between conductor 242a and conductor 242b in oxide 230_2.

[0457] When multiple channel formation regions 235 are formed in parallel, the channel formation regions 235 located at the ends are likely to have variations in shape due to processing. In addition, in the process of removing a part of the insulator 280 and the stacked structure on the channel formation region of the oxide 230 to provide an opening and expose a part of the top surface of the oxide 230, the area of ​​the exposed top surface of the oxide 230 may vary due to the influence of the shape of the end of the region to be removed (also called the opening) or the distance between the oxide 230 and the end of the opening.

[0458] Therefore, by providing transistor 200D as shown in FIG. 32, even if a shape defect occurs in oxide 230_D of transistor 200D or in the opening on oxide 230_D, the shape of oxide 230 formed in the region sandwiched between transistors 200D becomes uniform.

[0459] Therefore, by disposing the transistor 200D adjacent to the transistor 200, when a plurality of transistors 200 are provided, the variation in characteristics among the plurality of transistors 200 can be reduced.

[0460] In the semiconductor device shown in FIG. 32, the transistor 200 has a plurality of channel formation regions for one gate electrode. The transistor 200 shown in FIG. 32 can obtain a large on-current by having a plurality of channel formation regions. In addition, since each channel formation region has a structure covered with a gate electrode, that is, an s-channel structure, a large on-current can be obtained in each channel formation region. Alternatively, in the channel width direction of the transistor 200, the height of the bottom surface of the conductor 260 in a region where the conductor 260 and the oxide 230b do not overlap is lower than the height of the interface between the top surface of the oxide 230b and the insulator 250 when the bottom surface of the insulator 222 is used as a reference, so that a large on-current can be obtained in each channel formation region.

[0461] Note that for other configurations, the configuration of the semiconductor device in FIG. 1 can be referred to.

[0462] <Modification 4 of the semiconductor device> An example of a semiconductor device which is one embodiment of the present invention will be described below with reference to FIG.

[0463] FIG. 33A shows a top view of the semiconductor device 500. The x-axis shown in FIG. 33A is parallel to the channel length direction of the transistor 200, and the y-axis is perpendicular to the x-axis. FIG. 33B is a cross-sectional view corresponding to the portion indicated by the dashed line A1-A2 shown in FIG. 33A, and is also a cross-sectional view in the channel length direction of the transistor 200. FIG. 33C is a cross-sectional view corresponding to the portion indicated by the dashed line A3-A4 shown in FIG. 33A, and is also a cross-sectional view of the opening region 400c. Note that some elements are omitted in the top view of FIG. 33A for clarity.

[0464] In the semiconductor device shown in Fig. 33, the same reference numerals are attached to structures having the same functions as the structures constituting the semiconductor device shown in <Configuration example of semiconductor device>. In this section, the materials described in detail in <Configuration example of semiconductor device> can be used as the materials constituting the semiconductor device.

[0465] The semiconductor device 500 shown in Fig. 33 is a modification of the semiconductor device shown in Fig. 1. The semiconductor device 500 shown in Fig. 33 differs from the semiconductor device shown in Fig. 1 in that an opening region 400c is formed in a region of the insulator 282 and the insulator 280 that does not overlap with the transistor 200.

[0466] The semiconductor device 500 has a plurality of transistors 200, a plurality of opening regions 400a, a plurality of opening regions 400b, and a plurality of opening regions 400c arranged in a matrix. A plurality of conductors 260 functioning as gate electrodes of the transistors 200 are provided extending in the y-axis direction. The opening regions 400a and 400b are disposed on the oxide 230 as in the semiconductor device shown in FIG. 1, but the opening region 400c is formed in a region that does not overlap with the oxide 230 and the conductor 260. A sealing portion 265 is formed to surround the plurality of transistors 200, the plurality of conductors 260, the plurality of opening regions 400a, the plurality of opening regions 400b, and the plurality of opening regions 400c. The number, arrangement, and size of the transistors 200, the conductors 260, the opening regions 400a, the opening regions 400b, and the opening regions 400c are not limited to the structure shown in FIG. 33, and may be appropriately set according to the design of the semiconductor device 500.

[0467] As shown in Fig. 2B, opening region 400a and opening region 400b are arranged to overlap conductor 240a and conductor 240b. In contrast, as shown in Fig. 2C, opening region 400c is not arranged to overlap conductor 240, but the other structures are similar to opening region 400a and opening region 400b. Therefore, for details of opening region 400c, the description of opening region 400 in Fig. 2B above can be referred to.

[0468] By providing the opening region 400c that does not overlap with the transistor 200 and performing heat treatment, a larger amount of oxygen contained in the insulator 280 can be diffused outward while oxygen is supplied to the oxide 230 of the transistor 200. This makes it possible to prevent an excessive amount of oxygen from being supplied to the transistor 200 even when the arrangement density of the transistors 200 is low, that is, when the transistors 200 are sparsely arranged.

[0469] In addition, in FIG. 33A, the shape of the opening region 400c in top view is substantially rectangular, but the present invention is not limited to this. For example, the shape of the opening region 400c in top view may be rectangular, elliptical, circular, rhombic, or a combination of these. The area and arrangement interval of the opening region 400c can be appropriately set according to the design of the semiconductor device including the transistor 200. For example, in a region where the density of the transistor 200 is low, the area of ​​the opening region 400c may be increased or the arrangement interval of the opening region 400c may be narrowed. For example, in a region where the density of the transistor 200 is high, the area of ​​the opening region 400c may be narrowed or the arrangement interval of the opening region may be widened.

[0470] According to one embodiment of the present invention, a semiconductor device having favorable electrical characteristics can be provided. According to one embodiment of the present invention, a semiconductor device with favorable reliability can be provided. According to one embodiment of the present invention, a semiconductor device with large on-state current can be provided. According to one embodiment of the present invention, a semiconductor device with little variation in transistor characteristics can be provided. According to one embodiment of the present invention, a semiconductor device that can be miniaturized or highly integrated can be provided. According to one embodiment of the present invention, a semiconductor device with low power consumption can be provided. According to one embodiment of the present invention, a method for manufacturing a semiconductor device with high productivity can be provided.

[0471] The structures, methods, and the like described in this embodiment can be used in appropriate combination with other structures, methods, and the like described in this embodiment or structures, methods, and the like described in other embodiments.

[0472] (Embodiment 2) In this embodiment mode, one mode of a semiconductor device will be described with reference to FIGS.

[0473] [Storage device 1] 34 illustrates an example of a semiconductor device (memory device) according to one embodiment of the present invention. In the semiconductor device of one embodiment of the present invention, a transistor 200 is provided above a transistor 300, and a capacitor 100 is provided above the transistors 300 and 200. Note that the transistor 200 described in the above embodiment can be used as the transistor 200.

[0474] The transistor 200 is a transistor in which a channel is formed in a semiconductor layer including an oxide semiconductor. Since the off-state current of the transistor 200 is small, stored data can be retained for a long time by using the transistor 200 in a memory device. In other words, a refresh operation is not required or the frequency of the refresh operation is extremely low, so that the power consumption of the memory device can be sufficiently reduced.

[0475] 34, a wiring 1001 is electrically connected to a source of a transistor 300, and a wiring 1002 is electrically connected to a drain of the transistor 300. A wiring 1003 is electrically connected to one of a source and a drain of the transistor 200, a wiring 1004 is electrically connected to a first gate of the transistor 200, and a wiring 1006 is electrically connected to a second gate of the transistor 200. The gate of the transistor 300 and the other of the source and drain of the transistor 200 are electrically connected to one electrode of the capacitor 100, and a wiring 1005 is electrically connected to the other electrode of the capacitor 100.

[0476] Moreover, the memory device shown in FIG. 34 can be arranged in a matrix to form a memory cell array.

[0477] <Transistor 300> The transistor 300 is provided on a substrate 311 and includes a conductor 316 functioning as a gate, an insulator 315 functioning as a gate insulator, a semiconductor region 313 formed of a part of the substrate 311, and a low-resistance region 314a and a low-resistance region 314b functioning as a source region or a drain region. The transistor 300 may be either a p-channel type or an n-channel type.

[0478] Here, in the transistor 300 shown in FIG. 34, a semiconductor region 313 (a part of a substrate 311) in which a channel is formed has a convex shape. A conductor 316 is provided so as to cover the side and top surface of the semiconductor region 313 via an insulator 315. Note that the conductor 316 may be made of a material that adjusts the work function. Such a transistor 300 is also called a FIN type transistor because it uses a convex portion of a semiconductor substrate. Note that an insulator that contacts the upper part of the convex portion and functions as a mask for forming the convex portion may be provided. Note that, although a case where a convex portion is formed by processing a part of a semiconductor substrate has been shown here, a semiconductor film having a convex shape may be formed by processing an SOI substrate.

[0479] Note that the transistor 300 illustrated in FIG. 34 is just an example, and the present invention is not limited to this structure. An appropriate transistor may be used depending on the circuit configuration or driving method.

[0480] <Capacitive element 100> The capacitor 100 is provided above the transistor 200. The capacitor 100 includes a conductor 110 that functions as a first electrode, a conductor 120 that functions as a second electrode, and an insulator 130 that functions as a dielectric. Here, the insulator 130 is preferably an insulator that can be used as the insulator 286 described in the above embodiment.

[0481] The conductor 112 and the conductor 110 can be formed at the same time. The conductor 112 functions as a plug or a wiring electrically connected to the capacitor 100, the transistor 200, or the transistor 300. The conductor 112 and the conductor 110 correspond to the conductor 246 in the above embodiment.

[0482] 34, the conductor 112 and the conductor 110 are shown to have a single-layer structure, but are not limited to this configuration and may have a laminated structure of two or more layers. For example, a conductor having barrier properties and a conductor having high adhesion to the conductor having high conductivity may be formed between a conductor having barrier properties and a conductor having high conductivity.

[0483] The insulator 130 can be made of, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, aluminum oxynitride, aluminum nitride oxide, aluminum nitride, hafnium oxide, hafnium oxynitride, hafnium nitride oxide, hafnium nitride, or the like, and can be provided as a stacked layer or a single layer.

[0484] For example, it is preferable to use a laminated structure of a material with high dielectric strength, such as silicon oxynitride, and a high dielectric constant (high-k) material for the insulator 130. With this configuration, the capacitance element 100 can ensure sufficient capacitance by having an insulator with high dielectric constant (high-k), and the capacitance element 100 can have improved dielectric strength by having an insulator with high dielectric strength, thereby suppressing electrostatic breakdown of the capacitance element 100.

[0485] Examples of high dielectric constant (high-k) material insulators (materials with a high relative dielectric constant) include gallium oxide, hafnium oxide, zirconium oxide, oxides having aluminum and hafnium, oxynitrides having aluminum and hafnium, oxides having silicon and hafnium, oxynitrides having silicon and hafnium, and nitrides having silicon and hafnium.

[0486] On the other hand, materials with high dielectric strength (materials with low dielectric constant) include silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide with added fluorine, silicon oxide with added carbon, silicon oxide with added carbon and nitrogen, silicon oxide or resin with voids, etc.

[0487] <Wiring layer> Between each structure, a wiring layer having an interlayer film, wiring, plugs, etc. may be provided. Also, a plurality of wiring layers may be provided according to the design. Here, a conductor having a function as a plug or wiring may be collectively given the same symbol as a plurality of structures. Also, in this specification, the wiring and the plug electrically connected to the wiring may be integrated. That is, there are cases where a part of the conductor functions as the wiring, and cases where a part of the conductor functions as the plug.

[0488] For example, an insulator 320, an insulator 322, an insulator 324, and an insulator 326 are stacked in this order as an interlayer film over the transistor 300. A conductor 328, a conductor 330, and the like that are electrically connected to the capacitor 100 or the transistor 200 are embedded in the insulator 320, the insulator 322, the insulator 324, and the insulator 326. The conductor 328 and the conductor 330 function as plugs or wirings.

[0489] The insulator functioning as an interlayer film may also function as a planarizing film that covers the uneven shape underneath. For example, the top surface of the insulator 322 may be planarized by a planarization process using a chemical mechanical polishing (CMP) method or the like to enhance flatness.

[0490] A wiring layer may be provided on the insulator 326 and the conductor 330. For example, in Fig. 34, an insulator 350, an insulator 352, and an insulator 354 are stacked in this order. A conductor 356 is formed in the insulator 350, the insulator 352, and the insulator 354. The conductor 356 functions as a plug or a wiring.

[0491] Similarly, a conductor 218, a conductor constituting the transistor 200 (conductor 205), and the like are embedded in the insulators 210, 212, 214, and 216. Note that the conductor 218 functions as a plug or wiring electrically connected to the capacitor 100 or the transistor 300. Furthermore, an insulator 150 is provided over the conductor 120 and the insulator 130.

[0492] Here, similarly to the insulator 241 shown in the above embodiment, the insulator 217 is provided in contact with the side surface of the conductor 218 functioning as a plug. The insulator 217 is provided in contact with the inner wall of the opening formed in the insulators 210, 212, 214, and 216. In other words, the insulator 217 is provided between the conductor 218 and the insulators 210, 212, 214, and 216. Note that the conductor 205 can be formed in parallel with the conductor 218, and therefore the insulator 217 may be formed in contact with the side surface of the conductor 205.

[0493] As the insulator 217, for example, an insulator such as silicon nitride, aluminum oxide, or silicon nitride oxide may be used. Since the insulator 217 is provided in contact with the insulator 210, the insulator 212, the insulator 214, and the insulator 222, it is possible to prevent impurities such as water or hydrogen from the insulator 210 or the insulator 216 from being mixed into the oxide 230 through the conductor 218. In particular, silicon nitride is preferable because it has a high barrier property against hydrogen. In addition, it is possible to prevent oxygen contained in the insulator 210 or the insulator 216 from being absorbed by the conductor 218.

[0494] The insulator 217 can be formed by a method similar to that of the insulator 241. For example, a silicon nitride film is formed by a PEALD method, and an opening reaching the conductor 356 is formed by anisotropic etching.

[0495] Examples of insulators that can be used as the interlayer film include insulating oxides, nitrides, oxynitrides, nitride oxides, metal oxides, metal oxynitrides, and metal nitride oxides.

[0496] For example, by using a material with a low dielectric constant for the insulator that functions as an interlayer film, the parasitic capacitance generated between wirings can be reduced. Therefore, it is advisable to select a material according to the function of the insulator.

[0497] For example, the insulator 150, the insulator 210, the insulator 352, the insulator 354, etc. preferably have an insulator with a low relative dielectric constant. For example, the insulator preferably has silicon oxide to which fluorine has been added, silicon oxide to which carbon has been added, silicon oxide to which carbon and nitrogen have been added, silicon oxide having voids, or resin. Alternatively, the insulator preferably has a laminated structure of silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide to which fluorine has been added, silicon oxide to which carbon has been added, silicon oxide to which carbon and nitrogen have been added, or silicon oxide having voids, and resin. Silicon oxide and silicon oxynitride are thermally stable, so that a laminated structure that is thermally stable and has a low relative dielectric constant can be obtained by combining them with a resin. Examples of the resin include polyester, polyolefin, polyamide (nylon, aramid, etc.), polyimide, polycarbonate, and acrylic.

[0498] Furthermore, when a transistor using an oxide semiconductor is surrounded by an insulator that has a function of suppressing the permeation of oxygen and impurities such as hydrogen, the electrical characteristics of the transistor can be stabilized. Therefore, the insulators 214, 212, and 350 can be made of insulators that have a function of suppressing the permeation of oxygen and impurities such as hydrogen.

[0499] As an insulator having a function of suppressing the permeation of impurities such as hydrogen and oxygen, for example, an insulator containing boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, or tantalum may be used in a single layer or a stacked layer. Specifically, as an insulator having a function of suppressing the permeation of impurities such as hydrogen and oxygen, metal oxides such as aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, or tantalum oxide, silicon nitride oxide, or silicon nitride may be used.

[0500] Conductors that can be used for wiring and plugs include materials containing one or more metal elements selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, etc. Also, semiconductors with high electrical conductivity, typified by polycrystalline silicon containing impurity elements such as phosphorus, and silicides such as nickel silicide may be used.

[0501] For example, the conductor 328, the conductor 330, the conductor 356, the conductor 218, the conductor 112, etc. can be formed of a single layer or a stack of conductive materials such as metal materials, alloy materials, metal nitride materials, or metal oxide materials formed from the above materials. It is preferable to use a high melting point material such as tungsten or molybdenum that has both heat resistance and conductivity, and it is preferable to use tungsten. Alternatively, it is preferable to form the conductor from a low resistance conductive material such as aluminum or copper. By using a low resistance conductive material, the wiring resistance can be reduced.

[0502] <Wiring or plug of layer provided with oxide semiconductor> Note that when an oxide semiconductor is used for the transistor 200, an insulator having an excess oxygen region may be provided near the oxide semiconductor. In that case, an insulator having a barrier property is preferably provided between the insulator having the excess oxygen region and a conductor provided in the insulator having the excess oxygen region.

[0503] 34, for example, an insulator 241 may be provided between the insulator 280 and the insulator 286 and the conductor 240. When the insulator 241 is provided in contact with the insulator 222, the insulator 282, and the insulator 283, the insulator 224 and the transistor 200 can be sealed with an insulator having barrier properties.

[0504] In other words, the insulator 241 can prevent excess oxygen contained in the insulator 224 and the insulator 280 from being absorbed by the conductor 240. Furthermore, the insulator 241 can prevent hydrogen, which is an impurity, from diffusing into the transistor 200 through the conductor 240.

[0505] As the insulator 241, an insulating material having a function of suppressing the diffusion of impurities such as water or hydrogen, and oxygen, may be used. For example, it is preferable to use silicon nitride, silicon nitride oxide, aluminum oxide, or hafnium oxide. In particular, silicon nitride is preferable because it has high barrier properties against hydrogen. In addition, other metal oxides such as magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, or tantalum oxide may be used.

[0506] As described in the above embodiment, the transistor 200 may be sealed with the insulators 212, 214, 282, and 283. Such a structure can reduce the intrusion of hydrogen contained in the insulators 274, 150, and the like into the insulator 280 and the like.

[0507] Here, the conductor 240 penetrates the insulator 283, and the conductor 218 penetrates the insulator 214 and the insulator 212, but as described above, the insulator 241 is provided in contact with the conductor 240, and the insulator 217 is provided in contact with the conductor 218. This makes it possible to reduce hydrogen that is mixed into the inside of the insulators 212, 214, 282, and 283 through the conductors 240 and 218. In this way, the transistor 200 is sealed with the insulators 212, 214, 282, 283, 241, and 217, making it possible to reduce impurities such as hydrogen contained in the insulator 274, etc., from entering from the outside.

[0508] As described in the previous embodiment, the opening region 400 is formed in the insulator 282 and the insulator 280, and the conductor 240 is provided to penetrate the opening region 400. The opening region 400 is provided not only around the conductor 240 in contact with the source electrode or drain electrode of the transistor 200, but also around the conductor 240 in contact with the conductor 218. With this configuration, an opening into which the conductor 240 in contact with the source electrode or drain electrode of the transistor 200 is embedded and an opening into which the conductor 240 in contact with the conductor 218 is embedded can be relatively easily formed at the same time.

[0509] <Dicing line> In the following, a dicing line (sometimes called a scribe line, a dividing line, or a cutting line) that is provided when a large-area substrate is divided into individual semiconductor elements to extract multiple semiconductor devices in chip form will be described. As a dividing method, for example, first, grooves (dicing lines) for dividing the semiconductor elements are formed in the substrate, and then the substrate is cut along the dicing lines to divide (split) the substrate into multiple semiconductor devices.

[0510] 34, for example, it is preferable to design the region where the insulator 283 and the insulator 214 contact each other so as to overlap the dicing line. That is, openings are provided in the insulators 282, 280, 272, 222, and 216 near the region that will become the dicing line provided on the outer edge of the memory cell having the multiple transistors 200.

[0511] That is, insulator 214 and insulator 283 are in contact with each other through openings provided in insulators 282 , 280 , 272 , 222 , and 216 .

[0512] With this structure, the transistor 200 can be surrounded by the insulator 212, the insulator 214, the insulator 282, and the insulator 283. At least one of the insulator 212, the insulator 214, the insulator 282, and the insulator 283 has a function of suppressing diffusion of oxygen, hydrogen, and water, and therefore, even if the substrate is divided into a plurality of chips by dividing the substrate into each circuit region in which the semiconductor element described in this embodiment is formed, impurities such as hydrogen or water can be prevented from entering from the side direction of the divided substrate and diffusing into the transistor 200.

[0513] Furthermore, this structure can prevent excess oxygen in the insulator 280 from diffusing to the outside. Therefore, the excess oxygen in the insulator 280 is efficiently supplied to the oxide in which a channel is formed in the transistor 200. The oxygen can reduce oxygen vacancies in the oxide in which a channel is formed in the transistor 200. As a result, the oxide in which a channel is formed in the transistor 200 can be an oxide semiconductor with low density of defect states and stable characteristics. That is, fluctuations in the electrical characteristics of the transistor 200 can be suppressed and reliability can be improved.

[0514] In the memory device shown in Fig. 34, the shape of the capacitor 100 is a planar type, but the memory device shown in this embodiment is not limited to this. For example, the shape of the capacitor 100 may be a cylindrical type as shown in Fig. 35. In the memory device shown in Fig. 35, the configuration below the insulator 150 is similar to that of the semiconductor device shown in Fig. 34.

[0515] The capacitive element 100 shown in FIG. 35 includes an insulator 150 on an insulator 130, an insulator 142 on an insulator 150, a conductor 115 arranged in an opening formed in the insulator 150 and the insulator 142, an insulator 145 on the conductor 115 and the insulator 142, a conductor 125 on the insulator 145, and an insulator 152 on the conductor 125 and the insulator 145. Here, at least a part of the conductor 115, the insulator 145, and the conductor 125 are arranged in the opening formed in the insulator 150 and the insulator 142. Also, an insulator 154 is arranged on the insulator 152, and a conductor 153 and an insulator 156 are arranged on the insulator 154. Here, the conductor 140 is provided in an opening formed in the insulator 130, the insulator 150, the insulator 142, the insulator 145, the insulator 152, and the insulator 154.

[0516] The conductor 115 functions as the lower electrode of the capacitance element 100, the conductor 125 functions as the upper electrode of the capacitance element 100, and the insulator 145 functions as the dielectric of the capacitance element 100. The capacitance element 100 has a configuration in which the upper electrode and the lower electrode face each other across the dielectric not only on the bottom surface but also on the side surface in the openings of the insulators 150 and 142, and the capacitance per unit area can be increased. Therefore, the deeper the opening is, the larger the capacitance of the capacitance element 100 can be. Increasing the capacitance per unit area of ​​the capacitance element 100 in this way can promote miniaturization or high integration of semiconductor devices.

[0517] The insulator 152 may be made of an insulator that can be used for the insulator 280. The insulator 142 preferably functions as an etching stopper when forming an opening in the insulator 150, and may be made of an insulator that can be used for the insulator 214.

[0518] The shape of the openings formed in the insulator 150 and the insulator 142 when viewed from above may be a rectangle, a polygon other than a rectangle, a polygon with curved corners, or a circle including an ellipse. Here, it is preferable that the area of ​​the opening overlapping with the transistor 200 is large when viewed from above. With such a configuration, the occupation area of ​​a semiconductor device including the capacitor 100 and the transistor 200 can be reduced.

[0519] The conductor 115 is disposed in contact with the insulator 142 and an opening formed in the insulator 150. The top of the conductor 115 preferably approximately coincides with the upper surface of the insulator 142. The lower surface of the conductor 115 contacts the conductor 110 through the opening of the insulator 130. The conductor 115 is preferably formed by an ALD method, a CVD method, or the like, and may be formed using a conductor that can be used for the conductor 205, for example.

[0520] The insulator 145 is disposed so as to cover the conductor 115 and the insulator 142. For example, the insulator 145 is preferably formed by an ALD method, a CVD method, or the like. The insulator 145 may be formed using, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, zirconium oxide, aluminum oxide, aluminum oxynitride, aluminum nitride oxide, aluminum nitride, hafnium oxide, hafnium oxynitride, hafnium nitride oxide, hafnium nitride, or the like, and can be provided as a stacked layer or a single layer. For example, the insulator 145 can be an insulating film stacked in this order of zirconium oxide, aluminum oxide, and zirconium oxide.

[0521] Moreover, it is preferable to use a material with high dielectric strength, such as silicon oxynitride, or a high dielectric constant (high-k) material for the insulator 145. Alternatively, a laminated structure of a material with high dielectric strength and a material with high dielectric constant (high-k) may be used.

[0522] Examples of insulators made of high dielectric constant (high-k) materials (materials with high relative dielectric constant) include gallium oxide, hafnium oxide, zirconium oxide, oxides having aluminum and hafnium, oxynitrides having aluminum and hafnium, oxides having silicon and hafnium, oxynitrides having silicon and hafnium, and nitrides having silicon and hafnium. By using such high-k materials, the capacitance of the capacitance element 100 can be sufficiently secured even if the insulator 145 is made thick. By making the insulator 145 thick, the leakage current occurring between the conductor 115 and the conductor 125 can be suppressed.

[0523] On the other hand, materials with high dielectric strength include silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide with added fluorine, silicon oxide with added carbon, silicon oxide with added carbon and nitrogen, silicon oxide with vacancies, and resin. For example, silicon nitride (SiN x ), silicon oxide (SiO x ), and silicon nitride (SiN x ) can be used. Alternatively, an insulating film can be used in which zirconium oxide, silicon oxide formed by the ALD method, and zirconium oxide are laminated in this order. By using such an insulator with high dielectric strength, the dielectric strength is improved and electrostatic breakdown of the capacitor element 100 can be suppressed.

[0524] The conductor 125 is disposed so as to fill the openings formed in the insulator 142 and the insulator 150. The conductor 125 is electrically connected to the wiring 1005 via the conductor 140 and the conductor 153. The conductor 125 is preferably formed by an ALD method, a CVD method, or the like, and may be formed using a conductor that can be used for the conductor 205, for example.

[0525] The conductor 153 is provided over the insulator 154 and is covered with the insulator 156. The conductor 153 may be any conductor that can be used for the conductor 112, and the insulator 156 may be any insulator that can be used for the insulator 152. Here, the conductor 153 is in contact with the top surface of the conductor 140 and functions as a terminal of the capacitor 100, the transistor 200, or the transistor 300.

[0526] [Storage device 2] An example of a semiconductor device (memory device) according to one embodiment of the present invention is illustrated in FIG.

[0527] <Memory device configuration example 1> Fig. 36 is a cross-sectional view of a semiconductor device including a memory device 290. The memory device 290 shown in Fig. 36 includes a capacitor device 292 in addition to the transistor 200 shown in Fig. 1A to Fig. 1D. Fig. 36 corresponds to a cross-sectional view of the transistor 200 in the channel length direction.

[0528] The capacitance device 292 includes a conductor 242b, an insulator 271b provided on the conductor 242b, an insulator 272 provided in contact with the upper surface of the insulator 271b, the side surface of the insulator 271b, and the side surface of the conductor 242b, and a conductor 294 on the insulator 272. That is, the capacitance device 292 configures a MIM (Metal-Insulator-Metal) capacitance. Note that one of a pair of electrodes included in the capacitance device 292, that is, the conductor 242b, can also serve as a source electrode of a transistor. In addition, a dielectric layer included in the capacitance device 292 can also serve as a protective layer provided in the transistor, that is, the insulator 271 and the insulator 272. Therefore, a part of the manufacturing process of the transistor can be used in the manufacturing process of the capacitance device 292, and therefore a semiconductor device with high productivity can be obtained. In addition, one of a pair of electrodes of the capacitor 292, that is, the conductor 242b, also serves as a source electrode of the transistor, so that the area in which the transistor and the capacitor are arranged can be reduced.

[0529] Note that the conductor 294 may be made of, for example, a material that can be used for the conductor 242.

[0530] As shown in the previous embodiment, the opening region 400a and the opening region 400b are formed in the insulator 282 and the insulator 280, and the conductor 240a is provided to penetrate the opening region 400a. However, the conductor 240 is not provided in the opening region 400b, and the insulator 274 is embedded in the recess on the insulator 283. The opening region 400a and the opening region 400b are respectively arranged on the conductor 242a and the conductor 242b, and are arranged approximately line-symmetrically with the conductor 260 of the transistor 200 as the axis of symmetry. Therefore, approximately equal amounts of oxygen can be supplied to the oxide 230 of the transistor 200 from the source side and the drain side. This can prevent a large bias in the amount of oxygen vacancy between the source side and the drain side in the channel formation region of the transistor 200.

[0531] <Modifications of memory device> Hereinafter, an example of a semiconductor device having a transistor 200, an opening region 400, and a capacitance device 292 according to one embodiment of the present invention, which is different from that shown in the previous <Configuration example 1 of memory device>, will be described with reference to FIG. 37A, FIG. 37B, and FIG. 38. Note that in the semiconductor device shown in FIG. 37A, FIG. 37B, and FIG. 38, structures having the same functions as those of the semiconductor device shown in the previous embodiment and <Configuration example 1 of memory device> (see FIG. 36) are denoted with the same reference numerals. Note that in this section, the materials for the transistor 200, the opening region 400, and the capacitance device 292 can be the materials described in detail in the previous embodiment and <Configuration example 1 of memory device>. Note that, although the memory device shown in FIG. 36 is used as the memory device in FIG. 37A, FIG. 37B, FIG. 38, and the like, the memory device is not limited to this.

[0532] <<Memory Device Variation 1>> Below, an example of a semiconductor device 600 including a transistor 200a, a transistor 200b, a capacitor device 292a, and a capacitor device 292b according to one embodiment of the present invention will be described with reference to FIG. 37A.

[0533] 37A is a cross-sectional view in the channel length direction of a semiconductor device 600 having a transistor 200a, a transistor 200b, a capacitance device 292a, and a capacitance device 292b. Here, the capacitance device 292a has a conductor 242a, an insulator 271a on the conductor 242a, an insulator 272 in contact with the upper surface of the insulator 271a, a side surface of the insulator 271a, and a side surface of the conductor 242a, and a conductor 294a on the insulator 272. The capacitance device 292b has a conductor 242b, an insulator 271b on the conductor 242b, an insulator 272 in contact with the upper surface of the insulator 271b, a side surface of the insulator 271b, and a side surface of the conductor 242b, and a conductor 294b on the insulator 272.

[0534] As shown in FIG. 37A, the semiconductor device 600 has a linear symmetrical configuration with the dashed line A3-A4 as the axis of symmetry. The conductor 242c serves as one of the source electrode or drain electrode of the transistor 200a and one of the source electrode or drain electrode of the transistor 200b. An insulator 271c is provided on the conductor 242c. An oxide 243c is provided under the conductor 242c. The conductor 246 functions as a wiring, and the conductor 240 functions as a plug to connect the transistor 200a and the transistor 200b. In this way, by configuring the two transistors, the two capacitance devices, and the wiring and the plugs as described above, a semiconductor device that can be miniaturized or highly integrated can be provided.

[0535] The configuration example of the semiconductor device shown in FIG. 36 can be referred to for the configuration and effects of each of the transistor 200a, the transistor 200b, the capacitance device 292a, and the capacitance device 292b.

[0536] As shown in the previous embodiment, the opening regions 400a, 400b, and 400d are formed in the insulator 282 and the insulator 280, and the conductor 240 is provided to penetrate the opening region 400d. However, the conductor 240 is not provided in the opening region 400a and the opening region 400b, and the insulator 274 is embedded in the recess on the insulator 283. The opening regions 400a, 400b, and 400d are respectively disposed on the conductor 242a, the conductor 242b, and the conductor 242c. The opening regions 400a and 400d are disposed approximately line-symmetrically with the conductor 260 of the transistor 200a as the axis of symmetry, and the opening regions 400b and 400d are disposed approximately line-symmetrically with the conductor 260 of the transistor 200b as the axis of symmetry. Therefore, the oxide 230 of the transistor 200a and the transistor 200b can be supplied with approximately equal amounts of oxygen from the source side and the drain side, which can prevent a large imbalance in the amount of oxygen vacancy between the source side and the drain side in the channel formation regions of the transistor 200a and the transistor 200b.

[0537] <<Memory Device Modification 2>> In the above, the transistor 200a, the transistor 200b, the capacitance device 292a, and the capacitance device 292b are given as examples of the configuration of the semiconductor device, but the semiconductor device shown in this embodiment is not limited to this. For example, as shown in FIG. 37B, a configuration may be adopted in which a semiconductor device 600 and a semiconductor device having a similar configuration to the semiconductor device 600 are connected via a capacitance portion. Also, a configuration may be adopted in which an opening region 400 is disposed between adjacent semiconductor devices 600 and a semiconductor device having a similar configuration to the semiconductor device 600. In this specification, a semiconductor device having the transistor 200a, the transistor 200b, the capacitance device 292a, and the capacitance device 292b is referred to as a cell. For the configurations of the transistor 200a, the transistor 200b, the capacitance device 292a, and the capacitance device 292b, the above description of the transistor 200a, the transistor 200b, the capacitance device 292a, and the capacitance device 292b can be referred to.

[0538] FIG. 37B is a cross-sectional view of a semiconductor device 600 having a transistor 200a, a transistor 200b, a capacitance device 292a, and a capacitance device 292b, and a cell having a similar configuration to the semiconductor device 600, connected via a capacitance portion.

[0539] As shown in FIG. 37B, the conductor 294b functioning as one electrode of the capacitance device 292b of the semiconductor device 600 is configured to also serve as one electrode of the capacitance device of the semiconductor device 601 having the same configuration as the semiconductor device 600. Although not shown, the conductor 294a functioning as one electrode of the capacitance device 292a of the semiconductor device 600 also serves as one electrode of the capacitance device of the semiconductor device adjacent to the left side of the semiconductor device 600, that is, in FIG. 37B, in the A1 direction. The right side of the semiconductor device 601, that is, in FIG. 37B, has a similar configuration for the cells in the A2 direction. That is, a cell array (also called a memory device layer) can be configured. By configuring the cell array in this way, the interval between adjacent cells can be reduced, so that the projection area of ​​the cell array can be reduced, and high integration is possible. Also, by arranging the cell array configuration shown in FIG. 37B in a...

Claims

1. a transistor having a gate electrode, a gate insulating film, a source electrode, and a drain electrode; a first insulator on the transistor; a second insulator on the first insulator; and a third insulator on the second insulator; and a first electrode in contact with an upper surface of the source electrode; a second electrode in contact with an upper surface of the drain electrode; a fourth insulator provided in contact with a side surface of the first electrode; a fifth insulator provided in contact with a side surface of the second electrode; the second insulator has a first opening overlapping the source electrode and a second opening overlapping the drain electrode; the third insulator is in contact with a side surface of the second insulator and an upper surface of the first insulator inside the first opening and the second opening, the first insulator has a first groove overlapping the first opening and a second groove overlapping the second opening; the first electrode is disposed through the first opening; the second electrode is disposed through the second opening; a side surface of the fourth insulator contacts the third insulator at the first opening and the first groove; A semiconductor device, wherein a side surface of the fifth insulator contacts the third insulator at the second opening and the second groove.

2. In claim 1, a side surface of the first electrode contacts the third insulator at the first opening and the first groove; a side surface of the second electrode contacting the third insulator in the second opening and the second groove.

3. In claim 1 or 2, The second insulator comprises aluminum oxide.

4. In any one of claims 1 to 3, the first insulator comprises silicon oxide; The semiconductor device, wherein the third insulator comprises silicon nitride.

5. In claim 4, the transistor includes an oxide semiconductor layer, the gate insulating film, the source electrode, and the drain electrode are provided on the oxide semiconductor layer; the gate electrode is provided on the gate insulating film, the first insulator has an opening formed therein, the opening overlapping a region between the source electrode and the drain electrode; The gate insulating film and the gate electrode are disposed in the opening.

6. In claim 5, a sixth insulator covering the oxide semiconductor layer, the source electrode, and the drain electrode; the sixth insulator has an opening formed therein, the opening overlapping a region between the source electrode and the drain electrode; The semiconductor device, wherein the first insulator is provided on the sixth insulator.

7. In claim 6, The sixth insulator comprises silicon nitride.

8. In any one of claims 1 to 7, the first insulator and the second insulator are formed in an island shape, The third insulator covers the first insulator and the second insulator.

9. In any one of claims 1 to 8, the second insulator has a third opening in a region not overlapping with the gate electrode, the source electrode, and the drain electrode; The third insulator contacts a side surface of the second insulator and an upper surface of the first insulator inside the third opening.

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