Thin film transistor and method for manufacturing thin film transistor

Abstract

A thin film transistor capable of improving the electrical durability of the thin film transistor against bending of a flexible substrate, and a method for manufacturing the thin film transistor are provided. [Solution] The gate insulating layer is composed of a first gate insulating film (21) made of an organic polymer compound that covers the second portion of the support surface and the gate electrode layer, and a second gate insulating film (22) made of an inorganic silicon compound that is sandwiched between the first gate insulating film (21) and the semiconductor layer (13), the thickness of the second gate insulating film (22) being 2 nm or more and 30 nm or less, and the hydrogen content of the second gate insulating film (22) being 5 at% or more and 13 at% or less.

Description

[Technical field]

[0001] The present invention relates to a thin film transistor including, as a gate insulating layer, a laminate of a first gate insulating film made of an organic polymer compound and a second gate insulating film made of an inorganic silicon compound, and a method for manufacturing the thin film transistor. [Background technology]

[0002] A thin film transistor having a gate insulating layer made of an organic polymer compound film and an inorganic silicon compound film has both voltage resistance and flexibility. In order to improve the electrical characteristics of the thin film transistor and to increase the adhesion between layers in the thin film transistor, the dielectric characteristic value (=(ε A / d A ) / (ε B / d B It has been proposed that the relative dielectric constant ε ) used in calculating the dielectric characteristic value should be 0.015 or more and 1.0 or less (see, for example, Patent Document 1). A is the relative dielectric constant of the first gate insulating film containing an organic polymer compound. Thickness d A is the thickness of the first gate insulating film. The relative dielectric constant ε B is the relative dielectric constant of the second gate insulating film containing an inorganic silicon compound. Thickness d B is the thickness of the second gate insulating film. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2010-21264 A Summary of the Invention [Problem to be solved by the invention]

[0004] The relative dielectric constant of the gate insulating layer is an index value indicating whether or not the amount of charge induced per unit area can be secured, and is also an index value indicating whether or not current leakage between the gate electrode and another electrode can be suppressed. On the other hand, the relative dielectric constant of the gate insulating layer is not closely related to the electrical durability of the flexible substrate against bending. Similarly, the above-mentioned dielectric characteristic value obtained by comparing the ease of dielectric polarization between the first gate insulating film and the second gate insulating film is also not closely related to the electrical durability of the flexible substrate against bending. As a result, even a configuration having a specific range of relative dielectric constant, and even a configuration having a specific range of dielectric characteristic value, does not improve the electrical durability of the flexible substrate against bending. [Means for solving the problem]

[0005] A thin film transistor for solving the above problem includes a flexible substrate having a support surface, a gate electrode layer located on a first portion of the support surface, a gate insulating layer covering a second portion of the support surface and the gate electrode layer, a semiconductor layer sandwiching the gate insulating layer between the gate electrode layer and the semiconductor layer, a source electrode layer in contact with a first end of the semiconductor layer, and a drain electrode layer in contact with a second end of the semiconductor layer. The gate insulating layer includes a first gate insulating film made of an organic polymer compound and covering the second portion and the gate electrode layer, and a second gate insulating film made of an inorganic silicon compound and sandwiched between the first gate insulating film and the semiconductor layer. The second gate insulating film has a thickness of 2 nm to 30 nm, and a hydrogen content of the second gate insulating film is 2 at% to 15 at%.

[0006] A thin film transistor for solving the above problems includes a flexible substrate having a support surface, a gate electrode layer located on a first portion of the support surface, a gate insulating layer covering a second portion of the support surface and the gate electrode layer, a semiconductor layer sandwiching the gate insulating layer between the gate electrode layer and the semiconductor layer, a source electrode layer in contact with a first end of the semiconductor layer, and a drain electrode layer in contact with a second end of the semiconductor layer. The gate insulating layer includes a first gate insulating film made of an organic polymer compound and covering the second portion and the gate electrode layer, and a second gate insulating film made of silicon oxide and sandwiched between the first gate insulating film and the semiconductor layer. The second gate insulating film has a thickness of 2 nm to 40 nm, and a hydrogen content of the second gate insulating film is 2 at % to 14 at %.

[0007] A thin film transistor for solving the above problem includes a flexible substrate having a support surface, a gate electrode layer located on a first portion of the support surface, a gate insulating layer covering a second portion of the support surface and the gate electrode layer, a semiconductor layer sandwiching the gate insulating layer between the gate electrode layer and the semiconductor layer, a source electrode layer in contact with a first end of the semiconductor layer, and a drain electrode layer in contact with a second end of the semiconductor layer. The gate insulating layer includes a first gate insulating film made of an organic polymer compound and covering the second portion and the gate electrode layer, and a second gate insulating film made of silicon nitride and sandwiched between the first gate insulating film and the semiconductor layer. The second gate insulating film has a thickness of 2 nm to 30 nm, and a hydrogen content of 5 at % to 18 at %.

[0008] According to the above-mentioned thin film transistors, it is possible to reduce the amount of change in threshold voltage and increase the field effect mobility of the semiconductor layer, and further to suppress the change in field effect mobility due to bending of the flexible substrate.

[0009] In the thin film transistor, the thickness of the second gate insulating film may be 5 nm or more and 25 nm or less, and the hydrogen content of the second gate insulating film may be 6 at % or more and 10 at % or less. With this thin film transistor, it is possible to suppress the change in field effect mobility due to bending of the flexible substrate in a configuration having a higher field effect mobility.

[0010] In the thin film transistor, the first gate insulating film has a relative dielectric constant ε A and thickness d A and the second gate insulating film has a relative dielectric constant ε B and thickness d B The gate insulating layer may satisfy the following formula (1): With this thin film transistor, it is possible to suppress a change in field effect mobility due to bending of a flexible substrate while maintaining high field effect mobility.

[0011] 0.001≦(ε A / d A ) / (ε B / d B )<0.015 … Equation (1) In the thin film transistor, the first gate insulating film may have a relative dielectric constant lower than the relative dielectric constant of the second gate insulating film, and the first gate insulating film may have a thickness of 300 nm or more and 2500 nm or less.

[0012] In the thin film transistor, the semiconductor layer may be an oxide semiconductor layer containing indium. A method for manufacturing a thin film transistor for solving the above problems includes forming a gate electrode layer on a first portion of a support surface of a flexible substrate, forming a gate insulating layer to cover a second portion of the support surface and the gate electrode layer, forming the semiconductor layer to sandwich the gate insulating layer between the gate electrode layer and the semiconductor layer, and forming a source electrode layer in contact with a first end of the semiconductor layer and a drain electrode layer in contact with a second end of the semiconductor layer. Forming the gate insulating layer includes forming a first gate insulating film made of an organic polymer compound that covers the second portion and the gate electrode layer by a coating method, and forming a second gate insulating film made of an inorganic silicon compound and sandwiched between the first gate insulating film and the semiconductor layer by a plasma CVD method. The second gate insulating film has a thickness of 2 nm to 30 nm, and a hydrogen content of the second gate insulating film is 2 at% to 15 at%.

[0013] A method for manufacturing a thin film transistor for solving the above problems includes forming a gate electrode layer on a first portion of a support surface of a flexible substrate, forming a gate insulating layer to cover a second portion of the support surface and the gate electrode layer, forming the semiconductor layer to sandwich the gate insulating layer between the gate electrode layer and the semiconductor layer, and forming a source electrode layer in contact with a first end of the semiconductor layer and a drain electrode layer in contact with a second end of the semiconductor layer. Forming the gate insulating layer includes forming a first gate insulating film made of an organic polymer compound that covers the second portion and the gate electrode layer by a coating method, and forming a second gate insulating film made of silicon oxide and sandwiched between the first gate insulating film and the semiconductor layer by a plasma CVD method. The second gate insulating film has a thickness of 2 nm to 40 nm, and a hydrogen content of the second gate insulating film is 2 at% to 14 at%.

[0014] A method for manufacturing a thin film transistor for solving the above problems includes forming a gate electrode layer on a first portion of a support surface of a flexible substrate, forming a gate insulating layer to cover a second portion of the support surface and the gate electrode layer, forming the semiconductor layer to sandwich the gate insulating layer between the gate electrode layer and the semiconductor layer, and forming a source electrode layer in contact with a first end of the semiconductor layer and a drain electrode layer in contact with a second end of the semiconductor layer. Forming the gate insulating layer includes forming a first gate insulating film made of an organic polymer compound that covers the second portion and the gate electrode layer by a coating method, and forming a second gate insulating film made of silicon nitride and sandwiched between the first gate insulating film and the semiconductor layer by a plasma CVD method. The second gate insulating film has a thickness of 2 nm to 30 nm, and a hydrogen content of the second gate insulating film is 5 at % to 18 at %.

[0015] According to the above-mentioned manufacturing method of the thin film transistor, it is possible to reduce the variation of the threshold voltage and increase the field effect mobility of the semiconductor layer, and further, it is possible to suppress the variation of the field effect mobility due to bending of the flexible substrate. Effect of the Invention

[0016] According to the above configuration, it is possible to improve the electrical durability of the thin film transistor against bending of the flexible substrate. [Brief description of the drawings]

[0017] [Figure 1] FIG. 2 is a cross-sectional view showing a first example of a multilayer structure of a thin film transistor. [Diagram 2] FIG. 11 is a cross-sectional view showing a second example of a multilayer structure of a thin film transistor. [Diagram 3] FIG. 11 is a cross-sectional view showing a thin film transistor according to a comparative example. [Figure 4] Scatter plot showing mobility reduction versus thickness and hydrogen content. [Diagram 5]Scatter plot showing mobility reduction rate versus thickness and dielectric property value. [Figure 6] 1 is a table showing the relationship between the layer configuration and the rate of decrease in mobility in each example. [Figure 7] 1 is a table showing the relationship between the layer configuration and the rate of decrease in mobility in each comparative example. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0018] An embodiment of a thin film transistor and a method for manufacturing the thin film transistor are described below. First, the multi-layer structure of the thin film transistor is described, then the constituent materials and dimensions of each layer of the thin film transistor are described, and then the method for manufacturing the thin film transistor is described.

[0019] Fig. 1 shows a first example of a multilayer structure of a thin film transistor, and Fig. 2 shows a second example of a multilayer structure of a thin film transistor. In the following, the top and bottom surfaces of each component of a thin film transistor will be described from the viewpoints of Fig. 1 and Fig. 2, respectively.

[0020] Furthermore, since the source and drain in a thin film transistor are determined by the operation of the driving circuit of the thin film transistor, one electrode layer may switch its function from source to drain, and another electrode layer may switch its function from drain to source.

[0021] [Multilayer structure] As shown in Fig. 1, the first example of the thin film transistor is a bottom-gate top-contact type transistor. The thin film transistor includes a flexible substrate 11, a gate electrode layer 12, a first gate insulating film 21, a second gate insulating film 22, a semiconductor layer 13, a source electrode layer 14, and a drain electrode layer 15. The first gate insulating film 21 and the second gate insulating film 22 constitute a gate insulating layer.

[0022] The flexible substrate 11 and the gate electrode layer 12 are aligned in a channel depth direction Z, which is the upward direction in Fig. 1. The source electrode layer 14 and the drain electrode layer 15 are aligned in a channel length direction X, which is the rightward direction in Fig. 1. The channel width direction Y is perpendicular to the channel length direction X and the channel depth direction Z.

[0023] The upper surface of the flexible substrate 11 is a support surface 11S extending in the channel length direction X and the channel width direction Y. The support surface 11S includes a first portion 11S1 and a second portion 11S2 that are in contact with each other in the channel length direction X. The area of ​​the first portion 11S1 is smaller than the area of ​​the second portion 11S2. The first portion 11S1 is in contact with the lower surface of the gate electrode layer 12. The second portion 11S2 is in contact with a part of the lower surface of the first gate insulating film 21.

[0024] The first gate insulating film 21 is in contact with the upper surface of the gate electrode layer 12. The first gate insulating film 21 may cover the entire supporting surface 11S, or may cover a portion of the supporting surface 11S. The lower surface of the second gate insulating film 22 contacts the upper surface of the first gate insulating film 21. The second gate insulating film 22 may cover the entire first gate insulating film 21 or may cover a part of the first gate insulating film 21. The second gate insulating film 22 covers the upper surface of the gate electrode layer 12 such that the second gate insulating film 22 and the gate electrode layer 12 sandwich the first gate insulating film 21.

[0025] The lower surface of the semiconductor layer 13 contacts the upper surface of the second gate insulating film 22. The semiconductor layer 13 covers the upper surface of the gate electrode layer 12 such that the semiconductor layer 13 and the gate electrode layer 12 sandwich the first gate insulating film 21 and the second gate insulating film 22. In the channel length direction X, the length of the semiconductor layer 13 is greater than the length of the gate electrode layer 12.

[0026] A part of the lower surface of the source electrode layer 14 contacts the upper surface of the semiconductor layer 13. The other part of the lower surface of the source electrode layer 14 contacts the upper surface of the second gate insulating film 22. The source electrode layer 14 covers the first end of the semiconductor layer 13 in the direction opposite to the channel length direction X so as to be connected to the first end, which is the end of the semiconductor layer 13.

[0027] A part of the lower surface of the drain electrode layer 15 contacts the upper surface of the semiconductor layer 13. The other part of the lower surface of the drain electrode layer 15 contacts the upper surface of the second gate insulating film 22. The drain electrode layer 15 covers the second end of the semiconductor layer 13 in the channel length direction X so as to be connected to the second end, which is the end of the semiconductor layer 13.

[0028] The source electrode layer 14 and the drain electrode layer 15 are spaced apart from each other. In the channel length direction X, the length L between the source electrode layer 14 and the drain electrode layer 15 is smaller than the length of the gate electrode layer 12. In this case, the region between the source electrode layer 14 and the drain electrode layer 15 in the semiconductor layer 13 is the channel region C. The length of the channel region C in the channel length direction X, i.e., the length L between the source electrode layer 14 and the drain electrode layer 15, is the channel length. Moreover, the length of the channel region C in the channel width direction Y is the channel width.

[0029] When the channel length at each position in the channel width direction Y in one thin film transistor is not constant, the average value of all the channel lengths is the channel length of one thin film transistor. When the length L is longer than the length of the gate electrode layer 12, the region of the semiconductor layer 13 that overlaps with the gate electrode layer 12 in the channel depth direction Z is the channel region C.

[0030] As shown in Figure 2, the thin film transistor is a bottom-gate bottom-contact type transistor. Below, we will mainly explain the structure that differs from a bottom-gate top-contact type transistor.

[0031] The lower surface of the source electrode layer 14 contacts the upper surface of the second gate insulating film 22. The lower surface of the drain electrode layer 15 contacts the upper surface of the second gate insulating film 22. A portion of the lower surface of the semiconductor layer 13 is in contact with the second gate insulating film 22. A portion of the lower surface of the semiconductor layer 13 forms a channel region C that fills the gap between the source electrode layer 14 and the drain electrode layer 15 in the channel length direction X.

[0032] A first end portion, which is an end portion in the opposite direction to the channel length direction X on the lower surface of the semiconductor layer 13, covers the upper surface of the source electrode layer 14 so as to contact the upper surface of the source electrode layer 14. A second end portion, which is an end portion in the channel length direction X on the lower surface of the semiconductor layer 13, covers the upper surface of the drain electrode layer 15 so as to contact the upper surface of the drain electrode layer 15.

[0033] [Flexible board] The flexible substrate 11 has an insulating upper surface. The flexible substrate 11 may be a transparent substrate or an opaque substrate. The flexible substrate 11 may be an insulating film, a metal foil having an insulating support surface 11S, an alloy foil having an insulating support surface 11S, or a flexible thin glass plate.

[0034] The material constituting the flexible substrate 11 is at least one selected from the group consisting of organic polymer compounds, composite materials of organic materials and inorganic materials, metals, alloys, and inorganic polymer compounds.

[0035] Flexible substrate 11 may be a single-layer structure or a multi-layer structure. When flexible substrate 11 is a multi-layer structure, the constituent material of each layer constituting flexible substrate 11 is any one selected from the group consisting of organic polymer compounds, composite materials, metals, alloys, and inorganic polymer compounds.

[0036] When the flexible substrate 11 is a multi-layer structure, the flexible substrate 11 may include a base substrate and a release layer configured to be peelable from the base substrate. The release layer is peeled off from the base substrate together with the element structure. The release layer including the element structure may be attached to another flexible substrate. Flexible substrates include papers, cellophane substrates, cloths, recycled fibers, leather, nylon substrates, and polyurethane substrates that have low heat resistance. In this case, the release layer and the flexible substrate constitute another flexible substrate 11.

[0037] The organic polymer compound is at least one selected from the group consisting of polymethyl methacrylate, polyacrylate, polycarbonate, polystyrene, polyethylene sulfide, polyethersulfone, polyolefin, polyethylene terephthalate, polyethylene naphthalate, cycloolefin polymer, polyethersulfene, triacetyl cellulose, polyvinyl fluoride film, ethylene-tetrafluoroethylene copolymer, polyimide, fluorine-based polymer, and cyclic polyolefin-based polymer.

[0038] The composite material is a glass fiber reinforced acrylic polymer or a glass fiber reinforced polycarbonate. The metal is aluminum or copper. The alloy is an iron chromium alloy, an iron nickel alloy, or an iron nickel chromium alloy. The inorganic polymer compound is an alkali-free glass containing silicon oxide, boron oxide, and aluminum oxide, or an alkali glass containing silicon oxide, sodium oxide, and calcium oxide.

[0039] [Electrode layer] Each of the electrode layers 12, 14, and 15 may be a single-layer structure or a multilayer structure. When each of the electrode layers 12, 14, and 15 is a multilayer structure, each of the electrode layers 12, 14, and 15 preferably has a bottom layer that enhances adhesion to the layer below it, and a top layer that enhances adhesion to the layer above it.

[0040] The material constituting each of the electrode layers 12, 14, and 15 may be a metal, an alloy, or a metal oxide having electrical conductivity. The materials constituting each of the electrode layers 12, 14, and 15 may be different from each other or the same.

[0041] The metal is at least one of a transition metal, an alkali metal, and an alkaline earth metal. The transition metal is at least one selected from the group consisting of indium, aluminum, gold, silver, platinum, titanium, copper, nickel, and tungsten. The alkali metal is lithium or cesium. The alkaline earth metal is at least one of magnesium and calcium. The alloy is any one selected from the group consisting of molybdenum niobium (MoNb), iron chromium, aluminum lithium, magnesium silver, aluminum neodymium alloy, and aluminum neodymium zirconia alloy ().

[0042] The metal oxide is any one selected from the group consisting of indium oxide, tin oxide, zinc oxide, cadmium oxide, indium cadmium oxide, cadmium tin oxide, and zinc tin oxide. The metal oxide may contain impurities. The metal oxide containing impurities is indium oxide containing at least one impurity selected from the group consisting of tin, zinc, titanium, cerium, hafnium, zirconium, and molybdenum. The metal oxide containing impurities may be tin oxide containing antimony or fluorine. The metal oxide containing impurities may be zinc oxide containing at least one impurity selected from the group consisting of gallium, aluminum, and boron.

[0043] When the material constituting the semiconductor layer 13 is a metal oxide, each of the electrode layers 14 and 15 may be composed of the same constituent elements as the semiconductor layer 13 and have a sufficiently higher impurity concentration than the semiconductor layer 13.

[0044] When the range of materials applicable to each of the electrode layers 12, 14, and 15 is expanded, the electrical resistivity of each of the electrode layers 12, 14, and 15 is preferably 5.0×10 -5 In order to suppress the power consumption of the thin film transistor, the electrical resistivity of each of the electrode layers 12, 14, and 15 is preferably 1.0×10 -2 Ω·cm or less.

[0045] To suppress the electrical resistance of each of the electrode layers 12, 14, 15, the thickness of each of the electrode layers 12, 14, 15 is preferably 50 nm or more. To improve the flatness of each layer constituting the thin film transistor, the thickness of each of the electrode layers 12, 14, 15 is preferably 300 nm or less.

[0046] [Semiconductor layer] The material constituting the semiconductor layer 13 may be an inorganic semiconductor or an organic semiconductor. The inorganic semiconductor may be an oxide semiconductor, amorphous silicon, or a compound semiconductor. The oxide semiconductor contains at least one of indium and zinc.

[0047] When the light transmittance and field effect mobility (hereinafter also referred to as mobility) of the semiconductor layer 13 are to be increased, the semiconductor layer 13 is preferably an oxide semiconductor layer containing indium. The oxide semiconductor is more preferably an In-M-Zn-based oxide. The In-M-Zn-based oxide contains indium (In) and zinc (Zn), and also contains at least one metal element (M) selected from the group consisting of aluminum, titanium, gallium (Ga), germanium, yttrium, zirconium, lanthanum, cerium, hafnium, and tin.

[0048] To improve the uniformity of the thickness of the semiconductor layer 13, the thickness of the semiconductor layer 13 is preferably 5 nm or more. To reduce the amount of material used for the semiconductor layer 13, the thickness of the semiconductor layer 13 is preferably 100 nm or less. To achieve both improved uniformity of the thickness and reduced amount of material used, the thickness of the semiconductor layer 13 is preferably 5 nm or more and 100 nm or less. Furthermore, to increase the effectiveness of obtaining these effects, the thickness of the semiconductor layer 13 is more preferably 10 nm or more and 50 nm or less.

[0049] In order to increase the mobility, the electrical resistivity of the semiconductor layer 13 is preferably 1.0×10 4 In order to increase the current on / off ratio, which is the ratio of the on current value to the off current value, the electrical resistivity of the semiconductor layer 13 is preferably 1.0×10 -1In order to improve both the mobility and the current on / off ratio, the electrical resistivity of the semiconductor layer 13 is preferably 1.0×10 -1 Ω cm or more 1.0×10 4 Furthermore, in order to enhance the effectiveness of obtaining these effects, the electrical resistivity of the semiconductor layer 13 is preferably 1.0×10 0 Ω cm or more 1.0×10 3 Ω·cm or less.

[0050] [Insulating film] The material constituting the first gate insulating film 21 is an organic polymer compound. The organic polymer compound is at least one selected from the group consisting of polyvinylphenol, polyimide, polyvinyl alcohol, acrylic polymer, epoxy polymer, fluorine-based polymer including amorphous fluorine polymer, melamine polymer, furan polymer, xylene polymer, polyamide-imide polymer, and silicone polymer. When the heat resistance of the first gate insulating film 21 is to be increased, the organic polymer compound is preferably at least one selected from the group consisting of polyimide, acrylic polymer, and fluorine-based polymer.

[0051] The first gate insulating film 21 may be a single layer film or a multilayer film. When the first gate insulating film 21 is a multilayer film, the constituent materials of each layer constituting the first gate insulating film 21 are organic polymer compounds.

[0052] The relative dielectric constant ε of the first gate insulating film 21 A is not less than 2.0 and not more than 5.0. When the thickness of the first gate insulating film 21 is reduced to increase the mobility, the relative dielectric constant of the first gate insulating film 21 is preferably not less than 3.0 and not more than 4.0.

[0053] In order to suppress current leakage between the gate electrode layer 12 and the other electrode layers 14 and 15, the thickness of the first gate insulating film 21 is preferably 500 nm or more. In order to suppress the gate voltage for driving the thin film transistor, the thickness of the first gate insulating film 21 is preferably 10 μm or less. In order to suppress current leakage and gate voltage, the thickness of the first gate insulating film 21 is preferably 500 nm or more and 10 μm or less. Furthermore, in order to increase the effectiveness of obtaining these effects, increase the uniformity of the thickness of the first gate insulating film 21, and improve the productivity of the first gate insulating film 21, the thickness of the first gate insulating film 21 is more preferably 1000 nm or more and 5000 nm or less. The thickness of the first gate insulating film 21 is further preferably 1000 nm or more and 2500 nm or less.

[0054] In order to improve the voltage resistance of the gate insulating layer, the resistivity of the gate insulating layer is preferably 1×10 11 Furthermore, when the first gate insulating film 21 is thinned, the resistivity of the gate insulating layer is preferably 1×10 13 Ω·cm or more.

[0055] The material constituting the second gate insulating film 22 is an inorganic silicon compound that does not have a long-range order. The inorganic silicon compound is at least one selected from the group consisting of silicon oxide, silicon nitride, and silicon oxynitride. Elements constituting silicon nitride include oxygen, silicon, and hydrogen. Elements constituting silicon nitride include nitrogen, silicon, and hydrogen. Elements constituting silicon oxynitride include oxygen, nitrogen, silicon, and hydrogen.

[0056] The relative dielectric constant ε of the second gate insulating film 22 B is the relative dielectric constant ε of the first gate insulating film 21 A or more, and is equal to or more than 3.5 and equal to or less than 10. In order to make the inorganic silicon compound into a continuous film without being scattered like islands, the thickness of the second gate insulating film 22 is equal to or more than 2 nm.

[0057] The second gate insulating film 22 may be a single layer film or a multilayer film. When the second gate insulating film 22 is a multilayer film, the constituent material of each layer constituting the second gate insulating film 22 is an inorganic silicon compound.

[0058] Silicon oxide contains hydrogen in at least one of the forms of a silicon-hydrogen bond and an oxygen-hydrogen bond. The ratio of the oxygen content of silicon oxide to the silicon content of silicon oxide is 2 or less, which is the stoichiometric ratio of silicon dioxide.

[0059] Silicon nitride contains hydrogen in at least one of the forms of silicon-hydrogen bonds and nitrogen-hydrogen bonds. The ratio of the nitrogen content of silicon nitride to the silicon content of silicon nitride is 4 / 3 or less, which is the stoichiometric ratio of trisilicon tetranitride.

[0060] Silicon oxynitride contains hydrogen in at least one of the following states: a bond between silicon and hydrogen, a bond between oxygen and hydrogen, and a bond between nitrogen and hydrogen. The composition of silicon oxynitride may have a higher nitrogen content than an oxygen content, or the oxygen content may be higher than the nitrogen content.

[0061] Hydrogen contained in the inorganic silicon compound forms defects in the lattice of the inorganic silicon compound that forms a short-range order, and reduces the fluctuation of the short-range order caused by bending of the flexible substrate 11. Note that as the hydrogen content increases, the number of dangling bonds of silicon contained in the inorganic silicon compound decreases. In addition, since the oxygen and nitrogen contents contained in the inorganic silicon compound tend to decrease, when the semiconductor layer 13 is an oxide semiconductor, it is easy to maintain a suitable amount of oxygen vacancies in the oxide semiconductor. On the other hand, when the hydrogen content is excessive, hydrogen tends to dissociate from silicon in the second gate insulating film 22, and the dissociated hydrogen may diffuse, causing a change in the threshold voltage.

[0062] Therefore, when the material constituting the second gate insulating film 22 is at least one of silicon oxide, silicon nitride, and silicon oxynitride, in order to improve the durability of the electrical characteristics against bending of the flexible substrate 11, the second gate insulating film 22 satisfies the following conditions 1 and 2. (Condition 1) The hydrogen content is 2 at % or more and 15 at % or less. (Condition 2) Thickness d B is less than 30 nm.

[0063] Furthermore, when the material constituting the second gate insulating film 22 is silicon oxide, in order to increase the durability of the electrical characteristics against bending of the flexible substrate 11, the second gate insulating film 22 satisfies the following conditions 3 and 4. (Condition 3) The hydrogen content is 2 at % or more and 14 at % or less. (Condition 4) Thickness d B is less than 40 nm.

[0064] Furthermore, in order to increase the effectiveness of improving the durability of the electrical characteristics, the hydrogen content of the silicon oxide is preferably 6 at % or more and 10 at % or less, and the thickness of the second gate insulating film 22 is preferably 5 nm or more and 25 nm or less.

[0065] Furthermore, when the material constituting the second gate insulating film 22 is silicon nitride, in order to increase the durability of the electrical characteristics against bending of the flexible substrate 11, the second gate insulating film 22 satisfies the following conditions 5 and 6. (Condition 5) The hydrogen content is 5 at % or more and 18 at % or less. (Condition 6) Thickness d B is less than 30 nm.

[0066] In order to improve the electrical characteristics of the thin film transistor, the gate insulating layer, which is a laminated structure of the first gate insulating film 21 and the second gate insulating film 22, preferably satisfies the following formula (1). A and thickness d A The second gate insulating film 22 has a relative dielectric constant ε B and thickness d B and 0.001≦(ε A / d A ) / (ε B / d B )<0.015 … Equation (1)

[0067] To increase the voltage resistance of the gate insulating layer, the dielectric characteristic value K(=(ε A / d A ) / (ε B / d B ) is preferably less than 0.015. For increased mobility, the dielectric characteristic value K is preferably 0.001 or more.

[0068] [Method of manufacturing thin film transistor] The method for manufacturing a bottom-gate-top-contact transistor includes a first step of forming a gate electrode layer 12 on a flexible substrate 11, a second step of laminating a first gate insulating film 21 on the gate electrode layer 12, and a third step of laminating a second gate insulating film 22 on the first gate insulating film 21. The method for manufacturing a bottom-gate-top-contact transistor also includes a fourth step of laminating a semiconductor layer 13 on the second gate insulating film 22, and a fifth step of laminating a source electrode layer 14 and a drain electrode layer 15 on the semiconductor layer 13.

[0069] In the manufacturing method of the bottom gate-bottom contact transistor, in the fourth step, the source electrode layer 14 and the drain electrode layer 15 are laminated on the second gate insulating film 22. In the fifth step, the semiconductor layer 13 is laminated on the source electrode layer 14, the drain electrode layer 15, and the second gate insulating film 22. The method used in the fourth step is the same as the method used in the fifth step in the manufacturing method of the bottom gate-top contact transistor. The method used in the fifth step is the same as the method used in the fourth step in the manufacturing method of the bottom gate-top contact transistor. Therefore, in the following, the manufacturing method of the bottom gate-top contact transistor will be mainly described, and a duplicated description of the manufacturing method of the bottom gate-bottom contact transistor will be omitted.

[0070] In the first step, the gate electrode layer 12 may be formed by a film formation method using a mask that follows the shape of the gate electrode layer 12. Alternatively, the gate electrode layer 12 may be formed by a method in which an electrode film that becomes the gate electrode layer 12 is formed, and then the electrode film is processed into the shape of the gate electrode layer 12 by an etching method.

[0071] The film formation method used to form the gate electrode layer 12 is at least one selected from the group consisting of a vacuum deposition method, an ion plating method, a sputtering method, a laser ablation method, a spin coating method using a conductive paste, a dip coating method, and a slit die coating method, or is at least one selected from the group consisting of a screen printing method, a letterpress printing method, an intaglio printing method, a lithographic printing method, and an inkjet method.

[0072] In the second step, the first gate insulating film 21 may be formed by a coating method using a mask that follows the shape of the first gate insulating film 21. Alternatively, the first gate insulating film 21 may be formed by a method in which a coating film that becomes the first gate insulating film 21 is formed, and then the coating film is processed into the shape of the first gate insulating film 21 by a photolithography method.

[0073] The coating method used to form the first gate insulating film 21 is at least one selected from the group consisting of spin coating, dip coating, slit die coating, screen printing, and inkjet, using a coating liquid containing an organic polymer compound. In the coating method, a coating film is formed by baking a liquid film made of the coating liquid. When a photolithography method is used to form the first gate insulating film 21, the coating liquid contains a photosensitive polymer.

[0074] In the third step, the second gate insulating film 22 may be formed by a film formation method using a mask that follows the shape of the second gate insulating film 22. Alternatively, the second gate insulating film 22 may be formed by a method in which an insulating film that will become the second gate insulating film 22 is formed, and then the insulating film is processed into the shape of the second gate insulating film 22 by an etching method.

[0075] The film formation method used to form the second gate insulating film 22 is at least one selected from the group consisting of a laser ablation method, a plasma CVD method, a photo-CVD method, a thermal CVD method, a sputtering method, and a sol-gel method, or at least one coating method selected from the group consisting of a spin coating method using a coating liquid containing a precursor of an inorganic polymer compound, a dip coating method, a slit die coating method, a screen printing method, and an inkjet method.

[0076] In the fourth step, the semiconductor layer 13 may be formed by a film formation method using a mask that follows the shape of the semiconductor layer 13. Alternatively, the semiconductor layer 13 may be formed by a method in which a semiconductor film that becomes the semiconductor layer 13 is formed, and then the semiconductor film is processed into the shape of the semiconductor layer 13 by an etching method.

[0077] The semiconductor layer 13 is formed by a sputtering method or a CVD method. The sputtering method includes a DC sputtering method in which a direct current voltage is applied to the flexible substrate 11, and an RF sputtering method in which a high frequency is applied to a film formation space. The method of adding impurities includes a plasma treatment method, an ion implantation method, an ion doping method, and a plasma immersion ion implantation method.

[0078] In the fifth step, the source electrode layer 14 and the drain electrode layer 15 may be formed by a film formation method using a mask that follows the shape of the electrode layer. Alternatively, the source electrode layer 14 and the drain electrode layer 15 may be formed by a method in which an electrode film that becomes the electrode layers 14 and 15 is formed, and then the electrode film is processed into the shape of the source electrode layer 14 and the drain electrode layer 15 by an etching method.

[0079] The film formation method used for forming the source electrode layer 14 and the drain electrode layer 15 is at least one selected from the group consisting of vacuum evaporation method, ion plating method, sputtering method, laser ablation method, spin coating method using conductive paste, dip coating method, and slit die coating method. Alternatively, the film formation method used for forming the gate electrode layer 12 is at least one selected from the group consisting of screen printing method, relief printing method, intaglio printing method, lithographic printing method, and inkjet method.

[0080] [Example 1] First, a polyimide film was used as the flexible substrate 11, and a MoNb film with a thickness of 100 nm was used as the gate electrode layer 12. The gate electrode layer 12 was formed by using a non-heating sputtering method with a MoNb sintered body as a target, with a shadow mask disposed on the upper surface of the flexible substrate 11. The film formation conditions of the MoNb film by the non-heating sputtering method are shown below.

[0081] <Film formation conditions of MoNb film> · Target composition ratio: Mo(at%):Nb(at%) = 9:1 · Sputtering gas: Argon · Sputtering gas flow rate: 45 sccm · Film formation pressure: 1.0 Pa · Target power: 200 W (DC)

[0082] Next, an acrylic polymer film with a thickness d A of 1000 nm was used as the first gate insulating film 21, and a silicon oxide film with a thickness d B of 2 nm was used as the second gate insulating film 22. The acrylic polymer film was formed by first laminating a coating film on the upper surfaces of the flexible substrate 11 and the gate electrode layer 12 using a spin coating method with an acrylic polymer as an organic polymer compound. Then, the coating film was fired to obtain an acrylic polymer film.

[0083] Note that the first gate insulating film 21 of Example 1 was formed on a substrate for measuring the relative dielectric constant ε A and the relative dielectric constant ε AAs a result of measuring the relative dielectric constant ε A The film formation conditions for the above acrylic polymer film by spin coating are shown below.

[0084] <Acrylic polymer film formation conditions> Substrate rotation speed: 730 rpm / 30 sec Pre-baking temperature: 90℃ Pre-baking time: 2 minutes · Main firing temperature: 200℃ - Firing time: 1 hour

[0085] The silicon oxide film was formed by laminating the silicon oxide film on the top surface of the acrylic polymer film using a parallel plate plasma CVD method. B The silicon oxide film of Example 1 was formed on the substrate for measuring the relative dielectric constant ε B As a result of measuring the relative dielectric constant ε B The film formation conditions for the silicon oxide film by the parallel plate plasma CVD method are shown below. <Conditions for forming silicon oxide film> ·Substrate temperature: 200℃ Reactive gas: Silane / nitrous oxide Reactive gas flow rate: 65sccm (silane), 500sccm (nitrous oxide) Deposition pressure: 200Pa High frequency power: 500W High frequency power frequency: 13.56MHz

[0086] The dielectric characteristic value K of the gate insulating layer of Example 1 was 0.00149. Hydrogen content r H The silicon oxide film of Example 1 was formed on a substrate for measuring the hydrogen content r H The hydrogen content r in the second gate insulating film 22 in Example 1 was measured.H was 9.7 at%. In addition, the silicon content in the silicon oxide film of Example 1 using Rutherford Backscattering Spectrometry (RBS) was 31.2 at%, the oxygen content was 58.0 at%, and it was confirmed that nitrogen and carbon were below the detection limit.

[0087] Next, an InGaZnO film with a thickness of 35 nm was used as the semiconductor layer 13. The InGaZnO film was formed by a non-heating sputtering method using a shadow mask disposed on the upper surface of the second gate insulating film 22 and using an InGaZnO sintered body as a target. The film formation conditions of the InGaZnO film by the non-heating sputtering method are shown below. <Film Formation Conditions of InGaZnO Film> · Target composition ratio: atomic mass% In:Ga:Zn:O = 1:1:1:4 · Sputtering gas: argon / oxygen · Sputtering gas flow rate: 50 sccm (argon), 0.2 sccm (oxygen) · Film formation pressure: 1.0 Pa · Target power: 300 W · Target frequency: 13.56 MHz

[0088] Next, a MoNb film with a thickness of 100 nm was used as the source electrode layer 14. Also, a MoNb film with a thickness of 100 nm was used as the drain electrode layer 15. The source electrode layer 14 and the drain electrode layer 15 were formed by a non-heating sputtering method using a shadow mask disposed on the upper surfaces of the second gate insulating film 22 and the semiconductor layer 13 and using a MoNb sintered body as a target. The film formation conditions of the MoNb film by the non-heating sputtering method are shown below. <Film Formation Conditions of MoNb Film> · Target composition ratio: atomic mass% Mo:Nb = 9:1 · Sputtering gas: argon · Sputtering gas flow rate: 45 sccm · Film formation pressure: 1.0 Pa · Target power: 200 W (DC)

[0089] Then, the flexible substrate 11, the gate electrode layer 12, the first gate insulating film 21, the second gate insulating film 22, the semiconductor layer 13, the source electrode layer 14, and the drain electrode layer 15 were annealed at 150° C., thereby obtaining the bottom-gate top-contact type transistor of Example 1. The channel length in the thin film transistor of Example 1 was 200 μm, and the channel width was 2000 μm.

[0090] [Example 2] The second gate insulating film 22 has a thickness d B A bottom-gate top-contact transistor of Example 2 was obtained by using a silicon oxide film having a thickness of 5 nm and maintaining the same configuration as Example 1 except for the second gate insulating film 22. In forming the second gate insulating film 22, the film formation time was changed from the film formation conditions of Example 1, and the conditions other than the film formation time were maintained the same as Example 1 to obtain the silicon oxide film of Example 2.

[0091] Hydrogen content r in the second gate insulating film 22 in Example 2 H The relative dielectric constant ε of the second gate insulating film 22 in Example 2 was 9.7 at %. B was 4.7, and the dielectric characteristic value K of the gate insulating layer of Example 2 was 0.00372. The channel length of the thin film transistor of Example 2 was 200 μm, and the channel width was 2000 μm.

[0092] [Example 3] The second gate insulating film 22 has a thickness d B A bottom-gate top-contact type transistor of Example 3 was obtained by using a silicon oxide film having a thickness of 20 nm and by maintaining the same configuration as Example 1 except for the second gate insulating film 22. In forming the second gate insulating film 22, the film formation time was changed from the film formation conditions of Example 1, and the conditions other than the film formation time were maintained the same as Example 1 to obtain the silicon oxide film of Example 3.

[0093] Hydrogen content r in the second gate insulating film 22 in Example 3 H The relative dielectric constant ε Bwas 4.7, and the dielectric characteristic value K of the gate insulating layer of Example 3 was 0.01489. The channel length of the thin film transistor of Example 3 was 200 μm, and the channel width was 2000 μm.

[0094] [Example 4] A bottom-gate top-contact transistor of Example 4 was obtained by using a silicon nitride film with a thickness of 5 nm as the second gate insulating film 22 and by making the configuration the same as that of Example 1 except for the second gate insulating film 22. The silicon nitride film was formed on the upper surface of the acrylic polymer film by using a parallel plate plasma CVD method. The conditions for forming the silicon nitride film by the plasma CVD method are shown below. <Conditions for forming silicon nitride film> ·Substrate temperature: 200℃ Reactive gas: silane / ammonia / hydrogen / nitrogen Reaction gas flow rate: 10sccm (silane), 70sccm (ammonia) 3000sccm (hydrogen), 2000sccm (nitrogen) Deposition pressure: 300Pa High frequency power: 500W High frequency power frequency: 13.56MHz

[0095] Hydrogen content r in the second gate insulating film 22 in Example 4 H The relative dielectric constant ε of the second gate insulating film 22 in Example 4 was 14.1 at %. B was 7.8, and the dielectric characteristic value K of the gate insulating layer of Example 4 was 0.00224. The channel length of the thin film transistor of Example 4 was 200 μm, and the channel width was 2000 μm. It was confirmed by Rutherford Backscattering Spectrometry (RBS) that the silicon content in the silicon nitride film of Example 4 was 40.1 at%, the nitrogen content was 43.5 at%, the oxygen content was 1.9 at%, and the carbon was below the detection limit.

[0096] [Example 5] The second gate insulating film 22 has a thickness d B A bottom-gate top-contact type transistor of Example 5 was obtained by using a silicon nitride film having a thickness of 15 nm and by maintaining the same configuration as Example 1 except for the second gate insulating film 22. In forming the second gate insulating film 22, the film formation time was changed from the film formation conditions of Example 4, and the conditions other than the film formation time were kept the same to obtain a silicon nitride film.

[0097] Hydrogen content r in the second gate insulating film 22 in Example 5 H The relative dielectric constant ε of the second gate insulating film 22 in Example 5 was 14.1 at %. B was 7.8, and the dielectric characteristic value K of the gate insulating layer of Example 5 was 0.01346. The channel length of the thin film transistor of Example 5 was 200 μm, and the channel width was 2000 μm.

[0098] [Example 6] The second gate insulating film 22 has a thickness d B A bottom-gate top-contact transistor of Example 6 was obtained using a silicon oxynitride film having a thickness of 20 nm, with the configuration being the same as that of Example 1 except for the second gate insulating film 22. The silicon oxynitride film was formed on the upper surface of the acrylic polymer film by using a parallel plate plasma CVD method. The conditions for forming the silicon oxynitride film by the plasma CVD method are shown below. <Conditions for forming silicon oxynitride film> ·Substrate temperature: 200℃ Reactive gas: silane / ammonia / hydrogen / nitrous oxide Reaction gas flow rate: 10sccm (silane), 60sccm (ammonia) 3000sccm (hydrogen), 1500sccm (nitrogen) Deposition pressure: 300Pa High frequency power: 500W High frequency power frequency: 13.56MHz

[0099] Hydrogen content r in the second gate insulating film 22 in Example 6 H The relative dielectric constant εB was 6.1, and the dielectric characteristic value K of the gate insulating layer of Example 6 was 0.01147. The channel length of the thin film transistor of Example 6 was 200 μm, and the channel width was 2000 μm.

[0100] [Example 7] The second gate insulating film 22 has a thickness d B A bottom-gate top-contact transistor of Example 7 was obtained by using a silicon oxide film having a thickness of 5 nm and by using the same configuration as Example 1 except for the second gate insulating film 22. The silicon oxide film was formed by laminating the silicon oxide film on the upper surface of the acrylic polymer film using a parallel plate plasma CVD method. The film formation conditions for the silicon oxide film by the parallel plate plasma CVD method are shown below. <Conditions for forming silicon oxide film> ·Substrate temperature: 200℃ Reactive gas: Silane / nitrous oxide Reactive gas flow rate: 65sccm (silane), 600sccm (nitrous oxide) Deposition pressure: 200Pa High frequency power: 500W High frequency power frequency: 13.56MHz

[0101] Hydrogen content r in the second gate insulating film 22 in Example 7 H The relative dielectric constant ε B was 4.2, and the dielectric characteristic value K of the gate insulating layer of Example 7 was 0.00417. The channel length of the thin film transistor of Example 7 was 200 μm, and the channel width was 2000 μm.

[0102] [Example 8] The second gate insulating film 22 has a thickness d BA bottom-gate top-contact transistor of Example 8 was obtained by using a silicon oxide film having a thickness of 25 nm and maintaining the same configuration as Example 1 except for the second gate insulating film 22. The silicon oxide film was formed by laminating the silicon oxide film on the upper surface of the acrylic polymer film using a parallel plate plasma CVD method. The silicon oxide film was formed by changing the film formation time in the film formation conditions of Example 1 and maintaining the same conditions as Example 1 except for the film formation time, thereby obtaining the silicon oxide film of Example 8.

[0103] Hydrogen content r in the second gate insulating film 22 in Example 8 H The relative dielectric constant ε B was 4.7, and the dielectric characteristic value K of the gate insulating layer of Example 8 was 0.01861. The channel length of the thin film transistor of Example 8 was 200 μm, and the channel width was 2000 μm.

[0104] [Example 9] The first gate insulating film 21 has a thickness d A The second gate insulating film 22 was an acrylic polymer film having a thickness of d B A bottom-gate top-contact transistor of Example 9 was obtained using a silicon oxide film having a thickness of 3 nm, and the configuration was the same as that of Example 1 except for the first gate insulating film 21 and the second gate insulating film 22. In forming the acrylic film, the coating amount was changed from the film-forming conditions of Example 8, and the conditions other than the coating amount were the same as those of Example 1, to obtain an acrylic polymer film of Example 9. In forming the silicon oxide film, the film-forming time was changed from the film-forming conditions of Example 1, and the conditions other than the film-forming time were the same as those of Example 1, to obtain a silicon oxide film of Example 9.

[0105] Hydrogen content r in the second gate insulating film 22 in Example 9 H The relative dielectric constant ε B was 4.7, and the dielectric characteristic value K of the gate insulating layer of Example 9 was 0.00089. The channel length of the thin film transistor of Example 9 was 200 μm, and the channel width was 2000 μm.

[0106] [Example 10] The first gate insulating film 21 has a thickness d A The second gate insulating film 22 is an acrylic polymer film having a thickness of d B A bottom-gate top-contact transistor of Example 10 was obtained using a silicon nitride film having a thickness of 4 nm, with the configuration being the same as that of Example 4 except for the first gate insulating film 21 and the second gate insulating film 22. In forming the acrylic film, the coating amount was changed from the film-forming conditions of Example 4, and the conditions other than the coating amount were the same as that of Example 4, to obtain an acrylic polymer film of Example 10. In forming the silicon nitride film, the film-forming time was changed from the film-forming conditions of Example 4, and the conditions other than the film-forming time were the same as that of Example 4, to obtain a silicon nitride film of Example 10.

[0107] Hydrogen content r in the second gate insulating film 22 in Example 10 H The relative dielectric constant ε B was 7.8, and the dielectric characteristic value K of the gate insulating layer of Example 10 was 0.00090. The channel length of the thin film transistor of Example 10 was 200 μm, and the channel width was 2000 μm.

[0108] [Example 11] The first gate insulating film 21 has a thickness d A The second gate insulating film 22 is an acrylic polymer film having a thickness of d B A bottom-gate top-contact transistor of Example 11 was obtained by using a silicon oxide film having a thickness of 7 nm and maintaining the same configuration as Example 1 except for the first gate insulating film 21 and the second gate insulating film 22. In forming the acrylic film, the coating amount was changed from the film-forming conditions of Example 1, and the conditions other than the coating amount were maintained the same as Example 1, to obtain an acrylic polymer film of Example 11. In forming the silicon oxide film, the film-forming time was changed from the film-forming conditions of Example 1, and the conditions other than the film-forming time were maintained the same as Example 1, to obtain a silicon oxide film of Example 11.

[0109] Hydrogen content r in the second gate insulating film 22 in Example 11 H The relative dielectric constant ε B was 4.7, and the dielectric characteristic value K of the gate insulating layer of Example 11 was 0.00869. The channel length of the thin film transistor of Example 11 was 200 μm, and the channel width was 2000 μm.

[0110] [Example 12] The first gate insulating film 21 has a thickness d A The second gate insulating film 22 is an acrylic polymer film having a thickness of d B A bottom-gate top-contact transistor of Example 12 was obtained by using a silicon oxide film having a thickness of 7 nm and maintaining the same configuration as Example 1 except for the first gate insulating film 21 and the second gate insulating film 22. In forming the acrylic film, the coating amount was changed from the film-forming conditions of Example 1, and the conditions other than the coating amount were maintained the same as Example 1, to obtain an acrylic polymer film of Example 12. In forming the silicon oxide film, the film-forming time was changed from the film-forming conditions of Example 1, and the conditions other than the film-forming time were maintained the same as Example 1, to obtain a silicon oxide film of Example 12.

[0111] Hydrogen content r in the second gate insulating film 22 in Example 12 H The relative dielectric constant ε B was 4.7, and the dielectric characteristic value K of the gate insulating layer of Example 12 was 0.01303. The channel length of the thin film transistor of Example 12 was 200 μm, and the channel width was 2000 μm. [Example 13] The first gate insulating film 21 has a thickness d A The second gate insulating film 22 is an acrylic polymer film having a thickness of d BA bottom-gate top-contact transistor of Example 13 was obtained by using a silicon nitride film having a thickness of 4 nm and maintaining the same configuration as Example 4 except for the first gate insulating film 21 and the second gate insulating film 22. In forming the acrylic film, the coating amount was changed from the film-forming conditions of Example 1, and the conditions other than the coating amount were maintained the same as Example 1, to obtain an acrylic polymer film of Example 13. In forming the silicon nitride film, the film-forming time was changed from the film-forming conditions of Example 4, and the conditions other than the film-forming time were maintained the same as Example 4, to obtain a silicon nitride film of Example 13. Hydrogen content r in the second gate insulating film 22 in Example 13 H The relative dielectric constant ε of the second gate insulating film 22 in Example 13 was 14.1 at %. B was 7.8, and the dielectric characteristic value K of the gate insulating layer of Example 13 was 0.00598. The channel length of the thin film transistor of Example 13 was 200 μm, and the channel width was 2000 μm. [Example 14] The first gate insulating film 21 has a thickness d A The second gate insulating film 22 is an acrylic polymer film having a thickness of d B A bottom-gate top-contact transistor of Example 14 was obtained using a silicon nitride film having a thickness of 4 nm, with the configuration being the same as that of Example 4 except for the first gate insulating film 21 and the second gate insulating film 22. In forming the acrylic film, the coating amount was changed from the film-forming conditions of Example 4, and the conditions other than the coating amount were the same as that of Example 4, to obtain an acrylic polymer film of Example 14. In forming the silicon nitride film, the film-forming time was changed from the film-forming conditions of Example 4, and the conditions other than the film-forming time were the same as that of Example 4, to obtain a silicon nitride film of Example 14. Hydrogen content r in the second gate insulating film 22 in Example 14 H The relative dielectric constant ε of the second gate insulating film 22 in Example 14 was 14.1 at %. B was 7.8, and the dielectric characteristic value K of the gate insulating layer of Example 14 was 0.00298. The channel length of the thin film transistor of Example 14 was 200 μm, and the channel width was 2000 μm. [Example 15] The second gate insulating film 22 has a thickness d B A bottom-gate top-contact transistor of Example 15 was obtained using a silicon oxide film having a thickness of 25 nm, with the configuration being the same as that of Example 1 except for the second gate insulating film 22. The silicon oxide film was formed by laminating the silicon oxide film on the upper surface of the acrylic polymer film using a parallel plate plasma CVD method. The film formation conditions for the silicon oxide film using the parallel plate plasma CVD method are shown below. <Conditions for forming silicon oxide film> ·Substrate temperature: 200℃ Reactive gas: Silane / nitrous oxide Reactive gas flow rate: 65sccm (silane), 400sccm (nitrous oxide) Deposition pressure: 200Pa High frequency power: 500W High frequency power frequency: 13.56MHz Hydrogen content r in the second gate insulating film 22 in Example 13 H The relative dielectric constant ε of the second gate insulating film 22 in Example 13 was 12.1 at %. B was 4.7, and the dielectric characteristic value K of the gate insulating layer of Example 15 was 0.01861. The channel length of the thin film transistor of Example 15 was 200 μm, and the channel width was 2000 μm. [Example 16] The second gate insulating film 22 has a thickness d B A bottom-gate top-contact transistor of Example 16 was obtained using a silicon nitride film having a thickness of 25 nm, with the configuration being the same as that of Example 4 except for the second gate insulating film 22. The silicon nitride film was formed on the upper surface of the acrylic polymer film by using a parallel plate plasma CVD method. The conditions for forming the silicon nitride film by the plasma CVD method are shown below. <Conditions for forming silicon nitride film> ·Substrate temperature: 200℃ Reactive gas: silane / ammonia / hydrogen / nitrogen Reaction gas flow rate: 10sccm (silane), 70sccm (ammonia) 2500sccm (hydrogen), 2000sccm (nitrogen) Deposition pressure: 300Pa High frequency power: 500W High frequency power frequency: 13.56MHz Hydrogen content r in the second gate insulating film 22 in Example 16 H The relative dielectric constant ε B was 7.8, and the dielectric characteristic value K of the gate insulating layer of Example 16 was 0.01122. The channel length of the thin film transistor of Example 16 was 200 μm, and the channel width was 2000 μm.

[0112] [Comparative Example 1] 3, the thin film transistor of Comparative Example 1 is a multilayer structure obtained by omitting the second gate insulating film 22 from the bottom-gate bottom-contact type transistor described in FIG. 2. That is, the thin film transistor of Comparative Example 1 includes a source electrode layer 14 and a drain electrode layer 15 on the upper surface of a first gate insulating film 21. The thin film transistor of Comparative Example 1 also includes a semiconductor layer 13 on the upper surface of the source electrode layer 14, the upper surface of the drain electrode layer 15, and the upper surface of the first gate insulating film 21 so as to connect the source electrode layer 14 and the drain electrode layer 15.

[0113] In forming the thin film transistor of Comparative Example 1, similarly to the formation of the thin film transistor of Example 1, a polyimide film was used as the flexible substrate 11, a MoNb film having a thickness of 100 nm was used as the gate electrode layer 12, and an acrylic polymer film having a thickness of 1000 nm was used as the first gate insulating film 21. The film forming conditions for the MoNb film and the acrylic polymer film were the same as those of Example 1.

[0114] In the formation of the thin film transistor of Comparative Example 1, a shadow mask was placed on the upper surface of the first gate insulating film 21, and a MoNb film having a thickness of 100 nm was formed as the source electrode layer 14, and a MoNb film having a thickness of 100 nm was formed as the drain electrode layer 15. The conditions for forming the MoNb film were the same as those for Example 1, that is, the non-heated sputtering method. Next, an InGaZnO film was formed as the semiconductor layer 13 on the upper surface of the first gate insulating film 21 so as to connect the source electrode layer 14 and the drain electrode layer 15. The conditions for forming the InGaZnO film were the same as those for Example 1, that is, the non-heated sputtering method. Then, as in Example 1, annealing was performed at 150°C to obtain the thin film transistor of Comparative Example 1. The channel length of the thin film transistor of Comparative Example 1 was 200 μm, and the channel width was 2000 μm.

[0115] [Comparative Example 2] The second gate insulating film 22 has a thickness d B A bottom-gate top-contact transistor of Comparative Example 2 was obtained by using a silicon oxide film having a thickness of 50 nm and by maintaining the same configuration as in Example 1 except for the second gate insulating film 22. In forming the second gate insulating film 22, the film formation time was changed from the film formation conditions in Example 1, and the conditions other than the film formation time were maintained the same as in Example 1 to obtain the silicon oxide film of Comparative Example 2.

[0116] Hydrogen content r in the second gate insulating film 22 of Comparative Example 2 H The relative dielectric constant ε B was 4.7, and the dielectric characteristic value K of the gate insulating layer of Comparative Example 2 was 0.03723. The channel length of the thin film transistor of Comparative Example 2 was 200 μm, and the channel width was 2000 μm.

[0117] [Comparative Example 3] The second gate insulating film 22 has a thickness d BA bottom-gate top-contact transistor of Comparative Example 3 was obtained by using a silicon nitride film having a thickness of 35 nm and by maintaining the same configuration as in Example 4 except for the second gate insulating film 22. In forming the second gate insulating film 22, the film formation time was changed from the film formation conditions in Example 4, and the conditions other than the film formation time were maintained the same as in Example 4 to obtain the silicon nitride film of Comparative Example 3.

[0118] Hydrogen content r in the second gate insulating film 22 of Comparative Example 3 H The relative dielectric constant ε B was 7.8, and the dielectric characteristic value K of the gate insulating layer of Comparative Example 4 was 0.01571. The channel length of the thin film transistor of Comparative Example 4 was 200 μm, and the channel width was 2000 μm.

[0119] [Comparative Example 4] The second gate insulating film 22 has a thickness d B A bottom-gate top-contact transistor of Comparative Example 4 was obtained by using a silicon oxide film having a thickness of 5 nm and by using the same configuration as in Example 1 except for the second gate insulating film 22. The silicon oxide film was formed by laminating the silicon oxide film on the upper surface of the acrylic polymer film using a parallel plate plasma CVD method. The film formation conditions for the silicon oxide film using the parallel plate plasma CVD method are shown below. <Conditions for forming silicon oxide film> ·Substrate temperature: 200℃ Reactive gas: Silane / nitrous oxide Reactive gas flow rate: 65sccm (silane), 700sccm (nitrous oxide) Deposition pressure: 200Pa High frequency power: 500W High frequency power frequency: 13.56MHz

[0120] Hydrogen content r in the second gate insulating film 22 of Comparative Example 4 H The relative dielectric constant ε Bwas 3.9, and the dielectric characteristic value K of the gate insulating layer of Comparative Example 4 was 0.00449. The channel length of the thin film transistor of Comparative Example 4 was 200 μm, and the channel width was 2000 μm.

[0121] [Comparative Example 5] A bottom-gate top-contact transistor of Comparative Example 5 was obtained by using a silicon nitride film with a thickness of 10 nm as the second gate insulating film 22 and by making the configuration the same as that of Example 4 except for the second gate insulating film 22. The silicon nitride film was formed on the upper surface of the acrylic polymer film by using a parallel plate plasma CVD method. The conditions for forming the silicon nitride film by the plasma CVD method are shown below. <Conditions for forming silicon nitride film> ·Substrate temperature: 200℃ Reactive gas: silane / ammonia / hydrogen / nitrogen Reaction gas flow rate: 10sccm (silane), 70sccm (ammonia) 2000sccm (hydrogen), 2000sccm (nitrogen) Deposition pressure: 300Pa High frequency power: 500W High frequency power frequency: 13.56MHz

[0122] Hydrogen content r in the second gate insulating film 22 of Comparative Example 5 H The relative dielectric constant ε B was 6.8, and the dielectric characteristic value K of the gate insulating layer of Comparative Example 5 was 0.00515. The channel length of the thin film transistor of Comparative Example 5 was 200 μm, and the channel width was 2000 μm.

[0123] [Comparative Example 6] The second gate insulating film 22 has a thickness d BA bottom-gate top-contact transistor of Comparative Example 6 was obtained by using a silicon oxide film having a thickness of 25 nm and by using the same configuration as in Example 1 except for the second gate insulating film 22. The silicon oxide film was formed by laminating the silicon oxide film on the upper surface of the acrylic polymer film using a parallel plate plasma CVD method. The film formation conditions for the silicon oxide film using the parallel plate plasma CVD method are shown below. <Conditions for forming silicon oxide film> ·Substrate temperature: 200℃ Reactive gas: Silane / nitrous oxide Reactive gas flow rate: 65sccm (silane), 800sccm (nitrous oxide) Deposition pressure: 200Pa High frequency power: 500W High frequency power frequency: 13.56MHz

[0124] Hydrogen content r in the second gate insulating film 22 of Comparative Example 6 H The relative dielectric constant ε B was 3.9, and the dielectric characteristic value K of the gate insulating layer of Comparative Example 6 was 0.02244. The channel length of the thin film transistor of Comparative Example 6 was 200 μm, and the channel width was 2000 μm.

[0125] [Comparative Example 7] The second gate insulating film 22 has a thickness d B A bottom-gate top-contact transistor of Comparative Example 7 was obtained by using a silicon oxide film having a thickness of 15 nm and by using the same configuration as in Example 1 except for the second gate insulating film 22. In forming the silicon oxide film, a parallel plate plasma CVD method was used to laminate the silicon oxide film on the upper surface of the acrylic polymer film. The film forming conditions for the silicon oxide film by the parallel plate plasma CVD method are shown below. <Conditions for forming silicon oxide film> ·Substrate temperature: 200℃ Reactive gas: Silane / nitrous oxide Reactive gas flow rate: 65sccm (silane), 300sccm (nitrous oxide) Deposition pressure: 200Pa High frequency power: 500W High frequency power frequency: 13.56MHz

[0126] Hydrogen content r in the second gate insulating film 22 of Comparative Example 7 H The relative dielectric constant ε B was 5.1, and the dielectric characteristic value K of the gate insulating layer of Comparative Example 7 was 0.01029. The channel length of the thin film transistor of Comparative Example 7 was 200 μm, and the channel width was 2000 μm.

[0127] [Comparative Example 8] A bottom-gate top-contact transistor of Comparative Example 8 was obtained by using a silicon nitride film with a thickness of 15 nm as the second gate insulating film 22 and by making the configuration the same as that of Example 4 except for the second gate insulating film 22. The silicon nitride film was formed on the upper surface of the acrylic polymer film by using a parallel plate plasma CVD method. The conditions for forming the silicon nitride film by the plasma CVD method are shown below. <Conditions for forming silicon nitride film> ·Substrate temperature: 200℃ Reactive gas: silane / ammonia / hydrogen / nitrogen Reaction gas flow rate: 10sccm (silane), 70sccm (ammonia) 5000sccm (hydrogen), 2000sccm (nitrogen) Deposition pressure: 300Pa High frequency power: 500W High frequency power frequency: 13.56MHz

[0128] Hydrogen content r in the second gate insulating film 22 of Comparative Example 8 H The relative dielectric constant ε B was 8.1, and the dielectric characteristic value K of the gate insulating layer of Comparative Example 8 was 0.00648. The channel length of the thin film transistor of Comparative Example 8 was 200 μm, and the channel width was 2000 μm.

[0129] [evaluation] The transfer characteristics of the thin film transistors of Examples 1 to 16 and Comparative Examples 1 to 8 were measured using a semiconductor parameter analyzer (B1500A, manufactured by Agilent Technologies, Inc.). From the transfer characteristics, the mobility, the change in threshold voltage ΔVth before and after the load test, and the reduction rate of the mobility before and after the bending test were calculated.

[0130] To measure the threshold voltage and calculate the mobility, first, the voltage of the source electrode layer 14 was set to 0 V, and the source-drain voltage Vds between the source electrode layer 14 and the drain electrode layer 15 was set to 10 V, and the transfer characteristic, which is the relationship between the gate voltage Vgs and the drain current Id, was obtained. The gate voltage Vgs is the voltage between the source electrode layer 14 and the gate electrode layer 12. The drain current Id is the current flowing through the drain electrode layer 15. At this time, the gate voltage Vgs was changed by changing the voltage of the gate electrode layer 12 from -20 V to +20 V. Then, the gate voltage Vgs when the drain current Id was 1 mA was measured as the threshold voltage.

[0131] Next, the transfer characteristic between the gate voltage Vgs and the drain current Id was used to calculate the mutual conductance Gm (A / V), which is the change in the drain current Id relative to the change in the gate voltage Vgs. Then, the relative dielectric constant ε A and thickness d A , the relative dielectric constant ε of the second gate insulating film 22 B and thickness d B The mobility was calculated by applying the channel length, channel width, and source-drain voltage Vds. The relationship between the transconductance Gm and the source-drain voltage Vds is that the transconductance Gm is proportional to the product of the source-drain voltage Vds, the capacitance of the gate insulating layer, and the mobility. The transconductance Gm is expressed by d(Id) / d(Vg).

[0132] In the load test (Negative Bias Temperature Stress: NBTS) used to measure the change in threshold voltage ΔVth, the voltage of the gate electrode layer 12 was set to -20V, the source-drain voltage Vds was set to 0V, the stress temperature was set to 60°C, and the stress application time was set to 1 hour. That is, the source electrode layer 14 and the drain electrode layer 15 of the thin film transistor were set to the same potential, and a potential lower than that of the source electrode layer 14 and the drain electrode layer 15 was applied to the gate electrode layer 12 for a certain period of time. Then, the threshold voltage after the load test was subtracted from the threshold voltage before the load test, and the subtracted value was measured as the change in threshold voltage ΔVth.

[0133] In the bending test used to measure the mobility reduction rate, the flexible substrate 11 was bent and returned to a curvature radius of 1 mm, and the bending of the flexible substrate 11 was repeated 100,000 times. The ratio of the difference between the mobility before and after the bending test to the mobility before the bending test was calculated as the mobility reduction rate.

[0134] FIG. 4 shows the thickness d of the second gate insulating film 22 for Examples 1 to 16 and Comparative Examples 1 to 8. B and hydrogen content r H 4 shows the mobility reduction rate for the second gate insulating film 22 which is a silicon oxide film and the mobility reduction rate is less than 20%. The filled circles in FIG. 4 show the mobility reduction rate for the second gate insulating film 22 which is a silicon oxide film and the mobility reduction rate is 20% or more. The filled squares in FIG. 4 show the mobility reduction rate for the second gate insulating film 22 which is a silicon nitride film and the mobility reduction rate is less than 20%. The filled squares in FIG. 4 show the mobility reduction rate for the second gate insulating film 22 which is a silicon nitride film and the mobility reduction rate is 20% or more. The filled triangles in FIG. 4 show the mobility reduction rate for the second gate insulating film 22 which is a silicon oxynitride film and the mobility reduction rate is 19% or less.

[0135] FIG. 5 shows the thickness d of the second gate insulating film 22 for Examples 1 to 16 and Comparative Examples 1 to 8. Band the dielectric characteristic value K. The open circles in FIG. 5 indicate a level where the second gate insulating film 22 is a silicon oxide film and the mobility reduction rate is less than 20%. The filled circles in FIG. 5 indicate a level where the second gate insulating film 22 is a silicon oxide film and the mobility reduction rate is 20% or more. The open squares in FIG. 5 indicate a level where the second gate insulating film 22 is a silicon nitride film and the mobility reduction rate is less than 20%. The filled squares in FIG. 5 indicate a level where the second gate insulating film 22 is a silicon nitride film and the mobility reduction rate is 20% or more. The open triangles in FIG. 5 indicate a level where the second gate insulating film 22 is a silicon oxynitride film and the mobility reduction rate is 19% or less.

[0136] 6 and 7 show the relative dielectric constant ε of the first gate insulating film 21 for Examples 1 to 16 and Comparative Examples 1 to 8. A and thickness d A , the relative dielectric constant ε of the second gate insulating film 22 B , material, thickness d B , and hydrogen content r H , the dielectric characteristic value K, the mobility, the change in threshold voltage ΔVth, and the rate of decrease in mobility.

[0137] As shown in FIG. 6, the mobility in Examples 1 to 16 was 8.0 cm 2 On the other hand, the mobilities in Comparative Examples 1 and 4 to 8 were 5.1 cm 2 The value was low, below 1 / V.

[0138] The threshold voltage change amount ΔVth in each of Examples 1 to 16 was a small value of not less than −1.9 V and not more than −0.2 V. On the other hand, the threshold voltage change amount ΔVth in each of Comparative Examples 1 and 4 to 8 was a large value of not more than −10.0 V.

[0139] The mobility reduction rates in Examples 1 to 16 were low, at 19% or less, respectively, while the mobility reduction rates in Comparative Examples 1, 4, 5, and 8 were high, at 20% or more, respectively.

[0140] On the other hand, the thin film transistors of Comparative Examples 2 and 3 had a mobility of 11.4 cm 3 , which is similar to that of Examples 1 to 16. 2 / V or more, and the change in threshold voltage ΔVth was small, ranging from −1.1 V to −0.2 V, but cracking or peeling was observed after the bending test.

[0141] First, a comparison between Examples 1 to 16 and Comparative Example 1 confirmed that the presence of the second gate insulating film 22 suppresses the threshold voltage change amount ΔVth. On the other hand, a comparison between Examples 1 to 16 and Comparative Examples 4 to 8 confirmed that the hydrogen content r of the second gate insulating film 22 is important in maintaining high mobility and suppressing the threshold voltage change amount ΔVth. H It was found that there is a suitable range for the amount of

[0142] For example, the change in threshold voltage ΔVth and the reduction rate of mobility and the hydrogen content r H From the relationship, in inorganic silicon compounds containing oxygen, the hydrogen content r H It was found that if the hydrogen content r is 2 at % or more, the threshold voltage change amount ΔVth can be suppressed, and the mobility reduction rate can be suppressed to less than 20%. H It was found that if the hydrogen content r is 15 at % or less, the threshold voltage change ΔVth can be suppressed and high mobility can be obtained. H It was also confirmed that if the value was 14 at % (the intermediate value between Example 15 and Comparative Example 7) or less, the effectiveness of the effects of obtaining a low change amount ΔVth, high mobility, and a low rate of decrease thereof was enhanced.

[0143] For example, the change in threshold voltage ΔVth and the reduction rate of mobility and the hydrogen content r H From the relationship, even in inorganic silicon compounds containing nitrogen, the hydrogen content r HIt was found that if the hydrogen content r is 2 at % or more, the threshold voltage change amount ΔVth can be suppressed, and the mobility reduction rate can be suppressed to less than 20%. H It was found that if the hydrogen content r is 15 at % or less, the threshold voltage change ΔVth can be suppressed and high mobility can be obtained. H It was found that if the value was 18 at % (the intermediate value between Example 4 and Comparative Example 8) or less, the effectiveness of the effects of obtaining a low change amount ΔVth, high mobility, and a low rate of decrease thereof was enhanced.

[0144] Next, the thickness d shown in Examples 1 to 3, 6, and 8 and Comparative Example 2 B From the relationship between the thickness d of the inorganic silicon compound containing oxygen and the rate of decrease in mobility, B It was also found that the thinner the thickness d, the lower the rate of decrease in mobility. B From the relationship between the thickness d of the nitrogen-containing inorganic silicon compound and the mobility reduction rate, B It was found that the thinner the film, the smaller the rate of decrease in mobility.

[0145] From these, it is found from the comparison of each Example with Comparative Examples 4 to 8 that the hydrogen content of the inorganic silicon compound satisfies the condition 1, and from the comparison of each Example with Comparative Examples 1 to 3 that the thickness d B By satisfying condition 2, the 2 It was confirmed that a high mobility of at least 100 / V could be obtained. It was also confirmed that it was possible to suppress a decrease in mobility caused by bending of flexible substrate 11. It was also confirmed that such durability of mobility against bending of flexible substrate 11 could be obtained at a level that satisfied conditions 1 and 2 in a configuration in which dielectric characteristic value K satisfied formula 1.

[0146] In particular, when the second gate insulating film 22 is a silicon oxide film, a comparison between Examples 2 and 3 and Comparative Examples 6 and 7 reveals that the hydrogen content of the silicon oxide film satisfies Condition 3, and a comparison between Examples 1 and 8 and Comparative Examples 1 and 2 reveals that the thickness d BIt was found that the effectiveness of the effect of suppressing the decrease in mobility can be increased by satisfying condition 4. That is, the thickness d B Based on the intermediate value of , it was recognized that the effectiveness of the effect of suppressing the decrease in mobility can be increased by satisfying condition 4.

[0147] In particular, when the second gate insulating film 22 is a silicon nitride film, a comparison between Examples 4 and 5 and Comparative Examples 5 and 8 reveals that the hydrogen content of the silicon nitride film satisfies Condition 5, and a comparison between Examples 5 and 10 and Comparative Examples 1 and 3 reveals that the thickness d B It was found that by satisfying condition 6, the feasibility of suppressing the decrease in mobility can be improved. B Based on the intermediate value of , it was recognized that the feasibility of suppressing the decrease in mobility can be improved by satisfying condition 6.

[0148] Furthermore, it was confirmed that the configurations including the second gate insulating film 22 of Examples 2, 3, and 8 could obtain higher mobility than those of Examples 1, 7, and 9. Therefore, when the hydrogen content of the silicon oxide film is 6 at % or more and 10 at % or less, and the thickness d of the silicon oxide film is B If the thickness is 5 nm or more and 25 nm or less, it is possible to increase the mobility.

[0149] Moreover, it was found that the configurations including the second gate insulating film 22 of Examples 2 and 3 could obtain higher mobility than those of Examples 1, 7 to 9, and could obtain a low mobility reduction rate of 8% or less. Therefore, when the hydrogen content of the silicon oxide film is 6 at % or more and 10 at % or less, and the thickness d B In the case where the thickness is 5 nm or more and 20 nm or less, a higher mobility can be obtained after the bending test.

[0150] In addition, when Examples 9 and 10 are compared with Examples 11 to 14, the thickness d AIt was also found that a low change ΔVth, high mobility, and a low rate of decrease in mobility were obtained regardless of whether the thickness d of the first gate insulating film 21 was 300 nm or 2500 nm. A It was found that the thinner the thickness d of the first gate insulating film 21, the lower the change amount ΔVth, the higher the mobility, and the lower the rate of decrease in mobility. A is preferably 1000 nm or less, more preferably 600 nm or less, and even more preferably 400 nm or less.

[0151] According to the above embodiment, the following effects can be obtained. (1) If the configuration satisfies the above conditions 1 to 6, it is possible to reduce the amount of change in threshold voltage and increase the mobility of semiconductor layer 13, while also suppressing the change in mobility due to bending of flexible substrate 11. (2) When the dielectric characteristic value K is 0.001 or more and smaller than 0.015, it is possible to obtain an effect similar to that of (1) above with high mobility. [Explanation of symbols]

[0152] C: Channel region L: Channel length 11...Flexible substrate 11S…Support surface 11S1…Part 1 11S2…Second part 12...Gate electrode layer 13...Semiconductor layer 14...Source electrode layer 15...Drain electrode layer 21...First gate insulating film 22...Second gate insulating film

Claims

1. a flexible substrate having a support surface; a gate electrode layer located on a first portion of the support surface; a gate insulating layer covering a second portion of the support surface and the gate electrode layer; the gate electrode layer and the semiconductor layer sandwiching the gate insulating layer; a source electrode layer in contact with a first end of the semiconductor layer; a drain electrode layer in contact with a second end of the semiconductor layer; The thickness of the semiconductor layer is 10 nm or more and 50 nm or less, The electrical resistivity of the semiconductor layer is 1.0×10 −1 Ω·cm or more and 1.0×10 4 Ω·cm or less, The gate insulating layer is a first gate insulating film made of an organic polymer compound and covering the second portion and the gate electrode layer; a second gate insulating film made of an inorganic silicon compound and sandwiched between the first gate insulating film and the semiconductor layer; The second gate insulating film has a thickness of 2 nm to 30 nm, The hydrogen content of the second gate insulating film is 2 at % or more and 15 at % or less. Thin film transistor.

2. a flexible substrate having a support surface; a gate electrode layer located on a first portion of the support surface; a gate insulating layer covering a second portion of the support surface and the gate electrode layer; the gate electrode layer and the semiconductor layer sandwiching the gate insulating layer; a source electrode layer in contact with a first end of the semiconductor layer; a drain electrode layer in contact with a second end of the semiconductor layer; The thickness of the semiconductor layer is 10 nm or more and 50 nm or less, The electrical resistivity of the semiconductor layer is 1.0×10 −1 Ω·cm or more and 1.0×10 4 Ω·cm or less, The gate insulating layer is a first gate insulating film made of an organic polymer compound and covering the second portion and the gate electrode layer; a second gate insulating film made of silicon oxide and sandwiched between the first gate insulating film and the semiconductor layer; The second gate insulating film has a thickness of 2 nm to 40 nm, The hydrogen content of the second gate insulating film is 2 at % or more and 14 at % or less. Thin film transistor.

3. a flexible substrate having a support surface; a gate electrode layer located on a first portion of the support surface; a gate insulating layer covering a second portion of the support surface and the gate electrode layer; the gate electrode layer and the semiconductor layer sandwiching the gate insulating layer; a source electrode layer in contact with a first end of the semiconductor layer; a drain electrode layer in contact with a second end of the semiconductor layer; The thickness of the semiconductor layer is 10 nm or more and 50 nm or less, The electrical resistivity of the semiconductor layer is 1.0×10 −1 Ω·cm or more and 1.0×10 4 Ω·cm or less, The gate insulating layer is a first gate insulating film made of an organic polymer compound and covering the second portion and the gate electrode layer; a second gate insulating film made of silicon nitride and sandwiched between the first gate insulating film and the semiconductor layer; The second gate insulating film has a thickness of 2 nm to 30 nm, The hydrogen content of the second gate insulating film is 5 at % or more and 18 at % or less. Thin film transistor.

4. The second gate insulating film has a thickness of 5 nm or more and 25 nm or less, The hydrogen content of the second gate insulating film is 6 at % or more and 10 at % or less. The thin film transistor of claim 2 .

5. The first gate insulating film has a relative dielectric constant ε Ａ and thickness d Ａ and The second gate insulating film has a relative dielectric constant ε Ｂ and thickness d Ｂ and The gate insulating layer satisfies the following formula (1): 0.001 ≤ (ε Ａ / d Ａ ) / (ε Ｂ / d Ｂ ) < 0.015... Equation (1) The thin film transistor according to claim 1 .

6. the first gate insulating film has a relative dielectric constant lower than the relative dielectric constant of the second gate insulating film; The thickness of the first gate insulating film is 300 nm or more and 2500 nm or less. The thin film transistor according to claim 1 .

7. The semiconductor layer is an oxide semiconductor layer containing indium. The thin film transistor according to claim 1 .

8. forming a gate electrode layer on a first portion of the support surface of a flexible substrate; forming a gate insulating layer overlying a second portion of the support surface and the gate electrode layer; forming the semiconductor layer by a non-thermal sputtering method so that the gate insulating layer is sandwiched between the gate electrode layer and the semiconductor layer; and forming a source electrode layer in contact with a first end of the semiconductor layer and a drain electrode layer in contact with a second end of the semiconductor layer; forming the gate insulating layer forming a first gate insulating film made of an organic polymer compound that covers the second portion and the gate electrode layer by a coating method, and forming a second gate insulating film made of an inorganic silicon compound that is sandwiched between the first gate insulating film and the semiconductor layer by a plasma CVD method, The second gate insulating film has a thickness of 2 nm to 30 nm, The hydrogen content of the second gate insulating film is 2 at % or more and 15 at % or less. A method for manufacturing a thin film transistor.

9. forming a gate electrode layer on a first portion of the support surface of a flexible substrate; forming a gate insulating layer overlying a second portion of the support surface and the gate electrode layer; forming the semiconductor layer by a non-thermal sputtering method so that the gate insulating layer is sandwiched between the gate electrode layer and the semiconductor layer; and forming a source electrode layer in contact with a first end of the semiconductor layer and a drain electrode layer in contact with a second end of the semiconductor layer; forming the gate insulating layer forming a first gate insulating film made of an organic polymer compound that covers the second portion and the gate electrode layer by a coating method, and forming a second gate insulating film made of silicon oxide that is sandwiched between the first gate insulating film and the semiconductor layer by a plasma CVD method, The second gate insulating film has a thickness of 2 nm to 40 nm, The hydrogen content of the second gate insulating film is 2 at % or more and 14 at % or less. A method for manufacturing a thin film transistor.

10. forming a gate electrode layer on a first portion of the support surface of a flexible substrate; forming a gate insulating layer overlying a second portion of the support surface and the gate electrode layer; forming the semiconductor layer by a non-thermal sputtering method so that the gate insulating layer is sandwiched between the gate electrode layer and the semiconductor layer; and forming a source electrode layer in contact with a first end of the semiconductor layer and a drain electrode layer in contact with a second end of the semiconductor layer; forming the gate insulating layer forming a first gate insulating film made of an organic polymer compound that covers the second portion and the gate electrode layer by a coating method, and forming a second gate insulating film made of silicon nitride that is sandwiched between the first gate insulating film and the semiconductor layer by a plasma CVD method, The second gate insulating film has a thickness of 2 nm to 30 nm, The hydrogen content of the second gate insulating film is 5 at % or more and 18 at % or less. A method for manufacturing a thin film transistor.

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