Field-effect transistor

Abstract

A field effect transistor according to the present invention is provided with an etching stop structure (113) and an etching stop structure (114). The etching stop structure (113) is formed on a first side surface (106a), of a recessed region (111), serving as a boundary between the recessed region (111) and a cap layer (106) on a source electrode (107) side. The etching stop structure (114) is formed on a second side surface (106b), of the recessed region (111), serving as a boundary between the recessed region (111) and the cap layer (106) on a drain electrode (108) side.

Description

[Technical field]

[0001] The present invention relates to a field effect transistor. To Regarding. [Background technology]

[0002] In recent years, terahertz electronic devices and integrated circuits capable of handling the 0.3-3.0 THz terahertz frequency band have been attracting attention as elemental technologies for next-generation high-speed wireless communication, non-destructive internal inspection using 3D imaging, and component analysis using electromagnetic wave absorption. Generally, field-effect transistors made of compound semiconductors, which have particularly high physical properties and electron mobility, are used as electronic devices with good high-frequency characteristics.

[0003] A field effect transistor includes a semiconductor substrate, a gate electrode formed on the surface of the semiconductor substrate, and a source electrode and a drain electrode formed on both sides of the gate electrode. In particular, a high electron mobility transistor (HEMT), which has excellent high frequency characteristics, has a structure in which a buffer layer, a channel layer, a barrier layer, a stopper layer, and a cap layer are stacked on a semiconductor substrate. In addition, a carrier supply layer is formed on the barrier layer side of the channel layer, or on the buffer layer side of the channel layer. In such a structure, the position and doping amount of the carrier supply layer are designed according to the energy band design.

[0004] When a potential is applied to the gate electrode, carriers are supplied from the carrier supply layer to the channel layer according to the strength of the applied potential, modulating the concentration of the two-dimensional electron gas, and electrons move through the conduction channel formed between the source and drain electrodes. In the HEMT structure, the channel layer through which the carriers travel and the electron supply layer are spatially separated to suppress scattering by impurities. This configuration can improve electron mobility, thereby making it possible to achieve terahertz operation.

[0005] To apply HEMTs to terahertz integrated circuits, it is necessary not only to improve the high-frequency characteristics, but also to improve the uniformity of the device structure and make the integrated circuits operate according to the circuit design with a good yield.

[0006] For example, in Non-Patent Document 1, a resist pattern for forming a gate electrode is formed, then the gate insulating film is etched using this resist pattern as a mask to form an opening, the resist is removed, and the formed opening is used as a mask to perform recess etching of the cap layer. After this, the stopper layer, or the stopper layer and the barrier layer are etched in the depth direction by dry etching using Ar gas, after which a gate electrode is formed, and a field effect transistor structure with a reduced gate-channel distance is formed, thereby producing a HEMT.

[0007] In [Patent Document 1], an extra recess opening is formed on the drain side of the gate insulating film so that the drain side recess region is wider than the source side recess region, and an etching solution for forming the recess is infiltrated from both the gate opening and the recess opening to form an asymmetric recess structure. By depleting carriers over a wide region on the drain electrode side, the drain conductance is reduced, and high frequency characteristics are improved. [Prior art documents] [Patent documents]

[0008] [Patent Document 1] Patent No. 3715557 [Non-patent literature]

[0009] [Non-Patent Document 1] T. Suemitsu et al., "Improved Recessed-Gate Structure for Sub-0.1-μm-Gate InP-Based High Electron Mobility Transistors", Japanese Journal of Applied Physics, vol. 37, no. 1363-1372, 1998. Summary of the Invention [Problem to be solved by the invention]

[0010] However, the above-mentioned technology has a problem that it is difficult to control the amount of etching because wet etching is used to form the recess region. For example, in the technology described in Patent Document 1, an opening for forming an asymmetric recess and an opening for forming a gate insulating film are simultaneously formed, and wet etching is performed for a predetermined number of seconds to form a larger recess region on the drain side.

[0011] However, the etching rate during wet etching is sensitive to the concentration and composition of the etching solution, as well as the temperature, stirring conditions, and convection of the solution. The etching rate also varies greatly depending on the crystal quality and surface condition of the cap layer to be etched away. This causes variation in the amount of recess etching, and ultimately causes considerable variation in the high-frequency characteristics. Normally, this leads to a decrease in yield in integrated circuits that integrate at least tens to hundreds of HEMTs, creating a barrier to terahertz applications.

[0012] The present invention has been made to solve the above problems, and an object of the present invention is to enable the fabrication of a field effect transistor by accurately controlling the amount of etching for forming a recess. [Means for solving the problem]

[0013] The field effect transistor of the present invention comprises a buffer layer, a channel layer, a barrier layer, a carrier supply layer and a cap layer formed on a semiconductor substrate; a source electrode and a drain electrode formed on the cap layer and spaced apart from each other; an insulating layer formed on the cap layer between the source electrode and the drain electrode and having an opening; a recess region formed in the cap layer between the source electrode and the drain electrode; a gate electrode disposed between the source electrode and the drain electrode and formed on the insulating layer, with a portion of the gate electrode fitting into the recess region through the opening; and an etch stop structure formed on at least one of a first side of the recess region which is a boundary between the cap layer on the source electrode side and the recess region and a second side of the recess region which is a boundary between the cap layer on the drain electrode side and the recess region.

[0014] A method for manufacturing a field effect transistor according to the present invention includes a first step of forming a buffer layer, a channel layer, a barrier layer, a carrier supply layer, and a cap layer on a semiconductor substrate; a second step of forming a source electrode and a drain electrode spaced apart from each other on the cap layer; a third step of forming a groove extending in the gate width direction in the cap layer at least one of a boundary on the source electrode side of a region to be a recess region and a boundary on the drain electrode side of a region to be a recess region; and forming an etching stop structure on at least one of a first side surface of the recess region which is a boundary between the cap layer on the source electrode side of the groove and the recess region, and a second side surface of the recess region which is a boundary between the cap layer on the drain electrode side of the groove and the recess region. a fourth step of forming an insulating layer between the source electrode and the drain electrode on the cap layer in which the grooves are formed; a sixth step of forming an opening in the insulating layer; a seventh step of etching a part of the cap layer from the opening in a plan view toward the source electrode and the drain electrode to an etch stop structure by an etching process using the insulating layer having the opening as a mask, thereby forming a recess region in the cap layer below the opening; and an eighth step of depositing a gate electrode material from above the insulating layer to form a gate electrode that is disposed on the insulating layer, a part of which fits into the recess region through the opening, the gate electrode having a main portion made of the gate electrode material, and a protruding portion disposed between the main portion and the barrier layer. Effect of the Invention

[0015] As described above, according to the present invention, since an etching stop structure is provided, it becomes possible to manufacture a field effect transistor by accurately controlling the amount of etching for forming a recess. According to the present invention, the amount of recess etching can be accurately controlled. [Brief description of the drawings]

[0016] [Figure 1] FIG. 1 is a cross-sectional view showing a configuration of a field effect transistor according to an embodiment of the present invention. [Diagram 2] FIG. 2 is a cross-sectional view showing the configuration of another field effect transistor according to an embodiment of the present invention. [Diagram 3] FIG. 3 is a cross-sectional view showing the configuration of another field effect transistor according to an embodiment of the present invention. [Figure 4] FIG. 4 is a cross-sectional view showing the configuration of another field effect transistor according to an embodiment of the present invention. [Diagram 5] FIG. 5 is a cross-sectional view showing the configuration of another field effect transistor according to an embodiment of the present invention. [Figure 6A] FIG. 6A is a cross-sectional view showing a state of a field-effect transistor in the middle of a process, illustrating a method for manufacturing a field-effect transistor according to an embodiment of the present invention. [Figure 6B] FIG. 6B is a cross-sectional view showing a state of the field-effect transistor in the middle of a process, illustrating a method for manufacturing the field-effect transistor according to the embodiment of the present invention. [Figure 6C] FIG. 6C is a cross-sectional view showing a state of the field-effect transistor in the middle of a process, for illustrating a method for manufacturing the field-effect transistor according to the embodiment of the present invention. [Figure 6D] FIG. 6D is a cross-sectional view showing a state of the field-effect transistor in the middle of a process, illustrating a method for manufacturing the field-effect transistor according to the embodiment of the present invention. [Figure 6E]FIG. 6E is a cross-sectional view showing a state of the field-effect transistor in the middle of a process, illustrating a method for manufacturing the field-effect transistor according to the embodiment of the present invention. [Figure 6F] FIG. 6F is a cross-sectional view showing a state of the field effect transistor in the middle of a process, for illustrating a method for manufacturing the field effect transistor according to the embodiment of the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0017] Hereinafter, a field effect transistor according to an embodiment of the present invention will be described with reference to FIG.

[0018] This field effect transistor first includes a buffer layer 102, a channel layer 103, a barrier layer 104, a carrier supply layer 105, and a cap layer 106 formed on a semiconductor substrate 101. An etching stop layer 121 may also be formed between the carrier supply layer 105 and the cap layer 106. The etching stop layer 121 can be made of a material having high etching selectivity with respect to an etching solution used to etch the cap layer 106 to form the recess region 111.

[0019] For example, the semiconductor substrate 101 may be made of semi-insulating InP. The buffer layer 102 may be made of InAlAs and have a thickness of 100 to 300 nm. The channel layer 103 may be made of InGaAs and have a thickness of 5 to 20 nm. The barrier layer 104 may be made of InAlAs and have a thickness of 5 to 20 nm. The cap layer 106 may be made of, for example, 1×10 Si. 19 ~2×10 19 cm -3 The carrier supply layer 105 can be made of InGaAs doped with 1×10 ions of Si as an impurity in the barrier layer 104 by well-known sheet doping. 19 cm -3 It may be a doped layer.

[0020] The etching stop layer 121 may be made of InP and have a thickness of 2 to 5 nm. The channel layer 103 made of InGaAs can be etched by using an etching solution such as citric acid. On the other hand, the etching stop layer 121 made of InP is hardly etched by a citric acid-based etching solution, and therefore can be used as an etching stop layer.

[0021] This field effect transistor also includes a source electrode 107 and a drain electrode 108 formed and spaced apart from each other on the cap layer 106. The source electrode 107 and the drain electrode 108 are formed to sandwich a region that will be a recess region 111. The source electrode 107 and the drain electrode 108 can be formed of a laminated structure of metals such as Ti, Pt, Au, and Ni.

[0022] The field effect transistor also includes an insulating layer 109 formed on the cap layer 106 between the source electrode 107 and the drain electrode 108. The insulating layer 109 has an opening 110. In this example, the insulating layer 109 is formed over the source electrode 107 and the drain electrode 108. The insulating layer 109 is made of SiO 2 , SiN, Al 2 O 3 , HfO 2 The insulating material may be used.

[0023] The field effect transistor also includes a recess region 111 and a gate electrode 112. The recess region 111 is formed in the cap layer 106 between the source electrode 107 and the drain electrode 108. The recess region 111 can be referred to as a concave portion, a groove, or a through hole with a relatively large diameter formed in the cap layer 106. The gate electrode 112 is disposed between the source electrode 107 and the drain electrode 108, and is formed on the insulating layer 109, with a portion of the gate electrode 112 being embedded in the recess region 111 through an opening 110. The gate electrode 112 is formed from the opening 110 in the depth direction to the etching stop layer 121. The gate electrode 112 can be formed mainly from a composite structure of Ti, Pt, Au, and Mo. The gate electrode 112 can be a T-type, Y-type, or Γ-type, with the upper portion being wider than the lower portion in a plan view, in order to achieve a short gate length while minimizing the gate resistance.

[0024] This field effect transistor also includes an etch stop structure 113 and an etch stop structure 114. The etch stop structure 113 is formed on a first side surface 106a of the recess region 111, which is a boundary between the cap layer 106 on the source electrode 107 side and the recess region 111. The etch stop structure 114 is formed on a second side surface 106b of the recess region 111, which is a boundary between the cap layer 106 on the drain electrode 108 side and the recess region 111.

[0025] The etch stop structures 113 and 114 may be made of a material that has high etch selectivity with respect to the etchant used to etch the cap layer 106 to form the recessed region 111. The etch stop structures 113 and 114 may be made of, for example, SiO 2 , SiN, Al 2 O 3 , HfO 2 In this example, the etch stop structure 113 and the etch stop structure 114 are formed from a part of the insulating layer 109 extending from above the cap layer 106 to the first side surface 106a and the second side surface 106b.

[0026] By providing the etch stop structure 113 and the etch stop structure 114, it becomes possible to accurately control the amount of etching of the cap layer 106 in the direction of the source electrode 107 and the drain electrode 108 to form the recess region 111. Furthermore, according to the embodiment, since the etch stop layer 121 is also used, it is possible to accurately control the amount of etching of the cap layer 106 in the thickness direction to form the recess region 111.

[0027] 2, the etching stop structures 113a and 114a can be formed so as to extend partway through the cap layer 106 in the thickness direction without penetrating the cap layer 106. Even in this configuration, the etching stop structures 113 and 114 limit (suppress) the infiltration speed of the etching solution in the direction of the source electrode 107 and the drain electrode 108, and the amount of etching in the direction of the source electrode 107 and the drain electrode 108 can be controlled.

[0028] 3, the etching stop structure 113 can be formed only on the first side surface 106a which is the boundary between the cap layer 106 on the source electrode 107 side and the recess region 111. With this configuration, in the etching process for forming the recess region, the etching of the recess region 111 is stopped at a certain distance on the source electrode side, and more recess etching regions are formed on the drain electrode side, so that the recess regions on the source electrode side and the drain electrode side are formed asymmetrically. Similarly, the etching stop structure (not shown) can be formed only on the second side surface 106b which is the boundary between the cap layer 106 on the drain electrode 108 side and the recess region 111.

[0029] 4, the distance between the opening 110 (gate electrode 112) and the second side surface 106b (etching stop structure 113b) can be made larger than the distance between the opening 110 (gate electrode 112) and the first side surface 106a (etching stop structure 114b). By doing so, it is possible to realize a field effect transistor having excellent high frequency characteristics by reducing the drain conductance as an asymmetric recess structure.

[0030] 5, the etching stop structure 114c may be formed so as to penetrate into the lower layer of the cap layer 106 in the thickness direction. For example, the etching stop structure 114c may be formed to a depth halfway through the etching stop layer 121 or the barrier layer 104. With this configuration, the portion of the recess region 111 on the drain electrode side is formed to a depth of the barrier layer 104, whereby carrier depletion in the drain region reduces the drain conductance and improves the high frequency characteristics. The etching stop structure on the source electrode side may also be formed so as to penetrate into the lower layer of the cap layer 106 in the thickness direction.

[0031] Next, a field effect transistor according to an embodiment of the present invention and a method for manufacturing the same will be described with reference to FIGS. 6A to 6F.

[0032] 6A, a buffer layer 102, a channel layer 103, a barrier layer 104, a carrier supply layer 105, and a cap layer 106 are formed on a semiconductor substrate 101 (first step). In this example, the first step is performed in a state where the buffer layer 102, the channel layer 103, the barrier layer 104, the carrier supply layer 105, the etching stop layer 121, and the cap layer 106 are formed on the semiconductor substrate 101.

[0033] For example, a buffer layer 102 made of InAlAs and having a thickness of 100 to 300 nm, a channel layer 103 made of InGaAs and having a thickness of 5 to 20 nm, a barrier layer 104 made of InAlAs and having a thickness of 5 to 20 nm, and a 1×10 19 ~2×1019 cm -3 The cap layer 106 made of InGaAs doped with 1×10 ions is then stacked by crystal growth using metal organic chemical vapor deposition, molecular beam epitaxy, or the like. The barrier layer 104 is doped with 1×10 ions of Si as an impurity using the well-known sheet doping method. 19 cm -3 A doped carrier supply layer 105 is formed. In addition, an etching stop layer 121 made of InP and having a thickness of 2 to 5 nm is formed between the carrier supply layer 105 and the cap layer .

[0034] 6B, the source electrode 107 and the drain electrode 108 are formed on the cap layer 106, spaced apart from each other (second step). For example, Ti / Pt / Au is deposited on the cap layer 106 to form a metal film, and the metal film is patterned by known photolithography and etching techniques to form the source electrode 107 and the drain electrode 108. It is also possible to form the source electrode 107 and the drain electrode 108 by a known lift-off method. The source electrode 107 and the drain electrode 108 are ohmic-contacted to the cap layer 106.

[0035] Next, as shown in FIG. 6C, grooves 201, 202 extending in the gate width direction are formed in the cap layer 106 at least one of the boundary of the region to be the recess region 111 on the source electrode 107 side and the boundary of the region to be the recess region 111 on the drain electrode 108 side (third step).

[0036] First, a mask layer having openings in the areas of the grooves 201 and 202 is formed by a known electron beam lithography technique or a known photolithography technique. The mask layer can be made of a resist or an insulating material. Next, the cap layer 106 is selectively etched using the mask layer as a mask to form the grooves 201 and 202. For example, the grooves 201 and 202 can be formed by using an etching solution containing citric acid, phosphoric acid, or the like. Alternatively, the grooves 201 and 202 can be formed by dry etching using Cl, HI, HBr, or the like.

[0037] After the above-mentioned etching process, the mask layer is removed, and then a layer of material for forming an etching stop structure is formed inside the grooves 201 and 202 to form the etching stop structures 113 and 114 (fourth step). This layer can be formed by, for example, a well-known conformal method. The above-mentioned material can be SiO 2 In addition, AlN, which can be formed by deposition using atomic layer deposition (ALD) method, etc. 2 O 3 and HfO 2 The insulating layer may be formed of an insulating material such as

[0038] Next, an insulating layer 109 is formed between the source electrode 107 and the drain electrode 108 on the cap layer 106 in which the grooves 201 and 202 are formed (fifth step). Here, the insulating layer 109 is formed so as to cover the source electrode 107 and the drain electrode 108. For example, the insulating layer 109 is formed by a well-known plasma CVD method, etc., using SiO 2 and SiN x The insulating layer 109 can be formed by depositing an insulating material such as

[0039] Furthermore, as shown in FIG. 6D, an insulating layer 109 is formed on the cap layer 106 in which the grooves 201 and 202 are formed, and the insulating layer 109 is allowed to penetrate into the recess regions 111 in the grooves 201 and 202, thereby forming an etching stop structure 113 and an etching stop structure 114 (fourth step and fifth step).

[0040] 6E, an opening 110 is formed in the insulating layer 109 (sixth step). For example, the opening 110 can be formed by known electron beam lithography, photolithography, and etching techniques.

[0041] Next, as shown in FIG. 6F, a recess region 111 is formed in the cap layer 106 under the opening 110 (seventh step). The recess region 111 can be formed by etching a part of the cap layer 106 from the opening 110 toward the source electrode 107 and toward the drain electrode 108 in a plan view, up to the etching stop structure, by an etching process using the insulating layer 109 having the opening 110 as a mask. In this step, the recess region 111 is also formed by etching in the thickness direction up to the etching stop layer 121.

[0042] Thereafter, the gate electrode 112 is formed (eighth step), thereby obtaining the field effect transistor shown in Fig. 1. For example, by depositing a gate electrode material from above the insulating layer 109, it is possible to form the gate electrode 112 that is disposed on the insulating layer 109, a part of which fits into the recess region 111 through the opening 110, and has a main portion made of the gate electrode material and a protruding portion disposed between the main portion and the barrier layer 104. The gate electrode material can be deposited by, for example, a vacuum deposition method or a sputtering method.

[0043] As described above, according to the present invention, since an etching stop structure is provided, it is possible to accurately control the amount of etching for forming a recess and fabricate a field effect transistor. According to the present invention, it is possible to accurately control the amount of recess etching. Furthermore, by adopting a structure in which the position of the etching stop structure on the source side is farther away from the gate electrode than the etching stop structure on the drain side, it is possible to realize a field effect transistor with excellent high frequency characteristics by reducing the drain conductance as an asymmetric recess structure. With these simple means and structures, it is possible to fabricate a field effect transistor with excellent high frequency characteristics with good controllability.

[0044] It should be noted that the present invention is not limited to the above-described embodiments, and it is apparent that many modifications and combinations can be made by a person having ordinary knowledge in the art within the technical concept of the present invention. [Explanation of symbols]

[0045] 101...semiconductor substrate, 102...buffer layer, 103...channel layer, 104...barrier layer, 105...carrier supply layer, 106a...first side, 106b...second side, 107...source electrode, 108...drain electrode, 109...insulating layer, 110...opening, 111...recess region, 112...gate electrode, 113...etching stop structure, 114...etching stop structure, 121...etching stop layer.

Claims

1. A buffer layer, a channel layer, a barrier layer, a carrier supply layer, and a cap layer formed on a semiconductor substrate; a source electrode and a drain electrode formed on the cap layer and spaced apart from each other; an insulating layer having an opening formed on the cap layer between the source electrode and the drain electrode; a recess region formed in the cap layer between the source electrode and the drain electrode; a gate electrode disposed between the source electrode and the drain electrode, the gate electrode being formed on the insulating layer, the gate electrode having a portion that fits into the recess region through the opening; an etch stop structure formed on at least one of a first side of the recess region that is a boundary between the cap layer and the recess region on the source electrode side and a second side of the recess region that is a boundary between the cap layer and the recess region on the drain electrode side; Equipped with The etch stop structure is formed so as to extend into a layer below the cap layer in a thickness direction.

2. 2. The field effect transistor according to claim 1, A field effect transistor, wherein a distance between the opening and the second side surface is greater than a distance between the opening and the first side surface.

3. 3. The field effect transistor according to claim 1, a carrier supply layer and a cap layer, the carrier supply layer and the cap layer being disposed adjacent to each other;

Images