Electronic device and memory device

Abstract

To provide a technique for end-to-end DBI that enables power saving in a stacked memory device.SOLUTION: In a memory device 10, a data bus inversion (DBI) technique is used and utilized in various parallel input / output (IO) circuits in order to limit the number of simultaneous lane-switching and reduce electric power and simultaneous switching operation (SSO) noise. In a stacked memory device such as a high bandwidth memory (HBM) device, DBI is extended to a memory core, for significant reduction in one or more of power consumption, voltage droop and SSO noise. A memory core, a plurality of through silicon vias (TSV), and a data bus inversion logic connected between the memory core and the TSV may be included. The data bus inversion logic encodes and decodes a data signal on a signal path through the TSV according to data bus inversion of the data signal.SELECTED DRAWING: Figure 1

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