Method for manufacturing vertical semiconductor device

Abstract

To provide a vertical semiconductor device in which defects of contact plugs may be reduced.SOLUTION: The vertical semiconductor device of the present invention includes: a substrate; a stacked structure which includes insulation patterns and conductive patterns stacked repeatedly on each other on the substrate; an insulating interlayer which covers the stacked structure; a buffer pattern on the insulating interlayer; and a first contact plug which passes through the buffer pattern and the insulating interlayer and contacts at least part of pad patterns. The conductive patterns extend in a first direction parallel to an upper surface of the substrate, and edges of the conductive patterns have a staircase shape. The conductive patterns include the pad patterns defined by exposed portions of upper surfaces of the conductive patterns at the edges.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to a vertical semiconductor device, and more particularly to a vertical NAND flash memory device. [Background technology]

[0002] Recently, a vertical memory device has been developed in which memory cells are stacked vertically from a surface of a substrate. The edge of the stacked conductive line included in each memory cell has a step shape, and the upper surface of the edge is provided to a pad pattern. Contact plugs are formed on the pad patterns. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2019-96880 A Summary of the Invention [Problem to be solved by the invention]

[0004] The present invention has been made in consideration of the above-mentioned conventional techniques, and an object of the present invention is to provide a vertical semiconductor device which reduces defects in contact plugs. [Means for solving the problem]

[0005] In order to achieve the above-mentioned object, according to one aspect of the present invention, a vertical semiconductor device includes a substrate, a stacked structure in which insulating patterns and conductive patterns are repeatedly stacked on the substrate, an interlayer insulating film covering the stacked structure, a buffer pattern on the interlayer insulating film, and a first contact plug penetrating the buffer pattern and the interlayer insulating film and contacting at least a portion of a pad pattern, wherein the conductive pattern extends in a first direction parallel to an upper surface of the substrate, has a stepped edge, and includes the pad pattern defined by an exposed portion of the upper surface of the conductive pattern at the edge.

[0006] According to another aspect of the present invention, a vertical semiconductor device is provided, comprising: a substrate; a stacked structure in which insulating patterns and conductive patterns are repeatedly stacked on the substrate; a channel structure extending in the vertical direction through the stacked structure; an interlayer insulating film covering the stacked structure; a buffer pattern arranged to face at least a portion of a pad pattern on the interlayer insulating film; a first contact plug penetrating the buffer pattern and the interlayer insulating film to contact at least a portion of the pad pattern; a second contact plug penetrating only the interlayer insulating film to contact at least a portion of the pad pattern; and an upper wiring electrically connected to the first contact plug and the second contact plug, respectively, wherein the conductive pattern extends in a first direction parallel to an upper surface of the substrate, has an edge having a stepped shape, and includes the pad pattern defined by an exposed portion of an upper surface of the conductive pattern at the edge.

[0007] According to yet another aspect of the present invention, which has been made to achieve the above object, a vertical semiconductor device includes a substrate, a stacked structure in which insulating patterns and conductive patterns are repeatedly stacked on the substrate, an interlayer insulating film covering the stacked structure, a buffer pattern on the interlayer insulating film, the buffer pattern including a material having an etching selectivity with respect to the interlayer insulating film, and contact plugs penetrating the interlayer insulating film and contacting upper surfaces of each pad pattern, wherein the conductive pattern extends in a first direction parallel to an upper surface of the substrate, has a stepped edge, and includes the pad pattern defined by an exposed portion of the upper surface of the conductive pattern at the edge, and at least a portion of the contact plug penetrates the buffer pattern. Effect of the Invention

[0008] In accordance with the vertical semiconductor device of the present invention, a buffer pattern is provided on a pad structure, and at least a portion of the contact plugs pass through the buffer pattern, thereby reducing not-open and punching defects of the contact plugs. [Brief description of the drawings]

[0009] [Figure 1] 1 is a cross-sectional view illustrating a vertical semiconductor device according to an embodiment. [Diagram 2] 1 is a perspective view showing a portion of a pad structure of a vertical semiconductor device; [Diagram 3] 1 is a plan view showing a portion of a pad structure of a vertical semiconductor device; [Figure 4] 1A to 1C are cross-sectional views illustrating a method for manufacturing a vertical semiconductor device according to an embodiment. [Diagram 5] 1A to 1C are cross-sectional views illustrating a method for manufacturing a vertical semiconductor device according to an embodiment. [Figure 6] 1A to 1C are cross-sectional views illustrating a method for manufacturing a vertical semiconductor device according to an embodiment. [Figure 7] 1A to 1C are cross-sectional views illustrating a method for manufacturing a vertical semiconductor device according to an embodiment. [Figure 8] 1A to 1C are cross-sectional views illustrating a method for manufacturing a vertical semiconductor device according to an embodiment. [Figure 9] 1A to 1C are cross-sectional views illustrating a method for manufacturing a vertical semiconductor device according to an embodiment. [Figure 10] 1A to 1C are cross-sectional views illustrating a method for manufacturing a vertical semiconductor device according to an embodiment. [Figure 11] 1A to 1C are cross-sectional views illustrating a method for manufacturing a vertical semiconductor device according to an embodiment. [Figure 12] 1A to 1C are cross-sectional views illustrating a method for manufacturing a vertical semiconductor device according to an embodiment. [Figure 13] FIG. 4 is a cross-sectional view illustrating a second example of a vertical semiconductor device according to an embodiment. [Figure 14] 5A to 5C are cross-sectional views illustrating a second example of a method for manufacturing a vertical semiconductor device according to an embodiment. [Figure 15] 5A to 5C are cross-sectional views illustrating a second example of a method for manufacturing a vertical semiconductor device according to an embodiment. [Figure 16] FIG. 11 is a cross-sectional view illustrating a third example of a vertical semiconductor device according to an embodiment. [Figure 17]5A to 5C are cross-sectional views illustrating a third example of a method for manufacturing a vertical semiconductor device according to an embodiment. [Figure 18] 5A to 5C are cross-sectional views illustrating a third example of a method for manufacturing a vertical semiconductor device according to an embodiment. [Figure 19] FIG. 11 is a cross-sectional view illustrating a fourth example of a vertical semiconductor device according to an embodiment. [Figure 20] 11 is a cross-sectional view illustrating another example of the fourth example of a vertical semiconductor device according to an embodiment. [Figure 21] 10A to 10C are cross-sectional views illustrating a fourth example of a method for manufacturing a vertical semiconductor device according to an embodiment [Figure 22] 10A to 10C are cross-sectional views illustrating a fourth example of a method for manufacturing a vertical semiconductor device according to an embodiment [Diagram 23] 10A to 10C are cross-sectional views illustrating a fourth example of a method for manufacturing a vertical semiconductor device according to an embodiment [Figure 24] FIG. 11 is a cross-sectional view illustrating a fifth example of a vertical semiconductor device according to an embodiment. [Diagram 25] FIG. 13 is a cross-sectional view illustrating another example of the fifth example of the vertical semiconductor device according to the embodiment. [Figure 26] 1 is a cross-sectional view illustrating another example of a vertical semiconductor device according to an embodiment. [Figure 27] 1 is a plan view illustrating another example of a vertical semiconductor device according to an embodiment; [Figure 28] 1 is a plan view illustrating yet another example of a vertical semiconductor device according to an embodiment; [Figure 29] 10A to 10C are cross-sectional views illustrating another example of a method for manufacturing a vertical semiconductor device according to an embodiment. [Diagram 30] 10A to 10C are cross-sectional views illustrating another example of a method for manufacturing a vertical semiconductor device according to an embodiment. [Diagram 31] FIG. 13 is a cross-sectional view illustrating a sixth example of a vertical semiconductor device according to an embodiment. [Diagram 32] 10A to 10C are cross-sectional views illustrating another example of a method for manufacturing a vertical semiconductor device according to an embodiment. [Diagram 33] 10A to 10C are cross-sectional views illustrating another example of a method for manufacturing a vertical semiconductor device according to an embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0010] DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, specific examples of the present invention will be described in detail with reference to the drawings.

[0011] In the following description, a direction parallel to the surface of the substrate is referred to as a first direction, a direction parallel to the surface of the substrate and perpendicular to the first direction is referred to as a second direction, and a direction perpendicular to the surface of the substrate is referred to as a vertical direction.

[0012] 1 is a cross-sectional view of a vertical semiconductor device according to an embodiment, FIG 2 is a perspective view of a portion of a pad structure of the vertical semiconductor device, and FIG 3 is a plan view of a portion of a pad structure of the vertical semiconductor device.

[0013] 1 and 2, a substrate 100 is provided which is divided into a first region (R1) and a second region (R2). The first region (R1) is a cell region in which memory cells are provided, and the second region (R2) is a wiring region to which wiring is connected. In one embodiment, the second region (R2) is a region on both sides of the edge of the first region (R1) in a first direction.

[0014] Substrate 100 comprises a semiconductor material such as, for example, silicon or germanium.

[0015] A laminated structure in which insulating patterns 102 and conductive patterns 140 are alternately and repeatedly stacked is provided on the substrate 100. The conductive patterns 140 are stacked in a direction perpendicular to the top surface of the substrate 100 while being spaced apart from each other.

[0016] The laminated structure extends in a first direction that is parallel to the surface of the substrate 100. In one embodiment, a plurality of laminated structures are provided and spaced apart from each other in a second direction that is substantially perpendicular to the first direction.

[0017] The laminated structures are disposed on first and second regions (R1, R2) of the substrate 100. The laminated structure located on the first region R1 of the substrate is provided with a conductive pattern structure, and the laminated structure located on the second region R2 of the substrate is provided with a pad structure 142. The pad structure 142 contacts both side edges of the conductive pattern structure in a first direction. The pad structure 142 is provided to form wiring for applying an electrical signal to the conductive pattern structure.

[0018] A conductive pattern structure and a channel structure 130 penetrating the conductive pattern structure are included on the first region R1 of the substrate 100. The conductive pattern structure and the channel structure 130 are provided for a memory cell.

[0019] The conductive pattern 140 included in the conductive pattern structure includes a ground selection line (GSL), a string selection line (SSL), and a word line between the ground selection line and the string selection line.

[0020] The conductive pattern 140 includes a metal material. In one embodiment, not shown, the conductive pattern 140 includes a barrier metal pattern and a metal pattern. For example, the metal pattern may include tungsten, copper, cobalt, aluminum, etc., and the barrier metal pattern may include titanium, titanium nitride, tantalum, tantalum nitride, etc.

[0021] The channel structure 130 has a pillar shape penetrating the conductive pattern structure.

[0022] In this embodiment, a semiconductor pattern 120 is further provided between the substrate 100 and the channel structure 130. In this case, the channel structure 130 is formed on the semiconductor pattern 120. In another embodiment, the channel structure 130 directly contacts the substrate 100.

[0023] In this embodiment, the channel structure 130 includes a dielectric film structure 122 , a channel 124 , a buried insulating pattern 126 , and an upper conductive pattern 128 .

[0024] The dielectric layer structure 122 includes a tunnel insulating layer, a charge storage layer, and a blocking layer, which are stacked in sequence from the outer wall of the channel 124. The upper conductive pattern 128 includes polysilicon.

[0025] In one embodiment, the semiconductor pattern 120 comprises, for example, single crystal silicon or polysilicon.

[0026] The edge of the pad structure 142 in the first direction has a stepped shape. The conductive patterns 140 included in the pad structure 142 have different lengths in the first direction for each layer. Therefore, the top surface of each layer is exposed at the edge of the conductive patterns 140 in the first direction. That is, each conductive pattern 140 includes an extended portion and an exposed portion, and the exposed portions of the conductive patterns are provided as pad patterns 144. The heights of the top surfaces of the pad patterns 144 are different from each other.

[0027] In the present embodiment, the pad structure 142 has a plurality of step shapes in a first direction and a second direction, respectively. For example, a plurality of stacked conductive patterns 140 are provided in a vertical sidewall of one step layer in the first direction. Also, steps are formed in the second direction.

[0028] 2, four stacked conductive patterns 140 are provided in a first direction within a vertical sidewall of one staircase layer, and four staircases are formed in a second direction, so that the number of pad patterns 144 provided on the exposed portions of the conductive patterns 140 is 16.

[0029] In another embodiment, the pad structure is stepped in only the first direction, where the vertical sidewall of one stepped layer has one conductive pattern in the first direction.

[0030] A first interlayer insulating layer 106 is provided covering the pad structure 142. The first interlayer insulating layer 106 has a flat top surface. In one embodiment, the first interlayer insulating layer 106 and the top surface of the conductive pattern structure are flush with each other.

[0031] A second interlayer insulating layer 132 is disposed on the first interlayer insulating layer 106, the channel structure 130, and the conductive pattern structure. The first and second interlayer insulating layers 106 and 142 include silicon oxide.

[0032] A buffer pattern 150 is provided on at least a portion of the second interlayer insulating film 132 in the second region R2.

[0033] The buffer pattern 150 includes a material having a high etch selectivity with respect to a material included in the first interlayer insulating film, that is, the buffer pattern 150 includes a material having an etch rate lower than that of silicon oxide in a process of etching silicon oxide.

[0034] In one embodiment, the buffer pattern 150 includes an insulating material, for example, silicon nitride or aluminum oxide.

[0035] In the present embodiment, the buffer pattern 150 is disposed to face at least a portion of the pad pattern 144. The buffer pattern 150 faces a portion where over-etching defects are likely to occur when forming a contact hole exposing the pad pattern 144. As an example, the buffer pattern 150 has a shape of one pattern.

[0036] In one embodiment, the buffer pattern 150 has a uniform thickness depending on the position.

[0037] In this embodiment, the buffer pattern 150 is disposed to face the pad pattern 144 located on the step between the top step and the bottom step in the first direction. In this case, the buffer pattern 150 does not face the pad pattern 144 located on the top step and the pad pattern 144 located on the bottom step in the first direction. That is, the buffer pattern 150 is not provided on the pad pattern 144 located on the top step and the pad pattern 144 located on the bottom step in the first direction.

[0038] In another embodiment, the buffer pattern 150 is disposed to face the pad pattern 144 located above the bottom step in the first direction, in which case the buffer pattern is not provided on the pad pattern 144 located above the bottom step in the first direction.

[0039] In this embodiment, a third interlayer insulating layer 152 surrounding a sidewall of the buffer insulating pattern 150 is formed on the second interlayer insulating layer 132. In this embodiment, an upper surface of the third interlayer insulating layer 152 and an upper surface of the buffer insulating pattern 150 are located on the same plane.

[0040] Contact plugs 160a and 160b are in contact with the pad pattern 144. In one embodiment, the contact plugs 160a and 160b include a barrier metal pattern and a metal pattern. At least a portion of the contact plug 160a penetrates the buffer pattern 150.

[0041] The contact plugs include a first contact plug 160a and a second contact plug 160b. The first contact plug 160a penetrates the buffer pattern 150, the second interlayer insulating film 132, and the first interlayer insulating film 106 to contact an upper surface of the pad pattern 144. The second contact plug 160b penetrates the third interlayer insulating film 152, the second interlayer insulating film 132, and the first interlayer insulating film 106 to contact an upper surface of the pad pattern 144. That is, the second contact plug 160b does not penetrate the buffer pattern 150 but only penetrates the interlayer insulating films (152, 132, 106).

[0042] In this embodiment, the buffer pattern 150 is formed at a portion where the first and second contact plugs 160a and 160b are to be formed, facing the pad pattern 144 located between the uppermost layer and the lowermost layer.

[0043] In this embodiment, one buffer pattern 150 is penetrated by a plurality of first contact plugs 160a.

[0044] In this embodiment, the buffer pattern 150 contacts the sidewall of the top of the first contact plug 160a, so that the buffer pattern 150 and the top surface of the first contact plug 160a are substantially flush with each other.

[0045] 2 and 3, when 16 pad patterns 144 are arranged, the buffer pattern 150 overlaps the pad patterns (5 to 12) located in the second and third staircase layers in the first direction, and the buffer pattern 150 is not arranged on the pad patterns (1 to 4, 13 to 16) located in the first and fourth staircase layers in the first direction.

[0046] A fourth interlayer insulating film 170 is provided on the third interlayer insulating film 152. Bit line contacts are provided through the second to fourth interlayer insulating films (132, 152, 170) and are electrically connected to the upper conductive pattern 128 of the channel structure 130. Bit lines are provided on the fourth interlayer insulating film 170 and the bit line contacts. The bit line contacts and the bit lines are provided in a bit line structure 174.

[0047] An upper interconnection 176 is formed on the fourth interlayer insulating film 170 and electrically connected to the first and second contact plugs 160a and 160b through the fourth interlayer insulating film 170. The upper interconnection 176 includes an upper contact plug and a conductive line.

[0048] 4 to 12 are cross-sectional views showing a method for manufacturing a vertical semiconductor device according to an embodiment.

[0049] Referring to FIG. 4, a pre-mold structure 108 is formed on the substrate 100 in the first and second regions (R1, R2).

[0050] Specifically, insulating films 101 and sacrificial films 103 are alternately stacked on a substrate 100 to form a pre-mold structure 108. For example, the insulating film 101 is formed using silicon oxide. For example, the sacrificial film 103 is formed using a nitride-based material such as silicon nitride (SiN) or silicon boronitride (SiBN).

[0051] 5, the edge of the preliminary mold structure 108 formed on the substrate 100 in the second region R2 is stepwise etched to form a stepped mold structure 108a in which the insulating pattern 102 and the sacrificial layer pattern 104 are stacked on the substrate 100. The stepped mold structure 108a in the second region R2 has a stepped shape.

[0052] In the stepped mold structure 108a, the upper surface of the sacrificial layer pattern 104 is exposed at each stepped portion.

[0053] 6, a first interlayer insulating film 106 is formed to cover the stepped mold structure 108a. The top surface of the first interlayer insulating film 106 is planarized through a planarization process. The planarization process may include a chemical mechanical polishing and / or an etch-back process.

[0054] The stepped mold structure 108a in the first region R1 is anisotropically etched to form a channel hole penetrating the stepped mold structure 108a and exposing the surface of the substrate 100 in the first region. A channel structure 130 is formed inside the channel hole. In this embodiment, a semiconductor pattern 120 in contact with the substrate 100 is further formed below the channel structure 130.

[0055] A second interlayer insulating film 132 is formed on the stepped mold structure 108 a, the channel structure 130 and the first interlayer insulating film 106 .

[0056] 7, an opening (not shown) is formed in the stepped mold structure 108a extending in a first direction, and a lower surface of the opening exposes the surface of the substrate 100. As the opening is formed, the stepped mold structure 108a is separated.

[0057] Next, the sacrificial layer pattern 104 exposed by the opening is removed to form the gap 134 between the insulating patterns 102. The removal process includes a wet etching process or an isotropic dry etching process.

[0058] 8, a conductive pattern 140 is formed in the first and second regions R1 and R2 by filling the gap 134 with a conductive material, and then the conductive material formed in the opening is removed.

[0059] Therefore, a laminated structure is formed in which the insulating pattern 102 and the conductive pattern 140 are laminated. That is, a conductive pattern structure is formed in the first region R1, and a pad structure 142 having a staircase shape is formed in the second region R2.

[0060] In one embodiment, the height of the gaps 134 is uniform at each position, so that the gaps 134 can be easily filled with conductive material. Also, conductive material formed in the openings in a subsequent process can be easily removed.

[0061] Referring to FIG. 9, a buffer layer is formed on the second interlayer insulating layer 132 and then patterned to form a buffer pattern 150. The buffer layer is then patterned to form a buffer pattern 150. Referring to FIG.

[0062] In one embodiment, the buffer pattern 150 comprises an insulating material that has a high etch selectivity with respect to the first interlayer insulating film 106 .

[0063] In one embodiment, the buffer pattern 150 is formed to have a uniform thickness.

[0064] The buffer pattern 150 is formed on the second interlayer insulating film 132 in the second region. The buffer pattern 150 is disposed to face at least a portion of the pad pattern 144. In this embodiment, the buffer pattern 150 is formed as one pattern facing a portion where over-etching defects are likely to occur in a subsequent contact hole formation process. The buffer pattern 150 faces a portion where a plurality of contact holes are to be formed.

[0065] A third interlayer insulating film 152 is formed on the second interlayer insulating film 132 to cover the buffer pattern 150. Then, the third interlayer insulating film 152 is planarized to expose an upper surface of the buffer pattern 150. Thus, the third interlayer insulating film 152 surrounds the sidewalls of the buffer pattern 150.

[0066] In another embodiment, the buffer pattern 150 is formed through a damascene process, that is, a portion of the second interlayer insulating film is etched to form a trench, a buffer layer is formed within the trench, and then the buffer pattern 150 is formed by planarizing the buffer layer.

[0067] 10 and 11, contact holes 154a and 154b are formed through the third interlayer insulating film 152, the second interlayer insulating film 132, the buffer pattern 150, and the first interlayer insulating film 106 to expose the pad patterns 144.

[0068] A first contact hole 154a is formed in a portion where the buffer pattern 150 is to be formed, penetrating the buffer pattern 150, the second interlayer insulating film 132, and the first interlayer insulating film 106 to expose the pad pattern 144. A second contact hole 154b is formed in a portion where the buffer pattern 150 is not to be formed, penetrating the third interlayer insulating film 152, the second interlayer insulating film 132, and the first interlayer insulating film 106 to expose the pad pattern 144.

[0069] In this manner, a plurality of contact holes 154a, 154b exposing pad patterns having different heights are formed by performing the same etching process. However, the thickness of the first interlayer insulating film 106 on the pad pattern 144 located in the upper layer is different from the thickness of the first interlayer insulating film 106 on the pad pattern 144 located in the lower layer. Therefore, when performing an etching process to form the contact holes 154a, 154b, the thickness of the interlayer insulating film etched varies depending on the position of the contact holes 154a, 154b. For example, the etching thickness of the interlayer insulating film on the pad pattern 144 located in the upper layer to form the contact holes 154a, 154b is relatively small, and the etching thickness of the interlayer insulating film on the pad pattern 144 located in the lower layer is relatively large.

[0070] Therefore, while performing an etching process to expose the pad pattern 144 of the lower layer, the pad pattern 144 of the upper layer is over-etched. If the pad pattern 144 is over-etched, the pad pattern 144 is punched. Also, if the etching thickness is reduced to prevent the over-etching of the pad pattern 144 of the upper layer, a not-open defect occurs in which the pad pattern 144 of the lower layer is not exposed.

[0071] Meanwhile, when performing an etching process for forming a top contact hole on the top pad pattern 144, a relatively large amount of polymer P is filled inside the top contact hole. When the polymer P is filled, the pad pattern 144 at the bottom of the contact hole is not etched any further, so that the pad pattern 144 is not over-etched. Therefore, the top pad pattern 144 does not suffer from punching defects due to over-etching.

[0072] As described above, in the contact hole forming process, defects frequently occur due to excessive etching in the pad pattern 144 located between the uppermost layer and the lowermost layer.

[0073] In this embodiment, the buffer pattern 150 is formed on and facing the pad pattern 144 located between the uppermost layer and the lowermost layer.

[0074] In another embodiment, punching failure may occur due to insufficient polymer formed in the top contact hole, so in this case, the buffer pattern 150 is formed on and facing the pad pattern 144 located in the top layer.

[0075] 10 shows a state during an etching process for forming the first and second contact holes. As shown in FIG. 10, in the region where the first contact hole 154a is to be formed, the buffer pattern 150, the second interlayer insulating film 132, and the first interlayer insulating film 106 are sequentially etched. In addition, in the region where the second contact hole 154b is to be formed, the third interlayer insulating film 152, the second interlayer insulating film 132, and the first interlayer insulating film 106 are sequentially etched. Here, since the buffer pattern 150 has a lower etching rate than silicon oxide, the region where the first contact hole 154a is to be formed is etched slower than the region where the second contact hole 154b is to be formed at the beginning of etching. Meanwhile, the uppermost second contact hole 154b is filled with polymer and is not further etched.

[0076] Then, by performing an etching process, first and second contact holes 154a and 154b are formed on the upper surface, exposing the pad pattern 144, as shown in Fig. 11. By providing the buffer pattern 150, the pad pattern 144 located above the lowermost layer is not over-etched during the etching process for exposing the pad pattern 144 of the lowermost layer. Also, since sufficient etching can be performed to expose the pad pattern 144 of the lower layer, not-open defects of the contact holes are reduced.

[0077] After the etching process, a cleaning process is performed, during which the polymer contained in the contact holes of the top layer is removed.

[0078] Meanwhile, the buffer pattern 150 is positioned to face a portion of the pad pattern 144 where defects frequently occur due to excessive etching, but the position is not limited to the above.

[0079] Referring to FIG. 12, first and second contact plugs 160a and 160b are formed in the first and second contact holes 154a and 154b, respectively.

[0080] Specifically, a barrier metal layer is formed on the sidewalls and bottom surfaces of the first and second contact holes (154a, 154b), the buffer pattern 150, and the third interlayer insulating film 152, and a metal layer is formed on the barrier metal layer, which is then planarized to expose the top surfaces of the third interlayer insulating film 152 and the buffer pattern 150.

[0081] In another embodiment, the planarization process may be performed to expose the second interlayer insulating film 132. Therefore, the third interlayer insulating film 152 and the buffer pattern 150 are removed in the planarization process. In this case, if subsequent processes are performed in the same manner, a vertical semiconductor device similar to that shown in FIG 16 described below is manufactured.

[0082] 1 again, a fourth interlayer insulating film 170 is formed on the third interlayer insulating film 152. A bit line structure 174 is formed on the fourth interlayer insulating film 170, penetrating the second to fourth interlayer insulating films (132, 152, and 170) and electrically connected to the upper conductive pattern 128.

[0083] In addition, an upper wiring 176 is formed on the fourth interlayer insulating film 170 to penetrate the fourth interlayer insulating film 170 and to be electrically connected to the first and second contact plugs 160a and 160b.

[0084] FIG. 13 is a cross-sectional view illustrating a second example of a vertical semiconductor device according to an embodiment.

[0085] The vertical semiconductor device shown in FIG. 13 is the same as the vertical semiconductor device shown in FIG. 1 except for the thickness of the third interlayer insulating film.

[0086] 13, the third interlayer insulating film 152 has a shape covering the buffer pattern 150. That is, the third interlayer insulating film 152 is disposed on the buffer pattern 150. The top surface of the third interlayer insulating film 152 is flat.

[0087] In one embodiment, the top surface of the buffer pattern 150 is located below the top surface of the first contact plug 160a.

[0088] 14 and 15 are cross-sectional views illustrating a second example of a method for manufacturing a vertical semiconductor device according to an embodiment.

[0089] 14, first, the same processes as those described with reference to FIGS. 4 to 8 are performed. A buffer layer is formed on the second interlayer insulating layer 132, and the buffer layer is patterned to form a buffer pattern 150.

[0090] A third interlayer insulating film 152 is formed on the second interlayer insulating film 132 to cover the buffer pattern 150. Then, the third interlayer insulating film 152 is planarized so that the top surface of the buffer pattern 150 is not exposed.

[0091] Thereafter, a first contact hole 154a is formed in a portion where the buffer pattern 150 is to be formed, penetrating the third interlayer insulating film 152, the buffer pattern 150, the second interlayer insulating film 132, and the first interlayer insulating film 106 to expose the pad pattern 144. In addition, a second contact hole 154b is formed in a portion where the buffer pattern 150 is not to be formed, penetrating the third interlayer insulating film 152, the second interlayer insulating film 132, and the first interlayer insulating film 106 to expose the pad pattern 144.

[0092] Referring to FIG. 15, first and second contact plugs 160a and 160b are formed in the first and second contact holes 154a and 154b, respectively.

[0093] Next, a fourth interlayer insulating film 170 is formed on the third interlayer insulating film 152. A bit line structure 174 electrically connected to the upper conductive pattern and an upper wiring 176 electrically connected to the first and second contact plugs 160a and 160b are formed on the fourth interlayer insulating film 170. Thus, the vertical type semiconductor device shown in FIG. 13 can be manufactured.

[0094] FIG. 16 is a cross-sectional view illustrating a third example of a vertical semiconductor device according to an embodiment.

[0095] The vertical semiconductor device shown in FIG. 16 is the same as the vertical semiconductor device shown in FIG. 1, except that the buffer pattern and the third interlayer insulating film are not provided.

[0096] 16, no buffer pattern is provided opposite the contact plug 160. Also, no third interlayer insulating film is provided on the second interlayer insulating film 132.

[0097] 17 and 18 are cross-sectional views illustrating a third example of a method for manufacturing a vertical semiconductor device according to an embodiment.

[0098] 17, first, the same processes as those described with reference to FIGS. 4 to 8 are performed. A buffer layer is formed on the second interlayer insulating layer 132, and the buffer layer is patterned to form a buffer pattern 150.

[0099] Then, contact holes 154a and 154b are formed through the second interlayer insulating film 132, the buffer pattern 150, and the first interlayer insulating film 106 to expose the pad patterns 144.

[0100] That is, a first contact hole 154a is formed in a portion where the buffer pattern 150 is to be formed, penetrating the buffer pattern 150, the second interlayer insulating film 132, and the first interlayer insulating film 106 to expose the pad pattern 144. A second contact hole 154b is formed in a portion where the buffer pattern 150 is not to be formed, penetrating the second interlayer insulating film 132 and the first interlayer insulating film 106 to expose the pad pattern 144.

[0101] Referring to FIG. 18, contact plugs 160 are formed inside the first and second contact holes 154a and 154b.

[0102] Specifically, a barrier metal layer is formed on the sidewalls and bottom surfaces of the first and second contact holes 154a and 154b, the second interlayer insulating film 132, and the buffer pattern 150. After a metal layer is formed on the barrier metal layer, the surface is planarized to expose the top surface of the second interlayer insulating film 132. The buffer pattern 150 is removed during the planarization process. Therefore, the contact plug 160 does not penetrate the buffer pattern.

[0103] Next, a fourth interlayer insulating film 170 is formed on the second interlayer insulating film 132. A bit line structure 174 electrically connected to the upper conductive pattern and an upper interconnection 176 electrically connected to the contact plug 160 are formed on the fourth interlayer insulating film 170. Thus, the vertical semiconductor device shown in FIG. 16 can be manufactured.

[0104] 19 is a cross-sectional view illustrating a fourth example of a vertical semiconductor device according to an embodiment, and FIG 20 is a cross-sectional view illustrating another example of the fourth example of a vertical semiconductor device according to an embodiment.

[0105] The vertical semiconductor device shown in FIGS. 19 and 20 is the same as the vertical semiconductor device shown in FIG. 1, except that the thickness of the buffer pattern varies depending on the position.

[0106] 19, the buffer pattern 150a has a different thickness depending on the portion of the pad pattern 144 that is over-etched during an etching process for forming a contact hole. In one embodiment, the buffer pattern 150a has a first thickness in the portion of the pad pattern 144 where punching defects most frequently occur, and a portion adjacent to the first thickness has a second thickness that is thinner than the first thickness.

[0107] As an example, the buffer pattern 150a has a first thickness at a portion where the first contact plug 160a is formed, which faces the pad pattern 144 located between the top layer and the bottom layer, and has a second thickness that is thinner than the first thickness at a portion where the first contact plug 160a is formed, which faces the pad patterns 144 of the top layer and the bottom layer.

[0108] For example, the buffer pattern 150a facing the pad pattern 144 located at the middle step of the steps in the first direction has the thickest first thickness, and a portion of the buffer pattern 150a adjacent to the portion having the first thickness has a thickness thinner than the first thickness.

[0109] In this embodiment, as shown in FIG. 19, a top surface of a portion of the buffer pattern 150a is flush with a top surface of the first contact plug 160a.

[0110] In another embodiment, as shown in FIG. 20, the entire top surface of the buffer pattern 150a is flush with the top surface of the first contact plug 160a.

[0111] 21 to 23 are cross-sectional views showing a fourth example of a manufacturing method for a vertical semiconductor device according to an embodiment.

[0112] 21, first, the same processes as those described with reference to FIGS. 4 to 8 are performed. A buffer layer is formed on the second interlayer insulating film 132, and the buffer layer is patterned to form a buffer pattern 150a. The buffer pattern 150a is formed to have different thicknesses depending on the position.

[0113] In one embodiment, a buffer layer is formed, an etching mask is formed, and the buffer layer is partially etched. The etching mask is then trimmed to remove a portion of the etching mask. The buffer layer is then etched using the trimmed etching mask. The buffer pattern 150a is formed to have a stepped edge. Thus, the vertical semiconductor device shown in FIG. 19 can be manufactured through subsequent processes.

[0114] In another embodiment, the buffer pattern 150a may be formed through a damascene process. That is, a third interlayer insulating film is formed on the second interlayer insulating film 132, and a portion of the third interlayer insulating film is etched to form a trench. A buffer film is formed inside the trench and planarized to form the buffer pattern 150a having the shape shown in FIG. 20. Thus, the vertical type semiconductor device shown in FIG. 20 may be manufactured through subsequent processes.

[0115] Referring to FIG. 22, a third interlayer insulating film 152 is formed to cover the buffer pattern 150a, and the third interlayer insulating film 152 is planarized to expose an upper surface of the buffer pattern 150a.

[0116] Then, first and second contact holes 154a and 154b are formed through the third interlayer insulating film 152, the second interlayer insulating film 132, the buffer pattern 150a, and the first interlayer insulating film 106 to expose the pad patterns 144.

[0117] The buffer pattern 150a reduces defects such as excessive etching of the pad pattern 144 during the process of forming the first and second contact holes 154a and 154b.

[0118] Referring to FIG. 23, first and second contact plugs 160a and 160b are formed in the first and second contact holes 154a and 154b, respectively.

[0119] Specifically, a barrier metal layer is formed on the sidewalls and bottom surfaces of the first and second contact holes (154a, 154b), the third interlayer insulating film 152, and the buffer pattern 150a, and a metal layer is formed on the barrier metal layer, which is then planarized to expose the top surfaces of the third interlayer insulating film 152 and the buffer pattern 150a.

[0120] In another embodiment, the second interlayer insulating film 132 is removed by the planarization process. Accordingly, the third interlayer insulating film 152 and the buffer pattern 150a are removed by the planarization process. In this case, by performing the same subsequent processes, the same vertical semiconductor device as that shown in FIG. 16 can be manufactured.

[0121] Thereafter, a fourth interlayer insulating film 170, a bit line structure 174, and an upper wiring 176 are formed on the third interlayer insulating film 152, thereby completing the semiconductor device shown in FIG.

[0122] 24 is a cross-sectional view illustrating a fifth example of a vertical semiconductor device according to an embodiment, and FIG 25 is a cross-sectional view illustrating another example of the fifth example of a vertical semiconductor device according to an embodiment.

[0123] The vertical semiconductor device shown in FIGS. 24 and 25 is the same as the vertical semiconductor device shown in FIG. 1, except that the buffer pattern is formed in at least two layers.

[0124] 24, the buffer pattern includes a first buffer pattern 151a and a second buffer pattern 151b. The second buffer pattern 151b is disposed on the first buffer pattern 151a. The first and second buffer patterns 151a and 151b are spaced apart from each other in the vertical direction. In this embodiment, the second buffer pattern 151b is disposed to overlap the first buffer pattern 151a.

[0125] In one embodiment, the first buffer pattern 151a and the second buffer pattern 151b may be formed of the same material or different materials.

[0126] In one embodiment, the first buffer pattern 151a and the second buffer pattern 151b may be formed to the same thickness or to different thicknesses.

[0127] In this embodiment, the second buffer pattern 151b is additionally disposed in a portion where punching defects most frequently occur in the pad pattern 144. Therefore, some of the first contact plugs 160a penetrate the first buffer pattern 151a, and some of the first contact plugs 160a' penetrate the first and second buffer patterns 151a and 151b.

[0128] In this embodiment, the buffer pattern is formed in two or more layers spaced apart in the vertical direction.

[0129] In this manner, by including the first and second buffer patterns 151a and 151b, defects in the pad pattern 144 are reduced.

[0130] 25, the buffer pattern includes a first buffer pattern 151a and a second buffer pattern 151b. In this embodiment, the second buffer pattern 151b does not overlap the first buffer pattern 151a.

[0131] In one embodiment, the first buffer pattern 151a and the second buffer pattern 151b are formed of the same material. In this case, the first buffer pattern 151a and the second buffer pattern 151b have different thicknesses. For example, a thicker buffer pattern is disposed on a portion of the pad pattern 144 where punching defects are most likely to occur.

[0132] In one embodiment, the first buffer pattern 151a and the second buffer pattern 151b are formed of different materials. For example, the first and second buffer patterns 151a and 151b include materials having different etching rates in a process of etching silicon oxide. In this case, the first buffer pattern 151a and the second buffer pattern 151b have the same thickness or different thicknesses. In one embodiment, a buffer pattern including a material having a relatively lower etching rate in a process of etching silicon oxide is disposed on a portion of the pad pattern 144 where punching defects are most likely to occur.

[0133] In this manner, by including the first and second buffer patterns 151a and 151b, defects in the pad pattern 144 are reduced.

[0134] Fig. 26 is a cross-sectional view illustrating another example of a vertical semiconductor device according to an embodiment, Fig. 27 is a plan view illustrating another example of a vertical semiconductor device according to an embodiment, and Fig. 28 is a plan view illustrating yet another example of a vertical semiconductor device according to an embodiment.

[0135] The vertical semiconductor device shown in FIG. 26 is the same as the vertical semiconductor device shown in FIG. 1, except that the buffer pattern has an isolated pattern shape.

[0136] 26, a plurality of buffer patterns 150b are disposed on the pad structure 142. The buffer patterns 150b are disposed on each step layer in the first direction. The buffer patterns 150b are disposed to be spaced apart from each other at least in the first direction.

[0137] 27, the buffer patterns 150b have one pattern shape on each step layer in the second direction. That is, each buffer pattern extends in the second direction. Thus, the first contact plugs 160a in the second direction penetrate one buffer pattern 150b. In this case, the buffer pattern 150b includes an insulating material having a high etch selectivity with respect to silicon oxide.

[0138] 28, the buffer patterns 150b are formed as isolated patterns on each pad pattern 144. That is, one first contact plug 160a penetrates one buffer pattern 150b. In this case, the buffer pattern 150b includes an insulating material or a conductive material having a high etch selectivity with respect to silicon oxide. For example, the buffer pattern may include silicon nitride, aluminum oxide, polysilicon, tungsten, tungsten nitride, etc.

[0139] 29 and 30 are cross-sectional views illustrating another example of a method for manufacturing a vertical semiconductor device according to an embodiment.

[0140] 29, first, the same processes as those described with reference to Fig. 4 to Fig. 8 are performed. A buffer layer is formed on the second interlayer insulating layer 132, and the buffer layer is patterned to form a buffer pattern 150b.

[0141] In one embodiment, the buffer patterns 150b have one pattern shape on each step layer in the second direction, and in another embodiment, the buffer patterns have separate pattern shapes on each pad pattern 144. In this case, the pad patterns 144 include an insulating material or a conductive material.

[0142] Referring to FIG. 30, a third interlayer insulating film 152 is formed to cover the buffer pattern 150b, and the third interlayer insulating film 152 is planarized to expose an upper surface of the buffer pattern 150b.

[0143] Then, first and second contact plugs 160a and 160b are formed to penetrate the third interlayer insulating film 152, the second interlayer insulating film 132, the buffer pattern 150b, and the first interlayer insulating film 106 and to contact the pad patterns 144, respectively.

[0144] Next, a fourth interlayer insulating film 170, a bit line structure 174, and an upper wiring 176 are formed on the third interlayer insulating film 152, thereby completing the semiconductor device shown in FIG.

[0145] FIG. 31 is a cross-sectional view illustrating a sixth example of a vertical semiconductor device according to an embodiment.

[0146] The vertical semiconductor device shown in FIG. 31 is the same as the vertical semiconductor device shown in FIG. 1, except that the thickness of the pad pattern is greater than the thickness of the conductive pattern in the first region.

[0147] 31, the conductive pattern included in the pad structure 142 includes an extended portion and an exposed portion of the conductive pattern 140, and the exposed portion of the conductive pattern is provided to a pad pattern 144.

[0148] In one embodiment, the extension portion and the pad pattern 144 have different thicknesses. Specifically, the pad pattern 144 has a thickness greater than the extension portion. Therefore, defects such as punching are reduced when forming a contact hole on the pad pattern 144. The pad pattern 144 is referred to as a raised pad pattern.

[0149] In addition, a buffer pattern 150 is provided on at least a portion of the pad pattern 144 so as to face the pad pattern 144 .

[0150] Although not shown, the above-mentioned raised pad patterns can be applied to each of the above-mentioned embodiments, that is, the thickness of the pad pattern portion is thicker than the conductive pattern of the other portions.

[0151] 32 and 33 are cross-sectional views illustrating another example of a method for manufacturing a vertical semiconductor device according to an embodiment.

[0152] First, the steps described with reference to FIGS. 4 and 5 are performed to form the stepped mold structure 108a on the substrate 100 in the first and second regions R1 and R2.

[0153] 32, a second sacrificial film 180 is conformally formed on the surface of the stepped mold structure. In one embodiment, the second sacrificial film 180 comprises silicon nitride.

[0154] A mask pattern 182 is formed to cover the stepped mold structure formed in the first region of the substrate. Then, a plasma surface treatment process is performed on the upper surface of the second sacrificial layer 180. The plasma surface treatment process is performed such that damage is applied to the upper surface of the second sacrificial layer 180.

[0155] During the plasma surface treatment process, plasma is applied while having linearity in the vertical direction, so that the second sacrificial layer 180 formed on the sidewalls of the step layer is hardly damaged by plasma, whereas the flat top surface of the second sacrificial layer 180 is damaged by plasma.

[0156] That is, the plasma-treated portion of the second sacrificial layer 180 has a high film density and an increased impurity concentration in the film, resulting in a low etching rate, whereas the portion of the second sacrificial layer 180 located on the sidewall of the step layer that is not plasma-treated has a higher etching rate than the plasma-treated portion of the second sacrificial layer 180.

[0157] 33, the second sacrificial film 180 formed on the sidewalls of each step layer is selectively removed by a wet etching process.

[0158] The second sacrificial layer 180 formed on the sidewalls of each step layer has a relatively high etching rate and is therefore quickly etched during the etching process. Meanwhile, the second sacrificial layer 180 in the plasma-treated portion is hardly etched. Therefore, a second sacrificial layer pattern 180a is formed on the sacrificial layer pattern 104 on the upper surface of the step layer.

[0159] Thereafter, a vertical type semiconductor device as shown in FIG. 29 can be formed by performing substantially the same processes as those described with reference to FIG. 6 to FIG. 18. However, in the process of forming the gap through the process described with reference to FIG. 7, both the sacrificial layer pattern 104 and the second sacrificial layer pattern 180a are etched. Therefore, the height of the gap formed in the portion where the pad pattern is formed is greater than the height of the gap in other portions. Therefore, when the first conductive pattern is formed as described with reference to FIG. 8, the pad pattern 144 is formed thicker than the conductive patterns in other portions as shown in FIG. 31.

[0160] Although the embodiments of the present invention have been described in detail above with reference to the drawings, the present invention is not limited to the above-described embodiments and can be modified in various ways without departing from the technical spirit of the present invention. [Industrial Applicability]

[0161] The vertical semiconductor device of the present invention can reduce defects in contact plugs and can be used in a variety of electronic products. [Explanation of symbols]

[0162] 100 Substrates 101 Insulating film 102 Insulation Pattern 103 Sacrificial membrane 104 Sacrificial film pattern 106, 132, 152, 170 First to fourth interlayer insulating films 108 Pre-mold structure 108a Stepped mold structure 120 Semiconductor Pattern 122 Dielectric membrane structure 124 Channels 126 Buried insulation pattern 128 Upper conductive pattern 130 Channel Structures 134 Gap 140 Conductive Pattern 142 Pad Structure 144 Pad Pattern 150, 150a, 150b buffer patterns 151a, 151b First and second buffer patterns 154a, 154b First and second contact holes 160 Contact plug 160a, 160a' first contact plug 160b Second contact plug 174 Bit Line Structure 176 Upper Wiring 180 Second sacrificial film 182 Mask Pattern

Claims

1. A method for manufacturing a laminated structure in which insulating patterns and conductive patterns are repeatedly laminated on a substrate, comprising: forming an interlayer insulating film covering the laminated structure; forming a buffer pattern on the interlayer insulating film; forming a first contact plug penetrating the buffer pattern and the interlayer insulating film and contacting at least a portion of the pad pattern; forming a second contact plug penetrating only the interlayer insulating film and contacting an upper surface of the pad pattern; the conductive pattern extends in a first direction parallel to an upper surface of the substrate, has a stepped edge, and includes a pad pattern defined by an exposed portion of an upper surface of the conductive pattern at the edge; the buffer pattern is formed at a portion facing the pad pattern and located between a bottom and a top of a step portion of an edge of the conductive pattern located under the first contact plug and the second contact plug; an etching process of a contact hole in which the first contact plug and the second contact plug are to be formed is performed in the same process; a contact hole formed on the first insulating layer and having a contact pattern formed thereon, the contact hole being filled with a polymer when the contact hole reaches the pad pattern in the etching process.

2. 2. The method of claim 1, wherein the buffer pattern comprises a material having an etch selectivity with respect to the interlayer insulating film in the etching process.

3. the interlayer insulating film contains silicon oxide; 2. The method of claim 1, wherein the buffer pattern comprises a material having an etching rate lower than an etching rate of the silicon oxide in the etching process.

4. 2. The method of claim 1, wherein the buffer pattern has a uniform thickness or different thicknesses depending on the position.

5. the first portion of the buffer pattern has a first thickness; a second portion of the buffer pattern having a second thickness less than the first thickness; a first portion of the buffer pattern facing the pad pattern located between the bottom and top of a step portion of an edge of the conductive pattern; 5. The method of claim 4, wherein the second portion of the buffer pattern faces the pad pattern adjacent to the bottom and top of a step portion of an edge of the conductive pattern.

6. Further comprising a plurality of the first contact plugs; 2. The method of claim 1, wherein the first contact plugs penetrate one of the buffer patterns.

7. 7. The method of claim 6, wherein the buffer pattern comprises an insulating material.

8. 8. The method of claim 7, wherein the buffer pattern comprises silicon nitride or aluminum oxide.

9. A plurality of said buffer patterns; a plurality of the first contact plugs; 2 . The method of claim 1 , wherein each of the first contact plugs penetrates one of the buffer patterns. 3 .

10. 10. The method of claim 9, wherein the buffer pattern comprises an insulating material or a conductive material.

11. Further comprising a plurality of said buffer patterns; 2. The method of claim 1, wherein the buffer patterns are spaced apart from each other in a direction perpendicular to the surface of the substrate.

12. 2. The method of claim 1, further comprising a channel structure extending through the stacked structure in a direction perpendicular to the surface of the substrate.

13. A method for manufacturing a laminate structure comprising the steps of: forming a laminate structure in which insulating patterns and conductive patterns are repeatedly laminated on a substrate; forming a vertically extending channel structure through the laminate structure; forming an interlayer insulating film covering the laminated structure; forming a buffer pattern on the interlayer insulating film so as to face at least a part of the pad pattern; forming a first contact plug penetrating the buffer pattern and the interlayer insulating film and contacting at least a portion of the pad pattern; forming a second contact plug penetrating only the interlayer insulating film and contacting at least a portion of the pad pattern; forming upper interconnections electrically connected to the first contact plug and the second contact plug, the conductive pattern extends in a first direction parallel to an upper surface of the substrate, has a stepped edge, and includes a pad pattern defined by an exposed portion of an upper surface of the conductive pattern at the edge; the buffer pattern is formed at a portion facing the pad pattern and located between a bottom and a top of a step portion of an edge of the conductive pattern located under the first contact plug and the second contact plug; an etching process of a contact hole in which the first contact plug and the second contact plug are to be formed is performed in the same process; a contact hole formed on the first insulating layer and having a contact pattern formed thereon, the contact hole being filled with a polymer when the contact hole reaches the pad pattern in the etching process.

14. the interlayer insulating film contains silicon oxide; 14. The method of claim 13, wherein the buffer pattern comprises a material having an etching rate lower than an etching rate of the silicon oxide in the etching process.

15. 14. The method of claim 13, wherein the buffer pattern has a uniform thickness or a different thickness depending on the position.

16. Further comprising a plurality of the first contact plugs; 14. The method of claim 13, wherein the first contact plugs penetrate one of the buffer patterns.

17. The method for manufacturing a vertical semiconductor element as described in claim 1 or 13, characterized in that an upper surface of the buffer pattern is formed to be flush with an upper surface of the first contact plug.

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