Imaging device

Abstract

An imaging device according to one embodiment of the present disclosure is provided with: a first substrate that has a sensor pixel for performing photoelectric conversion; a second substrate that has a pixel circuit for outputting a pixel signal on the basis of electric charge outputted from the sensor pixel; and a third substrate that has a processing circuit for performing signal processing on the pixel signal. The first substrate, the second substrate, and the third substrate are layered in this order. A low dielectric constant region is provided in at least one of regions in the periphery of the circuit in which the electric charge is read from the sensor pixel and the pixel signal is outputted.

Description

[Technical field]

[0001] The present disclosure relates to an imaging device. [Background technology]

[0002] The miniaturization of the area per pixel of a two-dimensional imaging device has been realized by introducing a microprocess and improving the mounting density. In recent years, imaging devices with a three-dimensional structure have been developed to further miniaturize imaging devices and to realize high pixel density. An imaging device with a three-dimensional structure is constructed by stacking, for example, a semiconductor substrate having a plurality of sensor pixels and a semiconductor substrate having a signal processing circuit for processing signals obtained by each sensor pixel (see Patent Document 1). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2010-245506 A Summary of the Invention

[0004] In an imaging device with a three-dimensional structure, the internal circuit structure is more complex than in an imaging device with a two-dimensional structure, and therefore the effects of resistance, capacitance, and inductance of non-ideal electronic components or wiring are more likely to appear. Therefore, in an imaging device with a three-dimensional structure, it is desired to suppress the effects of resistance, capacitance, and inductance generated in electronic components or wiring.

[0005] Therefore, it is desirable to provide an imaging device capable of improving characteristics by reducing the capacitance component caused by the three-dimensional structure.

[0006] An imaging device according to one embodiment of the present disclosure comprises a first substrate having sensor pixels that perform photoelectric conversion, a second substrate having a pixel circuit that outputs a pixel signal based on an electric charge output from the sensor pixel, and a third substrate having a processing circuit that processes the pixel signal, the first substrate, the second substrate, and the third substrate being stacked in this order, and a low dielectric constant region being provided in at least one region around the circuit that reads out the electric charge from the sensor pixel and outputs the pixel signal.

[0007] An imaging device according to an embodiment of the present disclosure includes a first substrate having a sensor pixel that performs photoelectric conversion, a second substrate having a pixel circuit that outputs a pixel signal based on the charge output from the sensor pixel, and a third substrate having a processing circuit that processes the pixel signal, the first substrate, the second substrate, and the third substrate being stacked in this order, and a low dielectric constant region is provided in at least one region around the circuit that reads out the charge from the sensor pixel and outputs the pixel signal. As a result, for example, in the imaging device, in the second substrate having a second semiconductor substrate stacked with a second insulating layer, the dielectric constant of the wiring included in the second insulating layer or the space around the second semiconductor substrate can be reduced. [Brief description of the drawings]

[0008] [Figure 1] 1 is a schematic diagram showing an example of a schematic configuration of an imaging device 1 according to an embodiment of the present disclosure. [Diagram 2] 2 is a circuit diagram showing an example of a sensor pixel 12 and a pixel circuit 22. FIG. [Diagram 3] 4 is a circuit diagram showing another example of the sensor pixel 12 and the pixel circuit 22. FIG. [Figure 4] 4 is a circuit diagram showing another example of the sensor pixel 12 and the pixel circuit 22. FIG. [Diagram 5] 4 is a circuit diagram showing another example of the sensor pixel 12 and the pixel circuit 22. FIG. [Figure 6] 2 is a circuit diagram showing an example of a connection between a plurality of pixel circuits 22 and a plurality of vertical signal lines 24. FIG. [Figure 7]1 is a longitudinal sectional view showing an example of a cross-sectional configuration of an imaging device 1 in a layered direction. [Figure 8] 1 is a schematic diagram showing an example of a horizontal cross-sectional configuration of an imaging device 1. FIG. [Figure 9] 1 is a schematic diagram showing an example of a horizontal cross-sectional configuration of an imaging device 1. FIG. [Figure 10] 2 is a schematic diagram showing an example of a wiring layout in a horizontal plane of the imaging device 1. FIG. [Figure 11] 2 is a schematic diagram showing an example of a wiring layout in a horizontal plane of the imaging device 1. FIG. [Figure 12] 2 is a schematic diagram showing an example of a wiring layout in a horizontal plane of the imaging device 1. FIG. [Figure 13] 2 is a schematic diagram showing an example of a wiring layout in a horizontal plane of the imaging device 1. FIG. [Figure 14] 1 is a longitudinal sectional view showing an example of a sectional configuration in a stacking direction of an imaging device 1 according to a first embodiment. [Figure 15] 1 is a longitudinal sectional view showing a sectional configuration in a stacking direction of an imaging device 1 in which a floating diffusion FD is shared by a plurality of sensor pixels 12. FIG. [Figure 16] 2 is a plan view showing the planar arrangement of a second semiconductor substrate 21 and an isolation insulating layer 53 in a pixel region 13. FIG. [Figure 17] 1 is a plan view showing the planar arrangement of through-wires 54, connecting portions 59, and gate electrodes in a pixel region 13. FIG. [Figure 18] 11 is a plan view showing the planar arrangement of connection wiring 55 in a pixel region 13. FIG. [Figure 19] 1 is a plan view showing the planar arrangement of wiring included in a wiring layer 56 in a pixel region 13. FIG. [Figure 20A] 10 is a vertical cross-sectional view illustrating an example of a method for forming a low dielectric constant region 90A. FIG. [Figure 20B] 10 is a vertical cross-sectional view illustrating an example of a method for forming a low dielectric constant region 90A. FIG. [Figure 20C] 10 is a vertical cross-sectional view illustrating an example of a method for forming a low dielectric constant region 90A. FIG. [Figure 20D]10 is a vertical cross-sectional view illustrating an example of a method for forming a low dielectric constant region 90A. FIG. [Figure 20E] 10 is a vertical cross-sectional view illustrating an example of a method for forming low dielectric constant regions 90B and 90C. FIG. [Figure 20F] 10 is a vertical cross-sectional view illustrating an example of a method for forming low dielectric constant regions 90B and 90C. FIG. [Figure 20G] 10 is a vertical cross-sectional view illustrating an example of a method for forming low dielectric constant regions 90B and 90C. FIG. [Figure 21] 1A to 1C are schematic cross-sectional views illustrating variations in the cross-sectional shape of low dielectric constant regions 90A, 90B, and 90C. [Figure 22A] 10A to 10C are vertical cross-sectional views illustrating steps of another example of a method for forming a low dielectric constant region 90A. [Figure 22B] 10A to 10C are vertical cross-sectional views illustrating steps of another example of a method for forming a low dielectric constant region 90A. [Figure 22C] 10A to 10C are vertical cross-sectional views illustrating steps of another example of a method for forming a low dielectric constant region 90A. [Figure 22D] 10A to 10C are vertical cross-sectional views illustrating steps of another example of a method for forming a low dielectric constant region 90A. [Figure 22E] 10A to 10C are vertical cross-sectional views illustrating steps of another example of a method for forming a low dielectric constant region 90A. [Figure 22F] 10A to 10C are vertical cross-sectional views illustrating steps of another example of a method for forming a low dielectric constant region 90A. [Figure 22G] 10A to 10C are vertical cross-sectional views illustrating steps of another example of a method for forming a low dielectric constant region 90A. [Fig. 22H] 10A to 10C are vertical cross-sectional views illustrating steps of another example of a method for forming a low dielectric constant region 90A. [Figure 23] 10A and 10B are a cross-sectional view and a top view showing a schematic configuration of a laminate of a first substrate 10 and a second substrate 20 in a second embodiment. [Figure 24A] 12A to 12C are vertical cross-sectional views illustrating steps of a first method for forming a low dielectric constant region 1290. [Figure 24B] 12A to 12C are vertical cross-sectional views illustrating steps of a first method for forming a low dielectric constant region 1290. [Figure 24C]12A to 12C are vertical cross-sectional views illustrating steps of a first method for forming a low dielectric constant region 1290. [Figure 24D] 12A to 12C are vertical cross-sectional views illustrating steps of a first method for forming a low dielectric constant region 1290. [Figure 24E] 12A to 12C are vertical cross-sectional views illustrating steps of a first method for forming a low dielectric constant region 1290. [Figure 24F] 12A to 12C are vertical cross-sectional views illustrating steps of a first method for forming a low dielectric constant region 1290. [Figure 24G] 12A to 12C are vertical cross-sectional views illustrating steps of a first method for forming a low dielectric constant region 1290. [Fig. 24H] 12A to 12C are vertical cross-sectional views illustrating steps of a first method for forming a low dielectric constant region 1290. [Figure 24I] 12A to 12C are vertical cross-sectional views illustrating steps of a first method for forming a low dielectric constant region 1290. [Figure 24J] 12A to 12C are vertical cross-sectional views illustrating steps of a first method for forming a low dielectric constant region 1290. [Figure 24K] 12A to 12C are vertical cross-sectional views illustrating steps of a first method for forming a low dielectric constant region 1290. [Figure 24L] 12A to 12C are vertical cross-sectional views illustrating steps of a first method for forming a low dielectric constant region 1290. [Figure 25A] 12A to 12C are vertical cross-sectional views illustrating steps of a second method for forming a low dielectric constant region 1290. [Figure 25B] 12A to 12C are vertical cross-sectional views illustrating steps of a second method for forming a low dielectric constant region 1290. [Figure 25C] 12A to 12C are vertical cross-sectional views illustrating steps of a second method for forming a low dielectric constant region 1290. [Figure 25D] 12A to 12C are vertical cross-sectional views illustrating steps of a second method for forming a low dielectric constant region 1290. [Figure 25E] 12A to 12C are vertical cross-sectional views illustrating steps of a second method for forming a low dielectric constant region 1290. [Figure 25F] 12A to 12C are vertical cross-sectional views illustrating steps of a second method for forming a low dielectric constant region 1290. [Figure 26]1 is a schematic cross-sectional view showing an example of parasitic capacitance generated in a laminate in which a first substrate 10 and a second substrate 20 are laminated. [Figure 27] FIG. 13 is a vertical cross-sectional view showing a region where a low dielectric constant region is provided in a first mode of the third embodiment. [Figure 28] FIG. 13 is a vertical cross-sectional view showing a region where a low dielectric constant region is provided in a second mode of the third embodiment. [Figure 29A] 13A and 13B are a plan view and a longitudinal sectional view illustrating a first method for forming a low dielectric constant region 1391 in the first embodiment. [Figure 29B] 13A and 13B are a plan view and a longitudinal sectional view illustrating a first method for forming a low dielectric constant region 1391 in the first embodiment. [Figure 29C] 13A and 13B are a plan view and a longitudinal sectional view illustrating a first method for forming a low dielectric constant region 1391 in the first embodiment. [Diagram 30] 29B is a plan view and a longitudinal sectional view showing a variation of the formation of the opening 1393 shown in FIG. 29A. [Figure 31A] 13A and 13B are plan views and longitudinal sectional views showing variations in the shape of a low dielectric constant region 1391 in the first embodiment. [Figure 31B] 13A and 13B are plan views and longitudinal sectional views showing variations in the shape of a low dielectric constant region 1391 in the first embodiment. [Figure 31C] 13A and 13B are plan views and longitudinal sectional views showing variations in the shape of a low dielectric constant region 1391 in the first embodiment. [Figure 31D] 13A and 13B are plan views and longitudinal sectional views showing variations in the shape of a low dielectric constant region 1391 in the first embodiment. [Figure 31E] 13A and 13B are plan views and longitudinal sectional views showing variations in the shape of a low dielectric constant region 1391 in the first embodiment. [Fig. 31F] 13A and 13B are plan views and longitudinal sectional views showing variations in the shape of a low dielectric constant region 1391 in the first embodiment. [Figure 32A] 13A and 13B are a plan view and a longitudinal sectional view illustrating a second method for forming a low dielectric constant region 1391 in the first embodiment. [Figure 32B] 13A and 13B are a plan view and a longitudinal sectional view illustrating a second method for forming a low dielectric constant region 1391 in the first embodiment. [Figure 32C] 13A and 13B are a plan view and a longitudinal sectional view illustrating a second method for forming a low dielectric constant region 1391 in the first embodiment. [Figure 33A] 32A to 32C. FIG. 32B is a plan view and a longitudinal sectional view showing a variation in the formation of the opening 1393 shown in FIG. [Figure 33B] 32A to 32C. FIG. 32B is a plan view and a longitudinal sectional view showing a variation in the formation of the opening 1393 shown in FIG. [Figure 33C] 32A to 32C. FIG. 32B is a plan view and a longitudinal sectional view showing a variation in the formation of the opening 1393 shown in FIG. [Figure 34A] 13A and 13B are plan views and longitudinal sectional views showing variations in the shape of a low dielectric constant region 1391 in the first embodiment. [Figure 34B] 13A and 13B are plan views and longitudinal sectional views showing variations in the shape of a low dielectric constant region 1391 in the first embodiment. [Figure 34C] 13A and 13B are plan views and longitudinal sectional views showing variations in the shape of a low dielectric constant region 1391 in the first embodiment. [Figure 35A] 13A to 13C are vertical cross-sectional views illustrating a third method for forming a low dielectric constant region 1391 in the first embodiment. [Figure 35B] 13A to 13C are vertical cross-sectional views illustrating a third method for forming a low dielectric constant region 1391 in the first embodiment. [Figure 35C] 13A to 13C are vertical cross-sectional views illustrating a third method for forming a low dielectric constant region 1391 in the first embodiment. [Figure 35D] 13A to 13C are vertical cross-sectional views illustrating a third method for forming a low dielectric constant region 1391 in the first embodiment. [Figure 36A] 13A to 13C are vertical cross-sectional views illustrating a variation of a third method for forming a low dielectric constant region 1391 in the first embodiment. [Figure 36B] 13A to 13C are vertical cross-sectional views illustrating a variation of a third method for forming a low dielectric constant region 1391 in the first embodiment. [Figure 36C] 13A to 13C are vertical cross-sectional views illustrating a variation of a third method for forming a low dielectric constant region 1391 in the first embodiment. [Figure 37A] 13A to 13C are vertical cross-sectional views illustrating a fourth method for forming a low dielectric constant region 1391 in the first embodiment. [Figure 37B] 13A to 13C are vertical cross-sectional views illustrating a fourth method for forming a low dielectric constant region 1391 in the first embodiment. [Figure 37C] 13A to 13C are vertical cross-sectional views illustrating a fourth method for forming a low dielectric constant region 1391 in the first embodiment. [Figure 38A] FIG. 13 is a vertical cross-sectional view illustrating a first method for forming a low dielectric constant region 1392 in the second embodiment. [Figure 38B] FIG. 13 is a vertical cross-sectional view illustrating a first method for forming a low dielectric constant region 1392 in the second embodiment. [Figure 38C] FIG. 13 is a vertical cross-sectional view illustrating a first method for forming a low dielectric constant region 1392 in the second embodiment. [Figure 38D] FIG. 13 is a vertical cross-sectional view illustrating a first method for forming a low dielectric constant region 1392 in the second embodiment. [Figure 39A] FIG. 13 is a plan view showing variations in the shape of a low dielectric constant region 1392 in the second embodiment. [Figure 39B] FIG. 13 is a plan view showing variations in the shape of a low dielectric constant region 1392 in the second embodiment. [Figure 39C] FIG. 13 is a plan view showing variations in the shape of a low dielectric constant region 1392 in the second embodiment. [Figure 39D] FIG. 13 is a plan view showing variations in the shape of a low dielectric constant region 1392 in the second embodiment. [Figure 40A] FIG. 13 is a vertical cross-sectional view illustrating a second method for forming a low dielectric constant region 1392 in the second embodiment. [Figure 40B] FIG. 13 is a vertical cross-sectional view illustrating a second method for forming a low dielectric constant region 1392 in the second embodiment. [Figure 40C] FIG. 13 is a vertical cross-sectional view illustrating a second method for forming a low dielectric constant region 1392 in the second embodiment. [Figure 40D] FIG. 13 is a vertical cross-sectional view illustrating a second method for forming a low dielectric constant region 1392 in the second embodiment. [Figure 41A] 19A to 19C are vertical cross-sectional views illustrating a third method for forming a low dielectric constant region 1932 in the second embodiment. [Figure 41B] 19A to 19C are vertical cross-sectional views illustrating a third method for forming a low dielectric constant region 1932 in the second embodiment. [Figure 41C] 19A to 19C are vertical cross-sectional views illustrating a third method for forming a low dielectric constant region 1932 in the second embodiment. [Figure 41D] 19A to 19C are vertical cross-sectional views illustrating a third method for forming a low dielectric constant region 1932 in the second embodiment. [Figure 41E] 19A to 19C are vertical cross-sectional views illustrating a third method for forming a low dielectric constant region 1932 in the second embodiment. [Figure 42A] 19A to 19C are vertical cross-sectional views illustrating a fourth method for forming a low dielectric constant region 1932 in the second embodiment. [Figure 42B] 19A to 19C are vertical cross-sectional views illustrating a fourth method for forming a low dielectric constant region 1932 in the second embodiment. [Figure 42C] 19A to 19C are vertical cross-sectional views illustrating a fourth method for forming a low dielectric constant region 1932 in the second embodiment. [Fig.42D] 19A to 19C are vertical cross-sectional views illustrating a fourth method for forming a low dielectric constant region 1932 in the second embodiment. [Figure 42E] 19A to 19C are vertical cross-sectional views illustrating a fourth method for forming a low dielectric constant region 1932 in the second embodiment. [Diagram 43] 8 is a vertical cross-sectional view showing a modified example of the cross-sectional configuration shown in FIG. 7. [Diagram 44] 8 is a vertical cross-sectional view showing a modified example of the cross-sectional configuration shown in FIG. 7. [Diagram 45] 13 is a cross-sectional view in the thickness direction showing an example of the configuration of an imaging device according to a fourth modified example. FIG. [Figure 46] 13 is a cross-sectional view in the thickness direction showing an example of the configuration of an imaging device according to a fourth modified example. FIG. [Figure 47]13 is a cross-sectional view in the thickness direction showing an example of the configuration of an imaging device according to a fourth modified example. FIG. [Figure 48] FIG. 13 is a horizontal cross-sectional view showing an example of the layout of a plurality of pixel units according to a fourth modified example. [Figure 49] FIG. 13 is a horizontal cross-sectional view showing an example of the layout of a plurality of pixel units according to a fourth modified example. [Figure 50] FIG. 13 is a horizontal cross-sectional view showing an example of the layout of a plurality of pixel units according to a fourth modified example. [Figure 51] 8 is a schematic diagram showing a modified example of the cross-sectional configuration of the cut surfaces Sec1 and Sec2 in FIG. 7. FIG. [Figure 52] 8 is a schematic diagram showing a modified example of the cross-sectional configuration of the cut surfaces Sec1 and Sec2 in FIG. 7. FIG. [Figure 53] 8 is a schematic diagram showing a modified example of the cross-sectional configuration of the cut surfaces Sec1 and Sec2 in FIG. 7. FIG. [Figure 54] 8 is a schematic diagram showing a modified example of the cross-sectional configuration of the cut surfaces Sec1 and Sec2 in FIG. 7. FIG. [Figure 55] 8 is a schematic diagram showing a modified example of the cross-sectional configuration of the cut surfaces Sec1 and Sec2 in FIG. 7. FIG. [Figure 56] FIG. 13 is a schematic diagram showing another example of the cross-sectional configuration of the cutting plane Sec2 of the imaging device 1 according to the seventh modified example. [Figure 57] FIG. 13 is a schematic diagram showing another example of the cross-sectional configuration of the cutting plane Sec2 of the imaging device 1 according to the seventh modified example. [Figure 58] FIG. 1 is a schematic diagram showing a circuit configuration of a CMOS image sensor equipped with a column-parallel ADC. [Figure 59] FIG. 59 is a schematic diagram showing an example of the imaging device 1 shown in FIG. 58 configured by stacking three substrates. [Figure 60] 13 is a schematic diagram showing an example of a cross-sectional configuration of an imaging device 1 according to a tenth modified example. FIG. [Figure 61] 1 is a schematic diagram showing an example in which a low-resistance region 26 made of silicide such as CoSi2 or NiSi is applied to an imaging device 1 configured by stacking three substrates. [Figure 62] 1 is a block diagram illustrating an example of a functional configuration of an imaging device according to an embodiment of the present disclosure. [Figure 63] 63 is a plan view showing a schematic configuration of the imaging device shown in FIG. 62. [Figure 64] 64 is a schematic diagram showing a cross-sectional configuration taken along line III-III' shown in FIG. 63. [Figure 65] FIG. 63 is an equivalent circuit diagram of the pixel sharing unit shown in FIG. 62. [Figure 66] 10 is a diagram illustrating an example of a connection mode between a plurality of pixel sharing units and a plurality of vertical signal lines. [Figure 67] FIG. 65 is a schematic cross-sectional view showing an example of a specific configuration of the imaging device shown in FIG. 64. [Figure 68A] 68 is a schematic diagram illustrating an example of a planar configuration of a main part of the first substrate shown in FIG. 67. [Figure 68B] 68B is a schematic diagram showing the planar configuration of a pad portion together with a main portion of the first substrate shown in FIG. 68A. [Figure 69] 68 is a schematic diagram illustrating an example of a planar configuration of the second substrate (semiconductor layer) shown in FIG. 67. FIG. [Figure 70] 68 is a schematic diagram showing an example of a planar configuration of a pixel circuit and a main part of a first substrate, together with the first wiring layer shown in FIG. 67. [Figure 71] 68 is a schematic diagram illustrating an example of a planar configuration of the first wiring layer and the second wiring layer illustrated in FIG. 67. [Figure 72] 68 is a schematic diagram illustrating an example of a planar configuration of the second wiring layer and the third wiring layer shown in FIG. 67. [Figure 73] 68 is a schematic diagram illustrating an example of a planar configuration of the third wiring layer and the fourth wiring layer shown in FIG. 67. [Figure 74] FIG. 65 is a schematic diagram for explaining the path of an input signal to the imaging device shown in FIG. 64. [Figure 75] FIG. 65 is a schematic diagram for explaining a signal path of a pixel signal in the imaging device shown in FIG. 64. [Figure 76] 70 is a schematic diagram showing a modified example of the planar configuration of the second substrate (semiconductor layer) shown in FIG. 69. FIG. [Figure 77]77 is a schematic diagram showing the planar configuration of the pixel circuit shown in FIG. 76 as well as the first wiring layer and the main part of the first substrate. [Figure 78] 78 is a schematic diagram showing an example of a planar configuration of a second wiring layer together with the first wiring layer shown in FIG. 77. [Figure 79] 79 is a schematic diagram showing an example of a planar configuration of a third wiring layer together with the second wiring layer shown in FIG. 78. [Figure 80] 79A is a schematic diagram showing an example of a planar configuration of a fourth wiring layer together with the third wiring layer shown in FIG. 79. [Figure 81] FIG. 68B is a schematic diagram illustrating a modified example of the planar configuration of the first substrate shown in FIG. 68A. [Figure 82] 82 is a schematic diagram showing an example of a planar configuration of a second substrate (semiconductor layer) laminated on the first substrate shown in FIG. 81. FIG. [Figure 83] FIG. 83 is a schematic diagram showing an example of a planar configuration of a first wiring layer together with the pixel circuit shown in FIG. 82. [Figure 84] 84 is a schematic diagram showing an example of a planar configuration of a second wiring layer together with the first wiring layer shown in FIG. 83. [Figure 85] 85 is a schematic diagram showing an example of a planar configuration of a third wiring layer together with the second wiring layer shown in FIG. 84. [Figure 86] 86 is a schematic diagram showing an example of a planar configuration of a fourth wiring layer together with the third wiring layer shown in FIG. 85. [Figure 87] 82 is a schematic diagram illustrating another example of the planar configuration of the first substrate shown in FIG. 81. FIG. [Figure 88] 88 is a schematic diagram illustrating an example of a planar configuration of a second substrate (semiconductor layer) that is laminated on the first substrate illustrated in FIG. 87. FIG. [Figure 89] FIG. 89 is a schematic diagram showing an example of a planar configuration of a first wiring layer together with the pixel circuit shown in FIG. 88. [Figure 90] 89. FIG. 90 is a schematic diagram showing an example of a planar configuration of the second wiring layer together with the first wiring layer shown in FIG. 89. [Figure 91] 91 is a schematic diagram showing an example of a planar configuration of a third wiring layer together with the second wiring layer shown in FIG. 90. [Figure 92]92 is a schematic diagram showing an example of a planar configuration of a fourth wiring layer together with the third wiring layer shown in FIG. 91. [Figure 93] 65 is a schematic cross-sectional view illustrating another example of the imaging device shown in FIG. 64. [Figure 94] FIG. 94 is a schematic diagram for explaining the path of an input signal to the imaging device shown in FIG. 93. [Figure 95] FIG. 94 is a schematic diagram for explaining a signal path of a pixel signal in the imaging device shown in FIG. 93. [Figure 96] 68 is a schematic cross-sectional view illustrating another example of the imaging device shown in FIG. 67. [Figure 97] FIG. 67 is a diagram illustrating another example of the equivalent circuit shown in FIG. 65. [Figure 98] FIG. 68B is a schematic plan view illustrating another example of the pixel separating portion shown in FIG. 68A etc. [Figure 99] FIG. 1 is a diagram illustrating an example of a schematic configuration of an imaging system including an imaging device according to the above embodiment and its modified example. [Figure 100] A diagram showing an example of an imaging procedure of the imaging system shown in Figure 99. [Figure 101] 1 is a block diagram showing an example of a schematic configuration of a vehicle control system; [Figure 102] 4 is an explanatory diagram showing an example of the installation positions of an outside-vehicle information detection unit and an imaging unit; FIG. [Figure 103] 1 is a diagram illustrating an example of a schematic configuration of an endoscopic surgery system. [Figure 104] 2 is a block diagram showing an example of a functional configuration of a camera head and a CCU. FIG. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0009] Hereinafter, an embodiment of the present disclosure will be described in detail with reference to the drawings. The embodiment described below is a specific example of the present disclosure, and the technology according to the present disclosure is not limited to the following aspects. Furthermore, the arrangement, dimensions, and dimensional ratios of each component shown in each drawing of the present disclosure are not limited to those shown in each drawing.

[0010] The explanation will be given in the following order. 1. Configuration of the imaging device 2. First embodiment 3. Second embodiment 4. Third embodiment 5. Variations 6. Specific Examples 6.1. Embodiment (Image capture device having a stacked structure of three substrates) 6.2. Variation 1 (Planar Configuration Example 1) 6.3. Modification 2 (Planar Configuration Example 2) 6.4. Modification 3 (Planar Configuration Example 3) 6.5. Modification 4 (Example in which a contact part between substrates is provided in the center of the pixel array part) 6.6. Modification 5 (Example with Planar Type Transfer Transistor) 6.7. Modification 6 (Example in which one pixel is connected to one pixel circuit) 6.8. Modification 7 (Example of the configuration of the pixel separator) 6.9. Application Examples (Imaging Systems) 6.10.Application Examples

[0011] <<1. Configuration of the imaging device>> First, an imaging device to which the technology according to the present disclosure is applied will be described with reference to FIGS.

[0012] Fig. 1 is a schematic diagram showing an example of a schematic configuration of an imaging device 1 according to an embodiment of the present disclosure. As shown in Fig. 1, the imaging device 1 is an imaging device having a three-dimensional structure including a first substrate 10, a second substrate 20, and a third substrate 30, and is configured by bonding these three substrates together. The first substrate 10, the second substrate 20, and the third substrate 30 are laminated in this order.

[0013] The first substrate 10 includes a first semiconductor substrate 11 having a plurality of sensor pixels 12 that perform photoelectric conversion. The plurality of sensor pixels 12 are provided within a pixel region 13 of the first substrate 10 and arranged in a matrix.

[0014] The second substrate 20 includes a second semiconductor substrate 21 having pixel circuits 22 that output pixel signals based on charges from the sensor pixels 12. The pixel circuits 22 are, for example, provided for every four sensor pixels 12, and are readout circuits that sequentially read out charges photoelectrically converted from the four sensor pixels 12. The second substrate 20 also includes a plurality of pixel driving lines 23 extending in the row direction and a plurality of vertical signal lines 24 extending in the column direction.

[0015] The third substrate 30 includes a third semiconductor substrate 31 having a processing circuit 32 that processes pixel signals. The processing circuit 32 also has, for example, a vertical drive circuit 33, a column signal processing circuit 34, a horizontal drive circuit 35, and a system control circuit 36. The processing circuit 32 can output an output voltage Vout for each sensor pixel 12 from the horizontal drive circuit 35 to the outside.

[0016] The vertical drive circuit 33, for example, sequentially selects the plurality of sensor pixels 12 by row. The column signal processing circuit 34, for example, performs correlated double sampling on the pixel signals output from each sensor pixel 12 in the row selected by the vertical drive circuit 33. For example, the column signal processing circuit 34 can extract the signal level of the pixel signal by performing correlated double sampling, and hold pixel data according to the amount of light received by each sensor pixel 12. The horizontal drive circuit 35, for example, sequentially outputs the pixel data held in the column signal processing circuit 34 to the outside. The system control circuit 36, for example, controls the driving of each component in the processing circuit 32. In this way, the processing circuit 32 can output pixel data based on the amount of light received by each sensor pixel 12 to the outside.

[0017] Fig. 2 is a circuit diagram showing an example of a sensor pixel 12 and a pixel circuit 22. In the circuit diagram shown in Fig. 2, four sensor pixels 12 share one pixel circuit 22. Here, "shared" means that outputs from the four sensor pixels 12 are input to one common pixel circuit 22.

[0018] Each of the sensor pixels 12 has components in common with one another. In the following, when the components of the sensor pixels 12 are to be distinguished from one another, an identification number (1, 2, 3, 4) is added to the end of the reference number of the component. On the other hand, when the sensor pixels 12 are not to be distinguished from one another, the addition of an identification number to the end of the reference number of the component is omitted.

[0019] The sensor pixel 12 includes, for example, a photodiode PD, a transfer transistor TR electrically connected to the photodiode PD, and a floating diffusion FD that temporarily holds the charge output from the photodiode PD via the transfer transistor TR. The photodiode PD is a photoelectric conversion element that performs photoelectric conversion to generate a charge according to the amount of received light. The transfer transistor TR is, for example, a MOS (Metal-Oxide-Semiconductor) transistor.

[0020] The cathode of the photodiode PD is electrically connected to the source of the transfer transistor TR, the anode of the photodiode PD is electrically connected to the reference potential line, the drain of the transfer transistor TR is electrically connected to the floating diffusion FD, and the gate of the transfer transistor TR is electrically connected to the pixel drive line 23.

[0021] The floating diffusions FD of the sensor pixels 12 that share the pixel circuit 22 are electrically connected to each other and to an input terminal of the common pixel circuit 22. The pixel circuit 22 includes, for example, a reset transistor RST, a selection transistor SEL, and an amplification transistor AMP. The pixel circuit 22 further includes an optional selection transistor SEL.

[0022] The source of the reset transistor RST (i.e., the input end of the pixel circuit 22) is electrically connected to the floating diffusion FD, the drain of the reset transistor RST is electrically connected to the power supply line VDD and the drain of the amplification transistor AMP, and the gate of the reset transistor RST is electrically connected to the pixel drive line 23. The source of the amplification transistor AMP is electrically connected to the drain of the selection transistor SEL, and the gate of the amplification transistor AMP is electrically connected to the source of the reset transistor RST. The source of the selection transistor SEL (i.e., the output end of the pixel circuit 22) is electrically connected to the vertical signal line 24, and the gate of the selection transistor SEL is electrically connected to the pixel drive line 23.

[0023] The transfer transistor TR in the ON state transfers the charge photoelectrically converted by the photodiode PD to the floating diffusion FD. The reset transistor RST resets the potential of the floating diffusion FD to a predetermined potential. The reset transistor RST in the ON state resets the potential of the floating diffusion FD to the potential of the power supply line VDD. The selection transistor SEL controls the output timing of the pixel signal from the pixel circuit 22.

[0024] The amplification transistor AMP generates a pixel signal having a voltage corresponding to the level of the charge held in the floating diffusion FD. The amplification transistor AMP constitutes a so-called source follower type amplifier, and outputs a pixel signal having a voltage corresponding to the level of the charge generated in the photodiode PD. When the selection transistor SEL is turned on, the amplification transistor AMP amplifies the potential of the floating diffusion FD, and outputs a voltage corresponding to the amplified potential to the column signal processing circuit 34 via the vertical signal line 24. The reset transistor RST, the amplification transistor AMP, and the selection transistor SEL are, for example, MOS transistors.

[0025] 3 to 5 are circuit diagrams showing other examples of the sensor pixel 12 and the pixel circuit 22. In FIG.

[0026] 3, the selection transistor SEL may be provided between a power supply line VDD and the amplification transistor AMP. In this case, the drain of the reset transistor RST is electrically connected to the power supply line VDD and the drain of the selection transistor SEL. The source of the selection transistor SEL is electrically connected to the drain of the amplification transistor AMP, and the gate of the selection transistor SEL is electrically connected to the pixel drive line 23. The source of the amplification transistor AMP (i.e., the output terminal of the pixel circuit 22) is electrically connected to the vertical signal line 24, and the gate of the amplification transistor AMP is electrically connected to the source of the reset transistor RST.

[0027] Furthermore, as shown in FIG. 4 or FIG. 5, an FD conversion gain switching transistor FDG may be further provided between the source of the reset transistor RST and the gate of the amplification transistor AMP.

[0028] Since the charge Q is expressed as the product of the capacitance C and the voltage V, if the capacitance C of the floating diffusion FD is large, the voltage V after conversion in the amplification transistor AMP will be low. On the other hand, if the charge Q of the pixel signal is large, the floating diffusion FD will not be able to hold the charge Q from the photodiode PD unless the capacitance C of the floating diffusion FD is sufficiently large. It is also important that the capacitance C of the floating diffusion FD is appropriately large so that the voltage V converted by the amplification transistor AMP does not become excessively high. Therefore, the FD conversion gain switching transistor FDG is provided to switch the charge-to-voltage conversion efficiency in the pixel circuit 22.

[0029] When the FD conversion gain switching transistor FDG is in the on state, the capacitance C of the floating diffusion FD can be increased by the gate capacitance of the FD conversion gain switching transistor FDG compared to when it is in the off state. Therefore, by switching the on / off state of the FD conversion gain switching transistor FDG to make the capacitance C of the floating diffusion FD variable, the charge-voltage conversion efficiency in the pixel circuit 22 can be switched.

[0030] FIG. 6 is a circuit diagram showing an example of the connection between a plurality of pixel circuits 22 and a plurality of vertical signal lines 24. As shown in FIG.

[0031] 6, when a plurality of pixel circuits 22 are arranged side by side in the extension direction of the vertical signal lines 24 (for example, the column direction), a plurality of vertical signal lines 24 may be assigned to each pixel circuit 22. Note that in FIG. 6, in order to distinguish each of the vertical signal lines 24, an identification number (1, 2, 3, 4) is added to the end of the reference numeral of each of the vertical signal lines 24.

[0032] FIG. 7 is a vertical cross-sectional view showing an example of a cross-sectional configuration of the imaging device 1 in the layered direction.

[0033] 7, the imaging device 1 is configured by stacking a first substrate 10, a second substrate 20, and a third substrate 30 in this order. On the light incident surface side (also called the back side) of the first substrate 10, for example, a color filter 40 and a light receiving lens 50 are provided for each sensor pixel 12. In other words, the imaging device 1 is a so-called back-illuminated imaging device.

[0034] The first substrate 10 is configured by laminating a first insulating layer 46 on a first semiconductor substrate 11. The first semiconductor substrate 11 is a silicon substrate, and has, for example, a p-well layer 42 on and near a part of the surface, and a photodiode PD in the other region (i.e., a region deeper than the p-well layer 42). The p-well layer 42 is configured of a p-type semiconductor region, and the photodiode PD is configured of a semiconductor region of a different conductivity type (specifically, n-type) from the p-well layer 42. The first semiconductor substrate 11 has a floating diffusion FD inside the p-well layer 42, which is a semiconductor region of a different conductivity type (specifically, n-type) from the p-well layer 42.

[0035] The first substrate 10 has a photodiode PD, a transfer transistor TR, and a floating diffusion FD for each sensor pixel 12. The first substrate 10 has the transfer transistor TR and the floating diffusion FD on the side opposite to the light incident surface side of the first semiconductor substrate 11 (i.e., the front side or the second substrate 20 side).

[0036] The first substrate 10 has an element isolation portion 43 that isolates each of the sensor pixels 12. The element isolation portion 43 is formed extending in a normal direction of the main surface of the first semiconductor substrate 11 (a direction perpendicular to the surface of the first semiconductor substrate 11), and electrically isolates each of the sensor pixels 12 adjacent to each other. The element isolation portion 43 is made of, for example, silicon oxide penetrating the first semiconductor substrate 11.

[0037] The first substrate 10 has, for example, a p-well layer 44 in contact with the side surface of the element isolation portion 43 on the photodiode PD side. The p-well layer 44 is composed of a semiconductor region of a conductivity type (specifically, p-type) different from that of the photodiode PD. The first substrate 10 has, for example, a fixed charge film 45 in contact with the back surface of the first semiconductor substrate 11. The fixed charge film 45 is composed of an insulating film having a negative fixed charge in order to suppress the generation of dark current caused by the interface state on the light-receiving surface side of the first semiconductor substrate 11. Examples of materials for the fixed charge film 45 include hafnium oxide, zirconium oxide, aluminum oxide, titanium oxide, and tantalum oxide. The fixed charge film 45 can form a hole accumulation layer that suppresses the generation of electrons from the interface at the interface on the light-receiving surface side of the first semiconductor substrate 11 by inducing an electric field.

[0038] The color filter 40 is provided on the back surface side of the first semiconductor substrate 11. Specifically, the color filter 40 is provided, for example, in a position facing the sensor pixels 12 with respect to the fixed charge film 45 and in contact with the fixed charge film 45. The light receiving lens 50 is provided, for example, in a position facing the sensor pixels 12 with respect to the color filter 40 and the fixed charge film 45 and in contact with the color filter 40.

[0039] The second substrate 20 is formed by laminating a second insulating layer 52 on a second semiconductor substrate 21. The second semiconductor substrate 21 is a silicon substrate, and has one pixel circuit 22 for every four sensor pixels 12. The second substrate 20 has the pixel circuit 22 on the third substrate 30 side (i.e., the front surface side) of the second semiconductor substrate 21. The second substrate 20 is bonded to the first substrate 10 such that the back surface of the second semiconductor substrate 21 faces the front surface side of the first semiconductor substrate 11. That is, the second substrate 20 is bonded to the first substrate 10 face-to-back.

[0040] An isolation insulating layer 53 is provided on the second semiconductor substrate 21, and a through wiring 54 is provided inside the isolation insulating layer 53. The through wiring 54 is electrically insulated from the second semiconductor substrate 21 by having its side surface covered by the isolation insulating layer 53. The through wiring 54 extends in the normal direction to the main surface of the second semiconductor substrate 21, and electrically connects the elements of the first substrate 10 and the elements of the second substrate 20 to each other. Specifically, the through wiring 54 electrically connects the floating diffusion FD and the connection wiring 55. For example, one through wiring 54 is provided for each sensor pixel 12.

[0041] The second substrate 20 has, for example, a plurality of connection portions 59 electrically connected to the pixel circuits 22 or the second semiconductor substrate 21 in the second insulating layer 52. The wiring layer 56 has, for example, an interlayer insulating layer 57, a plurality of pixel driving lines 23 provided inside the interlayer insulating layer 57, and a plurality of vertical signal lines 24. The wiring layer 56 has, for example, one connection wiring 55 for every four sensor pixels 12 inside the interlayer insulating layer 57. The connection wiring 55 electrically connects the through wirings 54 of the four sensor pixels 12 that share the pixel circuit 22 to each other.

[0042] The wiring layer 56 further has a plurality of pad electrodes 58 inside the interlayer insulating layer 57. Each of the pad electrodes 58 is formed of a metal such as copper (Cu). Each of the pad electrodes 58 is exposed on the surface of the wiring layer 56 and is used for bonding the second substrate 20 and the third substrate 30 together and for electrically connecting the second substrate 20 and the third substrate 30 together. The plurality of pad electrodes 58 are provided, for example, one for each of the pixel driving lines 23 and the vertical signal lines 24.

[0043] Here, the second substrate 20 may be provided in a laminated structure of a plurality of semiconductor substrates and a plurality of insulating layers.

[0044] Specifically, the second substrate 20 may include two semiconductor substrates stacked in the thickness direction. For example, the second substrate 20 may be provided by stacking a semiconductor substrate on a second insulating layer 52 that is stacked on the second semiconductor substrate 21. For example, a transistor is provided on the semiconductor substrate further provided on the second insulating layer 52, and the transistor is electrically connected to the transistor provided on the second semiconductor substrate 21 via a connection portion 59.

[0045] That is, the pixel circuit 22 provided on the second substrate 20 may be provided separately on the second semiconductor substrate 21 and on a semiconductor substrate further stacked on the second insulating layer 52. Specifically, the amplification transistor AMP, the reset transistor RST, and the selection transistor SEL included in the pixel circuit 22 may be provided such that at least one transistor is provided on the second semiconductor substrate 21, and the remaining transistors are provided on a semiconductor substrate further stacked on the second insulating layer 52. As an example, the amplification transistor AMP may be provided on the second semiconductor substrate 21, and the reset transistor RST and the selection transistor SEL may be provided on a semiconductor substrate further stacked on the second insulating layer 52.

[0046] Alternatively, the second substrate 20 may include three semiconductor substrates stacked in the thickness direction. For example, the second substrate 20 may be provided by stacking an upper first semiconductor substrate on a second insulating layer 52 stacked on the second semiconductor substrate 21, and stacking an upper second semiconductor substrate on the upper first semiconductor substrate via an insulating layer. The stacked upper first semiconductor substrate and upper second semiconductor substrate may be provided with, for example, transistors, which are electrically connected to the transistors provided on the second semiconductor substrate 21 via connection portions 59 or the like.

[0047] That is, the pixel circuit 22 provided on the second substrate 20 may be provided separately on the second semiconductor substrate 21 and on the stacked upper first and second semiconductor substrates. Specifically, the amplification transistor AMP, reset transistor RST, and selection transistor SEL included in the pixel circuit 22 may be provided in each of the second semiconductor substrate 21, the upper first semiconductor substrate, and the upper second semiconductor substrate, with at least one transistor being provided in each of them. As an example, the amplification transistor AMP may be provided on the second semiconductor substrate 21, the reset transistor RST may be provided on an upper first semiconductor substrate further provided on the second semiconductor substrate 21, and the selection transistor SEL may be provided on an upper second semiconductor substrate further provided on the upper first semiconductor substrate.

[0048] In the second substrate 20 including a plurality of semiconductor substrates stacked in the thickness direction, the semiconductor substrates are stacked separately, thereby making it possible to reduce the area of ​​the semiconductor substrate occupied by one pixel circuit 22. By using such a second substrate 20, the chip area of ​​the imaging device 1 can be reduced.

[0049] Furthermore, by using such a second substrate 20, the imaging device 1 can selectively increase the area of ​​any one of the amplification transistor AMP, the reset transistor RST, and the selection transistor SEL included in the pixel circuit 22. This allows the imaging device 1 to further reduce noise by increasing the area of ​​the amplification transistor AMP.

[0050] The third substrate 30 is formed, for example, by laminating a third insulating layer 61 on a third semiconductor substrate 31. The third semiconductor substrate 31 is a silicon substrate and has a processing circuit 32. The third substrate 30 is bonded to the second substrate 20 with the front surfaces facing each other. Therefore, in the description of each component of the third substrate 30, the description of the top and bottom is reversed from the top and bottom direction in the drawings. The third substrate 30 is bonded to the second substrate 20 so that the front surface of the third semiconductor substrate 31 faces the front surface side of the second semiconductor substrate 21. In other words, the third substrate 30 is bonded to the second substrate 20 face-to-face.

[0051] The third substrate 30 has, for example, a wiring layer 62 on a third insulating layer 61. The wiring layer 62 has, for example, an interlayer insulating layer 63 and a plurality of pad electrodes 64 provided inside the interlayer insulating layer 63 and electrically connected to the processing circuit 32. Each of the pad electrodes 64 is formed of, for example, a metal such as copper (Cu). The pad electrodes 64 are exposed on the surface of the wiring layer 62 and are used for bonding the second substrate 20 and the third substrate 30 and for electrically connecting the second substrate 20 and the third substrate 30. The second substrate 20 and the third substrate 30 are electrically connected to each other by bonding the pad electrodes 58, 64 to each other. That is, the gate (transfer gate TG) of the transfer transistor TR is electrically connected to the processing circuit 32 via the through-wire 54 and the pad electrodes 58, 64.

[0052] Fig. 8 and Fig. 9 are schematic diagrams showing an example of a horizontal cross-sectional configuration of the imaging device 1. The upper diagrams of Fig. 8 and Fig. 9 are schematic diagrams showing an example of a cross-sectional configuration of a cut surface Sec1 in Fig. 7, and the lower diagrams of Fig. 8 and Fig. 9 are schematic diagrams showing an example of a cross-sectional configuration of a cut surface Sec2 in Fig. 7.

[0053] Figure 8 illustrates a configuration in which two sets of four 2 x 2 sensor pixels 12 are arranged in a first direction V1, and Figure 9 illustrates a configuration in which four sets of four 2 x 2 sensor pixels 12 are arranged in the first direction V1 and the second direction V2.

[0054] The first direction V1 is parallel to one of two arrangement directions (e.g., row direction and column direction) of the plurality of sensor pixels 12 arranged in a matrix shape, and the second direction V2 is parallel to the arrangement direction (e.g., column direction) perpendicular to the first direction.

[0055] The through wiring 54 is provided, for example, for each sensor pixel 12, and electrically connects the floating diffusion FD and a connection wiring 55 described later. The through wirings 47 and 48 are provided, for example, for each sensor pixel 12. The through wiring 47 electrically connects the p-well layer 42 of the first semiconductor substrate 11 and wiring in the second substrate 20. The through wiring 48 electrically connects the transfer gate TG and the pixel driving line 23.

[0056] 8, the plurality of through wirings 54, the plurality of through wirings 48, and the plurality of through wirings 47 are arranged in a band shape in the second direction V2 (the up-down direction in FIG. 8) within the plane of the first substrate 10. FIG. 8 illustrates an example in which the plurality of through wirings 54, the plurality of through wirings 48, and the plurality of through wirings 47 are arranged in two rows in the second direction V2.

[0057] 9, the plurality of through wirings 54, the plurality of through wirings 48, and the plurality of through wirings 47 are arranged in a strip shape in a first direction V1 (left-right direction in FIG. 9) within the plane of the first substrate 10. FIG. 9 illustrates an example in which the plurality of through wirings 54, the plurality of through wirings 48, and the plurality of through wirings 47 are arranged in two rows in the first direction V1.

[0058] In the four sensor pixels 12 sharing the pixel circuit 22, the four floating diffusions FD are arranged close to each other via, for example, the element isolation portion 43. In the four sensor pixels 12 sharing the pixel circuit 22, the four transfer gates TG are arranged so as to surround the four floating diffusions FD, and for example, the four transfer gates TG form a circular ring shape.

[0059] As shown in FIG. 8, the isolation insulating layer 53 is composed of a plurality of blocks extending in the second direction V2. The second semiconductor substrate 21 is composed of a plurality of island-shaped blocks 21A extending in the second direction V2 and arranged side by side in the second direction V2. Each of the blocks 21A is provided with, for example, a plurality of sets of a reset transistor RST, an amplification transistor AMP, and a selection transistor SEL. One pixel circuit 22 shared by four sensor pixels 12 is composed of, for example, a reset transistor RST, an amplification transistor AMP, and a selection transistor SEL present in an area corresponding to the four sensor pixels 12. For example, the pixel circuit 22 is composed of an amplification transistor AMP in the block 21A on the left side of the isolation insulating layer 53, and a reset transistor RST and a selection transistor SEL in the block 21A on the right side of the isolation insulating layer 53.

[0060] 9, the isolation insulating layer 53 is composed of a plurality of blocks extending in the first direction V1. The second semiconductor substrate 21 is composed of a plurality of island-shaped blocks 21A extending in the first direction V1 and arranged side by side in the first direction V1. Each of the blocks 21A is provided with, for example, a plurality of sets of a reset transistor RST, an amplification transistor AMP, and a selection transistor SEL. One pixel circuit 22 shared by four sensor pixels 12 is composed of, for example, a reset transistor RST, an amplification transistor AMP, and a selection transistor SEL present in an area corresponding to the four sensor pixels 12. For example, the pixel circuit 22 is composed of an amplification transistor AMP in the block 21A to the left of the isolation insulating layer 53, and a reset transistor RST and a selection transistor SEL in the block 21A to the right of the isolation insulating layer 53.

[0061] Fig. 10 to Fig. 13 are schematic diagrams showing an example of a wiring layout in a horizontal plane of the imaging device 1. As with Fig. 8, Fig. 10 to Fig. 13 show an example of a wiring layout in the case where one pixel circuit 22 shared by four sensor pixels 12 is provided in a region corresponding to the four sensor pixels 12. Fig. 10 to Fig. 13 each show, for example, the layout of wiring provided in different layers in the wiring layer 56.

[0062] 10 , for example, four adjacent through-wires 54 are electrically connected to a connection wire 55. The through-wires 54 are electrically connected to the gate of the amplification transistor AMP included in the block 21A on the left side of the isolation insulating layer 53 and the gate of the reset transistor RST included in the block 21A on the right side of the isolation insulating layer 53 via the connection wire 55 and a connection portion 59.

[0063] As shown in FIG. 11, for example, the power supply line VDD is disposed at a position corresponding to each of the pixel circuits 22 arranged side by side in the first direction V1. The power supply line VDD is electrically connected to the drain of the amplification transistor AMP and the drain of the reset transistor RST of each of the pixel circuits 22 arranged side by side in the first direction V1 via a connection portion 59. For example, two pixel driving lines 23 are disposed at a position corresponding to each of the pixel circuits 22 arranged side by side in the first direction V1. One of the pixel driving lines 23 functions as, for example, a wiring RSTG electrically connected to the gate of each of the reset transistors RST of the pixel circuits 22 arranged side by side in the first direction V1. The other of the pixel driving lines 23 functions as, for example, a wiring SELG electrically connected to the gate of each of the selection transistors SEL of the pixel circuits 22 arranged side by side in the first direction V1. For example, the source of the amplification transistor AMP and the drain of the selection transistor SEL are electrically connected to each other via a wiring 25.

[0064] As shown in FIG. 12, for example, two reference potential lines VSS are arranged at positions corresponding to each of the pixel circuits 22 arranged side by side in the first direction V1. Each of the reference potential lines VSS is electrically connected to a plurality of through-wires 47 at positions corresponding to each of the sensor pixels 12 arranged side by side in the second direction V2. For example, four pixel driving lines 23 are arranged at positions corresponding to each of the pixel circuits 22 arranged side by side in the first direction V1. Each of the four pixel driving lines 23 functions as a wiring TRG electrically connected to the through-wire 48 of one sensor pixel 12 corresponding to each of the pixel circuits 22 arranged side by side in the first direction V1. The four pixel driving lines 23 are electrically connected to the gates of the transfer transistors TR of the sensor pixels 12 arranged side by side in the first direction V1. In FIG. 12, in order to distinguish each of the wirings TRG, identification numbers (1, 2, 3, 4) are added to the end of the wirings TRG.

[0065] 13, for example, the vertical signal line 24 is disposed at a position corresponding to each of the pixel circuits 22 arranged side by side in the second direction V2. The vertical signal line 24 is electrically connected to the source of the amplification transistor AMP of each of the pixel circuits 22 arranged side by side in the second direction V2.

[0066] The technology according to the present disclosure is applied to the above-described stacked imaging device 1. The technology according to the present disclosure will be specifically described below.

[0067] <<2. First embodiment>> First, a technique according to a first embodiment of the present disclosure will be described with reference to Fig. 14 to Fig. 22H. The technique according to the present embodiment is to more efficiently improve the electrical characteristics of pixel circuits provided on the second substrate 20 by providing a low dielectric constant region around a specific wiring of the imaging device 1.

[0068] In the imaging device 1 configured by stacking three substrates, for example, charges photoelectrically converted by a photodiode PD provided on the first substrate 10 are output to an amplification transistor AMP provided on the second substrate via a through-wire 54. The through-wire 54 is provided inside an isolation insulating layer 53 that penetrates the second semiconductor substrate 21, and electrically connects the wiring provided on the first substrate 10 and the wiring provided on the second substrate 20.

[0069] Therefore, in the imaging device 1, a parasitic capacitance is formed by forming a capacitor structure between the through wiring 54, the isolation insulating layer 53, and the second semiconductor substrate 21. The formed parasitic capacitance affects the charge before being amplified by the amplification transistor AMP, thereby reducing the conversion efficiency when the charge is converted into a voltage in the pixel circuit 22.

[0070] The technology according to the present embodiment has been conceived in view of the above circumstances. The technology according to the present embodiment provides a low dielectric constant region in at least a part of the region around the circuit that converts the charge read from the floating diffusion FD of the sensor pixel 12 into a pixel signal. As a result, the technology according to the present embodiment can reduce the effect of parasitic capacitance on the pixel signal.

[0071] Next, the technology according to this embodiment will be described more specifically with reference to Fig. 14. Fig. 14 is a vertical cross-sectional view showing an example of a cross-sectional configuration in the stacking direction of the imaging device 1 according to this embodiment.

[0072] 14, the first substrate 10 has a photodiode PD in a region defined by an element isolation portion 43. Charges photoelectrically converted by the photodiode PD are output to a floating diffusion FD via a transfer transistor TR having a transfer gate TG. The output charge is temporarily held in the floating diffusion FD, and then output to a pixel circuit 22 provided on a second semiconductor substrate 21 via a through-wire 54.

[0073] The through wiring 54 extends in the stacking direction of the first semiconductor substrate 11 and the second semiconductor substrate 21, and is provided inside the isolation insulating layer 53 penetrating the second semiconductor substrate 21. The through wiring 54 outputs the charge temporarily held in the floating diffusion FD to the amplification transistor AMP of the pixel circuit 22, etc., via the connection wiring 55 and the connection portion 59.

[0074] The second substrate 20 further includes a wiring layer 56 on the second insulating layer 52. The wiring layer 56 includes, for example, an interlayer insulating layer 57, and a plurality of pixel driving lines 23 and a plurality of vertical signal lines 24 provided inside the interlayer insulating layer 57. The plurality of pixel driving lines 23 and the plurality of vertical signal lines 24 are electrically connected to the gates and sources of the selection transistors SEL of the pixel circuits 22. The plurality of pixel driving lines 23 and the plurality of vertical signal lines 24 control the selection transistors SEL, thereby controlling the output timing of pixel signals generated based on the charges output from the floating diffusions FD.

[0075] For example, metal wiring such as the through wiring 54, the connection wiring 55, the connection portion 59, the pixel driving line 23, and the vertical signal line 24 can be formed of a metal material such as copper (Cu), aluminum (Al), tungsten (W), etc. Furthermore, a barrier layer such as silicon carbide (SiC) or silicon carbonitride (SiCN) may be provided on the surface of these metal wirings to suppress diffusion of the metal used in forming the wirings.

[0076] In the imaging device 1 according to the present embodiment, as a first aspect, a low dielectric constant region 90A is provided in at least a partial region inside the isolation insulating layer 53. Specifically, the low dielectric constant region 90A is provided in at least a partial region between the through wiring 54 penetrating the inside of the isolation insulating layer 53 and the second semiconductor substrate 21, or between the through wirings 54 penetrating the inside of the isolation insulating layer 53. With this, the low dielectric constant region 90A can reduce the magnitude of the parasitic capacitance generated between the through wiring 54 and the second semiconductor substrate 21 or between other through wirings 54. Therefore, the low dielectric constant region 90A can improve the conversion efficiency when the charge is converted into a voltage in the amplification transistor AMP of the pixel circuit 22.

[0077] The low dielectric constant region 90A may be provided all around the periphery of the through wiring 54 provided inside the isolation insulating layer 53. By forming the low dielectric constant region 90A all around the periphery of the through wiring 54, the parasitic capacitance generated between the through wiring 54 and all conductors present around the through wiring 54 can be reduced.

[0078] Furthermore, the low dielectric constant region 90A may be provided so as to be longer in the stacking direction than the thickness of the second semiconductor substrate 21. In this way, the low dielectric constant region 90A is provided in the entire region in the stacking direction between the through wiring 54 and the second semiconductor substrate 21, so that the parasitic capacitance generated between the through wiring 54 and the second semiconductor substrate 21 can be further reduced.

[0079] The low dielectric constant region 90A is a region having a lower dielectric constant than the materials constituting the surrounding first insulating layer 46, the separation insulating layer 53, and the second insulating layer 52. For example, the low dielectric constant region 90A may be configured as a void with a vacuum inside, or a void with air sealed inside. In addition, when the first insulating layer 46, the separation insulating layer 53, and the second insulating layer 52 are made of silicon oxide (SiO2: relative dielectric constant 3.9), the low dielectric constant region 90A may be configured of a material having a relative dielectric constant lower than that of silicon oxide. Furthermore, the low dielectric constant region 90A may be configured of the above-mentioned void and a low dielectric constant material that fills a part of the inside of the void. Note that, as the low dielectric constant material, for example, carbon-added silicon (SiOC) or a dielectric material known as a low-k material such as porous silica can be used.

[0080] In addition, in the imaging device 1 according to the present embodiment, as a second aspect, a low dielectric constant region 90B is provided in at least a partial region around the wiring that electrically connects the through wiring 54 to the amplification transistor AMP. Specifically, the low dielectric constant region 90B is provided in at least a partial region around the connection wiring 55 or the connection portion 59 that electrically connects to the floating diffusion FD via the through wiring 54. With this, the low dielectric constant region 90B can reduce the parasitic capacitance generated in the wiring that electrically connects from the through wiring 54 onward to the amplification transistor AMP, similar to the through wiring 54. Therefore, the low dielectric constant region 90B can improve the conversion efficiency when converting a charge into a voltage in the amplification transistor AMP of the pixel circuit 22, similar to the low dielectric constant region 90A.

[0081] The low dielectric constant region 90B is a region having a lower dielectric constant than the materials constituting the surrounding second insulating layer 52 and the interlayer insulating layer 57. The low dielectric constant region 90B may be configured as a void with a vacuum inside or a void filled with air, similar to the low dielectric constant region 90A. The low dielectric constant region 90B may be configured as a region made of a low dielectric constant material, or may be configured of a void and a low dielectric constant material that fills a part of the inside of the void. Note that, as the low dielectric constant material, for example, a dielectric material known as a low-k material such as carbon-doped silicon (SiOC) or porous silica can be used.

[0082] Furthermore, in the imaging device 1 according to the present embodiment, as a third aspect, a low dielectric constant region 90C is provided in at least a partial region around the wiring included in the wiring layer 56 laminated on the second insulating layer 52. Specifically, the low dielectric constant region 90C is provided in at least a partial region around a plurality of vertical signal lines 24 electrically connected to the source of the selection transistor SEL that controls the output timing of a pixel signal generated based on the charge output from the floating diffusion FD. This allows the low dielectric constant region 90C to reduce the parasitic capacitance generated between the vertical signal line 24 and other wiring. Therefore, the low dielectric constant region 90C can realize high-speed signal processing and low power consumption in the pixel circuit 22 or the processing circuit 32.

[0083] The low dielectric constant region 90C is a region having a lower dielectric constant than the material constituting the surrounding interlayer insulating layer 57. The low dielectric constant region 90C may be configured as a void with a vacuum inside or a void filled with air, similar to the low dielectric constant regions 90A and 90B. The low dielectric constant region 90C may be configured as a region formed of a low dielectric constant material, or may be configured of a void and a low dielectric constant material that fills a part of the inside of the void. Note that, as the low dielectric constant material, for example, a dielectric material known as a low-k material such as carbon-doped silicon (SiOC) or porous silica can be used.

[0084] The low dielectric constant regions 90A, 90B, and 90C are provided independently of each other. Therefore, in the imaging device 1 according to this embodiment, at least one of the low dielectric constant regions 90A, 90B, and 90C may be provided, or all of the low dielectric constant regions 90A, 90B, and 90C may be provided.

[0085] Even if the second substrate 20 includes multiple semiconductor substrates stacked in the thickness direction, the imaging device 1 of this embodiment can provide a low dielectric constant region in at least a portion of the area surrounding the circuit that converts the charge read out from the floating diffusion FD into a pixel signal.

[0086] Specifically, when the second substrate 20 includes a plurality of semiconductor substrates stacked in the thickness direction, a circuit for converting the charge read from the floating diffusion FD into a pixel signal is provided across the stacked semiconductor substrates (i.e., the second semiconductor substrate 21 and at least one or more semiconductor substrates provided on the second semiconductor substrate 21). Therefore, low dielectric constant regions 90A, 90B, and 90C may be provided in at least a portion of the surrounding area of ​​the wiring provided in the vicinity of the stacked semiconductor substrates. The low dielectric constant regions 90A, 90B, and 90C may be provided in the surrounding area of ​​the wiring provided in the vicinity of each of the stacked semiconductor substrates, or may be provided continuously in the surrounding area of ​​the wiring provided in the vicinity of each of the stacked semiconductor substrates.

[0087] As a result, the imaging device 1 of this embodiment can more efficiently improve the electrical characteristics of the circuit provided on the second substrate 20, thereby further improving the conversion efficiency when converting the charge read out from the floating diffusion FD into a voltage.

[0088] Next, a variation of the configuration of the floating diffusion FD in the imaging device 1 according to this embodiment will be described with reference to Fig. 15. Fig. 15 is a longitudinal cross-sectional view showing a cross-sectional configuration in the stacking direction of the imaging device 1 in which the floating diffusion FD is shared by multiple sensor pixels 12.

[0089] 15, for example, the floating diffusion FD may be provided on an element isolation portion 43 that isolates adjacent photodiodes PD from each other. The floating diffusion FD is electrically connected to a plurality of transfer transistors TR that read out the charges photoelectrically converted by the adjacent photodiodes PD.

[0090] 15, the floating diffusion FD and the pixel circuit 22 subsequent to the floating diffusion FD are shared by adjacent sensor pixels 12. Note that the number of sensor pixels 12 sharing the floating diffusion FD and the pixel circuit 22 is not particularly limited, and may be, for example, 2, 4, 8, or 16.

[0091] In such an imaging device 1, by providing the low dielectric constant regions 90A, 90B, and 90C, it is possible to simultaneously improve the conversion efficiency when converting electric charge into electric potential in the multiple sensor pixels 12. Therefore, the imaging device 1 shown in Fig. 15 can improve the conversion efficiency in the multiple sensor pixels 12 with a smaller number of low dielectric constant regions 90A, 90B, and 90C, and therefore it is possible to suppress a decrease in the strength of the entire imaging device 1 due to the formation of the low dielectric constant regions 90A, 90B, and 90C.

[0092] (Planar arrangement of low dielectric constant regions) Next, an example of the planar arrangement of the low dielectric constant regions 90A, 90B, and 90C in the imaging device 1 according to this embodiment will be described with reference to Fig. 16 to Fig. 19. Fig. 16 to Fig. 19 show an example of the planar arrangement in which a floating diffusion FD and a pixel circuit 22 are shared by four sensor pixels 12 arranged in one direction.

[0093] Fig. 16 is a plan view showing the planar arrangement of the second semiconductor substrate 21 and the isolation insulating layer 53 in the pixel region 13. In Fig. 16, the photodiodes PD of the sensor pixels 12 are provided in the square regions surrounded by dashed lines.

[0094] As shown in FIG. 16, the second semiconductor substrate 21 is divided by an isolation insulating layer 53, and the isolation insulating layer 53 is provided corresponding to the boundary of each of the photodiodes PD of the sensor pixels 12 extending in one direction.

[0095] The second semiconductor substrate 21 is provided with an activation region AA and an element isolation region SA. The activation region AA is a region that becomes the source, drain, or channel region of a field effect transistor. The activation region AA is made of silicon or silicon doped with conductive impurities. The element isolation region SA is a region that electrically isolates each of the field effect transistors provided in the activation region AA. The element isolation region SA is formed by forming an insulating layer to a depth that does not penetrate the second semiconductor substrate 21 using a shallow trench isolation (STI) method or the like.

[0096] 17 is a plan view showing the planar arrangement of the through wirings 54, the connection parts 59, and the gate electrodes in the pixel region 13. In FIG. 17, four sensor pixels 12 arranged in one direction share one floating diffusion FD and pixel circuit 22.

[0097] As shown in Figure 17, in an active area AA extending in one direction, gate electrodes of a selection transistor SEL, an amplification transistor AMP, a reset transistor RST, and an FD conversion gain switching transistor FDG shared by four sensor pixels 12 are provided from one end to the other end.

[0098] Between these gate electrodes, there are provided, as connection parts 59, a contact CVout which outputs the output voltage to the outside via the horizontal drive circuit 35, a contact CVDD which is electrically connected to a power supply line VDD which supplies a power supply potential, a contact CVSS which is electrically connected to a reference potential line VSS which supplies a reference potential, and a contact CFD which is electrically connected to the floating diffusion FD.

[0099] The isolation insulating layer 53 is provided with a through contact TFD electrically connected to the floating diffusion FD and a through contact TVSS electrically connected to the reference potential line VSS as through wirings 54. The isolation insulating layer 53 is also provided with through contacts electrically connected to the transfer gates of the transfer transistors TR of the sensor pixels 12.

[0100] In this case, it is preferable that the low dielectric constant region 90A is provided in at least a part of the region around the contact CFD and the through contact TFD electrically connected to the floating diffusion FD. It is more preferable that the low dielectric constant region 90A is provided over the entire periphery of the region around the contact CFD and the through contact TFD.

[0101] FIG. 18 is a plan view showing the planar arrangement of the connection lines 55 in the pixel region 13. As shown in FIG.

[0102] As shown in FIG. 18, a wiring is provided as the connection wiring 55, which electrically connects each of the connection parts 59 and each of the through wirings 54 shown in FIG. 17 to each other. At this time, it is preferable that a low dielectric constant region 90B is provided in at least a part of the region around the connection wiring 55 that electrically connects to the floating diffusion FD. Specifically, it is preferable that the low dielectric constant region 90B is provided in at least a part of the region around the connection wiring 55 that transmits the charge output from the floating diffusion FD to the gate of the amplification transistor AMP via the contact CFD and the through contact TFD. For example, it is preferable that the low dielectric constant region 90B is provided in at least a part of the region around the connection wiring 55 surrounded by a dashed line in FIG. 18.

[0103] FIG. 19 is a plan view showing the planar arrangement of wires included in the wiring layer 56 in the pixel region 13. As shown in FIG.

[0104] 19, the wiring layer 56 includes a power supply line VDD, a reference potential line VSS, and a vertical signal line 24 (VSL) extending in a direction parallel to the extension direction of the separation and insulation layer 53. The vertical signal line 24 is provided in a region corresponding to each boundary of the photodiodes PD of the sensor pixels 12, and the power supply line VDD and the reference potential line VSS are provided on both sides of the vertical signal line 24. In this case, it is preferable that the low dielectric constant region 90C is provided in at least a part of the region around the vertical signal line 24. For example, it is preferable that the low dielectric constant region 90C is provided in at least a part of the region around the vertical signal line 24 surrounded by a dashed line in FIG. 19.

[0105] (Method of forming low dielectric constant region) Next, a method for forming the low dielectric constant regions 90A, 90B, and 90C in the imaging device 1 according to this embodiment will be described with reference to FIGS. 20A to 22H.

[0106] First, an example of a method for forming the low dielectric constant region 90A will be described with reference to Figures 20A to 20D. Figures 20A to 20D are vertical cross-sectional views illustrating an example of a method for forming the low dielectric constant region 90A.

[0107] As shown in FIG. 20A, a second semiconductor substrate 21 provided with an isolation insulating layer 53 is bonded to a first substrate 10 on which a photodiode PD, a floating diffusion FD, and a transfer transistor TR are formed.

[0108] 20B, slit-shaped openings 91A are formed in the regions of the isolation insulating layer 53 by dry etching or the like. Specifically, slit-shaped openings 91A of approximately uniform width are formed by dry etching or the like in the regions where the through wirings 54 will be formed in a later step and in the regions of the isolation insulating layer 53 between the second semiconductor substrates 21. By forming the openings 91A in the slit shape of approximately uniform width, each of the openings 91A can be uniformly blocked when the second insulating layer 52 is deposited in a later step.

[0109] 20C, a second insulating layer 52 is deposited on the second semiconductor substrate 21 by performing CVD (Chemical Vapor Deposition) or the like under conditions of low coverage. At this time, because the deposition of the second insulating layer 52 has low coverage, the upper portion of the opening 91A is blocked before the inside is filled. As a result, the void formed by blocking the upper portion of the opening 91A becomes the low dielectric constant region 90A.

[0110] 20D, photolithography, etching, and deposition are performed in sequence to form a connection portion 59 and a through-wire 54 in the second insulating layer 52. Here, the through-wire 54 is provided, for example, so as to be electrically connected to the floating diffusion FD and to position a low dielectric constant region 90A between the second insulating layer 52 and the second semiconductor substrate 21. Thereafter, a connection wire 55 is provided on the second insulating layer 52 to form an electrical connection from the connection portion 59 and the through-wire 54 to other wires. Through such a process, the imaging device 1 according to this embodiment can form a low dielectric constant region 90A.

[0111] Next, an example of a method for forming the low dielectric constant regions 90B and 90C will be described with reference to Figures 20E to 20G. Figures 20E to 20G are vertical cross-sectional views illustrating an example of a method for forming the low dielectric constant regions 90B and 90C.

[0112] 20E, by successively performing the steps shown in Fig. 20A and Fig. 20D, a second semiconductor substrate 21 is bonded to the first substrate 10 on which the photodiode PD, floating diffusion FD, and transfer transistor TR are formed, and a connection portion 59 and a through wiring 54 are formed on the surface of the second insulating layer 52. Furthermore, a connection wiring 55 and an interlayer insulating layer 57 are formed on the connection portion 59 and the through wiring 54.

[0113] 20F, slit-shaped openings 91B are formed by dry etching or the like in a part of the region between the connection wirings 55. Specifically, slit-shaped openings 91B with a substantially uniform width are formed by dry etching or the like in the region between the connection wirings 55. By forming the openings 91B in a slit shape with a substantially uniform width, each of the openings 91B can be uniformly blocked when the interlayer insulating layer 57 is further deposited in a later step.

[0114] Next, as shown in FIG. 20G, an interlayer insulating layer 57 is further deposited on the second insulating layer 52 by performing CVD or the like under conditions of low coverage. At this time, since the deposition of the interlayer insulating layer 57 has low coverage, the upper part of the opening 91B is blocked before the inside is filled. As a result, the void formed by blocking the upper part of the opening 91B becomes the low dielectric constant region 90B. Through such a process, the imaging device 1 according to this embodiment can form the low dielectric constant region 90B. Similarly, the imaging device 1 according to this embodiment can form the low dielectric constant region 90C.

[0115] FIG. 21 is a schematic cross-sectional view illustrating variations in the cross-sectional shape of low dielectric constant regions 90A, 90B, and 90C.

[0116] In the above embodiment, the cross-sectional shape of the low dielectric constant regions 90A, 90B, and 90C formed in the voids is illustrated as a rectangular shape. However, the cross-sectional shape of the low dielectric constant regions 90A, 90B, and 90C formed in the voids may be a shape other than a rectangular shape.

[0117] 21, the cross-sectional shape of an opening 1191 formed when etching a narrow pattern of insulating layer 1193 between wirings 1192 may be reverse tapered because the etchant does not sufficiently penetrate to the bottom of opening 1191. In addition, when opening 1191 formed between wirings 1192 is blocked by CVD or the like, the CVD deposit may also partially penetrate into the upper part of opening 1191, causing the cross-sectional shape of low dielectric constant regions 90A, 90B, 90C whose upper parts are blocked to be forward tapered or triangular.

[0118] That is, the cross-sectional shape of the low dielectric constant regions 90A, 90B, and 90C formed in the voids may vary depending on the method for forming the voids, and therefore the cross-sectional shape of the low dielectric constant regions 90A, 90B, and 90C is not limited to the shape described above.

[0119] Further, another example of a method for forming the low dielectric constant region 90A will be described with reference to Figures 22A to 22H. Figures 22A to 22H are vertical cross-sectional views illustrating the steps of another example of the method for forming the low dielectric constant region 90A.

[0120] 22A, a first substrate 10 having a first insulating layer 46 laminated on a first semiconductor substrate 11 having a photodiode PD and a floating diffusion FD formed thereon, and a second substrate 20 having a second insulating layer 52 and a wiring layer 56 laminated on a second semiconductor substrate 21 are bonded together. After that, an opening 91A is formed by removing the insulating layer around the through wiring 54 that electrically connects the floating diffusion FD of the first substrate 10 and various wirings of the second substrate 20 by etching or the like. Note that a SiN film may be formed as a protective film on the inner side and bottom surface of the opening 91A.

[0121] Next, as shown in FIG. 22B, a laminated substrate 1100 having a SiO2 film 1101 formed on its surface is prepared.

[0122] Then, as shown in FIG. 22C, the laminated substrate 1100 and the laminate of the first substrate 10 and the second substrate 20 are bonded together such that the SiO 2 film 1101 faces the wiring layer 56.

[0123] 22D, the bonded substrate 1100 is peeled off from the SiO2 film 1101. As a result, the upper opening surface of the opening 91A is sealed by the SiO2 film 1101 uniformly formed on the surface of the bonded substrate 1100, thereby forming a void, and a low dielectric constant region 90A is formed.

[0124] 22E, pad electrodes 58 electrically connected to various wires of the wiring layer 56 are formed on the surface of the SiO2 film 1101.

[0125] 22F, a third substrate 30 is prepared by laminating a wiring layer 62 on a third semiconductor substrate 31. A pad electrode 64 is formed on the surface of the wiring layer 62 in a similar manner to the pad electrode 58 provided on the surface of the SiO2 film 1101.

[0126] 22G, the laminate of the first substrate 10 and the second substrate 20 is bonded to the third substrate 30 so that the SiO2 film 1101 faces the wiring layer 62. At this time, the pad electrode 58 is bonded to the pad electrode 64, whereby electrical connections are formed between the various wirings of the second substrate 20 and the various wirings of the third substrate 30.

[0127] 22H, a color filter 40 and a light receiving lens 50 are provided on the back surface of the first substrate 10 opposite the surface on which the first insulating layer 46 is formed (i.e., the surface of the first semiconductor substrate 11 opposite the surface on which the first insulating layer 46 is formed). In this way, the imaging device 1 can be formed.

[0128] The technology according to the first embodiment of the present disclosure has been described in detail above. According to the technology according to this embodiment, it is possible to reduce the parasitic capacitance generated in the wiring of the pixel circuit 22 from the floating diffusion FD to the output of the pixel signal. Therefore, according to the technology according to this embodiment, it is possible to improve the charge-voltage conversion efficiency in the pixel circuit 22.

[0129] <<3. Second embodiment>> 23 to 25F, a technique according to a second embodiment of the present disclosure will be described. The technique according to the present embodiment is for more efficiently forming a low dielectric constant region between the through wiring 54 and the second semiconductor substrate 21.

[0130] As described in the first embodiment, in the imaging device 1, the effect of parasitic capacitance on the pixel signal can be reduced by providing a low dielectric constant region in at least a part of the region around the circuit that converts the charge read from the floating diffusion FD into a pixel signal. In particular, in the imaging device 1 configured by stacking three substrates, the low dielectric constant region 90A is provided in the region between the through wiring 54 and the second semiconductor substrate 21, so that the charge-voltage conversion efficiency can be prevented from being reduced by the parasitic capacitance.

[0131] In the first embodiment, photolithography and etching are performed on the isolation insulating layer 53 in order to provide the low dielectric constant region 90A in a predetermined region between the through wiring 54 and the second semiconductor substrate 21. However, such a formation method requires many additional steps to form the low dielectric constant region 90A.

[0132] The technology according to the present embodiment has been conceived in view of the above circumstances. The technology according to the present embodiment forms a low dielectric constant region 90A in a self-aligned manner between the through-hole wiring 54 and the second semiconductor substrate 21. As a result, the technology according to the present embodiment can reduce the steps for forming the low dielectric constant region 90A, and therefore the low dielectric constant region 90A can be formed between the through-hole wiring 54 and the second semiconductor substrate 21 with less additional cost.

[0133] First, the technology according to this embodiment will be described in more detail with reference to Fig. 23. Fig. 23 is a cross-sectional view and a top view that typically show the configuration of a laminate of a first substrate 10 and a second substrate 20 in this embodiment.

[0134] 23, in the laminate according to this embodiment, a first substrate 10 in which a first insulating layer 1246 (corresponding to the first insulating layer 46) is laminated on a first semiconductor substrate 1211 (corresponding to the first semiconductor substrate 11) and a second substrate 20 in which a second insulating layer 1252 (corresponding to the second insulating layer 52) is laminated on a second semiconductor substrate 1221 (corresponding to the second semiconductor substrate 21) are bonded together. The second semiconductor substrate 1221 (corresponding to the second semiconductor substrate 21) is divided by an isolation insulating layer 1253 (corresponding to the isolation insulating layer 53) provided so as to penetrate the second semiconductor substrate 1221.

[0135] For example, a field effect transistor Tr2 is provided on the second semiconductor substrate 1221 of the second substrate 1220. The field effect transistor Tr2 is composed of, for example, a gate electrode 1230 provided on the second semiconductor substrate 1221 via a gate insulating film 1231, a sidewall insulating film 1232 provided on the side of the gate electrode 1230, and a source region 1221S and a drain region 1221D provided on both sides of the gate electrode 1230 in the second semiconductor substrate 1221. In addition, a gate contact 1259, a source contact 1259S, and a drain contact 1259D are provided on the upper portions of the gate electrode 1230, the source region 1221S, and the drain region 1221D, respectively. In addition, for example, a field effect transistor Tr1 having a structure similar to that of the field effect transistor Tr2 is provided on the first semiconductor substrate 1211 of the first substrate 1210.

[0136] Here, each terminal of the field effect transistor Tr1 provided on the first substrate 1210 is electrically connected to each terminal of the field effect transistor Tr2 provided on the second substrate 1220 in an area not shown by through wiring 1254 provided to penetrate the isolation insulating layer 1253.

[0137] 23, the low dielectric constant region 1290 is provided on the side of the second semiconductor substrate 1221 so as to surround the entire periphery of the through wiring 1254 along the outer periphery of the isolation insulating layer 1253. As a result, the low dielectric constant region 1290 can reduce the parasitic capacitance generated between the through wiring 1254 and the second semiconductor substrate 1221.

[0138] The low dielectric constant region 1290 is a region having a dielectric constant lower than that of the material constituting the isolation insulating layer 1253. The low dielectric constant region 1290 may be configured as a void with a vacuum inside, or a void filled with air. Alternatively, the low dielectric constant region 1290 may be configured as a region formed of a low dielectric constant material, or may be configured by a void and a region in which a part of the void is filled with a low dielectric constant material. Note that, as the low dielectric constant material, for example, a dielectric material known as a low-k material such as carbon-doped silicon (SiOC) or porous silica can be used.

[0139] As will be described later, in the technology according to this embodiment, the low dielectric constant region 1290 is formed by using a sidewall on the inner side surface of a through hole provided in the second semiconductor substrate 1221 when forming the isolation insulating layer 1253. Therefore, according to the technology according to this embodiment, it is possible to form the low dielectric constant region 1290 in a self-aligned manner along the outer periphery of the isolation insulating layer 1253.

[0140] As mentioned in the first embodiment, the technique according to this embodiment can be applied even when the second substrate 20 includes a plurality of semiconductor substrates stacked in the thickness direction. Specifically, when the second substrate 20 includes a plurality of semiconductor substrates stacked in the thickness direction, the low dielectric constant region 1290 may be formed in a self-aligned manner along the periphery of the isolation insulating layer 1253 penetrating the plurality of stacked semiconductor substrates (i.e., the second semiconductor substrate 21 and at least one or more semiconductor substrates provided on the second semiconductor substrate 21).

[0141] (First method for forming low dielectric constant region) 24A to 24L, a first method for forming the low dielectric constant region 1290 in this embodiment will be described. FIG. 24A to FIG. 24L are vertical cross-sectional views illustrating the steps of the first method for forming the low dielectric constant region 1290.

[0142] 24A, a SiN film 1261 and a resist layer 1281 are formed on a second semiconductor substrate 1221, and then etching is performed to form an opening 1271 in a region where an isolation insulating layer 1253 will be formed in a later step. The opening 1271 is preferably provided to a depth sufficient to allow the second semiconductor substrate 1221 to be substantially penetrated in a later etching step.

[0143] Subsequently, as shown in FIG. 24B, after the resist layer 1281 is peeled off, a SiO 2 film 1262 and a SiN film 1263 are deposited along the surface shape of the second semiconductor substrate 1221 on the second semiconductor substrate 1221 in which the opening 1271 has been formed.

[0144] Next, as shown in FIG. 24C, the SiO 2 film 1262 and the SiN film 1263 are etched back over the entire surface by dry etching to form sidewalls 1263A on the side surfaces of the opening 1271.

[0145] 24D, an opening 1272 and an opening 1273 are formed by etching a region in the second semiconductor substrate 1221 that will become an element isolation region and a region in which the isolation insulating layer 1253 will be formed in a later stage. At this time, the opening 1273 may be provided so that a part of the second semiconductor substrate 1221 remains (i.e., so as not to penetrate the second semiconductor substrate 1221), or may be provided so as to penetrate the second semiconductor substrate 1221.

[0146] 24E, the openings 1272 and 1273 are filled with an isolation insulating layer 1253 made of SiO2, and the surface is planarized by performing CMP (Chemical Mechanical Polish). At this time, CMP of the isolation insulating layer 1253 is performed until the tip of the sidewall 1263A is exposed. This makes it possible to remove the sidewall 1263A from the exposed surface in a later process.

[0147] 24F, the SiN is peeled off to remove the sidewall 1263A and the SiN film 1261. As a result, a gap that functions as the low dielectric constant region 1290 is formed in the region where the sidewall 1263A was provided. Since a portion of the sidewall 1263A is exposed on the surface of the isolation insulating layer 1253 in the step shown in FIG. 24E, it can be removed by a method such as etching in the step shown in FIG. 24F.

[0148] 24G, after depositing a gate insulating film 1231, a gate electrode layer 1233 made of polysilicon or the like is deposited. By depositing the gate electrode layer 1233 under conditions of low embedding property, it is possible to prevent the gate electrode layer 1233 from entering the low dielectric constant region 1290, which is a gap.

[0149] 24H, the gate electrode layer 1233 is etched to form the gate electrode 1230. Furthermore, a conductive impurity is introduced into the second semiconductor substrate 1221 on both sides of the gate electrode 1230 to form an LDD (Lightly Doped Drain) region.

[0150] Subsequently, as shown in FIG. 24I, a SiO 2 film 1265 is deposited on the second semiconductor substrate 1221, the isolation insulating layer 1253, and the gate electrode 1230 under conditions of low embedding property, thereby closing the upper part of the gap.

[0151] 24J, a SiN film is deposited along the surface shape of the gate electrode 1230, and then etched back to form a sidewall insulating film 1232. Thereafter, a conductive impurity is introduced into the second semiconductor substrate 1221 further outside the sidewall insulating film 1232 to form a source region 1221S and a drain region 1221D.

[0152] 24K, the first substrate 10 provided with the field effect transistor Tr1 is bonded to the second substrate 20 formed in the steps up to FIG. 24J. Specifically, the second semiconductor substrate 1221 on the back surface side of the second substrate 20 is removed, so that the isolation insulating layer 1253 completely divides the second semiconductor substrate 1221. Then, the first substrate 10 is bonded to the back surface side of the second substrate 20.

[0153] 24L, a second insulating layer 1252 is deposited on the second semiconductor substrate 1221. Thereafter, in the region where the isolation insulating layer 1253 is formed, contacts are formed that reach various terminals of the field effect transistor Tr1 of the first substrate 10 from the second insulating layer 1252, thereby forming a laminate of the first substrate 10 and the second substrate 20 shown in FIG.

[0154] (Second method for forming low dielectric constant region) 25A to 25F, a second method for forming the low dielectric constant region 1290 in this embodiment will be described. Figures 25A to 25F are vertical cross-sectional views illustrating the steps of the second method for forming the low dielectric constant region 1290.

[0155] First, an opening 1272 and an opening 1273 are formed in a second semiconductor substrate 1221 through steps similar to those shown in FIGS. 24A to 24D.

[0156] 25A, the openings 1272 and 1273 are filled with an isolation insulating layer 1253 made of SiO2, and the surface is planarized by performing CMP (Chemical Mechanical Polish). At this time, the CMP to the isolation insulating layer 1253 is performed to such an extent that the tip of the sidewall 1263A is not exposed, and the sidewall 1263A is removed after the gate electrode 1230 and the like are formed. This makes it possible to prevent the void formed by removing the sidewall 1263A from being filled again when the gate electrode 1230 is formed.

[0157] 25B, the SiN film 1261 is removed by peeling off the SiN. Meanwhile, the sidewall 1263A remains. Thereafter, the isolation insulating layer 1253 is etched again to expose the tip of the sidewall 1263A on the surface of the isolation insulating layer 1253.

[0158] 25C, after depositing a gate insulating film 1231, a gate electrode layer made of polysilicon or the like is deposited and patterned to form a gate electrode 1230. Furthermore, on the upper surface of the gate electrode 1230, a SiO2 film 1230A is formed.

[0159] 25D, a conductive impurity is introduced into the second semiconductor substrate 1221 on both sides of the gate electrode 1230 to form an LDD (Lightly Doped Drain) region. Next, a SiO2 film is deposited along the surface shape of the gate electrode 1230, and then etched back to form a sidewall insulating film 1232A. Next, a conductive impurity is introduced into the second semiconductor substrate 1221 further outside the sidewall insulating film 1232A to form a source region 1221S and a drain region 122D.

[0160] 25E, the SiN is peeled off to remove the sidewall 1263A, thereby forming a gap that functions as the low dielectric constant region 1290 in the region where the sidewall 1263A was provided.

[0161] 25F, a SiO2 film 1265 is deposited on the isolation insulating layer 1253 under conditions of low embedding property to close the upper part of the gap. Next, a SiN film is deposited along the surface shape of the gate electrode 1230. Thereafter, a stack similar to the stack of the first substrate 10 and the second substrate 20 shown in FIG. 23 can be formed through steps similar to those shown in FIGS. 24K to 24L.

[0162] The technology according to the second embodiment of the present disclosure has been described in detail above. According to the technology according to this embodiment, it is possible to form the low dielectric constant region 1290 consisting of a gap between the through wiring 1254 and the second semiconductor substrate 1221 in a self-aligned manner without using lithography or the like. Therefore, according to the technology according to this embodiment, it is possible to form the low dielectric constant region 1290 between the through wiring 1254 and the second semiconductor substrate 1221 at a lower cost.

[0163] Note that sidewall 1263A that has not been completely removed may remain inside low dielectric constant region 1290 consisting of a void. Even in such a case, low dielectric constant region 1290 can reduce the magnitude of parasitic capacitance generated between through wiring 1254 and second semiconductor substrate 1221.

[0164] <<4. Third embodiment>> 26 to 42E, a technique according to a third embodiment of the present disclosure will be described. The technique according to the present embodiment reduces parasitic capacitance caused by a three-dimensional structure in which the first substrate 10 and the second substrate 20 are bonded together by providing a low dielectric constant region in the vicinity of the second semiconductor substrate 21.

[0165] In the imaging device 1 configured by stacking three substrates, a first semiconductor substrate 11 and a second semiconductor substrate 21 are stacked via a first insulating layer 46. Since parasitic capacitance occurs when an insulator is sandwiched between two conductors, the stacked second semiconductor substrate 21 may generate parasitic capacitance between the conductors present in various three-dimensional directions.

[0166] For example, an example of parasitic capacitance generated by the second semiconductor substrate 21 is shown in Fig. 26. Fig. 26 is a schematic cross-sectional view showing an example of parasitic capacitance generated in a laminate in which the first substrate 10 and the second substrate 20 are laminated.

[0167] 26, for example, in the laminate according to this embodiment, a first substrate 10 in which a first insulating layer 1342 (corresponding to the first insulating layer 46) is laminated on a first semiconductor substrate 1311 (corresponding to the first semiconductor substrate 11) and a second substrate 20 in which a second insulating layer 1352 (corresponding to the second insulating layer 52) is laminated on a second semiconductor substrate 1321 (corresponding to the second semiconductor substrate 21) are bonded together. In addition, the second semiconductor substrate 1321 (corresponding to the second semiconductor substrate 21) is divided by an isolation insulating layer 1353 (corresponding to the isolation insulating layer 53) provided penetrating the second semiconductor substrate 1321. A transfer gate TG, which is a gate of a transfer transistor, is provided on the first substrate 10, and a field effect transistor Tr2 including a gate electrode 1322 is provided on the second substrate 20. Furthermore, each terminal of the transfer transistor etc. provided on the first substrate 10 is electrically connected to the gate contact 1359 of the field effect transistor Tr2 provided on the second substrate 1320 in an area not shown by a through wiring 1360 provided through the isolation insulating layer 1353.

[0168] Here, the second semiconductor substrate 1321 generates parasitic capacitance between the side and the through-wire 1360, for example. Also, the second semiconductor substrate 1321 generates parasitic capacitance between the bottom and the transfer gate TG of the transfer transistor, for example. In particular, when the second semiconductor substrate 1321 is made thinner and the first insulating layer 1342 is made thinner, the distance between the second semiconductor substrate 1321 and the transfer gate TG becomes closer. In such a case, the parasitic capacitance and back bias generated between the field effect transistor Tr2 and the transfer gate TG significantly affect the characteristics of the field effect transistor Tr2.

[0169] The technology according to the present embodiment has been conceived in view of the above circumstances. The technology according to the present embodiment provides a low dielectric constant region on the side or below the second semiconductor substrate 1321 in order to reduce the magnitude of the above parasitic capacitance.

[0170] The technology according to the present embodiment will be described in more detail with reference to Fig. 27 and Fig. 28. Fig. 27 is a vertical cross-sectional view showing a region where a low dielectric constant region is provided in a first embodiment of the present embodiment. Fig. 28 is a vertical cross-sectional view showing a region where a low dielectric constant region is provided in a second embodiment of the present embodiment.

[0171] 27, in the imaging device 1 according to this embodiment, as a first mode, a low dielectric constant region 1391 is provided on a side of a second semiconductor substrate 1321 (corresponding to the second semiconductor substrate 21). Specifically, the low dielectric constant region 1391 is provided at least in a region between the second semiconductor substrate 1321 and a through-hole wiring 1360 provided in an isolation insulating layer 1353 in an in-plane direction. This allows the low dielectric constant region 1391 to reduce the magnitude of parasitic capacitance generated between the second semiconductor substrate 1321 and the through-hole wiring 1360.

[0172] The low dielectric constant region 1391 is a region having a dielectric constant lower than that of the material constituting the isolation insulating layer 1353. For example, the low dielectric constant region 1391 may be configured as a void region with a vacuum inside, or a void region with air sealed inside. The low dielectric constant region 1391 may also be a region formed of a material with a relative dielectric constant lower than that of the material constituting the isolation insulating layer 1353. Furthermore, the low dielectric constant region 1391 may be configured of a void region and a region in which a part of the void region is filled with a low dielectric constant material. Note that, as the low dielectric constant material, for example, a dielectric material known as a low-k material such as carbon-doped silicon (SiOC) or porous silica can be used.

[0173] 28, in the imaging device 1 according to this embodiment, as a second aspect, a low dielectric constant region 1392 is provided below the second semiconductor substrate (corresponding to the second semiconductor substrate 21). Specifically, the low dielectric constant region 1392 is provided in a region between the second semiconductor substrate 1321 and the transfer gate TG of the transfer transistor in the stacking direction. For example, the low dielectric constant region 1392 is provided at least in a region where the second semiconductor substrate 1321 and the transfer gate TG overlap when the second semiconductor substrate 1321 is viewed in a plan view in the stacking direction. This allows the low dielectric constant region 1392 to reduce the magnitude of the parasitic capacitance generated between the second semiconductor substrate 1321 and the transfer gate TG.

[0174] The low dielectric constant region 1392 is a region having a dielectric constant lower than that of the material constituting the first insulating layer 1342. For example, the low dielectric constant region 1392 may be configured as a void region with a vacuum inside, or a void region with air sealed inside. The low dielectric constant region 1392 may also be a region formed of a material with a relative dielectric constant lower than that of the material constituting the first insulating layer 1342. Furthermore, the low dielectric constant region 1392 may be configured of a void region and a region in which a part of the void region is filled with a low dielectric constant material. Note that, as the low dielectric constant material, for example, a dielectric material known as a low-k material such as carbon-doped silicon (SiOC) or porous silica can be used.

[0175] When the second substrate 20 includes a plurality of semiconductor substrates stacked in the thickness direction, a low dielectric constant region 1391 may be provided on the side of the stacked semiconductor substrates (i.e., the second semiconductor substrate 21 and at least one or more semiconductor substrates provided on the second semiconductor substrate 21) (first embodiment). Also, a low dielectric constant region 1392 may be provided below the stacked semiconductor substrates (i.e., the second semiconductor substrate 21 and at least one or more semiconductor substrates provided on the second semiconductor substrate 21) (second embodiment). This makes it possible for the imaging device 1 according to this embodiment to more efficiently reduce the parasitic capacitance generated between the semiconductor substrates included in the second substrate 20 and the wiring or electrodes.

[0176] (First mode) Hereinafter, the first aspect of the technology according to this embodiment will be described in more detail with reference to FIGS. 29A to 36C.

[0177] 29A to 29C are plan views and longitudinal sectional views illustrating a first method for forming a low dielectric constant region 1391 in the first embodiment.

[0178] 29A, the first insulating layer 1342 is formed by laminating films made of multiple insulating materials with different etching rates. Specifically, the first insulating layer 1342 is formed by alternately laminating SiO2 films and SiN films with different etching rates.

[0179] A second semiconductor substrate 1321 and a separation insulating layer 1353 are provided on the first insulating layer 1342. A gate electrode 1322 is provided on the second semiconductor substrate 1321 via a gate insulating film (not shown), thereby disposing a field effect transistor Tr2. A gate contact 1359 is electrically connected to the gate electrode 1322 of the field effect transistor Tr2, and a source or drain contact 1358 is electrically connected to the source or drain region of the second semiconductor substrate 1321. A SiN film 1365 functioning as a stress liner film or an etching stopper film may be formed on the surfaces of the second semiconductor substrate 1321 and the gate electrode 1322.

[0180] The isolation insulating layer 1353 is provided with through wiring 1360 penetrating the isolation insulating layer 1353 and the first insulating layer 1342. The through wiring 1360 electrically connects various wirings of the first substrate 10 and various wirings of the second substrate 20 in a region not shown.

[0181] In the first method for forming the low dielectric constant region 1391, first, lithography using a hard mask, dry etching of the second insulating layer 1352, removal of the SiN film 1365, and dry etching of the separation insulating layer 1353 are sequentially performed to form an opening 1393 in a region between the second semiconductor substrate 1321 and the through-hole wiring 1360. At this time, since the first insulating layer 1342 contains a SiN film having an etching rate different from that of the SiO2 film, etching of the first insulating layer 1342 in the stacking direction is stopped by the SiN film.

[0182] 29B, a liner film 1366 made of SiN is formed on the inner side and bottom surface of opening 1393. Liner film 1366 can increase the strength of the inner side and bottom surface of opening 1393, and is therefore a film that prevents opening 1393 from being crushed or deformed due to internal stress or the like.

[0183] Next, as shown in FIG. 29C, a low dielectric constant layer 1354 is deposited on the liner film 1366 by using CVD (Chemical Vapor Deposition) or the like under conditions of low embedding property, thereby blocking the upper part of the opening 1393 before the bottom of the opening 1393 is embedded. This allows a low dielectric constant region 1391 consisting of a void to be formed in the region where the opening 1393 is formed. Note that as a material for forming the low dielectric constant layer 1354, a material known as a low-k material can be appropriately used. Thereafter, the low dielectric constant layer 1354 is planarized by CMP (Chemical Mechanical Polish), and thus a wiring layer or the like can be further formed on the low dielectric constant layer 1354.

[0184] Fig. 30 is a plan view and a longitudinal sectional view showing a variation of the formation of the opening 1393 shown in Fig. 29A. As shown in Fig. 30, the first insulating layer 1342 may be provided as a single layer film of SiO2 film that does not include a SiN film. In such a case, since there is no SiN film that serves as an etching stopper, the etching termination of the lamination method of the separation insulating layer 1353 and the first insulating layer 1342 is controlled by the etching time.

[0185] Therefore, if there is no need to strictly control the end of the etching in the stacking direction of the first insulating layer 1342, the process of forming the first insulating layer 1342 can be further simplified by omitting the formation of the SiN film in the first insulating layer 1342.

[0186] 31A to 31F are plan views and longitudinal sectional views showing variations in the shape of the low dielectric constant region 1391 in the first mode.

[0187] As shown in FIG. 31A, the low dielectric constant region 1391 is provided as a gap. The low dielectric constant region 1391 is provided in at least a part of the region between the second semiconductor substrate 1321 and the through wiring 1360. The length of the low dielectric constant region 1391 in the direction perpendicular to the arrangement direction of the through wiring 1360 and the second semiconductor substrate 1321 in the plane of the second semiconductor substrate 1321 is preferably longer than both the through wiring 1360 and the second semiconductor substrate 1321. In addition, the length of the low dielectric constant region 1391 in the stacking direction is preferably longer than the thickness of the second semiconductor substrate 1321. That is, the cross section of the low dielectric constant region 1391 cut on a plane perpendicular to the arrangement direction of the through wiring 1360 and the second semiconductor substrate 1321 preferably has a size that includes the surface of the second semiconductor substrate 1321 facing the through wiring 1360. According to this, the low dielectric constant region 1391 can further reduce the magnitude of the parasitic capacitance between the second semiconductor substrate 1321 and the through-wire 1360.

[0188] 31B, the low dielectric constant region 1391 may be provided as a gap and provided in a planar shape of a slit. In such a case, the upper part of the opening formed in the isolation insulating layer 1353 is more easily blocked, so that the low dielectric constant region 1391 can be formed more easily.

[0189] 31C, the low dielectric constant region 1391 may be provided as a gap and adjacent to the through-hole wiring 1360. As long as the low dielectric constant region 1391 is a space between the second semiconductor substrate 1321 and the through-hole wiring 1360, the same effect can be obtained whether the low dielectric constant region 1391 is provided on the second semiconductor substrate 1321 side or on the through-hole wiring 1360 side.

[0190] 31D, the low dielectric constant region 1391 may be provided as a gap and in a substantially square shape. The larger the size of the low dielectric constant region 1391, the more the parasitic capacitance generated between the second semiconductor substrate 1321 and the through-hole wiring 1360 can be reduced. However, if the size of the low dielectric constant region 1391 is excessively large, the low dielectric constant region 1391 reduces the overall strength of the first substrate 10 and the second substrate. Therefore, when the overall strength of the first substrate 10 and the second substrate is prioritized, the low dielectric constant region 1391 is provided in a shape that is not excessively large.

[0191] 31E, the low dielectric constant region 1391 may be provided as a gap in a region surrounding the through-hole wiring 1360. Even in this case, since the low dielectric constant region 1391 is provided between the second semiconductor substrate 1321 and the through-hole wiring 1360, the low dielectric constant region 1391 can reduce the magnitude of the parasitic capacitance between the second semiconductor substrate 1321 and the through-hole wiring 1360.

[0192] 31F, when a plurality of through-wires 1360 are provided, the low dielectric constant region 1391 may be provided in the region between the through-wires 1360, in addition to the region between the second semiconductor substrate 1321 and the through-wires 1360. In such a case, the low dielectric constant region 1391 can also reduce the magnitude of parasitic capacitance occurring between the plurality of through-wires 1360.

[0193] 32A to 32C are plan views and longitudinal sectional views illustrating a second method for forming a low dielectric constant region 1391 in the first embodiment.

[0194] As shown in FIG. 32A, the second forming method is different from the first forming method in that wet etching is used to etch the isolation insulating layer 1353.

[0195] Specifically, as shown in FIG. 32A, first, lithography using a hard mask is performed, and the second insulating layer 1352 is removed, and then an opening 1393 is provided in the SiN film 1365.

[0196] 32B, a wet etching solution (e.g., a hydrogen fluoride solution) is applied to the isolation insulating layer 1353 through the opening 1393 formed in the SiN film 1365. This wet-etches the isolation insulating layer 1353, and a gap can be formed in the region between the second semiconductor substrate 1321 and the through-wire 1360.

[0197] In wet etching, compared to dry etching, the etching region spreads isotropically, so that the shape of the void becomes circular or spherical in the in-plane direction and stacking direction of the second semiconductor substrate 1321. Therefore, even if the size of the opening 1393 provided in the SiN film 1365 is small, a large void can be formed in the isolation insulating layer 1353.

[0198] The depth of the wet etching into the first insulating layer 1342 can be controlled by the formation position of the SiN film, which has an etching rate different from that of the SiO2 film in the first insulating layer 1342. On the other hand, the spread of the wet etching in the in-plane direction of the separation insulating layer 1353 can be controlled by the etching time.

[0199] 32C, a low dielectric constant layer 1354 is deposited on the SiN film 1365 by using CVD or the like under conditions of low embedding property, thereby closing the opening 1393. As a result, the gap formed in the isolation insulating layer 1353 becomes a low dielectric constant region 1391. Note that as a material for forming the low dielectric constant layer 1354, a material known as a low-k material can be appropriately used. Thereafter, the low dielectric constant layer 1354 is planarized by CMP (Chemical Mechanical Polish), so that a wiring layer or the like can be further formed on the low dielectric constant layer 1354.

[0200] In the second formation method, since the opening surface area of ​​the opening provided for forming the void is small, it is possible to prevent the low-k material or the like from entering the void when forming the low dielectric constant layer 1354. Moreover, in the second formation method, it becomes easier to close the upper part of the void.

[0201] 33A to 33C are plan views and longitudinal sectional views showing variations in the formation of the opening 1393 shown in FIGS. 32A to 32C.

[0202] As described above, in wet etching, the etching region spreads isotropically. Therefore, when the range where wet etching is performed is strictly controlled as shown in Figures 33A to 33C, the region where low dielectric constant region 1391 is to be formed is defined in advance by SiN film 1367.

[0203] Specifically, lithography using a hard mask and deposition of a SiN film 1367 are sequentially performed to form an area in which the bottom and side surfaces are covered with a SiN film 1367 in the isolation insulating layer 1353. Thereafter, as shown in FIG. 33A, an opening 1393 is provided in the SiN film 1365 by lithography.

[0204] 33B, a wet etching solution (e.g., a hydrogen fluoride solution) is applied to the isolation insulating layer 1353 through the opening 1393 formed in the SiN film 1365. This wet-etches the isolation insulating layer 1353, and a gap can be formed in the region between the second semiconductor substrate 1321 and the through-wire 1360. At this time, the region where the wet etching solution acts on the isolation insulating layer 1353 is defined by the SiN film 1367, so that it is possible to prevent the wet etching solution from acting on unintended regions due to over-etching.

[0205] 33C, a low dielectric constant layer 1354 is deposited on the SiN film 1365 using CVD or the like under conditions of low embedding property, thereby closing the opening 1393. As a result, the void formed in the isolation insulating layer 1353 becomes a low dielectric constant region 1391. Thereafter, the low dielectric constant layer 1354 is planarized using CMP (Chemical Mechanical Polish), so that a wiring layer or the like can be further formed on the low dielectric constant layer 1354.

[0206] 34A to 34C are plan views and longitudinal sectional views showing variations in the shape of the low dielectric constant region 1391 in the first mode.

[0207] 34A, the low dielectric constant region 1391 is provided as a gap. The low dielectric constant region 1391 is provided in at least a partial region between the second semiconductor substrate 1321 and the through wiring 1360. The length of the low dielectric constant region 1391 in a direction perpendicular to the arrangement direction of the through wiring 1360 and the second semiconductor substrate 1321 in the plane of the second semiconductor substrate 1321 is preferably longer than both the through wiring 1360 and the second semiconductor substrate 1321. In addition, the formation depth of the low dielectric constant region 1391 in the stacking direction is preferably longer than the thickness of the second semiconductor substrate 1321.

[0208] 34B, the low dielectric constant region 1391 may be provided as a gap and adjacent to the through-hole wiring 1360. As long as the low dielectric constant region 1391 is a space between the second semiconductor substrate 1321 and the through-hole wiring 1360, the same effect can be obtained whether the low dielectric constant region 1391 is provided on the second semiconductor substrate 1321 side or on the through-hole wiring 1360 side.

[0209] 34C , the low dielectric constant region 1391 may be provided as a gap and adjacent to both the through-hole wiring 1360 and the second semiconductor substrate 1321. In such a case, the low dielectric constant region 1391 is provided over the entire region between the through-hole wiring 1360 and the second semiconductor substrate 1321.

[0210] 34A to 34C, the position of low dielectric constant region 1391 can be controlled by the position of opening 1393 when wet etching isolation insulating layer 1353. The size and depth of low dielectric constant region 1391 can be controlled by the process time of wet etching. Note that the size and depth of the region where low dielectric constant region 1391 is formed can also be controlled by arranging a structure that is difficult to wet etch, such as a SiN film, as necessary.

[0211] 35A to 35D are vertical cross-sectional views illustrating a third method for forming the low dielectric constant region 1391 in the first embodiment.

[0212] 35A, first, a portion of the second semiconductor substrate 1321, the SiN film 1371, and the SiO2 film 1372 formed over the entire surface of the first insulating layer 1342 is removed by etching to form an opening 1393. The opening 1393 is formed in a region where the isolation insulating layer 1353 is to be formed.

[0213] Next, as shown in FIG. 35B, a SiO2 film 1373 is formed along the shape of the opening 1393 to improve the adhesion of the organic resin 1394. After that, the organic resin 1394 is filled in the region of the opening 1393 that forms the low dielectric constant region 1391, and a SiO2 film (not shown) is filled in the region of the opening 1393 that forms the isolation insulating layer 1353. That is, in the region where the opening 1393 is formed, a part of the region between the through wiring 1360 and the second semiconductor substrate 1321 is filled with the organic resin 1394 that will be removed in a later process and become a void. The organic resin 1394 can be an organic low-k material, and can be, for example, a polyaryl ether (PAE) resin represented by SiLK (registered trademark, Dow Corning).

[0214] 35C, a gate electrode 1322 is provided on the second semiconductor substrate 1321 via a gate insulating film (not shown), thereby forming a field effect transistor Tr2. A gate contact 1359 and a source or drain contact 1358 are electrically connected to the gate electrode 1322 of the field effect transistor Tr2 and the source or drain region of the second semiconductor substrate 1321, respectively. A SiN film 1365 functioning as a stress liner film or an etching stopper film is formed on the surfaces of the second semiconductor substrate 1321 and the gate electrode 1322.

[0215] Furthermore, in the isolation insulating layer 1353, in a region not shown, through wiring 1360 is formed to electrically connect various wirings of the first substrate 10 and various wirings of the second substrate 20. For example, the through wiring 1360 may be provided so as to penetrate the isolation insulating layer 1353 and the first insulating layer 1342.

[0216] 35D, organic resin 1394 embedded in isolation insulating layer 1353 is removed by reactive ion etching (RIE) via a through hole reaching organic resin 1394. This makes it possible to form a gap that will become low dielectric constant region 1391 in the region embedded with organic resin 1394. According to the third formation method, it is possible to selectively form a gap that will become low dielectric constant region 1391 in the region embedded with organic resin 1394.

[0217] 36A to 36C are vertical cross-sectional views illustrating a variation of the third method for forming the low dielectric constant region 1391 in the first embodiment.

[0218] 35A, a portion of the second semiconductor substrate 1321, the SiN film 1371, and the SiO2 film 1372 formed over the entire surface of the first insulating layer 1342 is removed by etching to form an opening 1393. Next, as shown in FIG. 36A, the opening 1393 is temporarily filled with an isolation insulating layer 1353, and then the isolation insulating layer 1353 in a region where a low dielectric constant region 1391 is to be formed is selectively removed by lithography and etching, and an organic resin 1394 is filled in.

[0219] 36C, in the same manner as in the process shown in FIG. 35C, a field effect transistor Tr2 is formed on the second semiconductor substrate 1321, and a gate contact 1359 and a source or drain contact 1358 are electrically connected to each terminal of the field effect transistor Tr2. Furthermore, in a region not shown in the figure, a through wiring 1360 is formed in the isolation insulating layer 1353 so as to penetrate the isolation insulating layer 1353 and the first insulating layer 1342, electrically connecting various wirings of the first substrate 10 and various wirings of the second substrate 20.

[0220] 36D, similarly to the process shown in FIG 35D, the organic resin 1394 embedded in the isolation insulating layer 1353 is removed by reactive ion etching (RIE) via the through-hole that reaches the organic resin 1394. This makes it possible to form a gap that becomes the low dielectric constant region 1391 in the region where the organic resin 1394 is embedded.

[0221] 36A to 36D, the region filled with organic resin 1394 can be more precisely controlled. Therefore, it is possible to prevent the presence of organic resin 1394 from making it more difficult to form through wiring 1360.

[0222] 37A to 37C are vertical cross-sectional views illustrating a fourth method for forming a low dielectric constant region 1391 in the first embodiment.

[0223] As shown in Figures 37A to 37C, in the fourth method for forming the low dielectric constant region 1391, the low dielectric constant region 1391 is formed in a region surrounded by a SiN film 1365 around the through wiring 1360 that electrically connects the first substrate 10 and the second substrate 20.

[0224] Specifically, the first substrate 10 is formed by laminating a first insulating layer 1342 on the first semiconductor substrate 1311, and the second substrate 20 is formed by laminating a second insulating layer 1352 on the second semiconductor substrate 1321. A photodiode (not shown) is provided on the first substrate 10, and a field effect transistor Tr2 (also called a pixel transistor) that processes a signal charge photoelectrically converted by the photodiode is provided on the second substrate 20. Each wiring or each terminal provided on the first substrate 10 is electrically connected to a gate electrode 1359, for example, via a gate contact 1359, by a through wiring 1360 that passes through an isolation insulating layer 1353 provided to penetrate the second semiconductor substrate 1321. The area around the through wiring 1360 provided on the side of the second semiconductor substrate 1321 is surrounded by a SiN film 1365, and the low dielectric constant region 1391 is provided in the area surrounded by the SiN film 1365.

[0225] A method for forming such low dielectric constant region 1391 will be described with reference to FIGS. 37A to 37C.

[0226] 37A, for example, a SiN film 1365 is formed so as to surround a part or the entire region of the isolation insulating layer 1353 of the second substrate 20. Then, a through wiring 1360 is formed so as to penetrate the region surrounded by the SiN film 1365. As a result, the SiN film 1365 is provided on the side of the second semiconductor substrate 1321 so as to surround the region around the through wiring 1360. Note that the SiN film 1365 may be provided continuously with, for example, the sidewall insulating film 1322S of the gate electrode 1322 of the field effect transistor Tr2.

[0227] 37B, an opening 1393 is formed by lithography and reactive ion etching (RIE) that penetrates the second insulating layer 1352 and the upper SiN film 1365 and reaches the inside of the region surrounded by the SiN film 1365. Then, a SiN film 1366 is formed along the inner side surface of the opening 1393 that exposes the second insulating layer 1352.

[0228] 37C, an etching solution is poured into the region surrounded by the SiN film 1365 through the opening 1393 to perform wet etching, and the isolation insulating layer 1353 inside the region surrounded by the SiN film 1365 is removed. As a result, a low dielectric constant region 1391, which is a void, is formed around the through-wire 1360. The low dielectric constant region 1391 may remain a void, or may be filled with a low-k material such as carbon-doped silicon (SiOC) or porous silica.

[0229] According to the fourth method for forming the low dielectric constant region 1391, the area in which the low dielectric constant region 1391 is formed can be limited to the area surrounded by the SiN film 1365, thereby suppressing variation in the shape or size of the low dielectric constant region 1391.

[0230] Moreover, in the fourth formation method, by previously forming a region surrounded by the SiN film 1365 in the isolation insulating layer 1353, the additional steps required for forming the low dielectric constant region 1391 can be limited to lithography, RIE etching, and wet etching. Therefore, the fourth formation method can form the low dielectric constant region 1391 at a lower cost.

[0231] (Second mode) The second aspect of the technology according to this embodiment will be described in more detail below with reference to FIGS. 38A to 42E.

[0232] 38A to 38D are vertical cross-sectional views illustrating a first method for forming a low dielectric constant region 1392 in the second embodiment.

[0233] As shown in FIG. 38A, first, an opening is made in a part of the first insulating layer 1342 of the first substrate 10, and a SiN film 1343 is deposited along the shape of the opening.

[0234] 38B, second semiconductor substrate 1321 held by support substrate 1380 and insulating layer 1344 are bonded to first insulating layer 1342 with the opening formed therein. Since the surface of insulating layer 1344 facing the opening formed in first insulating layer 1342 is flat, low dielectric constant region 1392 consisting of a gap is formed between the opening formed in first insulating layer 1342 and insulating layer 1344.

[0235] 38C, after the support substrate 1380 is peeled off, a SiN film 1371 and a SiO2 film 1372 are formed on the second semiconductor substrate 1321. Then, partial regions of the second semiconductor substrate 1321, the SiN film 1371, and the SiO2 film 1372 are removed by etching.

[0236] Next, as shown in FIG. 38D, the region removed by etching is filled with an isolation insulating layer 1353 to form a field effect transistor Tr2 and a through-hole wiring 1360. Specifically, a gate electrode 1322 is provided on a second semiconductor substrate 1321 via a gate insulating film (not shown), to form a field effect transistor Tr2. A gate contact 1359 and a source or drain contact 1358 are electrically connected to the gate electrode 1322 of the field effect transistor Tr2 and the source or drain region of the second semiconductor substrate 1321, respectively. A SiN film 1365 functioning as a stress liner film or an etching stopper film is formed on the surfaces of the second semiconductor substrate 1321 and the gate electrode 1322.

[0237] Furthermore, in the isolation insulating layer 1353, in a region not shown, through wiring 1360 is formed to electrically connect various wirings of the first substrate 10 and various wirings of the second substrate 20. For example, the through wiring 1360 may be provided so as to penetrate the isolation insulating layer 1353 and the first insulating layer 1342.

[0238] According to this, with a relatively small number of additional steps, the low dielectric constant region 1392 consisting of a gap can be formed below the second semiconductor substrate 1321. The low dielectric constant region 1392 has, for example, a rectangular shape, and can be formed in a region inside the planar region of the second semiconductor substrate 1321.

[0239] 39A to 39D are plan views showing variations in the shape of the low dielectric constant region 1392 in the second embodiment.

[0240] As shown in FIG. 39A, the low dielectric constant region 1392 provided as a void may be provided so as to extend to the outside of the planar region of the second semiconductor substrate 1321. As shown in FIG. 39B, the low dielectric constant region 1392 provided as a void may be provided in a plurality of rectangular shapes arranged parallel to each other. As shown in FIG. 39C, the low dielectric constant region 1392 provided as a void may be provided in a region larger than the planar region of the second semiconductor substrate 1321. Furthermore, as shown in FIG. 39D, the low dielectric constant region 1392 provided as a void may be provided in a plurality of rectangular shapes arranged parallel to each other and extending to the outside of the planar region of the second semiconductor substrate 1321.

[0241] In the first formation method, an insulating layer 1344 is provided between the low dielectric constant region 1392 and the second semiconductor substrate 1321. Therefore, the low dielectric constant region 1392 and the second semiconductor substrate 1321 can have planar shapes independent of each other.

[0242] Next, FIGS. 40A to 40D are vertical cross-sectional views illustrating a second method for forming the low dielectric constant region 1392 in the second embodiment.

[0243] 40A and 40B, a second semiconductor substrate 1321 held by a support substrate 1380 and an insulating layer 1344 are bonded to a first substrate 10 having a SiN film 1343 formed on a first insulating layer 1342. A part of the insulating layer 1344 provided on the second semiconductor substrate 1321 is opened, and a low dielectric constant region 1392 consisting of a gap is formed between the rear surface of the second semiconductor substrate 1321, the opening formed in the insulating layer 1344, and the SiN film 1343 on the first insulating layer 1342.

[0244] 40C, after the support substrate 1380 is peeled off, a SiN film 1371 and a SiO2 film 1372 are formed on the second semiconductor substrate 1321. Then, partial regions of the second semiconductor substrate 1321, the SiN film 1371, and the SiO2 film 1372 are removed by etching.

[0245] Next, as shown in FIG. 40D, the region removed by etching is filled with an isolation insulating layer 1353 to form a field effect transistor Tr2 and a through-hole wiring 1360. Specifically, a gate electrode 1322 is provided on a second semiconductor substrate 1321 via a gate insulating film (not shown), to form a field effect transistor Tr2. A gate contact 1359 and a source or drain contact 1358 are electrically connected to the gate electrode 1322 of the field effect transistor Tr2 and the source or drain region of the second semiconductor substrate 1321, respectively. A SiN film 1365 functioning as a stress liner film or an etching stopper film is formed on the surfaces of the second semiconductor substrate 1321 and the gate electrode 1322.

[0246] Furthermore, in the isolation insulating layer 1353, in a region not shown, through wiring 1360 is formed to electrically connect various wirings of the first substrate 10 and various wirings of the second substrate 20. For example, the through wiring 1360 may be provided so as to penetrate the isolation insulating layer 1353 and the first insulating layer 1342.

[0247] According to this, similarly to the first forming method, a low dielectric constant region 1392 consisting of a gap can be formed below the second semiconductor substrate 1321. The low dielectric constant region 1392 has, for example, a rectangular shape, and can be formed in a region inside the planar region of the second semiconductor substrate 1321.

[0248] In the second formation method, the back surface of the second semiconductor substrate 1321 is exposed to the low dielectric constant region 1390. Therefore, the low dielectric constant region 1392 can have any planar shape except for the case where the planar area of ​​the low dielectric constant region 1392 is larger than the planar area of ​​the second semiconductor substrate 1321 as shown in FIG.

[0249] 41A to 41E are vertical cross-sectional views illustrating a third method for forming the low dielectric constant region 1932 in the second embodiment.

[0250] As shown in Figures 41A and 41B, a second semiconductor substrate 1321 supported by a support substrate 1380 and an insulating layer 1344 containing organic resin 1394 are bonded to a first substrate 10 having a SiN film 1343 formed on a first insulating layer 1342.

[0251] Here, an opening is formed in the insulating layer 1344 provided on the second semiconductor substrate 1321, and the formed opening is filled with an organic resin 1394 made of an organic low-k material. As the organic low-k material, for example, a polyaryl ether (PAE) resin represented by SiLK (registered trademark, Dow Corning) can be used. The organic resin 1394 made of the organic low-k material is selectively removed in a later stage to form a low dielectric constant region 1390 made of a void.

[0252] 41C, after the support substrate 1380 is peeled off, a SiN film 1371 and a SiO2 film 1372 are formed on the second semiconductor substrate 1321. Then, partial regions of the second semiconductor substrate 1321, the SiN film 1371, and the SiO2 film 1372 are removed by etching. As a result, the organic resin 1394 provided on the second semiconductor substrate 1321 is exposed from the side surface of the second semiconductor substrate 1321.

[0253] 41D, the exposed organic resin 1394 is removed by reactive ion etching (RIE). As a result, a low dielectric constant region 1392 consisting of a void is formed below the second semiconductor substrate 1321.

[0254] Next, as shown in FIG. 41E, the region removed by etching in the process shown in FIG. 41C is filled with an isolation insulating layer 1353 to form a field effect transistor Tr2 and a through-hole wiring 1360. Specifically, a gate electrode 1322 is provided on a second semiconductor substrate 1321 via a gate insulating film (not shown), to form a field effect transistor Tr2. A gate contact 1359 and a source or drain contact 1358 are electrically connected to the gate electrode 1322 of the field effect transistor Tr2 and the source or drain region of the second semiconductor substrate 1321, respectively. A SiN film 1365 functioning as a stress liner film or an etching stopper film is formed on the surfaces of the second semiconductor substrate 1321 and the gate electrode 1322.

[0255] Furthermore, in the isolation insulating layer 1353, in a region not shown, through wiring 1360 is formed to electrically connect various wirings of the first substrate 10 and various wirings of the second substrate 20. For example, the through wiring 1360 may be provided so as to penetrate the isolation insulating layer 1353 and the first insulating layer 1342.

[0256] According to this, similarly to the first forming method, low dielectric constant regions 1392 consisting of voids can be formed below the second semiconductor substrate 1321. The low dielectric constant regions 1392 can be formed, for example, as a plurality of rectangular shapes extending from one side to the other side of the planar region of the second semiconductor substrate 1321.

[0257] In the third formation method, the organic resin 1394 is exposed by etching when forming the isolation insulating layer 1353, and the organic resin 1394 is removed by RIE in a subsequent stage. Therefore, the low dielectric constant region 1392 can have any planar shape except for the case where the planar region of the low dielectric constant region 1392 is included inside the planar region of the second semiconductor substrate 1321 as shown in Figures 38D and 39B, and the case where the planar region of the low dielectric constant region 1392 is larger than the planar region of the second semiconductor substrate 1321 as shown in Figure 39C.

[0258] 42A to 42E are vertical cross-sectional views illustrating a fourth method for forming the low dielectric constant region 1932 in the second embodiment.

[0259] As shown in Figures 42A and 42B, a second semiconductor substrate 1321 supported by a support substrate 1380 and an insulating layer 1344 containing organic resin 1394 are bonded to a first substrate 10 having a SiN film 1343 formed on a first insulating layer 1342.

[0260] Here, an opening is formed in the insulating layer 1344 provided on the second semiconductor substrate 1321, and the formed opening is filled with an organic resin 1394 made of an organic low-k material. As the organic low-k material, for example, a polyaryl ether (PAE) resin represented by SiLK (registered trademark, Dow Corning) can be used. The organic resin 1394 made of the organic low-k material is selectively removed in a later step to form a low dielectric constant region 1390 made of a void. The fourth forming method is different from the third forming method in that the region where the organic resin 1394 is formed is only below the second semiconductor substrate 1321.

[0261] 42C, after the support substrate 1380 is peeled off, a SiN film 1371 and a SiO2 film 1372 are formed on the second semiconductor substrate 1321. Then, partial regions of the second semiconductor substrate 1321, the SiN film 1371, and the SiO2 film 1372 are removed by etching. As a result, the organic resin 1394 provided on the second semiconductor substrate 1321 is exposed from the side surface of the second semiconductor substrate 1321.

[0262] 42D, the exposed organic resin 1394 is removed by reactive ion etching (RIE). As a result, a low dielectric constant region 1392 consisting of a void is formed below the second semiconductor substrate 1321.

[0263] Next, as shown in FIG. 42E, the region removed by etching in the process shown in FIG. 42C is filled with an isolation insulating layer 1353 to form a field effect transistor Tr2 and a through-hole wiring 1360. Specifically, a gate electrode 1322 is provided on a second semiconductor substrate 1321 via a gate insulating film (not shown), to form a field effect transistor Tr2. A gate contact 1359 and a source or drain contact 1358 are electrically connected to the gate electrode 1322 of the field effect transistor Tr2 and the source or drain region of the second semiconductor substrate 1321, respectively. A SiN film 1365 functioning as a stress liner film or an etching stopper film is formed on the surfaces of the second semiconductor substrate 1321 and the gate electrode 1322.

[0264] Furthermore, in the isolation insulating layer 1353, in a region not shown, through wiring 1360 is formed to electrically connect various wirings of the first substrate 10 and various wirings of the second substrate 20. For example, the through wiring 1360 may be provided so as to penetrate the isolation insulating layer 1353 and the first insulating layer 1342.

[0265] According to this, similarly to the first forming method, a low dielectric constant region 1392 consisting of a gap can be formed below the second semiconductor substrate 1321. The low dielectric constant region 1392 can be formed, for example, in a rectangular shape extending from one side to the other side of the planar region of the second semiconductor substrate 1321.

[0266] In the fourth formation method, the organic resin 1394 is exposed by etching when forming the isolation insulating layer 1353, and the organic resin 1394 is removed by RIE in a subsequent stage. Therefore, the low dielectric constant region 1392 can have any planar shape except for the case where the planar region of the low dielectric constant region 1392 is included inside the planar region of the second semiconductor substrate 1321 as shown in Figures 38D and 39B, and the case where the planar region of the low dielectric constant region 1392 is larger than the planar region of the second semiconductor substrate 1321 as shown in Figure 39C.

[0267] The technology according to the third embodiment of the present disclosure has been described in detail above. According to the technology according to this embodiment, it is possible to reduce the magnitude of the parasitic capacitance generated between the second semiconductor substrate 21 and the through-hole wiring 54 or the transfer gate TG, etc. Therefore, according to the technology according to this embodiment, it is possible to improve the electrical characteristics of the field-effect transistor provided on the second semiconductor substrate 21 in the imaging device 1 having a three-dimensional structure.

[0268] <<5. Modifications>> Below, a description will be given of a modification of the imaging device 1 to which the technology according to the present disclosure is applied.

[0269] (First Modification) First, a first modified example, which is a modified example of the cross-sectional configuration in the stacking direction of the imaging device 1, will be described with reference to Fig. 43. Fig. 43 is a vertical cross-sectional view showing a modified example of the cross-sectional configuration shown in Fig. 7.

[0270] 43, in the imaging device 1 according to the first modification, the transfer transistor TR has a planar transfer gate TG. Therefore, the transfer gate TG does not penetrate the p-well layer 42, but is formed on the surface of the first semiconductor substrate 11. Even when the planar transfer gate TG is used for the transfer transistor TR, the imaging device 1 can achieve the same effects as those described above.

[0271] (Second Modification) Next, a second modification which is a modification of the cross-sectional configuration in the stacking direction of the imaging device 1 will be described with reference to Fig. 44. Fig. 44 is a vertical cross-sectional view showing a modification of the cross-sectional configuration shown in Fig. 7.

[0272] As shown in FIG. 44, in the imaging device 1 according to the second modification, the second substrate 20 and the third substrate 30 are electrically connected in a region corresponding to the peripheral region 14 in the first substrate 10. The peripheral region 14 is a region corresponding to a frame region provided on the periphery of the pixel region 13 of the first substrate 10. In the imaging device 1 according to the second modification, the second substrate 20 has a plurality of pad electrodes 58 in a region corresponding to the peripheral region 14, and the third substrate 30 has a plurality of pad electrodes 64 in a region corresponding to the peripheral region 14. As a result, the second substrate 20 and the third substrate 30 are electrically connected to each other by bonding the pad electrodes 58, 64 provided in the region corresponding to the peripheral region 14. Therefore, in the imaging device 1 according to the second modification, the possibility that the bonding of the pad electrodes 58, 64 affects the pixel region 13 can be reduced compared to the case where the pad electrodes 58, 64 are bonded to each other in the region corresponding to the pixel region 13.

[0273] (Third Modification) Further, with reference to Figs. 45 to 50, a configuration example of an imaging device 1B according to a third modified example will be described. Figs. 45 to 47 are cross-sectional views in the thickness direction showing a configuration example of an imaging device 1B according to a third modified example. Figs. 48 to 50 are cross-sectional views in the horizontal direction showing a layout example of a plurality of pixel units PU of an imaging device 1B according to a third modified example. Note that the cross-sectional views shown in Figs. 48 to 50 are merely schematic views, and are not intended to strictly and correctly show the actual structure. In the cross-sectional views shown in Figs. 48 to 50, the horizontal positions of the transistors and impurity diffusion layers are intentionally changed from position sec1 to sec3 in order to easily explain the configuration of the imaging device 1B on paper.

[0274] Specifically, in pixel unit PU of imaging device 1B shown in Fig. 45, the cross section at position sec1 corresponds to the cross section taken along line A1-A1' in Fig. 48, the cross section at position sec2 corresponds to the cross section taken along line B1-B1' in Fig. 49, and the cross section at position sec3 corresponds to the cross section taken along line C1-C1' in Fig. 50. Similarly, in imaging device 1B shown in Fig. 46, the cross section at position sec1 corresponds to the cross section taken along line A2-A2' in Fig. 48, the cross section at position sec2 corresponds to the cross section taken along line B2-B2' in Fig. 49, and the cross section at position sec3 corresponds to the cross section taken along line C2-C2' in Fig. 50. In the imaging device 1B shown in Figure 47, the cross section at position sec1 corresponds to the cross section of Figure 48 taken along line A3-A3', the cross section at position sec2 corresponds to the cross section of Figure 49 taken along line B3-B3', and the cross section at position sec3 corresponds to the cross section of Figure 50 taken along line C3-C3'.

[0275] 45 to 50, a second substrate 20 is laminated on a front surface 10a (one surface) of a first substrate (bottom substrate) 10. A photodiode PD, a transfer transistor TR, and a floating diffusion FD are provided on the front surface 10a of the first substrate 10. The photodiode PD, the transfer transistor TR, and the floating diffusion FD are provided for each sensor pixel 12.

[0276] The other surface (for example, the back surface) of the first substrate 10 is a light incidence surface. The imaging device 1B is a back-illuminated imaging device, and a color filter and a light receiving lens are provided on the back surface. The color filter and the light receiving lens are provided for each sensor pixel 12.

[0277] The first semiconductor substrate 11 of the first substrate 10 is made of, for example, a silicon substrate. A well layer WE of a first conductivity type (e.g., p-type) is provided on and near a part of the front surface of the first semiconductor substrate 11, and a photodiode PD of a second conductivity type (e.g., n-type) is provided in a region deeper than the well layer WE. In addition, a well contact layer having a higher p-type concentration than the well layer WE and an n-type floating diffusion FD are provided in the well layer WE. The well contact layer is provided to reduce contact resistance between the well layer WE and the wiring.

[0278] The first semiconductor substrate 11 is provided with an element isolation layer 16 that electrically isolates the adjacent sensor pixels 12 from each other. The element isolation layer 16 has, for example, an STI (Shallow Trench Isolation) structure and extends in the depth direction of the first semiconductor substrate 11. The element isolation layer 16 is made of, for example, silicon oxide. In addition, in the first semiconductor substrate 11, an impurity diffusion layer 17 is provided between the element isolation layer 16 and the photodiode PD. For example, the impurity diffusion layer 17 has a p-type layer and an n-type layer that are extended in the thickness direction of the first semiconductor substrate 11. The p-type layer is located on the element isolation layer 16 side, and the n-type layer is located on the photodiode PD side.

[0279] An insulating film 2015 is provided on the front surface 11a side of the first semiconductor substrate 11. The insulating film 2015 is, for example, one of a silicon oxide film (SiO), a silicon nitride film (SiN), a silicon oxynitride film (SiON), or a silicon carbonitride film (SiCN), or a film formed by stacking two or more of these films.

[0280] The second substrate 20 has a lower substrate 2210 and an upper substrate 2220. The lower substrate 2210 has a semiconductor substrate 2211. The semiconductor substrate 2211 is a silicon substrate made of, for example, single crystal silicon. An amplification transistor AMP and an element isolation layer 2213 surrounding the periphery of the amplification transistor AMP are provided on one surface (for example, the front surface 2211a) of the semiconductor substrate 2211. The element isolation layer 2213 electrically isolates one amplification transistor AMP from the other amplification transistor AMP of adjacent pixel units PU.

[0281] The lower substrate 2210 has an insulating film 2215 covering the front surface 2211a of the semiconductor substrate 2211. The insulating film 2215 covers the amplifying transistor AMP and the element isolation layer 2213. The lower substrate 2210 also has an insulating film 2217 covering the other surface (e.g., the back surface 2211b) of the semiconductor substrate 2211. The insulating films 2215 and 2217 are, for example, one of SiO, SiN, SiON, and SiCN, or a film in which two or more of these are laminated. The insulating film 2015 of the first substrate 10 and the insulating film 2217 of the lower substrate 2210 are bonded to each other to form an interlayer insulating film 2051.

[0282] The upper substrate 2220 has a semiconductor substrate 2221. The semiconductor substrate 2221 is, for example, a silicon substrate made of single crystal silicon. A reset transistor RST, a select transistor SEL, and an element isolation layer 2223 are provided on one surface (for example, a front surface 2221a) of the semiconductor substrate 2221. For example, the element isolation layer 2223 is provided between the reset transistor RST and the select transistor SEL, and between the select transistor SEL and a well layer of the semiconductor substrate 2221.

[0283] The upper substrate 2220 has an insulating film 2225 that covers the front surface 2221a, the back surface 2221b, and the side surfaces of the semiconductor substrate 2221. The insulating film 2225 is, for example, one of SiO, SiN, SiON, and SiCN, or a film in which two or more of these are laminated. The insulating film 2215 of the lower substrate 2210 and the insulating film 2225 of the upper substrate 2220 are bonded to each other to form an interlayer insulating film 2053.

[0284] The imaging device 1B includes a plurality of wirings L1 to L10 provided in the interlayer insulating films 2051 and 2053 and electrically connected to at least one of the first substrate 10 and the second substrate 20. The wiring L1 electrically connects the drain of the amplification transistor AMP to a power supply line VDD. The wiring L2 electrically connects four floating diffusions FD included in one pixel unit PU to a gate electrode AG of the amplification transistor AMP. The wiring L3 electrically connects the source of the amplification transistor AMP to the drain of the selection transistor SEL. The wiring L4 electrically connects the gate electrode SG of the selection transistor SEL to a pixel drive line.

[0285] The wiring L5 electrically connects the source of the selection transistor SEL to the vertical signal line. The wiring L6 electrically connects the drain of the reset transistor RST to the power supply line VDD. The wiring L7 electrically connects the gate electrode RG of the reset transistor RST to the pixel drive line. The wiring L8 electrically connects the source of the reset transistor RST to the wiring L2. The wiring L9 electrically connects the gate electrode TG of the transfer transistor TR to the pixel drive line. The wiring L10 electrically connects the well contact layer to a reference potential line that supplies a reference potential (e.g., ground potential: 0V).

[0286] In the wirings L1 to L10, the portions extending in the thickness direction of the laminate are made of tungsten (W), and the portions extending in a direction perpendicular to the thickness direction of the laminate (for example, the horizontal direction) are made of copper (Cu) or a Cu alloy mainly composed of Cu. However, the materials constituting the wirings L1 to L10 are not limited to these, and may be made of other materials.

[0287] The second substrate 20 has a plurality of pad electrodes 2227 connected to any of the above-mentioned wirings L1 to L10 (for example, wirings L1, L4 to L7, L9, and L10). The plurality of pad electrodes 2227 are made of, for example, Cu or a Cu alloy.

[0288] The third substrate 30 is disposed on the opposite side (for example, the front surface side) of the surface of the second substrate 20 facing the first substrate 10. The third substrate 30 includes a semiconductor substrate 2301, an insulating film 2304 covering the front surface 2301a side of the semiconductor substrate 2301, a plurality of wirings L30 provided on the front surface 2301a side of the semiconductor substrate 2301, and pad electrodes 2305 connected to the plurality of wirings L30, respectively. Note that the front surfaces of the third substrate 30 and the second substrate 20 are bonded together as described later. Therefore, the front surface 2301a of the semiconductor substrate 2301 faces downward.

[0289] The semiconductor substrate 2301 is, for example, a silicon substrate made of single crystal silicon. A plurality of transistors and impurity diffusion layers constituting a logic circuit are provided on the front surface 2301a side of the semiconductor substrate 2301. An insulating film 2304 covers the plurality of transistors and impurity diffusion layers constituting the logic circuit. The insulating film 2304 is provided with contact holes connected to these transistors and impurity diffusion layers.

[0290] The wiring L30 is provided in the contact hole. In the wiring L30, a portion extending in the thickness direction of the third substrate 30 is made of titanium (Ti) or cobalt (Co), and a portion extending in a direction perpendicular to the thickness direction of the third substrate 30 (for example, the horizontal direction) is made of Cu or a Cu alloy mainly composed of Cu. However, the material constituting the wiring L30 is not limited to these, and may be made of other materials.

[0291] A silicide 2303 (e.g., titanium silicide (TiSi) or cobalt silicide (CoSi2)) is formed at the connection between the wiring L30 and the semiconductor substrate 2301. The silicide 2303 makes the connection between the wiring L30 and the semiconductor substrate 2301 closer to an ohmic contact, and reduces the contact resistance. This increases the operation speed of the logic circuit.

[0292] Note that silicide is not formed on the first substrate 10 and the second substrate 20. This allows heat treatment at a temperature exceeding the heat resistance temperature of the silicide when forming the first substrate 10 and the second substrate 20. However, silicide may be formed on at least one of the first substrate 10 and the second substrate 20.

[0293] The multiple pad electrodes 2305 are made of, for example, Cu or a Cu alloy. In the thickness direction of the imaging device 1B, the pad electrodes 2305 of the third substrate 30 face and are electrically connected to the pad electrodes 2227 of the second substrate 20. For example, the pad electrodes 2305, 2227 are integrated by Cu-Cu bonding while facing each other. This electrically connects the second substrate 20 and the third substrate 30, and increases the strength of the bonding between the second substrate 20 and the third substrate 30.

[0294] In the imaging device 1B according to the third modification, one floating diffusion contact may be arranged for each of the plurality of sensor pixels 12. For example, four adjacent sensor pixels 12 may share one floating diffusion contact. Similarly, one well contact may be arranged for each of the plurality of sensor pixels 12. For example, four adjacent sensor pixels 12 may share one well contact.

[0295] Specifically, as shown in FIGS. 46 and 50, the imaging device 1B may share a common pad electrode 2102 arranged across a plurality of sensor pixels 12 and one wiring L2 provided on the common pad electrode 2102. For example, the imaging device 1B has an area in which the floating diffusions FD1 to FD4 of the four sensor pixels 12 are adjacent to each other via the element isolation layer 16 in a plan view. The common pad electrode 2102 is provided in this area. The common pad electrode 2102 is arranged across the four floating diffusions FD1 to FD4 and is electrically connected to each of the four floating diffusions FD1 to FD4. The common pad electrode 2102 is made of, for example, a polysilicon film doped with n-type impurities or p-type impurities.

[0296] Also, one wiring L2 (i.e., a contact for floating diffusion) is provided on the center of the common pad electrode 2102. As shown in Fig. 46 and Fig. 48 to Fig. 50, the wiring L2 provided on the center of the common pad electrode 2102 extends from the first substrate 10 through the lower substrate 2210 of the second substrate 20 to the upper substrate 2220 of the second substrate 20, and is connected to the gate electrode AG of the amplification transistor AMP via wiring provided on the upper substrate 2220, etc.

[0297] As shown in FIG. 45 and FIG. 50, the imaging device 1B may share a common pad electrode 2110 arranged across a plurality of sensor pixels 12 and one wiring L10 provided on the common pad electrode 2110. For example, the imaging device 1B has an area in which the well layers WE of the four sensor pixels 12 are adjacent to each other via the element isolation layer 16 in a plan view. The common pad electrode 2110 is provided in this area. The common pad electrode 2110 is arranged across the well layers WE of the four sensor pixels 12 and is electrically connected to each of the well layers WE of the four sensor pixels 12. As an example, the common pad electrode 2110 is arranged between one common pad electrode 2102 and the other common pad electrode 2102 arranged in the Y-axis direction. In the Y-axis direction, the common pad electrodes 2102 and 2110 are arranged alternately. The common pad electrode 2110 is made of, for example, a polysilicon film doped with n-type impurities or p-type impurities.

[0298] Also, one wiring L10 (i.e., a well contact) is provided on the center of the common pad electrode 2110. As shown in Fig. 45 and Figs. 48 to 50, the wiring L10 provided on the center of the common pad electrode 2110 extends from the first substrate 10 through the lower substrate 2210 of the second substrate 20 to the upper substrate 2220 of the second substrate 20, and is connected to a reference potential line that supplies a reference potential (for example, ground potential: 0V) via a wiring or the like provided on the upper substrate 2220.

[0299] The wiring L10 provided on the center of the common pad electrode 2110 is electrically connected to the upper surface of the common pad electrode 2110, the inner side surface of the through hole provided in the lower substrate 2210, and the inner side surface of the through hole provided in the upper substrate 2220. As a result, the well layer WE of the first semiconductor substrate 11 of the first substrate 10, the well layer of the lower substrate 2210 of the second substrate 20, and the well layer of the upper substrate 2220 are connected to a reference potential (for example, ground potential: 0 V).

[0300] The imaging device 1B according to the third modification further includes common pad electrodes 2102, 2110 provided on the front surface 11a side of the first semiconductor substrate 11 constituting the first substrate 10 and arranged to straddle a plurality of (for example, four) sensor pixels 12 adjacent to each other. The common pad electrode 2102 is electrically connected to the floating diffusions FD of the four sensor pixels 12, so that the wiring L2 connected to the floating diffusions FD can be shared for each of the four sensor pixels 12. In addition, the common pad electrode 2110 is electrically connected to the well layers WE of the four sensor pixels 12, so that the wiring L10 connected to the well layers WE can be shared for each of the four sensor pixels 12. This reduces the number of wirings L2, L10, so that the area of ​​the sensor pixels 12 can be reduced, and the imaging device 1B can be made smaller.

[0301] (Fourth Modification) Next, a fourth modified example which is a modified example of the horizontal cross-sectional configuration of the imaging device 1 will be described with reference to Fig. 51 and Fig. 52. The upper diagrams of Fig. 51 and Fig. 52 are schematic diagrams showing a modified example of the cross-sectional configuration of the cut surface Sec1 in Fig. 7, and the lower diagrams of Fig. 51 and Fig. 52 are schematic diagrams showing a modified example of the cross-sectional configuration of the cut surface Sec2 in Fig. 7.

[0302] 51 and 52, the plurality of through wirings 54, the plurality of through wirings 48, and the plurality of through wirings 47 are arranged in a band shape in a first direction V1 (left-right direction in FIGS. 51 and 52) within the plane of the first substrate 10. In FIGS. 51 and 52, a case is illustrated in which the plurality of through wirings 54, the plurality of through wirings 48, and the plurality of through wirings 47 are arranged in two rows in the first direction V1.

[0303] In the four sensor pixels 12 that share the pixel circuit 22, the four floating diffusions FD are arranged close to each other via, for example, an element isolation portion 43. In the four sensor pixels 12 that share the pixel circuit 22, the four transfer gates TG (TG1, TG2, TG3, TG4) are arranged to surround the four floating diffusions FD. For example, the four transfer gates TG are arranged to form a circular ring shape.

[0304] The isolation insulating layer 53 is composed of a plurality of blocks extending in the first direction V1. The second semiconductor substrate 21 is composed of a plurality of island-shaped blocks 21A extending in the first direction V1 and arranged side by side in the first direction V1. Each of the blocks 21A includes, for example, a reset transistor RST, an amplification transistor AMP, and a selection transistor SEL. One pixel circuit 22 shared by four sensor pixels 12 is not arranged corresponding to the four sensor pixels 12, but is arranged shifted in the second direction V2.

[0305] 51, one pixel circuit 22 shared by four sensor pixels 12 is configured with a reset transistor RST, an amplification transistor AMP, and a selection transistor SEL in an area obtained by shifting in the second direction V2 an area corresponding to the four sensor pixels 12 on the second substrate 20. For example, one pixel circuit 22 shared by the four sensor pixels 12 is configured with an amplification transistor AMP, a reset transistor RST, and a selection transistor SEL in one block 21A.

[0306] 52, one pixel circuit 22 shared by four sensor pixels 12 is configured with a reset transistor RST, an amplification transistor AMP, a selection transistor SEL, and an FD conversion gain switching transistor FDG in an area shifted in the second direction V2 from an area corresponding to the four sensor pixels 12 on the second substrate 20. For example, one pixel circuit 22 shared by four sensor pixels 12 is configured with an amplification transistor AMP, a reset transistor RST, a selection transistor SEL, and an FD conversion gain switching transistor FDG in one block 21A.

[0307] In the imaging device 1 according to the fourth modification, one pixel circuit 22 shared by four sensor pixels 12 is not disposed facing the four sensor pixels 12, but is disposed shifted in the second direction V2 from a position facing the four sensor pixels 12. With this configuration, the imaging device 1 according to the fourth modification can shorten the wiring 25 or omit the wiring 25 to configure the source of the amplification transistor AMP and the drain of the selection transistor SEL as a common impurity region. Therefore, the imaging device 1 according to the fourth modification can reduce the size of the pixel circuit 22.

[0308] (Fifth Modification) Next, a fifth modified example which is a modified example of the horizontal cross-sectional configuration of the imaging device 1 will be described with reference to Fig. 53. Fig. 53 is a schematic diagram showing a modified example of the cross-sectional configuration of the cut surfaces Sec1 and Sec2 in Fig. 7.

[0309] 53, the second semiconductor substrate 21 is composed of a plurality of island-shaped blocks 21A arranged side by side in the first direction V1 and the second direction V2 via an isolation insulating layer 53. Each of the blocks 21A includes, for example, a set of a reset transistor RST, an amplifying transistor AMP, and a selection transistor SEL. In this case, the imaging device 1 according to the fifth modification can suppress crosstalk between adjacent pixel circuits 22 by the isolation insulating layer 53, and therefore can suppress degradation of image resolution or degradation of image quality due to color mixing.

[0310] (Sixth Modification) Next, a sixth modified example which is a modified example of the horizontal cross-sectional configuration of the imaging device 1 will be described with reference to Fig. 54. Fig. 54 is a schematic diagram showing a modified example of the cross-sectional configuration of the cut surfaces Sec1 and Sec2 in Fig. 7.

[0311] 54, in the second semiconductor substrate 21, one pixel circuit 22 shared by four sensor pixels 12 is not arranged corresponding to the four sensor pixels 12, but is arranged shifted in the first direction V1. In the imaging device 1 according to the sixth modification, the second semiconductor substrate 21 is composed of a plurality of island-shaped blocks 21A arranged in the first direction V1 and the second direction V2 with an isolation insulating layer 53 interposed therebetween. Each of the blocks 21A is provided with, for example, a set of a reset transistor RST, an amplification transistor AMP, and a selection transistor SEL. In addition, in the imaging device 1 according to the sixth modification, a plurality of through wirings 47 and a plurality of through wirings 54 are arranged in the second direction V2.

[0312] As a result, the multiple through wires 47 are arranged between four through wires 54 sharing one pixel circuit 22 and four through wires 54 sharing another pixel circuit 22 adjacent to the pixel circuit 22 in the second direction V2. As a result, the imaging device 1 according to the sixth modified example can suppress crosstalk between adjacent pixel circuits 22 by the separation insulating layer 53 and the through wires 47, and therefore can suppress a decrease in image resolution or a decrease in image quality due to color mixing.

[0313] (Seventh Modification) Next, a seventh modification which is a modification of the horizontal cross-sectional configuration of the imaging device 1 will be described with reference to Fig. 55 to Fig. 57. Fig. 55 is a schematic diagram showing a modification of the cross-sectional configuration of the cut surfaces Sec1 and Sec2 in Fig. 7.

[0314] 55, in the imaging device 1 according to the seventh modification, the first substrate 10 has a photodiode PD and a transfer transistor TR (i.e., a transfer gate TG) for each sensor pixel 12, and a floating diffusion FD is shared by every four sensor pixels 12. Therefore, in the imaging device 1 according to the seventh modification, one through wiring 54 is provided for every four sensor pixels 12.

[0315] Moreover, in the imaging device 1 according to the seventh modification, the through wiring 47 is provided for each unit area corresponding to four sensor pixels 12 sharing one floating diffusion FD, which is shifted in the second direction V2 by one sensor pixel 12. That is, in the imaging device 1 according to the seventh modification, the through wiring 47 is provided between the unit area corresponding to four sensor pixels 12 sharing one floating diffusion FD and an adjacent unit area adjacent to the unit area in the second direction V2. Moreover, the through wiring 47 is shared by two sensor pixels 12 in the unit area present around the through wiring 47 and two sensor pixels 12 in the adjacent unit area present around the through wiring 47.

[0316] Furthermore, in the imaging device 1 according to the seventh modification, the first substrate 10 has an element isolation section 43 that isolates the photodiode PD and the transfer transistor TR for each sensor pixel 12. When the main surface of the first semiconductor substrate 11 is viewed in a plan view from the normal direction, the element isolation section 43 does not completely surround the sensor pixel 12, and has gaps (unformed regions) near the floating diffusion FD (i.e., the through wiring 54) and near the through wiring 47. These gaps allow the four sensor pixels 12 to share the through wiring 54, and the four sensor pixels 12 to share the through wiring 47 between a unit area and an adjacent unit area. Note that, in the imaging device 1 according to the seventh modification, the second substrate 20 has a pixel circuit 22 for each of the four sensor pixels 12 that share the floating diffusion FD.

[0317] 56 and 57 are schematic diagrams showing another example of the cross-sectional configuration of the cut surface Sec2 of the imaging device 1 according to the seventh modification. As shown in FIG. 56, the first substrate 10 may have a photodiode PD and a transfer transistor TR for each sensor pixel 12, and a floating diffusion FD may be shared by every four sensor pixels 12. Furthermore, the first substrate 10 may have an element isolation section 43 that separates the photodiode PD and the transfer transistor TR for each sensor pixel 12. Also, as shown in FIG. 57, the photodiode PD and the transfer transistor TR may be provided for each sensor pixel 12, and a floating diffusion FD may be shared by every four sensor pixels 12. Furthermore, the first substrate 10 may have an element isolation section 43 that separates the photodiode PD and the transfer transistor TR for each sensor pixel 12.

[0318] (Eighth Modification) Next, an eighth modified example which is a modified example of the circuit configuration of the imaging device 1 will be described with reference to Fig. 58. Fig. 58 is a schematic diagram showing the circuit configuration of a CMOS image sensor equipped with a column-parallel ADC (Analog to Digital Converter).

[0319] As shown in FIG. 58, the imaging device 1 of the eighth variant includes a pixel area 13 in which a plurality of sensor pixels 12, each including a photoelectric conversion element, are two-dimensionally arranged in a matrix (i.e., in a row and column form), a vertical drive circuit 33, a column signal processing circuit 34, a reference voltage supply unit 38, a horizontal drive circuit 35, a horizontal output line 37, and a system control circuit 36.

[0320] The system control circuit 36 ​​generates, based on the master clock MCK, clock signals and control signals that serve as references for the operations of the vertical drive circuit 33, the column signal processing circuit 34, the reference voltage supply unit 38, and the horizontal drive circuit 35. The system control circuit 36 ​​further supplies the generated clock signals and control signals to the vertical drive circuit 33, the column signal processing circuit 34, the reference voltage supply unit 38, and the horizontal drive circuit 35.

[0321] The vertical drive circuit 33 is formed on the first substrate 10 on which the sensor pixels 12 of the pixel region 13 are formed, and on the second substrate 20 on which the pixel circuits 22 are formed. The column signal processing circuit 34, the reference voltage supply unit 38, the horizontal drive circuit 35, the horizontal output line 37, and the system control circuit 36 ​​are formed on the third substrate 30.

[0322] Although not shown here, the sensor pixel 12 includes, for example, a photodiode PD and a transfer transistor TR that transfers the charge photoelectrically converted by the photodiode PD to the floating diffusion FD. The pixel circuit 22 includes, for example, a reset transistor RST that controls the potential of the floating diffusion FD, an amplification transistor AMP that outputs a signal according to the potential of the floating diffusion FD, and a selection transistor SEL for pixel selection.

[0323] The sensor pixels 12 are arranged two-dimensionally in the pixel region 13. For example, in the pixel region 13 in which the sensor pixels 12 are arranged in a matrix of n rows and m columns, a pixel drive line 23 is wired for each row, and a vertical signal line 24 is wired for each column. One ends of the multiple pixel drive lines 23 are connected to output terminals of a vertical drive circuit 33 corresponding to each row. The vertical drive circuit 33 is configured with a shift register or the like, and controls row addresses or row scanning of the pixel region 13 via the multiple pixel drive lines 23.

[0324] The column signal processing circuit 34 has, for example, ADCs (analog-to-digital conversion circuits) 34-1 to 34-m provided for each pixel column in the pixel region 13, i.e., for each vertical signal line 24. The column signal processing circuit 34 converts analog signals output for each column from each of the sensor pixels 12 in the pixel region 13 by the ADCs into digital signals and outputs the digital signals.

[0325] The reference voltage supplying unit 38 has, for example, a DAC (digital-analog conversion circuit) 38A, and generates a reference voltage Vref having a so-called ramp waveform whose level changes in a sloping manner as time passes. Note that the reference voltage supplying unit 38 may generate the reference voltage Vref having a ramp waveform using a means other than the DAC 38A.

[0326] The DAC 38A generates a reference voltage Vref having a ramp waveform based on a control signal CS1 and a clock CK from the system control circuit 36, and supplies the generated reference voltage Vref to the ADCs 34-1 to 34-m of the column signal processing circuit 34.

[0327] Each of the ADCs 34-1 to 34-m is configured to be capable of selectively performing AD conversion operations corresponding to each operation mode between a normal frame rate mode in a progressive scanning system in which information of all the sensor pixels 12 is read out, and a high-speed frame rate mode in which the frame rate is increased to N times (for example, twice) by setting the exposure time of the sensor pixels 12 to 1 / N compared to that in the normal frame rate mode. This switching of the operation mode is controlled by control signals CS2 and CS3 from the system control circuit 36. The system control circuit 36 ​​also generates control signals CS2 and CS3 for switching between the normal frame rate mode and the high-speed frame rate mode based on instruction information from an external system controller (not shown).

[0328] Since the ADCs 34-1 to 34-m all have the same configuration, the ADC 34-m will be described here as an example.

[0329] The ADC 34-m includes a comparator 34A, an up / down counter (U / DCNT) 34B, a transfer switch 34C, and a memory device 34D.

[0330] The comparator 34A compares the signal voltage Vx of the vertical signal line 24 corresponding to the signals output from each of the sensor pixels 12 in the m-th column of the pixel area 13 with a reference voltage Vref having a ramp waveform supplied from a reference voltage supply unit 38. For example, the comparator 34A sets the output Vco to an “H” level when the reference voltage Vref is greater than the signal voltage Vx, and sets the output Vco to an “L” level when the reference voltage Vref is equal to or less than the signal voltage Vx.

[0331] The up / down counter 34B is an asynchronous counter. The up / down counter 34B is supplied with a clock CK from the system control circuit 36 ​​based on a control signal CS2 provided from the system control circuit 36. The up / down counter 34B counts down or up in synchronization with the clock CK to measure a comparison period from the start to the end of the comparison operation in the comparator 34A.

[0332] Specifically, in the normal frame rate mode, the up / down counter 34B measures the comparison time during the first readout operation by counting down during the first readout operation from one sensor pixel 12. The up / down counter 34B also measures the comparison time during the second readout operation by counting up during the second readout operation.

[0333] On the other hand, in the high-speed frame rate mode, the up / down counter 34B holds the count result for the sensor pixels 12 in a certain row as is. After that, for the sensor pixels 12 in the next row, the up / down counter 34B takes over the previous count result and performs down counting during the first readout operation to measure the comparison time during the first readout. The up / down counter 34B also performs up counting during the second readout operation to measure the comparison time during the second readout.

[0334] The transfer switch 34C operates based on a control signal CS3 provided from the system control circuit 36. In the normal frame rate mode, the transfer switch 34C is turned on (closed) when the count operation of the up / down counter 34B for the sensor pixels 12 in a certain row is completed, thereby transferring the count result of the up / down counter 34B to the memory device 34D.

[0335] On the other hand, at a high frame rate of, for example, N=2, the transfer switch 34C remains in the OFF (open) state when the counting operation of the up / down counter 34B for a certain row of sensor pixels 12 is completed. After that, the transfer switch 34C turns ON when the counting operation of the up / down counter 34B for the next row of sensor pixels 12 is completed, thereby transferring the counting results of the up / down counter 34B for two vertical pixels to the memory device 34D.

[0336] In this manner, the analog signals supplied for each column from each of the sensor pixels 12 in the pixel region 13 via the vertical signal lines 24 are converted into N-bit digital signals by the operation of the comparators 34A and the up / down counters 34B in the ADCs 34-1 to 34-m and stored in the memory device 34D.

[0337] The horizontal drive circuit 35 is configured with a shift register and the like, and controls the column addresses and column scanning of the ADCs 34-1 to 34-m in the column signal processing circuit 34. The horizontal drive circuit 35 controls each of the ADCs 34-1 to 34-m to sequentially read out the AD converted N-bit digital signals to a horizontal output line 37. The read out N-bit digital signals are output as imaging data via the horizontal output line 37.

[0338] Although not shown in the figure, it is also possible to provide a circuit or the like for performing various signal processing on the imaging data output via the horizontal output line 37 in addition to the above-mentioned components.

[0339] In the imaging device 1 according to the eighth modification, the count result of the up / down counter 34B can be selectively transferred to the memory device 34D via the transfer switch 34C. This makes it possible to independently control the count operation of the up / down counter 34B and the read operation of the count result of the up / down counter 34B to the horizontal output line 37 in the imaging device 1 according to the eighth modification.

[0340] (Ninth Variation) Next, a ninth modified example which is a modified example of the laminated structure of the imaging device 1 will be described with reference to Fig. 59. Fig. 59 is a schematic diagram showing an example in which the imaging device 1 shown in Fig. 58 is configured by laminating three substrates.

[0341] As shown in FIG. 59, the imaging device 1 according to the ninth modification is configured by stacking a first substrate 10, a second substrate 20, and a third substrate. In the first substrate 10, a pixel region 13 including a plurality of sensor pixels 12 is formed in the center, and a vertical driving circuit 33 is formed around the pixel region 13. In addition, in the second substrate 20, a pixel circuit region 15 including a plurality of pixel circuits 22 is formed in the center, and a vertical driving circuit 33 is formed around the pixel circuit region 15. In addition, in the third substrate 30, a column signal processing circuit 34, a horizontal driving circuit 35, a system control circuit 36, a horizontal output line 37, and a reference voltage supply unit 38 are formed. Note that the vertical driving circuit 33 may be formed on both the first substrate 10 and the second substrate 20 as described above, or may be formed only on the first substrate 10, or may be formed only on the second substrate 20.

[0342] The imaging device 1 according to the ninth modification can suppress an increase in chip size or an increase in pixel area due to a structure for electrically connecting substrates to each other. As a result, the imaging device 1 according to the ninth modification can further reduce the area per pixel.

[0343] (Tenth Modification) Next, a tenth modification which is one modification of the cross-sectional configuration of the imaging device 1 will be described with reference to Fig. 60 and Fig. 61. Fig. 60 is a schematic diagram showing an example of the cross-sectional configuration of the imaging device 1 according to the tenth modification.

[0344] In the embodiment and the modified example described above, the imaging device 1 is configured by stacking three substrates, the first substrate 10, the second substrate 20, and the third substrate 30. However, the technology according to the present disclosure is not limited to the above example. For example, the imaging device 1 may be configured by stacking two substrates, the first substrate 10 and the second substrate 20.

[0345] As shown in FIG. 60, in such a case, the processing circuit 32 is formed separately on the first substrate 10 and the second substrate 20, for example.

[0346] In the processing circuit 32, the circuit 32A provided on the first substrate 10 side is provided with a transistor having a gate structure in which a high dielectric constant film made of a material that can withstand high temperature processes (e.g., a high-k material) and a metal gate electrode are stacked.

[0347] On the other hand, in the circuit 32B of the processing circuit 32 provided on the second substrate 20 side, a low-resistance region 26 made of silicide such as CoSi2 or NiSi is formed on the surface of the impurity diffusion region in contact with the source electrode and the drain electrode. The low-resistance region made of silicide is formed of a compound of the material of the semiconductor substrate and a metal, and has high heat resistance. Therefore, it becomes possible to use a high-temperature process such as thermal oxidation when forming the sensor pixel 12. In addition, the low-resistance region 26 made of silicide such as CoSi2 or NiSi can reduce contact resistance, and therefore the calculation speed in the processing circuit 32 can be increased.

[0348] The low-resistance region 26 made of silicide such as CoSi2 or NiSi may be provided in the imaging device 1 according to the embodiment and the modified example described above. Specifically, the low-resistance region 26 made of silicide such as CoSi2 or NiSi may also be provided in the imaging device 1 configured by stacking three substrates, the first substrate 10, the second substrate 20, and the third substrate 30. Fig. 61 is a schematic diagram showing an example in which the low-resistance region 26 made of silicide such as CoSi2 or NiSi is applied to the imaging device 1 configured by stacking three substrates.

[0349] 61, in the processing circuit 32 of the third substrate 30, a low-resistance region 26 made of silicide such as CoSi2 or NiSi may be formed on the surface of the impurity diffusion region in contact with the source electrode and the drain electrode. This makes it possible to use a high-temperature process such as thermal oxidation when forming the sensor pixels 12. In addition, the low-resistance region 26 made of silicide such as CoSi2 or NiSi can reduce contact resistance, thereby increasing the calculation speed in the processing circuit 32.

[0350] <<6. Specific Examples>> The technology according to the present disclosure described above can be applied to various imaging devices, etc. In the following, specific examples of imaging devices to which the technology according to the present disclosure can be applied and devices including the imaging devices will be described.

[0351] <6.1. Implementation form> [Functional configuration of imaging device 1] FIG. 62 is a block diagram showing an example of a functional configuration of an imaging device (imaging device 1) according to an embodiment of the present disclosure.

[0352] The imaging device 1 in FIG. 62 includes, for example, an input section 510A, a row driver section 520, a timing control section 530, a pixel array section 540, a column signal processing section 550, an image signal processing section 560, and an output section 510B.

[0353] In the pixel array section 540, pixels 541 are repeatedly arranged in an array. More specifically, a pixel sharing unit 539 including a plurality of pixels is a repeating unit, and this is repeatedly arranged in an array having a row direction and a column direction. In this specification, for convenience, the row direction may be called the H direction, and the column direction perpendicular to the row direction may be called the V direction. In the example of FIG. 62, one pixel sharing unit 539 includes four pixels (pixels 541A, 541B, 541C, and 541D). Each of the pixels 541A, 541B, 541C, and 541D has a photodiode PD (illustrated in FIG. 67, etc., which will be described later). The pixel sharing unit 539 is a unit that shares one pixel circuit (pixel circuit 210 in FIG. 64, which will be described later). In other words, one pixel circuit (pixel circuit 210, which will be described later) is included for every four pixels (pixels 541A, 541B, 541C, and 541D). By operating this pixel circuit in a time-division manner, pixel signals of the pixels 541A, 541B, 541C, and 541D are sequentially read out. The pixels 541A, 541B, 541C, and 541D are arranged in, for example, 2 rows and 2 columns. In the pixel array section 540, a plurality of row driving signal lines 542 and a plurality of vertical signal lines (column readout lines) 543 are provided in addition to the pixels 541A, 541B, 541C, and 541D. The row driving signal line 542 drives the pixels 541 included in each of a plurality of pixel sharing units 539 arranged in a row direction in the pixel array section 540. The row driving signal line 542 drives each pixel arranged in a row direction among the pixel sharing units 539. As will be described in detail later with reference to FIG. 65, the pixel sharing unit 539 is provided with a plurality of transistors. In order to drive each of these transistors, a plurality of row driving signal lines 542 are connected to one pixel sharing unit 539. The pixel sharing unit 539 is connected to the vertical signal line (column readout line) 543. Pixel signals are read out via the vertical signal line (column readout line) 543 from each of the pixels 541A, 541B, 541C, and 541D included in the pixel sharing unit 539.

[0354] The row driving unit 520 includes, for example, a row address control unit that determines the position of the row for driving the pixels, in other words, a row decoder unit, and a row driving circuit unit that generates signals for driving the pixels 541A, 541B, 541C, and 541D.

[0355] The column signal processing unit 550 includes, for example, a load circuit unit that is connected to the vertical signal line 543 and forms a source follower circuit together with the pixels 541A, 541B, 541C, and 541D (pixel sharing units 539). The column signal processing unit 550 may include an amplifier circuit unit that amplifies a signal read out from the pixel sharing unit 539 via the vertical signal line 543. The column signal processing unit 550 may include a noise processing unit. In the noise processing unit, for example, a system noise level is removed from the signal read out from the pixel sharing unit 539 as a result of photoelectric conversion.

[0356] The column signal processing unit 550 has, for example, an analog-to-digital converter (ADC). In the analog-to-digital converter, the signal read from the pixel sharing unit 539 or the analog signal that has been subjected to the noise processing is converted into a digital signal. The ADC includes, for example, a comparator unit and a counter unit. In the comparator unit, the analog signal to be converted is compared with a reference signal to be compared therewith. In the counter unit, the time until the comparison result in the comparator unit is inverted is measured. The column signal processing unit 550 may include a horizontal scanning circuit unit that controls scanning of the readout column.

[0357] The timing control section 530 supplies signals for controlling timing to the row driving section 520 and the column signal processing section 550 based on a reference clock signal and a timing control signal input to the device.

[0358] The image signal processing unit 560 is a circuit that performs various signal processing on data obtained as a result of photoelectric conversion, in other words, data obtained as a result of the imaging operation in the imaging device 1. The image signal processing unit 560 includes, for example, an image signal processing circuit unit and a data holding unit. The image signal processing unit 560 may also include a processor unit.

[0359] One example of signal processing executed by the image signal processing unit 560 is a tone curve correction process that imparts more gradation to the AD converted imaging data when the data is of a dark subject, and reduces the gradation when the data is of a bright subject. In this case, it is desirable to store in advance in the data storage unit of the image signal processing unit 560 characteristic data of the tone curve based on which the gradation of the imaging data is to be corrected.

[0360] The input section 510A is for inputting, for example, the above-mentioned reference clock signal, timing control signal, characteristic data, and the like from outside the device to the imaging device 1. The timing control signal is, for example, a vertical synchronization signal and a horizontal synchronization signal. The characteristic data is, for example, for storage in a data holding section of the image signal processing section 560. The input section 510A includes, for example, an input terminal 511, an input circuit section 512, an input amplitude changing section 513, an input data conversion circuit section 514, and a power supply section (not shown).

[0361] The input terminal 511 is an external terminal for inputting data. The input circuit unit 512 is for taking in the signal input to the input terminal 511 into the inside of the imaging device 1. The input amplitude change unit 513 changes the amplitude of the signal taken in by the input circuit unit 512 to an amplitude that is easily used inside the imaging device 1. The input data conversion circuit unit 514 changes the arrangement of the data string of the input data. The input data conversion circuit unit 514 is composed of, for example, a serial-parallel conversion circuit. In this serial-parallel conversion circuit, a serial signal received as input data is converted into a parallel signal. Note that, in the input unit 510A, the input amplitude change unit 513 and the input data conversion circuit unit 514 may be omitted. The power supply unit supplies power set to various voltages required inside the imaging device 1 based on a power source supplied from the outside to the imaging device 1.

[0362] When the imaging device 1 is connected to an external memory device, the input unit 510A may be provided with a memory interface circuit that receives data from the external memory device. The external memory device may be, for example, a flash memory, an SRAM, or a DRAM.

[0363] The output unit 510B outputs image data to the outside of the device. This image data is, for example, image data captured by the imaging device 1 and image data signal-processed by the image signal processing unit 560. The output unit 510B includes, for example, an output data conversion circuit unit 515, an output amplitude change unit 516, an output circuit unit 517, and an output terminal 518.

[0364] The output data conversion circuit unit 515 is configured, for example, by a parallel-serial conversion circuit, and the output data conversion circuit unit 515 converts the parallel signal used inside the imaging device 1 into a serial signal. The output amplitude change unit 516 changes the amplitude of the signal used inside the imaging device 1. The signal with the changed amplitude can be easily used by an external device connected to the outside of the imaging device 1. The output circuit unit 517 is a circuit that outputs data from inside the imaging device 1 to the outside of the device, and the output circuit unit 517 drives a wiring outside the imaging device 1 connected to an output terminal 518. The output terminal 518 outputs data from the imaging device 1 to the outside of the device. In the output unit 510B, the output data conversion circuit unit 515 and the output amplitude change unit 516 may be omitted.

[0365] When the imaging device 1 is connected to an external memory device, the output unit 510B may be provided with a memory interface circuit that outputs data to the external memory device. The external memory device may be, for example, a flash memory, an SRAM, or a DRAM.

[0366] [Schematic configuration of imaging device 1] FIG. 63 and FIG. 64 show an example of a schematic configuration of the imaging device 1. The imaging device 1 includes three substrates (a first substrate 100, a second substrate 200, and a third substrate 300). FIG. 63 shows a schematic planar configuration of each of the first substrate 100, the second substrate 200, and the third substrate 300, and FIG. 64 shows a schematic cross-sectional configuration of the first substrate 100, the second substrate 200, and the third substrate 300 stacked on top of each other. FIG. 64 corresponds to the cross-sectional configuration along line III-III' shown in FIG. 63. The imaging device 1 is a three-dimensional imaging device formed by bonding three substrates (the first substrate 100, the second substrate 200, and the third substrate 300). The first substrate 100 includes a semiconductor layer 100S and a wiring layer 100T. The second substrate 200 includes a semiconductor layer 200S and a wiring layer 200T. The third substrate 300 includes a semiconductor layer 300S and a wiring layer 300T. Here, the combination of the wiring included in each of the first substrate 100, the second substrate 200, and the third substrate 300 and the interlayer insulating film around it is called the wiring layer (100T, 200T, 300T) provided on each substrate (the first substrate 100, the second substrate 200, and the third substrate 300) for convenience. The first substrate 100, the second substrate 200, and the third substrate 300 are stacked in this order, and the semiconductor layer 100S, the wiring layer 100T, the semiconductor layer 200S, the wiring layer 200T, the wiring layer 300T, and the semiconductor layer 300S are arranged in this order along the stacking direction. The specific configurations of the first substrate 100, the second substrate 200, and the third substrate 300 will be described later. The arrow shown in FIG. 64 indicates the incident direction of the light L to the imaging device 1. In this specification, for convenience, in the following cross-sectional views, the light incident side of the imaging device 1 may be referred to as "bottom", "lower side", or "downward", and the side opposite the light incident side may be referred to as "upper side", "upper side", or "upper". Also, in this specification, for convenience, with respect to a substrate having a semiconductor layer and a wiring layer, the wiring layer side may be referred to as the front side, and the semiconductor layer side may be referred to as the back side. Note that the description in the specification is not limited to the above names. The imaging device 1 is, for example, a back-illuminated imaging device in which light is incident from the back side of the first substrate 100 having a photodiode.

[0367] The pixel array section 540 and the pixel sharing unit 539 included in the pixel array section 540 are both configured using both the first substrate 100 and the second substrate 200. The first substrate 100 is provided with a plurality of pixels 541A, 541B, 541C, and 541D that the pixel sharing unit 539 has. Each of these pixels 541 has a photodiode (a photodiode PD described later) and a transfer transistor (a transfer transistor TR described later). The second substrate 200 is provided with a pixel circuit (a pixel circuit 210 described later) that the pixel sharing unit 539 has. The pixel circuit reads out pixel signals transferred from the photodiodes of the pixels 541A, 541B, 541C, and 541D via the transfer transistors, or resets the photodiodes. In addition to such pixel circuits, the second substrate 200 has a plurality of row driving signal lines 542 extending in the row direction and a plurality of vertical signal lines 543 extending in the column direction. The second substrate 200 further has a power supply line 544 (such as a power supply line VDD described later) extending in the row direction. The third substrate 300 has, for example, an input section 510A, a row driver 520, a timing control section 530, a column signal processing section 550, an image signal processing section 560, and an output section 510B. The row driver 520 is provided, for example, in a region that partially overlaps with the pixel array section 540 in the stacking direction (hereinafter simply referred to as the stacking direction) of the first substrate 100, the second substrate 200, and the third substrate 300. More specifically, the row driver 520 is provided in a region that partially overlaps with the pixel array section 540 in the stacking direction (FIG. 63). The column signal processing section 550 is provided, for example, in a region that partially overlaps with the pixel array section 540 in the stacking direction. More specifically, the column signal processing section 550 is provided in a region overlapping the vicinity of an end portion in the V direction of the pixel array section 540 in the stacking direction (FIG. 63). Although not shown, the input section 510A and the output section 510B may be disposed in a portion other than the third substrate 300, for example, on the second substrate 200. Alternatively, the input section 510A and the output section 510B may be provided on the back surface (light incident surface) side of the first substrate 100.The pixel circuits provided on the second substrate 200 may also be called pixel transistor circuits, pixel transistor groups, pixel transistors, pixel readout circuits, or readout circuits. In this specification, the term pixel circuits is used.

[0368] The first substrate 100 and the second substrate 200 are electrically connected by, for example, through electrodes (through electrodes 120E, 121E in FIG. 67 described later). The second substrate 200 and the third substrate 300 are electrically connected by, for example, contact portions 201, 202, 301, 302. The second substrate 200 is provided with contact portions 201, 202, and the third substrate 300 is provided with contact portions 301, 302. The contact portion 201 of the second substrate 200 contacts the contact portion 301 of the third substrate 300, and the contact portion 202 of the second substrate 200 contacts the contact portion 302 of the third substrate 300. The second substrate 200 has a contact region 201R in which a plurality of contact portions 201 are provided, and a contact region 202R in which a plurality of contact portions 202 are provided. The third substrate 300 has a contact region 301R in which a plurality of contact parts 301 are provided, and a contact region 302R in which a plurality of contact parts 302 are provided. The contact regions 201R, 301R are provided between the pixel array section 540 and the row driver section 520 in the stacking direction (FIG. 64). In other words, the contact regions 201R, 301R are provided, for example, in a region where the row driver section 520 (third substrate 300) and the pixel array section 540 (second substrate 200) overlap in the stacking direction, or in a region nearby the region. The contact regions 201R, 301R are disposed, for example, at the end in the H direction of such a region (FIG. 63). In the third substrate 300, for example, the contact region 301R is provided at a position that overlaps with a part of the row driver section 520, specifically, the end in the H direction of the row driver section 520 (FIGS. 63 and 64). The contact sections 201 and 301 connect, for example, the row driving section 520 provided on the third substrate 300 and the row driving signal line 542 provided on the second substrate 200. The contact sections 201 and 301 may connect, for example, the input section 510A provided on the third substrate 300 to a power supply line 544 and a reference potential line (a reference potential line VSS described later). The contact regions 202R and 302R are provided between the pixel array section 540 and the column signal processing section 550 in the stacking direction (FIG. 64).In other words, the contact regions 202R and 302R are provided in, for example, a region where the column signal processing section 550 (the third substrate 300) and the pixel array section 540 (the second substrate 200) overlap in the stacking direction, or in a region adjacent thereto. The contact regions 202R and 302R are arranged, for example, at the end in the V direction of such a region (FIG. 63). In the third substrate 300, for example, the contact region 301R is provided at a position overlapping a part of the column signal processing section 550, specifically, an end in the V direction of the column signal processing section 550 (FIGS. 63 and 64). The contact sections 202 and 302 are for connecting, for example, pixel signals (signals corresponding to the amount of charge generated as a result of photoelectric conversion in the photodiodes) output from each of the multiple pixel sharing units 539 of the pixel array section 540 to the column signal processing section 550 provided on the third substrate 300. The pixel signals are sent from the second substrate 200 to the third substrate 300.

[0369] FIG. 64 is an example of a cross-sectional view of the imaging device 1 as described above. The first substrate 100, the second substrate 200, and the third substrate 300 are electrically connected via wiring layers 100T, 200T, and 300T. For example, the imaging device 1 has an electrical connection portion that electrically connects the second substrate 200 and the third substrate 300. Specifically, the contact portions 201, 202, 301, and 302 are formed with electrodes formed of a conductive material. The conductive material is formed of a metal material such as copper (Cu), aluminum (Al), and gold (Au). The contact regions 201R, 202R, 301R, and 302R electrically connect the second substrate and the third substrate by directly joining wirings formed as electrodes, for example, to each other, thereby enabling input and / or output of signals between the second substrate 200 and the third substrate 300.

[0370] The electrical connection portion that electrically connects the second substrate 200 and the third substrate 300 can be provided at a desired location. For example, as described as the contact regions 201R, 202R, 301R, and 302R in FIG. 64, the electrical connection portion may be provided in a region that overlaps with the pixel array section 540 in the stacking direction. The electrical connection portion may also be provided in a region that does not overlap with the pixel array section 540 in the stacking direction. Specifically, the electrical connection portion may be provided in a region that overlaps with a peripheral portion disposed outside the pixel array section 540 in the stacking direction.

[0371] The first substrate 100 and the second substrate 200 are provided with, for example, connection holes H1 and H2. The connection holes H1 and H2 penetrate the first substrate 100 and the second substrate 200 (FIG. 64). The connection holes H1 and H2 are provided outside the pixel array section 540 (or a portion overlapping the pixel array section 540) (FIG. 63). For example, the connection hole H1 is disposed outside the pixel array section 540 in the H direction, and the connection hole H2 is disposed outside the pixel array section 540 in the V direction. For example, the connection hole H1 reaches the input section 510A provided on the third substrate 300, and the connection hole H2 reaches the output section 510B provided on the third substrate 300. The connection holes H1 and H2 may be hollow or may contain a conductive material at least in part. For example, there is a configuration in which a bonding wire is connected to an electrode formed as the input section 510A and / or the output section 510B. Alternatively, there is a configuration in which an electrode formed as the input section 510A and / or the output section 510B is connected to a conductive material provided in the connection holes H1, H2. The conductive material provided in the connection holes H1, H2 may be embedded in a part or all of the connection holes H1, H2, or the conductive material may be formed on the side walls of the connection holes H1, H2.

[0372] 64 shows a structure in which the input section 510A and the output section 510B are provided on the third substrate 300, but the present invention is not limited to this. For example, the input section 510A and / or the output section 510B can be provided on the second substrate 200 by sending a signal of the third substrate 300 to the second substrate 200 via the wiring layers 200T and 300T. Similarly, the input section 510A and / or the output section 510B can be provided on the first substrate 100 by sending a signal of the second substrate 200 to the first substrate 100 via the wiring layers 100T and 200T.

[0373] FIG. 65 is an equivalent circuit diagram showing an example of the configuration of the pixel sharing unit 539. The pixel sharing unit 539 includes a plurality of pixels 541 (four pixels 541, 541A, 541B, 541C, and 541D, are shown in FIG. 65), one pixel circuit 210 connected to the plurality of pixels 541, and a vertical signal line 543 connected to the pixel circuit 210. The pixel circuit 210 includes, for example, four transistors, specifically, an amplification transistor AMP, a selection transistor SEL, a reset transistor RST, and an FD conversion gain switching transistor FDG. As described above, the pixel sharing unit 539 is configured to sequentially output pixel signals of the four pixels 541 (pixels 541A, 541B, 541C, and 541D) included in the pixel sharing unit 539 to the vertical signal line 543 by operating one pixel circuit 210 in a time-division manner. A state in which one pixel circuit 210 is connected to multiple pixels 541 and the pixel signals of the multiple pixels 541 are output in a time-division manner by the single pixel circuit 210 is referred to as "multiple pixels 541 sharing one pixel circuit 210."

[0374] The pixels 541A, 541B, 541C, and 541D have components in common with each other. Hereinafter, in order to distinguish the components of the pixels 541A, 541B, 541C, and 541D from each other, the identification number 1 is added to the end of the reference numeral of the component of the pixel 541A, the identification number 2 is added to the end of the reference numeral of the component of the pixel 541B, the identification number 3 is added to the end of the reference numeral of the component of the pixel 541C, and the identification number 4 is added to the end of the reference numeral of the component of the pixel 541D. When it is not necessary to distinguish the components of the pixels 541A, 541B, 541C, and 541D from each other, the identification numbers at the end of the reference numerals of the components of the pixels 541A, 541B, 541C, and 541D are omitted.

[0375] The pixels 541A, 541B, 541C, and 541D each have, for example, a photodiode PD, a transfer transistor TR electrically connected to the photodiode PD, and a floating diffusion FD electrically connected to the transfer transistor TR. In the photodiodes PD (PD1, PD2, PD3, and PD4), the cathode is electrically connected to the source of the transfer transistor TR, and the anode is electrically connected to a reference potential line (for example, ground). The photodiode PD photoelectrically converts incident light and generates a charge according to the amount of light received. The transfer transistors TR (transfer transistors TR1, TR2, TR3, and TR4) are, for example, n-type CMOS (Complementary-Metal-Oxide Semiconductor) transistors. In the transfer transistor TR, the drain is electrically connected to the floating diffusion FD, and the gate is electrically connected to a drive signal line. This drive signal line is a part of a plurality of row drive signal lines 542 (see FIG. 62) connected to one pixel sharing unit 539. The transfer transistor TR transfers the charge generated in the photodiode PD to the floating diffusion FD. The floating diffusion FD (floating diffusions FD1, FD2, FD3, FD4) is an n-type diffusion layer region formed in a p-type semiconductor layer. The floating diffusion FD is a charge holding means that temporarily holds the charge transferred from the photodiode PD, and is also a charge-voltage conversion means that generates a voltage according to the amount of charge.

[0376] The four floating diffusions FD (floating diffusions FD1, FD2, FD3, and FD4) included in one pixel shared unit 539 are electrically connected to each other and to the gate of the amplification transistor AMP and the source of the FD conversion gain switching transistor FDG. The drain of the FD conversion gain switching transistor FDG is connected to the source of the reset transistor RST, and the gate of the FD conversion gain switching transistor FDG is connected to a drive signal line. This drive signal line is a part of a plurality of row drive signal lines 542 connected to one pixel shared unit 539. The drain of the reset transistor RST is connected to a power supply line VDD, and the gate of the reset transistor RST is connected to the drive signal line. This drive signal line is a part of a plurality of row drive signal lines 542 connected to one pixel shared unit 539. The gate of the amplification transistor AMP is connected to the floating diffusion FD, the drain of the amplification transistor AMP is connected to the power supply line VDD, and the source of the amplification transistor AMP is connected to the drain of the selection transistor SEL. The source of the selection transistor SEL is connected to a vertical signal line 543, and the gate of the selection transistor SEL is connected to the drive signal line. This drive signal line is part of a plurality of row drive signal lines 542 connected to one pixel sharing unit 539 .

[0377] When the transfer transistor TR is turned on, the transfer transistor TR transfers the charge of the photodiode PD to the floating diffusion FD. The gate (transfer gate TG) of the transfer transistor TR includes, for example, a so-called vertical electrode, and is provided extending from the surface of the semiconductor layer (semiconductor layer 100S in FIG. 67 described later) to a depth reaching the PD, as shown in FIG. 67 described later. The reset transistor RST resets the potential of the floating diffusion FD to a predetermined potential. When the reset transistor RST is turned on, the potential of the floating diffusion FD is reset to the potential of the power supply line VDD. The selection transistor SEL controls the output timing of the pixel signal from the pixel circuit 210. The amplification transistor AMP generates, as the pixel signal, a signal of a voltage according to the level of the charge held in the floating diffusion FD. The amplification transistor AMP is connected to the vertical signal line 543 via the selection transistor SEL. In the column signal processing unit 550, the amplification transistor AMP configures a source follower together with a load circuit unit (see FIG. 62) connected to the vertical signal line 543. When the selection transistor SEL is turned on, the amplification transistor AMP outputs the voltage of the floating diffusion FD to the column signal processing unit 550 via the vertical signal line 543. The reset transistor RST, the amplification transistor AMP, and the selection transistor SEL are, for example, N-type CMOS transistors.

[0378] The FD conversion gain switching transistor FDG is used to change the gain of the charge-voltage conversion in the floating diffusion FD. In general, the pixel signal is small when shooting in a dark place. Based on Q=CV, when performing charge-voltage conversion, if the capacitance (FD capacitance C) of the floating diffusion FD is large, V when converted to voltage by the amplification transistor AMP will be small. On the other hand, in a bright place, the pixel signal becomes large, so if the FD capacitance C is not large, the floating diffusion FD cannot receive the charge of the photodiode PD. Furthermore, the FD capacitance C needs to be large so that V when converted to voltage by the amplification transistor AMP does not become too large (in other words, so that it becomes small). In consideration of this, when the FD conversion gain switching transistor FDG is turned on, the gate capacitance of the FD conversion gain switching transistor FDG increases, so the overall FD capacitance C becomes large. On the other hand, when the FD conversion gain switching transistor FDG is turned off, the overall FD capacitance C becomes small. In this way, by switching the FD conversion gain switching transistor FDG on and off, the FD capacitance C can be made variable and the conversion efficiency can be switched. The FD conversion gain switching transistor FDG is, for example, an N-type CMOS transistor.

[0379] It is also possible to configure the pixel circuit 210 without providing the FD conversion gain switching transistor FDG. In this case, for example, the pixel circuit 210 is composed of three transistors, for example, an amplification transistor AMP, a selection transistor SEL, and a reset transistor RST. The pixel circuit 210 has at least one pixel transistor, for example, an amplification transistor AMP, a selection transistor SEL, a reset transistor RST, and an FD conversion gain switching transistor FDG.

[0380] The selection transistor SEL may be provided between the power supply line VDD and the amplification transistor AMP. In this case, the drain of the reset transistor RST is electrically connected to the power supply line VDD and the drain of the selection transistor SEL. The source of the selection transistor SEL is electrically connected to the drain of the amplification transistor AMP, and the gate of the selection transistor SEL is electrically connected to the row drive signal line 542 (see FIG. 62). The source of the amplification transistor AMP (the output terminal of the pixel circuit 210) is electrically connected to the vertical signal line 543, and the gate of the amplification transistor AMP is electrically connected to the source of the reset transistor RST. Although not shown in the figure, the number of pixels 541 sharing one pixel circuit 210 may be other than four. For example, two or eight pixels 541 may share one pixel circuit 210.

[0381] FIG. 66 shows an example of a connection between a plurality of pixel sharing units 539 and a vertical signal line 543. For example, four pixel sharing units 539 arranged in a column direction are divided into four groups, and a vertical signal line 543 is connected to each of the four groups. For the sake of simplicity, FIG. 66 shows an example in which each of the four groups has one pixel sharing unit 539, but each of the four groups may include a plurality of pixel sharing units 539. In this way, in the imaging device 1, a plurality of pixel sharing units 539 arranged in a column direction may be divided into groups including one or more pixel sharing units 539. For example, a vertical signal line 543 and a column signal processing unit 550 are connected to each of the groups, so that pixel signals can be read out simultaneously from each group. Alternatively, in the imaging device 1, one vertical signal line 543 may be connected to a plurality of pixel sharing units 539 arranged in a column direction. In this case, pixel signals are read out sequentially in a time-division manner from the plurality of pixel sharing units 539 connected to one vertical signal line 543.

[0382] [Specific configuration of imaging device 1] FIG. 67 shows an example of a cross-sectional configuration perpendicular to the main surfaces of the first substrate 100, the second substrate 200, and the third substrate 300 of the imaging device 1. FIG. 67 is a schematic representation for making it easier to understand the positional relationship of the components, and may differ from the actual cross section. In the imaging device 1, the first substrate 100, the second substrate 200, and the third substrate 300 are stacked in this order. The imaging device 1 further has a light receiving lens 401 on the back side (light incident surface side) of the first substrate 100. A color filter layer (not shown) may be provided between the light receiving lens 401 and the first substrate 100. The light receiving lens 401 is provided, for example, for each of the pixels 541A, 541B, 541C, and 541D. The imaging device 1 is, for example, a back-illuminated imaging device. The imaging device 1 has a pixel array section 540 arranged in the center and a peripheral section 540B arranged outside the pixel array section 540.

[0383] The first substrate 100 has, in order from the light receiving lens 401 side, an insulating film 111, a fixed charge film 112, a semiconductor layer 100S, and a wiring layer 100T. The semiconductor layer 100S is made of, for example, a silicon substrate. The semiconductor layer 100S has, for example, a p-well layer 115 in a part of the surface (the surface on the wiring layer 100T side) and in the vicinity thereof, and has an n-type semiconductor region 114 in the other region (region deeper than the p-well layer 115). For example, the n-type semiconductor region 114 and the p-well layer 115 form a pn junction type photodiode PD. The p-well layer 115 is a p-type semiconductor region.

[0384] Fig. 68A shows an example of the planar configuration of the first substrate 100. Fig. 68A mainly shows the planar configuration of the pixel separation portion 117, the photodiode PD, the floating diffusion FD, the VSS contact region 118, and the transfer transistor TR of the first substrate 100. The configuration of the first substrate 100 will be described using Fig. 68A together with Fig. 67.

[0385] A floating diffusion FD and a VSS contact region 118 are provided near the surface of the semiconductor layer 100S. The floating diffusion FD is composed of an n-type semiconductor region provided in the p-well layer 115. The floating diffusions FD (floating diffusions FD1, FD2, FD3, FD4) of the pixels 541A, 541B, 541C, and 541D are provided close to each other in the center of the pixel sharing unit 539 (FIG. 68A), for example. Although details will be described later, the four floating diffusions (floating diffusions FD1, FD2, FD3, FD4) included in this pixel sharing unit 539 are electrically connected to each other via electrical connection means (pad section 120 described later) in the first substrate 100 (more specifically, in the wiring layer 100T). Furthermore, the floating diffusion FD is connected from the first substrate 100 to the second substrate 200 (more specifically, from the wiring layer 100T to the wiring layer 200T) via an electrical means (a through electrode 120E described below). In the second substrate 200 (more specifically, inside the wiring layer 200T), the floating diffusion FD is electrically connected to the gate of the amplification transistor AMP and the source of the FD conversion gain switching transistor FDG by this electrical means.

[0386] The VSS contact region 118 is a region electrically connected to the reference potential line VSS, and is arranged apart from the floating diffusion FD. For example, in the pixels 541A, 541B, 541C, and 541D, the floating diffusion FD is arranged at one end of each pixel in the V direction, and the VSS contact region 118 is arranged at the other end (FIG. 68A). The VSS contact region 118 is, for example, composed of a p-type semiconductor region. The VSS contact region 118 is connected to, for example, a ground potential or a fixed potential. This allows a reference potential to be supplied to the semiconductor layer 100S.

[0387] The first substrate 100 is provided with a transfer transistor TR together with a photodiode PD, a floating diffusion FD, and a VSS contact region 118. The photodiode PD, the floating diffusion FD, the VSS contact region 118, and the transfer transistor TR are provided in each of the pixels 541A, 541B, 541C, and 541D. The transfer transistor TR is provided on the front surface side (the side opposite to the light incident surface side, the second substrate 200 side) of the semiconductor layer 100S. The transfer transistor TR has a transfer gate TG. The transfer gate TG includes, for example, a horizontal portion TGb facing the front surface of the semiconductor layer 100S and a vertical portion TGa provided in the semiconductor layer 100S. The vertical portion TGa extends in the thickness direction of the semiconductor layer 100S. One end of the vertical portion TGa is in contact with the horizontal portion TGb, and the other end is provided in the n-type semiconductor region 114. By configuring the transfer transistor TR with such a vertical transistor, transfer failure of pixel signals is less likely to occur, and the readout efficiency of pixel signals can be improved.

[0388] The horizontal part TGb of the transfer gate TG extends from a position facing the vertical part TGa toward, for example, the center of the pixel sharing unit 539 in the H direction (FIG. 68A). This allows the H direction position of the through electrode (through electrode TGV described below) that reaches the transfer gate TG to be closer to the H direction positions of the through electrodes (through electrodes 120E, 121E described below) connected to the floating diffusion FD and the VSS contact region 118. For example, the multiple pixel sharing units 539 provided on the first substrate 100 have the same configuration (FIG. 68A).

[0389] The semiconductor layer 100S is provided with a pixel separator 117 that separates the pixels 541A, 541B, 541C, and 541D from one another. The pixel separator 117 is formed extending in a normal direction of the semiconductor layer 100S (a direction perpendicular to the surface of the semiconductor layer 100S). The pixel separator 117 is provided to separate the pixels 541A, 541B, 541C, and 541D from one another, and has, for example, a lattice-like planar shape (FIGS. 68A and 68B). The pixel separator 117 electrically and optically separates the pixels 541A, 541B, 541C, and 541D from one another. The pixel separator 117 includes, for example, a light-shielding film 117A and an insulating film 117B. The light-shielding film 117A is made of, for example, tungsten (W) or the like. The insulating film 117B is provided between the light shielding film 117A and the p-well layer 115 or the n-type semiconductor region 114. The insulating film 117B is made of, for example, silicon oxide (SiO). The pixel separator 117 has, for example, a full trench isolation (FTI) structure and penetrates the semiconductor layer 100S. Although not shown, the pixel separator 117 is not limited to an FTI structure that penetrates the semiconductor layer 100S. For example, it may have a deep trench isolation (DTI) structure that does not penetrate the semiconductor layer 100S. The pixel separator 117 extends in the normal direction of the semiconductor layer 100S and is formed in a partial region of the semiconductor layer 100S.

[0390] The semiconductor layer 100S is provided with, for example, a first pinning region 113 and a second pinning region 116. The first pinning region 113 is provided near the back surface of the semiconductor layer 100S, and is disposed between the n-type semiconductor region 114 and the fixed charge film 112. The second pinning region 116 is provided on a side surface of the pixel separating section 117, specifically, between the pixel separating section 117 and the p-well layer 115 or the n-type semiconductor region 114. The first pinning region 113 and the second pinning region 116 are formed of, for example, a p-type semiconductor region.

[0391] A fixed charge film 112 having a negative fixed charge is provided between the semiconductor layer 100S and the insulating film 111. A first pinning region 113 of the hole accumulation layer is formed at the interface on the light-receiving surface (rear surface) side of the semiconductor layer 100S due to an electric field induced by the fixed charge film 112. This suppresses the generation of dark current due to the interface state on the light-receiving surface side of the semiconductor layer 100S. The fixed charge film 112 is formed, for example, of an insulating film having a negative fixed charge. Examples of materials for the insulating film having a negative fixed charge include hafnium oxide, zirconium oxide, aluminum oxide, titanium oxide, and tantalum oxide.

[0392] A light-shielding film 117A is provided between the fixed charge film 112 and the insulating film 111. This light-shielding film 117A may be provided continuously with the light-shielding film 117A constituting the pixel separating section 117. The light-shielding film 117A between the fixed charge film 112 and the insulating film 111 is selectively provided, for example, at a position facing the pixel separating section 117 in the semiconductor layer 100S. The insulating film 111 is provided so as to cover this light-shielding film 117A. The insulating film 111 is made of, for example, silicon oxide.

[0393] The wiring layer 100T provided between the semiconductor layer 100S and the second substrate 200 has an interlayer insulating film 119, pad portions 120 and 121, a passivation film 122, an interlayer insulating film 123, and a bonding film 124 in this order from the semiconductor layer 100S side. The horizontal portion TGb of the transfer gate TG is provided in this wiring layer 100T, for example. The interlayer insulating film 119 is provided over the entire surface of the semiconductor layer 100S and is in contact with the semiconductor layer 100S. The interlayer insulating film 119 is made of, for example, a silicon oxide film. The configuration of the wiring layer 100T is not limited to the above, and may be any configuration having wiring and an insulating film.

[0394] FIG. 68B shows the configuration of the pad sections 120 and 121 together with the planar configuration shown in FIG. 68A. The pad sections 120 and 121 are provided in selective regions on the interlayer insulating film 119. The pad section 120 is for connecting the floating diffusions FD (floating diffusions FD1, FD2, FD3, and FD4) of the pixels 541A, 541B, 541C, and 541D to each other. The pad section 120 is disposed, for example, in the center of the pixel sharing unit 539 in plan view for each pixel sharing unit 539 (FIG. 68B). This pad section 120 is disposed so as to straddle the pixel separating section 117, and is disposed so as to overlap at least a portion of each of the floating diffusions FD1, FD2, FD3, and FD4 (FIGS. 67 and 68B). Specifically, the pad section 120 is formed in a region that overlaps at least a portion of each of the plurality of floating diffusions FD (floating diffusions FD1, FD2, FD3, FD4) that share the pixel circuit 210 and at least a portion of the pixel separation section 117 formed between the plurality of photodiodes PD (photodiodes PD1, PD2, PD3, PD4) that share the pixel circuit 210 in a direction perpendicular to the surface of the semiconductor layer 100S. The interlayer insulating film 119 is provided with a connection via 120C for electrically connecting the pad section 120 and the floating diffusions FD1, FD2, FD3, FD4. The connection via 120C is provided in each of the pixels 541A, 541B, 541C, 541D. For example, a portion of the pad section 120 is embedded in the connection via 120C, so that the pad section 120 and the floating diffusions FD1, FD2, FD3, FD4 are electrically connected.

[0395] The pad portion 121 is for connecting the multiple VSS contact regions 118 to each other. For example, the VSS contact regions 118 provided in the pixels 541C and 541D of one pixel sharing unit 539 adjacent to each other in the V direction and the VSS contact regions 118 provided in the pixels 541A and 541B of the other pixel sharing unit 539 are electrically connected by the pad portion 121. The pad portion 121 is provided, for example, so as to straddle the pixel separation portion 117, and is arranged so as to overlap at least a part of each of the four VSS contact regions 118. Specifically, the pad portion 121 is formed in a region that overlaps at least a part of each of the multiple VSS contact regions 118 and at least a part of the pixel separation portion 117 formed between the multiple VSS contact regions 118 in a direction perpendicular to the surface of the semiconductor layer 100S. The interlayer insulating film 119 is provided with a connection via 121C for electrically connecting the pad portion 121 and the VSS contact region 118. The connection via 121C is provided in each of the pixels 541A, 541B, 541C, and 541D. For example, a part of the pad portion 121 is embedded in the connection via 121C, thereby electrically connecting the pad portion 121 and the VSS contact region 118. For example, the pad portion 120 and the pad portion 121 of each of the multiple pixel sharing units 539 aligned in the V direction are disposed at approximately the same position in the H direction ( FIG. 68B ).

[0396] By providing the pad section 120, it is possible to reduce the wiring for connecting each floating diffusion FD to the pixel circuit 210 (for example, the gate electrode of the amplification transistor AMP) in the entire chip. Similarly, by providing the pad section 121, it is possible to reduce the wiring for supplying a potential to each VSS contact region 118 in the entire chip. This makes it possible to reduce the area of ​​the entire chip, suppress electrical interference between wiring in miniaturized pixels, and / or reduce costs by reducing the number of components.

[0397] The pad parts 120 and 121 can be provided at desired positions on the first substrate 100 and the second substrate 200. Specifically, the pad parts 120 and 121 can be provided on either the wiring layer 100T or the insulating region 212 of the semiconductor layer 200S. When provided on the wiring layer 100T, the pad parts 120 and 121 may be directly in contact with the semiconductor layer 100S. Specifically, the pad parts 120 and 121 may be directly connected to at least a part of each of the floating diffusion FD and / or the VSS contact region 118. Also, the pad parts 120 and 121 may be provided at desired positions in the insulating region 212 of the wiring layer 100T and the semiconductor layer 200S by providing connection vias 120C and 121C from each of the floating diffusion FD and / or the VSS contact region 118 connected to the pad parts 120 and 121.

[0398] In particular, when the pad portions 120, 121 are provided in the wiring layer 100T, it is possible to reduce the number of wirings connected to the floating diffusion FD and / or the VSS contact region 118 in the insulating region 212 of the semiconductor layer 200S. This makes it possible to reduce the area of ​​the insulating region 212 for forming the through wiring for connecting the floating diffusion FD to the pixel circuit 210, among the second substrate 200 for forming the pixel circuit 210. Therefore, it is possible to secure a large area for the second substrate 200 for forming the pixel circuit 210. By securing the area for the pixel circuit 210, it is possible to form a large pixel transistor, which can contribute to improving image quality by reducing noise, etc.

[0399] In particular, when an FTI structure is used for the pixel separation section 117, it is preferable to provide a floating diffusion FD and / or a VSS contact region 118 in each pixel 541, and therefore, by using the configuration of the pad sections 120, 121, the wiring connecting the first substrate 100 and the second substrate 200 can be significantly reduced.

[0400] 68B, for example, the pad section 120 to which the floating diffusions FD are connected and the pad section 121 to which the VSS contact regions 118 are connected are alternately arranged in a straight line in the V direction. The pad sections 120 and 121 are formed at positions surrounded by the photodiodes PD, the transfer gates TG, and the floating diffusions FD. This allows elements other than the floating diffusions FD and the VSS contact regions 118 to be freely arranged on the first substrate 100 on which the elements are formed, and the layout of the entire chip can be made more efficient. In addition, symmetry in the layout of the elements formed in each pixel sharing unit 539 is ensured, and the variation in the characteristics of each pixel 541 can be suppressed.

[0401] The pad parts 120 and 121 are made of, for example, polysilicon (Poly Si), more specifically, doped polysilicon to which impurities are added. The pad parts 120 and 121 are preferably made of a conductive material with high heat resistance, such as polysilicon, tungsten (W), titanium (Ti), and titanium nitride (TiN). This makes it possible to form the pixel circuit 210 after bonding the semiconductor layer 200S of the second substrate 200 to the first substrate 100. The reason for this will be explained below. In the following explanation, the method of forming the pixel circuit 210 after bonding the semiconductor layer 200S of the first substrate 100 to the semiconductor layer 200S of the second substrate 200 is called the first manufacturing method.

[0402] Here, it is also conceivable to form the pixel circuits 210 on the second substrate 200 and then bond it to the first substrate 100 (hereinafter referred to as the second manufacturing method). In this second manufacturing method, electrodes for electrical connection are formed in advance on the surface of the first substrate 100 (surface of the wiring layer 100T) and the surface of the second substrate 200 (surface of the wiring layer 200T). When the first substrate 100 and the second substrate 200 are bonded together, the electrodes for electrical connection formed on the surfaces of the first substrate 100 and the second substrate 200 come into contact with each other at the same time. As a result, an electrical connection is formed between the wiring included in the first substrate 100 and the wiring included in the second substrate 200. Therefore, by configuring the imaging device 1 using the second manufacturing method, it is possible to manufacture the imaging device using an appropriate process according to the configuration of each of the first substrate 100 and the second substrate 200, for example, and it is possible to manufacture a high-quality, high-performance imaging device.

[0403] In such a second manufacturing method, when the first substrate 100 and the second substrate 200 are bonded together, an alignment error may occur due to a manufacturing device for bonding. In addition, the first substrate 100 and the second substrate 200 have a diameter of, for example, several tens of centimeters, and when the first substrate 100 and the second substrate 200 are bonded together, the substrates may expand and contract in microscopic regions of the first substrate 100 and the second substrate 200. This expansion and contraction of the substrates is caused by a slight difference in the timing at which the substrates contact each other. Due to such expansion and contraction of the first substrate 100 and the second substrate 200, an error may occur in the position of the electrodes for electrical connection formed on the surface of the first substrate 100 and the surface of the second substrate 200. In the second manufacturing method, it is preferable to take measures so that the electrodes of the first substrate 100 and the second substrate 200 contact each other even if such an error occurs. Specifically, at least one, and preferably both, of the electrodes of the first substrate 100 and the second substrate 200 are made large in consideration of the above-mentioned error. Therefore, when the second manufacturing method is used, for example, the size (size in the substrate planar direction) of the electrode formed on the surface of the first substrate 100 or the second substrate 200 becomes larger than the size of the internal electrode extending in the thickness direction from the inside of the first substrate 100 or the second substrate 200 to the surface.

[0404] On the other hand, by forming the pad parts 120, 121 from a heat-resistant conductive material, it becomes possible to use the first manufacturing method. In the first manufacturing method, after forming the first substrate 100 including the photodiode PD and the transfer transistor TR, the first substrate 100 and the second substrate 200 (semiconductor layer 2000S) are bonded together. At this time, the second substrate 200 is in a state in which the patterns of the active elements and wiring layers constituting the pixel circuits 210 have not yet been formed. Since the second substrate 200 is in a state before the patterns are formed, even if an error occurs in the bonding position when the first substrate 100 and the second substrate 200 are bonded together, this bonding error does not cause an error in the alignment between the pattern of the first substrate 100 and the pattern of the second substrate 200. This is because the pattern of the second substrate 200 is formed after the first substrate 100 and the second substrate 200 are bonded together. When forming a pattern on the second substrate, for example, an exposure device for pattern formation performs pattern formation while using the pattern formed on the first substrate as a target for alignment. For the above reasons, errors in the bonding positions of the first substrate 100 and the second substrate 200 do not pose a problem in manufacturing the imaging device 1 in the first manufacturing method. For the same reason, errors caused by expansion and contraction of the substrates in the second manufacturing method do not pose a problem in manufacturing the imaging device 1 in the first manufacturing method.

[0405] In the first manufacturing method, after the first substrate 100 and the second substrate 200 (semiconductor layer 200S) are bonded together in this manner, active elements are formed on the second substrate 200. After that, the through electrodes 120E, 121E and the through electrodes TGV (FIG. 67) are formed. In forming the through electrodes 120E, 121E, and TGV, for example, a pattern of the through electrodes is formed from above the second substrate 200 using reduced projection exposure by an exposure device. Since reduced projection exposure is used, even if an error occurs in the alignment between the second substrate 200 and the exposure device, the magnitude of the error is only a fraction (the reciprocal of the reduced projection magnification) of the error in the second substrate 200 in the second manufacturing method. Therefore, by configuring the imaging device 1 using the first manufacturing method, it becomes easier to align the elements formed on the first substrate 100 and the second substrate 200, and a high-quality, high-performance imaging device can be manufactured.

[0406] The imaging device 1 manufactured using such a first manufacturing method has different characteristics from the imaging device manufactured using the second manufacturing method. Specifically, in the imaging device 1 manufactured using the first manufacturing method, for example, the through electrodes 120E, 121E, and TGV have a substantially constant thickness (size in the substrate plane direction) from the second substrate 200 to the first substrate 100. Alternatively, when the through electrodes 120E, 121E, and TGV have a tapered shape, they have a tapered shape with a constant inclination. The imaging device 1 having such through electrodes 120E, 121E, and TGV makes it easy to miniaturize the pixels 541.

[0407] Here, when the imaging device 1 is manufactured by the first manufacturing method, since the active elements are formed on the second substrate 200 after bonding the first substrate 100 and the second substrate 200 (semiconductor layer 200S), the first substrate 100 is also affected by the heat treatment required for forming the active elements. For this reason, as described above, it is preferable to use a conductive material with high heat resistance for the pad parts 120, 121 provided on the first substrate 100. For example, it is preferable to use a material with a higher melting point (i.e., higher heat resistance) for the pad parts 120, 121 than at least a part of the wiring material included in the wiring layer 200T of the second substrate 200. For example, a conductive material with high heat resistance such as doped polysilicon, tungsten, titanium, or titanium nitride is used for the pad parts 120, 121. This makes it possible to manufacture the imaging device 1 by using the first manufacturing method described above.

[0408] The passivation film 122 is provided over the entire surface of the semiconductor layer 100S so as to cover the pad portions 120 and 121 (FIG. 67). The passivation film 122 is made of, for example, a silicon nitride (SiN) film. The interlayer insulating film 123 covers the pad portions 120 and 121 with the passivation film 122 therebetween. This interlayer insulating film 123 is provided over the entire surface of the semiconductor layer 100S. The interlayer insulating film 123 is made of, for example, a silicon oxide (SiO) film. The bonding film 124 is provided on the bonding surface between the first substrate 100 (specifically, the wiring layer 100T) and the second substrate 200. That is, the bonding film 124 is in contact with the second substrate 200. This bonding film 124 is provided over the entire main surface of the first substrate 100. The bonding film 124 is made of, for example, a silicon nitride film.

[0409] The light receiving lens 401 faces, for example, the semiconductor layer 100S with the fixed charge film 112 and the insulating film 111 therebetween (FIG. 67). The light receiving lens 401 is provided, for example, at a position facing the photodiode PD of each of the pixels 541A, 541B, 541C, and 541D.

[0410] The second substrate 200 has a semiconductor layer 200S and a wiring layer 200T in this order from the first substrate 100 side. The semiconductor layer 200S is made of a silicon substrate. A well region 211 is provided in the semiconductor layer 200S across the thickness direction. The well region 211 is, for example, a p-type semiconductor region. The second substrate 200 is provided with a pixel circuit 210 arranged for each pixel sharing unit 539. The pixel circuit 210 is provided, for example, on the front surface side (the wiring layer 200T side) of the semiconductor layer 200S. In the imaging device 1, the second substrate 200 is bonded to the first substrate 100 such that the back surface side (the semiconductor layer 200S side) of the second substrate 200 faces the front surface side (the wiring layer 100T side) of the first substrate 100. That is, the second substrate 200 is bonded to the first substrate 100 face-to-back.

[0411] 69 to 73 show an example of the planar configuration of the second substrate 200. FIG. 69 shows the configuration of the pixel circuit 210 provided near the surface of the semiconductor layer 200S. FIG. 70 shows the configuration of the wiring layer 200T (specifically, the first wiring layer W1 described later), the semiconductor layer 200S connected to the wiring layer 200T, and each part of the first substrate 100. FIG. 71 to FIG. 73 show an example of the planar configuration of the wiring layer 200T. Hereinafter, the configuration of the second substrate 200 will be described with reference to FIG. 67 and FIG. 69 to FIG. 73. In FIG. 69 and FIG. 70, the outline of the photodiode PD (the boundary between the pixel isolation portion 117 and the photodiode PD) is shown by a dashed line, and the boundary between the semiconductor layer 200S and the element isolation region 213 or the insulating region 212 in the portion overlapping the gate electrode of each transistor constituting the pixel circuit 210 is shown by a dotted line. In the portion overlapping with the gate electrode of the amplifying transistor AMP, a boundary between the semiconductor layer 200S and the element isolation region 213 and a boundary between the element isolation region 213 and the insulating region 212 are provided on one side in the channel width direction.

[0412] The second substrate 200 is provided with an insulating region 212 that divides the semiconductor layer 200S and an element isolation region 213 provided in a part of the semiconductor layer 200S in the thickness direction (FIG. 67). For example, in the insulating region 212 provided between two pixel circuits 210 adjacent to each other in the H direction, the through electrodes 120E, 121E and through electrodes TGV (through electrodes TGV1, TGV2, TGV3, TGV4) of two pixel sharing units 539 connected to the two pixel circuits 210 are arranged (FIG. 70).

[0413] The insulating region 212 has approximately the same thickness as the semiconductor layer 200S (FIG. 67). The semiconductor layer 200S is divided by this insulating region 212. The through electrodes 120E, 121E and the through electrodes TGV are arranged in this insulating region 212. The insulating region 212 is made of, for example, silicon oxide.

[0414] The through electrodes 120E, 121E are provided penetrating the insulating region 212 in the thickness direction. The upper ends of the through electrodes 120E, 121E are connected to the wiring of the wiring layer 200T (first wiring layer W1, second wiring layer W2, third wiring layer W3, and fourth wiring layer W4 described later). The through electrodes 120E, 121E are provided penetrating the insulating region 212, the bonding film 124, the interlayer insulating film 123, and the passivation film 122, and the lower ends are connected to the pad parts 120, 121 (FIG. 67). The through electrodes 120E are for electrically connecting the pad part 120 and the pixel circuit 210. That is, the floating diffusion FD of the first substrate 100 is electrically connected to the pixel circuit 210 of the second substrate 200 by the through electrodes 120E. The through electrode 121E is for electrically connecting the pad portion 121 and the reference potential line VSS of the wiring layer 200T. That is, the through electrode 121E electrically connects the VSS contact region 118 of the first substrate 100 to the reference potential line VSS of the second substrate 200.

[0415] The through electrode TGV is provided to penetrate the insulating region 212 in the thickness direction. The upper end of the through electrode TGV is connected to the wiring of the wiring layer 200T. This through electrode TGV is provided to penetrate the insulating region 212, the bonding film 124, the interlayer insulating film 123, the passivation film 122, and the interlayer insulating film 119, and its lower end is connected to the transfer gate TG (FIG. 67). Such a through electrode TGV is for electrically connecting the transfer gate TG (transfer gates TG1, TG2, TG3, TG4) of each of the pixels 541A, 541B, 541C, 541D to the wiring of the wiring layer 200T (a part of the row driving signal line 542, specifically, the wirings TRG1, TRG2, TRG3, TRG4 in FIG. 72 described later). That is, the transfer gate TG of the first substrate 100 is electrically connected to the wiring TRG of the second substrate 200 by the through electrode TGV, so that a drive signal is sent to each of the transfer transistors TR (transfer transistors TR1, TR2, TR3, TR4).

[0416] The insulating region 212 is a region for providing the through electrodes 120E, 121E and the through electrodes TGV for electrically connecting the first substrate 100 and the second substrate 200 insulated from the semiconductor layer 200S. For example, the through electrodes 120E, 121E and the through electrodes TGV (through electrodes TGV1, TGV2, TGV3, TGV4) connected to the two pixel circuits 210 (pixel sharing units 539) adjacent to each other in the H direction are provided in the insulating region 212. The insulating region 212 is provided, for example, extending in the V direction (FIGS. 69 and 70). Here, the position of the through electrodes TGV in the H direction is arranged closer to the position of the through electrodes 120E, 121E in the H direction than the position of the vertical part TGa by devising the arrangement of the horizontal part TGb of the transfer gate TG (FIGS. 68A and 70). For example, the through electrode TGV is disposed at approximately the same position as the through electrodes 120E, 120E in the H direction. This allows the through electrodes 120E, 121E and the through electrode TGV to be provided together in the insulating region 212 extending in the V direction. As another arrangement example, it is possible to provide the horizontal part TGb only in the region overlapping the vertical part TGa. In this case, the through electrode TGV is formed approximately directly above the vertical part TGa, and the through electrode TGV is disposed, for example, in the approximately center of each pixel 541 in the H direction and the V direction. At this time, the position of the through electrode TGV in the H direction and the position of the through electrodes 120E, 121E in the H direction are largely shifted. For example, an insulating region 212 is provided around the through electrodes TGV and the through electrodes 120E, 121E to electrically insulate them from the adjacent semiconductor layer 200S. When the position of the through electrode TGV in the H direction is significantly separated from the positions of the through electrodes 120E, 121E in the H direction, it is necessary to provide an insulating region 212 independently around each of the through electrodes 120E, 121E, and TGV. This results in the semiconductor layer 200S being divided into small pieces. In contrast, a layout in which the through electrodes 120E, 121E and the through electrode TGV are collectively disposed in the insulating region 212 extending in the V direction can increase the size of the semiconductor layer 200S in the H direction. This makes it possible to secure a large area for the semiconductor element formation region in the semiconductor layer 200S.This makes it possible, for example, to increase the size of the amplification transistor AMP and suppress noise.

[0417] As described with reference to FIG. 65, the pixel sharing unit 539 has a structure in which the floating diffusions FD provided in the respective pixels 541 are electrically connected to each other, and the pixels 541 share one pixel circuit 210. The floating diffusions FD are electrically connected to each other by a pad section 120 provided on the first substrate 100 (FIGS. 67 and 68B). The electrical connection section (pad section 120) provided on the first substrate 100 and the pixel circuit 210 provided on the second substrate 200 are electrically connected to each other via one through electrode 120E. As another structural example, it is also possible to provide the electrical connection section between the floating diffusions FD on the second substrate 200. In this case, the pixel sharing unit 539 is provided with four through electrodes connected to the floating diffusions FD1, FD2, FD3, and FD4, respectively. Therefore, in the second substrate 200, the number of through electrodes penetrating the semiconductor layer 200S increases, and the insulating region 212 that insulates the periphery of these through electrodes becomes larger. In comparison, the structure in which the pad portion 120 is provided in the first substrate 100 (FIGS. 67 and 68B) can reduce the number of through electrodes and make the insulating region 212 smaller. Therefore, a large area can be secured for the semiconductor element formation region in the semiconductor layer 200S. This makes it possible, for example, to increase the size of the amplification transistor AMP and suppress noise.

[0418] The element isolation region 213 is provided on the surface side of the semiconductor layer 200S. The element isolation region 213 has an STI (Shallow Trench Isolation) structure. In the element isolation region 213, the semiconductor layer 200S is dug in the thickness direction (perpendicular to the main surface of the second substrate 200), and an insulating film is embedded in the dug portion. The insulating film is made of, for example, silicon oxide. The element isolation region 213 isolates a plurality of transistors constituting the pixel circuit 210 according to the layout of the pixel circuit 210. The semiconductor layer 200S (specifically, the well region 211) extends below the element isolation region 213 (deep in the semiconductor layer 200S).

[0419] Here, with reference to Figures 68A, 68B, and 69, the difference between the outer shape (outer shape in the substrate planar direction) of the pixel sharing unit 539 on the first substrate 100 and the outer shape of the pixel sharing unit 539 on the second substrate 200 will be described.

[0420] In the imaging device 1, a pixel sharing unit 539 is provided across both the first substrate 100 and the second substrate 200. For example, the outer shape of the pixel sharing unit 539 provided on the first substrate 100 and the outer shape of the pixel sharing unit 539 provided on the second substrate 200 are different from each other.

[0421] 68A and 68B, the outlines of the pixels 541A, 541B, 541C, and 541D are indicated by dashed lines, and the outline shape of the pixel sharing unit 539 is indicated by a thick line. For example, the pixel sharing unit 539 of the first substrate 100 is configured with two pixels 541 (pixels 541A and 541B) arranged adjacent to each other in the H direction, and two pixels 541 (pixels 541C and 541D) arranged adjacent to each other in the V direction. That is, the pixel sharing unit 539 of the first substrate 100 is configured with four pixels 541 arranged in two rows and two columns adjacent to each other, and the pixel sharing unit 539 of the first substrate 100 has a substantially square outline shape. In the pixel array section 540, such pixel sharing units 539 are arranged adjacent to each other at a two pixel pitch in the H direction (a pitch equivalent to two pixels 541) and at a two pixel pitch in the V direction (a pitch equivalent to two pixels 541).

[0422] In Fig. 69 and Fig. 70, the outlines of the pixels 541A, 541B, 541C, and 541D are indicated by dashed lines, and the outline shape of the pixel sharing unit 539 is indicated by a thick line. For example, the outline shape of the pixel sharing unit 539 of the second substrate 200 is smaller than that of the pixel sharing unit 539 of the first substrate 100 in the H direction, and is larger than that of the pixel sharing unit 539 of the first substrate 100 in the V direction. For example, the pixel sharing unit 539 of the second substrate 200 is formed with a size (area) equivalent to one pixel in the H direction, and is formed with a size equivalent to four pixels in the V direction. That is, the pixel sharing unit 539 of the second substrate 200 is formed with a size equivalent to adjacent pixels arranged in one row x four columns, and the pixel sharing unit 539 of the second substrate 200 has a substantially rectangular outline shape.

[0423] For example, in each pixel circuit 210, the selection transistor SEL, the amplification transistor AMP, the reset transistor RST, and the FD conversion gain switching transistor FDG are arranged in this order in the V direction (FIG. 69). By providing the outer shape of each pixel circuit 210 in a substantially rectangular shape as described above, it is possible to arrange four transistors (the selection transistor SEL, the amplification transistor AMP, the reset transistor RST, and the FD conversion gain switching transistor FDG) in one direction (the V direction in FIG. 69). This allows the drain of the amplification transistor AMP and the drain of the reset transistor RST to be shared in one diffusion region (the diffusion region connected to the power supply line VDD). For example, it is also possible to provide the formation region of each pixel circuit 210 in a substantially square shape (see FIG. 82 described later). In this case, two transistors are arranged along one direction, and it becomes difficult to share the drain of the amplification transistor AMP and the drain of the reset transistor RST in one diffusion region. Therefore, by providing the formation region of the pixel circuit 210 in a substantially rectangular shape, it becomes easier to arrange the four transistors close to each other, and the formation region of the pixel circuit 210 can be made smaller. That is, the pixel can be miniaturized. Furthermore, when it is not necessary to reduce the formation area of ​​the pixel circuit 210, it is possible to increase the formation area of ​​the amplification transistor AMP and suppress noise.

[0424] For example, in addition to the selection transistor SEL, the amplification transistor AMP, the reset transistor RST, and the FD conversion gain switching transistor FDG, a VSS contact region 218 connected to the reference potential line VSS is provided near the surface of the semiconductor layer 200S. The VSS contact region 218 is, for example, configured of a p-type semiconductor region. The VSS contact region 218 is electrically connected to the VSS contact region 118 of the first substrate 100 (semiconductor layer 100S) via the wiring of the wiring layer 200T and the through electrode 121E. This VSS contact region 218 is provided, for example, at a position adjacent to the source of the FD conversion gain switching transistor FDG with the element isolation region 213 therebetween (FIG. 69).

[0425] Next, with reference to Fig. 68B and Fig. 69, the positional relationship between the pixel sharing unit 539 provided on the first substrate 100 and the pixel sharing unit 539 provided on the second substrate 200 will be described. For example, one of the two pixel sharing units 539 arranged in the V direction of the first substrate 100 (for example, the upper side of the paper surface in Fig. 68B) is connected to one of the two pixel sharing units 539 arranged in the H direction of the second substrate 200 (for example, the left side of the paper surface in Fig. 69). For example, the other of the two pixel sharing units 539 arranged in the V direction of the first substrate 100 (for example, the lower side of the paper surface in Fig. 68B) is connected to the other of the two pixel sharing units 539 arranged in the H direction of the second substrate 200 (for example, the right side of the paper surface in Fig. 69).

[0426] For example, of two pixel sharing units 539 arranged in the H direction of the second substrate 200, the internal layout (arrangement of transistors, etc.) of one pixel sharing unit 539 is substantially equal to a layout obtained by inverting the internal layout of the other pixel sharing unit 539 in the V direction and H direction. The effects obtained by this layout will be described below.

[0427] In two pixel sharing units 539 aligned in the V direction of the first substrate 100, each pad section 120 is disposed at the center of the outer shape of the pixel sharing unit 539, that is, the center of the pixel sharing unit 539 in the V direction and the H direction (FIG. 68B). On the other hand, since the pixel sharing unit 539 of the second substrate 200 has an outer shape of a substantially rectangle elongated in the V direction as described above, for example, the amplification transistor AMP connected to the pad section 120 is disposed at a position shifted upward from the center of the pixel sharing unit 539 in the V direction on the paper. For example, when the internal layout of two pixel sharing units 539 aligned in the H direction of the second substrate 200 is the same, the distance between the amplification transistor AMP of one pixel sharing unit 539 and the pad section 120 (for example, the pad section 120 of the pixel sharing unit 539 on the upper side of the paper in FIG. 7) becomes relatively short. However, the distance between the amplification transistor AMP of the other pixel sharing unit 539 and the pad section 120 (for example, the pad section 120 of the pixel sharing unit 539 on the lower side of the paper surface of FIG. 7) becomes longer. Therefore, the area of ​​the wiring required to connect the amplification transistor AMP and the pad section 120 becomes larger, and there is a concern that the wiring layout of the pixel sharing unit 539 becomes complicated. This may affect the miniaturization of the imaging device 1.

[0428] In contrast, by inverting the internal layouts of the two pixel sharing units 539 arranged in the H direction of the second substrate 200 at least in the V direction, the distance between the amplifier transistors AMP and the pad section 120 of both of these two pixel sharing units 539 can be shortened. Therefore, compared with a configuration in which the internal layouts of the two pixel sharing units 539 arranged in the H direction of the second substrate 200 are the same, it is easier to miniaturize the imaging device 1. Note that the planar layout of each of the multiple pixel sharing units 539 of the second substrate 200 is symmetrical within the range shown in FIG. 69, but becomes asymmetrical when the layout of the first wiring layer W1 shown in FIG. 70 described later is included.

[0429] In addition, it is preferable that the internal layouts of the two pixel sharing units 539 arranged in the H direction of the second substrate 200 are also inverted with respect to each other in the H direction. The reason for this will be described below. As shown in FIG. 70, the two pixel sharing units 539 arranged in the H direction of the second substrate 200 are connected to the pad portions 120, 121 of the first substrate 100. For example, the pad portions 120, 121 are disposed in the center portions in the H direction of the two pixel sharing units 539 arranged in the H direction of the second substrate 200 (between the two pixel sharing units 539 arranged in the H direction). Therefore, by inverting the internal layouts of the two pixel sharing units 539 arranged in the H direction of the second substrate 200 with respect to each other in the H direction, the distance between each of the multiple pixel sharing units 539 of the second substrate 200 and the pad portions 120, 121 can be reduced. That is, it becomes easier to miniaturize the imaging device 1.

[0430] In addition, the position of the outline of the pixel sharing unit 539 of the second substrate 200 does not have to be aligned with the position of any of the outlines of the pixel sharing unit 539 of the first substrate 100. For example, of the two pixel sharing units 539 arranged in the H direction of the second substrate 200, in one pixel sharing unit 539 (for example, the left side of the paper in FIG. 70), the outline of one side in the V direction (for example, the upper side of the paper in FIG. 70) is disposed outside the outline of one side in the V direction of the corresponding pixel sharing unit 539 of the first substrate 100 (for example, the upper side of the paper in FIG. 68B). In addition, of the two pixel sharing units 539 arranged in the H direction of the second substrate 200, in the other pixel sharing unit 539 (for example, the right side of the paper in FIG. 70), the outline of the other side in the V direction (for example, the lower side of the paper in FIG. 70) is disposed outside the outline of the other side in the V direction of the corresponding pixel sharing unit 539 of the first substrate 100 (for example, the lower side of the paper in FIG. 68B). In this way, by disposing the pixel sharing unit 539 of the second substrate 200 and the pixel sharing unit 539 of the first substrate 100 relative to each other, it is possible to shorten the distance between the amplification transistor AMP and the pad section 120. Therefore, it becomes easier to miniaturize the imaging device 1.

[0431] Furthermore, the positions of the outlines of the multiple pixel sharing units 539 on the second substrate 200 do not have to be aligned with each other. For example, two pixel sharing units 539 aligned in the H direction of the second substrate 200 are arranged with the positions of the outlines in the V direction shifted. This makes it possible to shorten the distance between the amplification transistor AMP and the pad section 120. This makes it easier to miniaturize the imaging device 1.

[0432] With reference to FIG. 68B and FIG. 70, the repeated arrangement of the pixel sharing units 539 in the pixel array section 540 will be described. The pixel sharing unit 539 of the first substrate 100 has a size equivalent to two pixels 541 in the H direction and a size equivalent to two pixels 541 in the V direction (FIG. 68B). For example, in the pixel array section 540 of the first substrate 100, the pixel sharing units 539 having a size equivalent to four pixels 541 are repeatedly arranged adjacent to each other at a two pixel pitch (a pitch equivalent to two pixels 541) in the H direction and at a two pixel pitch (a pitch equivalent to two pixels 541) in the V direction. Alternatively, the pixel array section 540 of the first substrate 100 may be provided with a pair of pixel sharing units 539 in which two pixel sharing units 539 are arranged adjacent to each other in the V direction. In the pixel array section 540 of the first substrate 100, for example, a pair of pixel sharing units 539 are repeatedly arranged adjacent to each other at a two pixel pitch (a pitch equivalent to two pixels 541) in the H direction and a four pixel pitch (a pitch equivalent to four pixels 541) in the V direction. The pixel sharing unit 539 of the second substrate 200 has a size of one pixel 541 in the H direction and a size of four pixels 541 in the V direction ( FIG. 70 ). For example, the pixel array section 540 of the second substrate 200 is provided with a pair of pixel sharing units 539 including two pixel sharing units 539 each having a size equivalent to four pixels 541. The pixel sharing units 539 are arranged adjacent to each other in the H direction and offset from each other in the V direction. In the pixel array section 540 of the second substrate 200, for example, a pair of pixel sharing units 539 are repeatedly arranged adjacent to each other with no gaps at a two pixel pitch (a pitch equivalent to two pixels 541) in the H direction and at a four pixel pitch (a pitch equivalent to four pixels 541) in the V direction. By repeatedly arranging the pixel sharing units 539 in this way, it is possible to arrange the pixel sharing units 539 without any gaps. This makes it easier to miniaturize the imaging device 1.

[0433] It is preferable that the amplification transistor AMP has a three-dimensional structure, such as a Fin type (FIG. 67). This increases the effective gate width, making it possible to suppress noise. The selection transistor SEL, the reset transistor RST, and the FD conversion gain switching transistor FDG have, for example, a planar structure. The amplification transistor AMP may have a planar structure. Alternatively, the selection transistor SEL, the reset transistor RST, or the FD conversion gain switching transistor FDG may have a three-dimensional structure.

[0434] The wiring layer 200T includes, for example, a passivation film 221, an interlayer insulating film 222, and a plurality of wirings (a first wiring layer W1, a second wiring layer W2, a third wiring layer W3, and a fourth wiring layer W4). The passivation film 221 is in contact with, for example, the surface of the semiconductor layer 200S, and covers the entire surface of the semiconductor layer 200S. This passivation film 221 covers the gate electrodes of the selection transistor SEL, the amplification transistor AMP, the reset transistor RST, and the FD conversion gain switching transistor FDG. The interlayer insulating film 222 is provided between the passivation film 221 and the third substrate 300. This interlayer insulating film 222 separates the plurality of wirings (the first wiring layer W1, the second wiring layer W2, the third wiring layer W3, and the fourth wiring layer W4). The interlayer insulating film 222 is made of, for example, silicon oxide.

[0435] In the wiring layer 200T, for example, from the semiconductor layer 200S side, a first wiring layer W1, a second wiring layer W2, a third wiring layer W3, a fourth wiring layer W4, and contact parts 201, 202 are provided in this order, and these are insulated from each other by an interlayer insulating film 222. In the interlayer insulating film 222, a plurality of connection parts are provided to connect the first wiring layer W1, the second wiring layer W2, the third wiring layer W3, or the fourth wiring layer W4 to the layers below them. The connection parts are parts in which a conductive material is embedded in connection holes provided in the interlayer insulating film 222. For example, in the interlayer insulating film 222, a connection part 218V is provided to connect the first wiring layer W1 and the VSS contact region 218 of the semiconductor layer 200S. For example, the hole diameter of such a connection part that connects elements of the second substrate 200 to each other is different from the hole diameters of the through electrodes 120E, 121E and the through electrodes TGV. Specifically, the diameter of the connection hole connecting the elements of the second substrate 200 is preferably smaller than the diameter of the through electrodes 120E, 121E and the through electrode TGV. The reason for this will be described below. The depth of the connection part (connection part 218V, etc.) provided in the wiring layer 200T is smaller than the depth of the through electrodes 120E, 121E and the through electrode TGV. Therefore, the connection part can be filled with a conductive material more easily than the through electrodes 120E, 121E and the through electrode TGV. By making the diameter of the connection part smaller than the diameter of the through electrodes 120E, 121E and the through electrode TGV, it becomes easier to miniaturize the imaging device 1.

[0436] For example, the first wiring layer W1 connects the through electrode 120E to the gate of the amplification transistor AMP and the source of the FD conversion gain switching transistor FDG (specifically, a connection hole reaching the source of the FD conversion gain switching transistor FDG). The first wiring layer W1 connects, for example, the through electrode 121E to the connection portion 218V, thereby electrically connecting the VSS contact region 218 of the semiconductor layer 200S to the VSS contact region 118 of the semiconductor layer 100S.

[0437] Next, the planar configuration of the wiring layer 200T will be described with reference to Fig. 71 to Fig. 73. Fig. 71 shows an example of the planar configuration of the first wiring layer W1 and the second wiring layer W2. Fig. 72 shows an example of the planar configuration of the second wiring layer W2 and the third wiring layer W3. Fig. 73 shows an example of the planar configuration of the third wiring layer W3 and the fourth wiring layer W4.

[0438] For example, the third wiring layer W3 includes wirings TRG1, TRG2, TRG3, TRG4, SELL, RSTL, and FDGL extending in the H direction (row direction) (FIG. 72). These wirings correspond to the row driving signal lines 542 described with reference to FIG. 65. The wirings TRG1, TRG2, TRG3, and TRG4 are for sending driving signals to the transfer gates TG1, TG2, TG3, and TG4, respectively. The wirings TRG1, TRG2, TRG3, and TRG4 are connected to the transfer gates TG1, TG2, TG3, and TG4 via the second wiring layer W2, the first wiring layer W1, and the through-electrode 120E, respectively. The wiring SELL is for sending a driving signal to the gate of the selection transistor SEL, the wiring RSTL is for sending a driving signal to the gate of the reset transistor RST, and the wiring FDGL is for sending a driving signal to the gate of the FD conversion gain switching transistor FDG, respectively. The wirings SELL, RSTL, and FDGL are each connected to the gates of the selection transistor SEL, the reset transistor RST, and the FD conversion gain switching transistor FDG via the second wiring layer W2, the first wiring layer W1, and a connection portion.

[0439] For example, the fourth wiring layer W4 includes a power supply line VDD, a reference potential line VSS, and a vertical signal line 543 extending in the V direction (column direction) (FIG. 73). The power supply line VDD is connected to the drain of the amplification transistor AMP and the drain of the reset transistor RST via the third wiring layer W3, the second wiring layer W2, the first wiring layer W1, and a connection part. The reference potential line VSS is connected to the VSS contact region 218 via the third wiring layer W3, the second wiring layer W2, the first wiring layer W1, and a connection part 218V. The reference potential line VSS is also connected to the VSS contact region 118 of the first substrate 100 via the third wiring layer W3, the second wiring layer W2, the first wiring layer W1, the through electrode 121E, and the pad part 121. The vertical signal line 543 is connected to the source (Vout) of the selection transistor SEL via the third wiring layer W3, the second wiring layer W2, the first wiring layer W1, and a connection part.

[0440] The contact parts 201 and 202 may be provided at positions overlapping the pixel array part 540 in a plan view (for example, FIG. 64), or may be provided in the outer peripheral part 540B of the pixel array part 540 (for example, FIG. 67). The contact parts 201 and 202 are provided on the surface of the second substrate 200 (surface on the wiring layer 200T side). The contact parts 201 and 202 are made of metal such as Cu (copper) and Al (aluminum). The contact parts 201 and 202 are exposed on the surface of the wiring layer 200T (surface on the third substrate 300 side). The contact parts 201 and 202 are used for electrical connection between the second substrate 200 and the third substrate 300 and for bonding the second substrate 200 and the third substrate 300 together.

[0441] Fig. 67 shows an example in which a peripheral circuit is provided in the peripheral portion 540B of the second substrate 200. This peripheral circuit may include a part of the row driving section 520 or a part of the column signal processing section 550. Also, as shown in Fig. 64, the peripheral circuit may not be arranged in the peripheral portion 540B of the second substrate 200, and the connection holes H1 and H2 may be arranged in the vicinity of the pixel array section 540.

[0442] The third substrate 300 has, for example, a wiring layer 300T and a semiconductor layer 300S in this order from the second substrate 200 side. For example, the surface of the semiconductor layer 300S is provided on the second substrate 200 side. The semiconductor layer 300S is made of a silicon substrate. A circuit is provided on the surface side of the semiconductor layer 300S. Specifically, for example, at least a part of the input unit 510A, the row driver 520, the timing control unit 530, the column signal processing unit 550, the image signal processing unit 560, and the output unit 510B is provided on the surface side of the semiconductor layer 300S. The wiring layer 300T provided between the semiconductor layer 300S and the second substrate 200 includes, for example, an interlayer insulating film, a plurality of wiring layers separated by the interlayer insulating film, and contact units 301 and 302. The contact parts 301 and 302 are exposed on the surface (surface on the second substrate 200 side) of the wiring layer 300T, and the contact part 301 is in contact with the contact part 201 of the second substrate 200, and the contact part 302 is in contact with the contact part 202 of the second substrate 200. The contact parts 301 and 302 are electrically connected to circuits (for example, at least one of the input part 510A, the row driving part 520, the timing control part 530, the column signal processing part 550, the image signal processing part 560, and the output part 510B) formed in the semiconductor layer 300S. The contact parts 301 and 302 are made of metals such as Cu (copper) and aluminum (Al). For example, the external terminal TA is connected to the input part 510A via the connection hole part H1, and the external terminal TB is connected to the output part 510B via the connection hole part H2.

[0443] Here, the features of the imaging device 1 will be described.

[0444] In general, an imaging device mainly consists of a photodiode and a pixel circuit. Increasing the area of ​​the photodiode increases the charge generated as a result of photoelectric conversion, thereby improving the signal-to-noise ratio (S / N ratio) of the pixel signal, and enabling the imaging device to output better image data (image information). On the other hand, increasing the size of the transistors (especially the size of the amplifying transistors) included in the pixel circuit reduces the noise generated in the pixel circuit, thereby improving the S / N ratio of the imaging signal, and enabling the imaging device to output better image data (image information).

[0445] However, in an imaging device in which a photodiode and a pixel circuit are provided on the same semiconductor substrate, if the area of ​​the photodiode is increased within the limited area of ​​the semiconductor substrate, the size of the transistor in the pixel circuit may be reduced, and if the size of the transistor in the pixel circuit is increased, the area of ​​the photodiode may be reduced.

[0446] To solve these problems, for example, the imaging device 1 of the present embodiment uses a structure in which a plurality of pixels 541 share one pixel circuit 210, and the shared pixel circuit 210 is arranged so as to overlap the photodiode PD. This makes it possible to maximize the area of ​​the photodiode PD and to maximize the size of the transistor provided in the pixel circuit 210 within the limited area of ​​the semiconductor substrate. This improves the S / N ratio of the pixel signal, and enables the imaging device 1 to output better image data (image information).

[0447] When realizing a structure in which a plurality of pixels 541 share one pixel circuit 210 and this is arranged to overlap the photodiode PD, a plurality of wirings connected to one pixel circuit 210 extend from the floating diffusion FD of each of the plurality of pixels 541. In order to secure a large area of ​​the semiconductor substrate 200 in which the pixel circuit 210 is formed, for example, a connection wiring can be formed that connects the plurality of extending wirings to each other and combines them into one. Similarly, for the plurality of wirings extending from the VSS contact region 118, a connection wiring can be formed that connects the plurality of extending wirings to each other and combines them into one.

[0448] For example, if a connection wiring that interconnects the multiple wirings extending from the floating diffusion FD of each of the multiple pixels 541 is formed in the semiconductor substrate 200 that forms the pixel circuit 210, it is conceivable that the area for forming the transistors included in the pixel circuit 210 will be reduced. Similarly, if a connection wiring that interconnects the multiple wirings extending from the VSS contact region 118 of each of the multiple pixels 541 and combines them into one is formed in the semiconductor substrate 200 that forms the pixel circuit 210, it is conceivable that the area for forming the transistors included in the pixel circuit 210 will be reduced.

[0449] In order to solve these problems, for example, the imaging device 1 of this embodiment can have a structure in which a plurality of pixels 541 share one pixel circuit 210, and the shared pixel circuit 210 is arranged superimposed on a photodiode PD, and the first substrate 100 can be provided with a connection wiring that interconnects and combines the floating diffusions FD of the plurality of pixels 541, and a connection wiring that interconnects and combines the VSS contact regions 118 provided in each of the plurality of pixels 541.

[0450] Here, when the above-mentioned second manufacturing method is used as a manufacturing method for providing the first substrate 100 with the connection wiring for connecting the floating diffusions FD of the plurality of pixels 541 to one another and the connection wiring for connecting the VSS contact regions 118 of the plurality of pixels 541 to one another, for example, the first substrate 100 and the second substrate 200 can be manufactured using an appropriate process according to the configuration of each substrate, and a high-quality, high-performance imaging device can be manufactured. In addition, the connection wiring of the first substrate 100 and the second substrate 200 can be formed by a simple process. Specifically, when the above-mentioned second manufacturing method is used, an electrode connected to the floating diffusion FD and an electrode connected to the VSS contact region 118 are provided on the surface of the first substrate 100 and the surface of the second substrate 200, which are the bonding interface between the first substrate 100 and the second substrate 200. Furthermore, it is preferable to make the electrodes formed on the surfaces of the two substrates large so that the electrodes can contact each other even if a positional deviation occurs between the electrodes provided on the surfaces of the two substrates when the first substrate 100 and the second substrate 200 are bonded together. In this case, it may become difficult to arrange the electrodes within the limited area of ​​each pixel of the imaging device 1.

[0451] In order to solve the problem of needing a large electrode at the bonding inte...

Claims

1. a first substrate having sensor pixels that perform photoelectric conversion; a pixel circuit that outputs a pixel signal based on the charge output from the sensor pixel; a second substrate having a second semiconductor substrate and a plurality of wirings; a third substrate having a processing circuit for processing the pixel signal; Equipped with the first substrate, the second substrate, and the third substrate are stacked in this order; The first substrate and the second substrate are provided with an insulating region and a low dielectric constant region having a dielectric constant lower than that of the insulating region, the sensor pixel and the pixel circuit are electrically connected by through-wiring that penetrates the second semiconductor substrate and is connected to each of the plurality of wirings; the low dielectric constant region includes a first low dielectric constant region and a second low dielectric constant region that are physically separated from each other; the first low dielectric constant region is provided in a region surrounding the through-hole wiring, The second low dielectric constant region is provided in a region between the plurality of wirings. Imaging device.

2. The sensor pixel includes a photoelectric conversion element, a transfer transistor electrically connected to the photoelectric conversion element, and a floating diffusion that temporarily holds the charge output from the photoelectric conversion element via the transfer transistor; 2. The imaging device according to claim 1, wherein the pixel circuit comprises: a reset transistor that resets a potential of the floating diffusion to a predetermined potential; an amplification transistor that generates, as the pixel signal, a signal having a voltage corresponding to a level of the charge held in the floating diffusion; and a selection transistor that controls an output timing of the pixel signal from the amplification transistor.

3. the first substrate includes a first semiconductor substrate having the photoelectric conversion element, the transfer transistor, and the floating diffusion provided on a front surface side thereof; the second semiconductor substrate has the reset transistor, the amplification transistor, and the selection transistor provided on a front surface side thereof; The imaging device according to claim 2 , wherein the second substrate is bonded to the front surface side of the first semiconductor substrate with a back surface side of the second semiconductor substrate opposite to the front surface facing the front surface side.

4. The imaging device according to claim 3 , wherein the through-hole interconnect electrically connects the floating diffusion and the amplifying transistor.

5. the first substrate includes the photoelectric conversion element and the transfer transistor for each of the sensor pixels, and the floating diffusion is shared by a plurality of the sensor pixels; the second substrate includes the pixel circuit for each of the plurality of sensor pixels that share the floating diffusion; The imaging device according to claim 3 , wherein the through wiring electrically connects the floating diffusion shared by each of a plurality of the sensor pixels and the amplification transistor.

6. The imaging device according to claim 3 , wherein the low dielectric constant region is provided at least in a region between the through-hole wiring and the second semiconductor substrate.

7. The imaging device according to claim 6 , wherein the low dielectric constant region is provided in a region that completely surrounds the through-hole wiring.

8. The second semiconductor substrate has a through hole through which the through wiring passes, The imaging device according to claim 3 , wherein the low dielectric constant region is provided in a region along an inner periphery of the through hole.

9. The imaging device according to claim 8 , wherein the low dielectric constant region is provided in a region corresponding to a sidewall on an inner surface of the through hole.

10. The imaging device according to claim 8 , wherein the through-hole includes a plurality of through-wires.

11. The imaging device according to claim 3 , wherein the low dielectric constant region is provided in a region on one or more sides of the reset transistor, the amplifier transistor, or the selection transistor.

12. The imaging device according to claim 1 , wherein the low dielectric constant region is provided in at least a region corresponding to a side of the second semiconductor substrate.

13. The imaging device according to claim 8 , wherein the low dielectric constant region is provided in a region surrounded by an insulating material having an etching rate different from that of an insulating material filling the through hole.

14. The imaging device according to claim 3 , wherein the low dielectric constant region is provided in a region below one or more of the reset transistor, the amplifying transistor, and the selection transistor.

15. 15. The imaging device according to claim 14, wherein the low dielectric constant region is provided at least in a planar region where, when viewed in a plane from the stacking direction, the amplification transistor provided in the second semiconductor substrate and a gate electrode of the transfer transistor provided in the first semiconductor substrate overlap with each other.

16. The imaging device according to claim 14 , wherein the low dielectric constant region is provided adjacent to the back surface of the second semiconductor substrate.

17. The imaging device according to claim 1 , wherein the low dielectric constant region has a planar shape that is rectangular.

18. The imaging device of claim 1, wherein the low dielectric constant region is composed of a void and a low dielectric constant material that fills a portion of the inside of the void and has a lower dielectric constant than the surrounding area of ​​the low dielectric constant region.

19. The imaging device described in Claim 18, wherein the low dielectric constant material constituting the low dielectric constant region is carbon-doped silicon or porous silica.

Images