Display device and display panel

Abstract

To provide a display device and display panel, which enable implementation of a narrow bezel while improving image quality.SOLUTION: A display device according to an exemplary embodiment comprises: a plurality of sub-pixels; a plurality of data lines, arranged in a column direction, comprising a first data line group arranged in a first area corresponding to a data driving circuit and a second data line group arranged in a second area located on outside of the first area; a plurality of gate lines arranged in a row direction; a first data link line group having a linear structure connected to the first data line group in a bezel area; and a second data link line group having a bent structure in which horizontal second data link lines having the same length are connected to the second data line group through a display area.SELECTED DRAWING: Figure 6

Description

[Technical field]

[0001] An embodiment of the present disclosure relates to a display device and a display panel, and more specifically, to a display device and a display panel capable of realizing a narrow bezel and improving image quality by forming data link lines arranged in a display area of ​​a display panel to have equal lengths. [Background technology]

[0002] As the information society develops, various demands for display devices that display images are increasing, and various types of display devices such as liquid crystal displays (LCDs) and organic light emitting displays are being used.

[0003] Among such display devices, an organic light emitting display device uses an organic light emitting diode (OLED) that emits light by itself, and thus has advantages in terms of a fast response speed, high contrast, luminous efficiency, brightness, viewing angle, and the like.

[0004] Such an organic light emitting display device includes an organic light emitting diode arranged in each of a plurality of subpixels arranged on a display panel, and can display an image by controlling the brightness of each subpixel by controlling the current flowing through the organic light emitting diode to cause the organic light emitting diode to emit light.

[0005] In such display devices, research is being actively conducted to minimize the width of the bezel area formed around the outer periphery of the display area, thereby reducing the overall weight and size of the display device and improving the appearance of the display device. Summary of the Invention [Problem to be solved by the invention]

[0006] The inventors of the present disclosure have invented a display device and a display panel that can improve image quality while achieving a narrow bezel.

[0007] The embodiments of the present disclosure may provide a display device and a display panel capable of implementing a narrow bezel and improving image quality by forming data link lines located in a display area of ​​a display panel with equal lengths.

[0008] An embodiment of the present disclosure may provide a display device and a display panel that can realize a narrow bezel and improve image quality by connecting data lines in a first region corresponding to a data driving circuit with a first data link line group having a straight structure and connecting data lines in a second region corresponding to an outer shell of the data driving circuit with a second data link line group having an equal length and a bent structure. [Means for solving the problem]

[0009] An embodiment of the present disclosure may provide a display device including a display panel including a plurality of sub-pixels, a plurality of data lines arranged in a column direction, and a plurality of gate lines arranged in a row direction, a data driving circuit that supplies data voltages to the display panel through the plurality of data lines, a gate driving circuit that supplies gate signals to the display panel through the plurality of gate lines, and a timing controller that controls the data driving circuit and the gate driving circuit, wherein the display panel includes a first data link line group having a straight structure connecting first data line groups arranged in a first region corresponding to the data driving circuit, and a second data link line group having a bent structure connecting second data line groups arranged in a second region corresponding to an outer shell of the data driving circuit with horizontal second data link lines of the same length.

[0010] An embodiment of the present disclosure may provide a display panel including a plurality of sub-pixels, a first data line group arranged in a first region corresponding to a data driving circuit and a second data line group arranged in a second region corresponding to an outer shell of the data driving circuit, a plurality of data lines arranged in a column direction, a plurality of gate lines arranged in a row direction, a first data link line group having a straight structure connected to the first data line group in a bezel region, and a second data link line group having a bent structure in which horizontal second data link lines of the same length are connected to the second data line group through a display region. Effect of the Invention

[0011] According to an embodiment of the present disclosure, it is possible to provide a display device and a display panel that can improve image quality while realizing a narrow bezel.

[0012] Furthermore, according to the embodiment of the present disclosure, data link lines located in the display area of ​​the display panel are arranged to have equal lengths, thereby realizing a narrow bezel and improving image quality.

[0013] In addition, according to the implementation of the present disclosure, the data lines in the first region corresponding to the data driving circuit are connected by a first data link line group having a straight structure, and the data lines in the second region corresponding to the outer shell of the data driving circuit are connected by a second data link line group having a bent structure having the same length, thereby implementing a narrow bezel and improving image quality. [Brief description of the drawings]

[0014] [Figure 1] 1 is a diagram illustrating a schematic diagram of a display device according to an embodiment of the present disclosure. [Diagram 2] FIG. 1 is a diagram illustrating a system of a display device according to an embodiment of the present disclosure. [Diagram 3] 1 is a diagram illustrating a sub-pixel circuit of a display device according to an embodiment of the present disclosure. [Figure 4] FIG. 2 is a plan view showing an example of a display panel. [Diagram 5] 5 is an enlarged view of part A in FIG. 4. [Figure 6] 1 is a plan view illustrating a structure of a display panel according to an embodiment of the present disclosure. [Figure 7] 4 is a diagram illustrating only a connection structure of data lines arranged in a first region corresponding to a data driving circuit in a display device according to an embodiment of the present disclosure; [Figure 8] 4 is a diagram illustrating only a connection structure of data lines arranged in a second region corresponding to an outer shell of a data driving circuit in a display device according to an embodiment of the present disclosure; [Figure 9] 11 is a diagram illustrating an example of a phenomenon in which stains occur in a certain area when the lengths of horizontal second data link lines are different in a display device according to an embodiment of the present disclosure. [Figure 10] 11 is a circuit diagram illustrating a phenomenon in which stains appear due to a second data link line group having a bent structure in a display device according to an embodiment of the present disclosure. [Figure 11] 13 is a diagram showing a stain due to the shape of a horizontal second data link line in a display device according to an embodiment of the present disclosure. [Figure 12] 11A and 11B are plan views illustrating exemplary display panel structures having different arrangement structures of horizontal second data link lines in a display device according to an embodiment of the present disclosure. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0015] Hereinafter, an embodiment of the present invention will be described in detail with reference to the exemplary drawings. When adding reference numerals to components in each drawing, the same numerals may be used for the same components even if they are displayed in different drawings. In addition, when describing the present invention, if a detailed description of a related known configuration or function is determined to deviate from the gist of the present invention, the detailed description may be omitted. When "includes," "has," "is made," and the like are used in this specification, other elements may be added unless "only" is used. When a component is expressed in the singular, it may include a plural unless otherwise expressly specified.

[0016] In addition, in describing components of the present invention, terms such as 1, 2, A, B, (a), (b), etc. are used. These terms are merely used to distinguish the components from other components, and do not limit the nature, order, sequence, number, etc. of the corresponding components.

[0017] In describing the positional relationship of components, when two or more components are described as being "coupled," "coupled," or "connected," it should be understood that the two or more components may be directly "coupled," "coupled," or "connected," but that other components may also be further "intervening," "coupled," "coupled," or "connected" to the two or more components, where the other components may be included in one or more of the two or more components that are "coupled," "coupled," or "connected" to each other.

[0018] In describing a time flow relationship associated with components, operating methods, manufacturing methods, etc., when a time or flow precedence relationship is described using, for example, "after," "following," "next to," or "before," cases that are not consecutive may be included unless "immediately" or "directly" is used.

[0019] On the other hand, when a numerical value or its corresponding information (e.g., level, etc.) for a component is mentioned, the numerical value or its corresponding information may be interpreted as including an error range that may occur due to various factors (e.g., process factors, internal or external impact, noise, etc.) even if not expressly stated otherwise.

[0020] Hereinafter, various embodiments of the disclosure will be described in detail with reference to the accompanying drawings.

[0021] FIG. 1 is a schematic diagram of a display device according to an embodiment of the present disclosure.

[0022] Referring to FIG. 1, a display device 100 according to an embodiment of the present disclosure may include a display panel 110 and a driving circuit for driving the display panel 110 .

[0023] The display panel 110 may include a display area (DA) where an image is displayed and a bezel area (BA) where an image is not displayed. The bezel area (BA) is also called a non-display area.

[0024] The display panel 110 may include a plurality of sub-pixels (SP) for displaying an image. For example, the plurality of sub-pixels (SP) may be disposed in a display area (DA). In some cases, at least one sub-pixel (SP) may be disposed in a bezel area (BA). The at least one sub-pixel (SP) disposed in the bezel area (BA) may also be referred to as a domi-sub-pixel.

[0025] The display panel 110 may include a plurality of signal wirings for driving a plurality of sub-pixels (SP). For example, the plurality of signal wirings may include a plurality of data lines (DL) and a plurality of gate lines (GL). The signal wirings may further include signal wirings other than the plurality of data lines (DL) and the plurality of gate lines (GL) according to the structure of the sub-pixels (SP). For example, the other signal wirings may include a driving voltage line and a reference voltage line.

[0026] The data lines (DL) and the gate lines (GL) may cross each other. Each of the data lines (DL) may be arranged to extend in a first direction. Each of the gate lines (GL) may be arranged to extend in a second direction. Here, the first direction may be a column direction, and the second direction may be a row direction. In this specification, the column direction and the row direction are relative. For example, the column direction may be a vertical direction, and the row direction may be a horizontal direction. As another example, the column direction may be a horizontal direction, and the row direction may be a vertical direction.

[0027] The driving circuit may include a data driving circuit 130 for driving a plurality of data lines (DL) and a gate driving circuit 120 for driving a plurality of gate lines (GL). The driving circuit may further include a timing controller 140 for controlling the data driving circuit 130 and the gate driving circuit 120.

[0028] The data driving circuit 130 is a circuit for driving a plurality of data lines (DL) and can output data signals (also called data voltages) corresponding to image signals from the plurality of data lines (DL). The gate driving circuit 120 is a circuit for driving a plurality of gate lines (GL) and can generate gate signals and output the gate signals to the plurality of gate lines (GL). The gate signals may include one or more scan signals and light emission signals.

[0029] The timing controller 140 can start scanning according to the timing implemented in each frame and control data driving at an appropriate time according to the scanning. The timing controller 140 can convert input image data input from the outside into a data signal format used in the data driving circuit 130 and supply the converted image data (DATA) to the data driving circuit 130.

[0030] The timing controller 140 may receive display drive control signals together with input image data from an external host system 200. For example, the display drive control signals may include a vertical sync signal, a horizontal sync signal, an input data enable signal, and a clock signal.

[0031] The timing controller 140 can generate a data drive control signal (DCS) and a gate drive control signal (GCS) based on the display drive control signals input from the host system 200. The timing controller 140 can control the drive operation and drive timing of the data drive circuit 130 by supplying the data drive control signal (DCS) to the data drive circuit 130. The timing controller 140 can control the drive operation and drive timing of the gate drive circuit 120 by supplying the gate drive control signal (GCS) to the gate drive circuit 120.

[0032] The data driving circuit 130 may include one or more source driving integrated circuits (SDICs). Each source driving integrated circuit may include a shift register, a latch circuit, a digital to analog converter (DAC), an output buffer, etc. Each source driving integrated circuit may further include an analog to digital converter (ADC) in some cases.

[0033] For example, each source driving integrated circuit may be connected to the display panel 110 using a Tape Automated Bonding (TAB) method, or may be connected to a bonding pad of the display panel 110 using a Chip On Glass (COG) or Chip On Panel (COP) method, or may be configured using a Chip On Film (COF) method and connected to the display panel 110.

[0034] The gate driving circuit 120 can output a gate signal of a turn-on level voltage or a gate signal of a turn-off level voltage under the control of the timing controller 140. The gate driving circuit 120 can sequentially drive a plurality of gate lines (GL) by sequentially supplying gate signals of a turn-on level voltage to the plurality of gate lines (GL).

[0035] The gate driving circuit 120 may include one or more gate driving integrated circuits (GDICs).

[0036] The gate driving circuit 120 may be connected to the display panel 110 by a tape automated bonding (TAB) method, or may be connected to a bonding pad of the display panel 110 by a chip on glass (COG) or chip on panel (COP) method, or may be connected to the display panel 110 according to a chip on film (COF) method. Alternatively, the gate driving circuit 120 may be formed in a bezel area (BA) of the display panel 110 in a gate in panel (GIP) type. The gate driving circuit 120 may be disposed on a substrate or may be connected to a substrate. That is, the gate driving circuit 120 may be disposed in a bezel area (BA) of a substrate in the case of a gate in panel (GIP) type. The gate driving circuit 120 may be connected to a substrate in the case of a chip on glass (COG) type, a chip on film (COF) type, or the like.

[0037] Meanwhile, at least one of the data driving circuit 130 and the gate driving circuit 120 may be disposed in the display area (DA). For example, at least one of the data driving circuit 130 and the gate driving circuit 120 may be disposed so as not to overlap with the sub-pixels (SP), or may be disposed so as to overlap with the sub-pixels (SP) partially or entirely.

[0038] The data driving circuit 130 may be connected to one side (e.g., upper or lower side) of the display panel 110. Depending on the driving method, panel design method, etc., the data driving circuit 130 may be connected to both sides (e.g., upper and lower sides) of the display panel 110, or may be connected to two or more of the four sides of the display panel 110.

[0039] The gate driving circuit 120 may be connected to one side (e.g., the left or right side) of the display panel 110. Depending on the driving method, panel design method, etc., the gate driving circuit 120 may be connected to both sides (e.g., the left and right sides) of the display panel 110, or may be connected to two or more of the four sides of the display panel 110.

[0040] The timing controller 140 may be a separate component from the data driving circuit 130, or may be integrated with the data driving circuit 130 to form an integrated circuit. The timing controller 140 may be a controller used in conventional display technology, a control device that includes a timing controller and can perform other control functions, or may be a circuit within the control device. The timing controller 140 may be formed of various circuits or electronic components such as an integrated circuit (IC), a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), or a processor.

[0041] The timing controller 140 may be mounted on a printed circuit board, a flexible printed circuit, etc., and may be electrically connected to the data driving circuit 130 and the gate driving circuit 120 through the printed circuit board, the flexible printed circuit, etc. The timing controller 140 may transmit and receive signals to and from the data driving circuit 130 through one or more predetermined interfaces. Here, for example, the interfaces may include a Low Voltage Differential Signaling (LVDS) interface, an EPI interface, a Serial Peripheral Interface (SP), etc.

[0042] The display device 100 according to the embodiment of the present disclosure may be a self-emitting display device in which the display panel 110 emits light by itself. When the display device 100 according to the embodiment of the present disclosure is a self-emitting display device, each of the sub-pixels (SP) may include a light-emitting element. For example, the display device 100 according to the embodiment of the present disclosure may be an organic light-emitting display device in which the light-emitting element is an organic light-emitting diode (OLED). As another example, the display device 100 according to the embodiment of the present disclosure may be an inorganic light-emitting display device in which the light-emitting element is an inorganic-based light-emitting diode. As another example, the display device 100 according to the embodiment of the present disclosure may be a quantum dot display device in which the light-emitting element is a quantum dot, which is a semiconductor crystal that emits light by itself.

[0043] FIG. 2 is a diagram illustrating a system of a display device according to an embodiment of the present disclosure.

[0044] Referring to FIG. 2, the display device 100 according to an embodiment of the present disclosure illustrates a case in which the data driving circuit 130 is configured in a COF (Chip On Film) type among various types (TAB, COG, COF, etc.), and the gate driving circuit 120 is configured in a GIP (Gate In Panel) type among various types (TAB, COG, COF, GIP, etc.).

[0045] When the gate driving circuit 120 is configured in the GIP form, a plurality of gate driving integrated circuits (GDICs) included in the gate driving circuit 120 may be directly formed in the bezel region of the display panel 110. In this case, the gate driving integrated circuits (GDICs) may receive various signals (clocks, gate high signals, gate low signals, etc.) required for generating scan signals through gate driving related signal wirings arranged in the bezel region.

[0046] Similarly, one or more source driving integrated circuits (SDICs) included in the data driving circuit 130 may be mounted on the source film (SF), and one side of the source film (SF) may be electrically connected to the display panel 110. Also, wiring for electrically connecting the source driving integrated circuits (SDICs) and the display panel 110 may be disposed on the upper portion of the source film (SF).

[0047] Such a display device 100 may include at least one source printed circuit board (SPCB) for circuit connections between multiple source driving integrated circuits (SDICs) and different devices, and a control printed circuit board (CPCB) for mounting control components and various electrical devices.

[0048] At this time, the other side of the source film (SF) on which the source driving integrated circuit (SDIC) is mounted may be connected to at least one source printed circuit board (SPCB). That is, one side of the source film (SF) on which the source driving integrated circuit (SDIC) is mounted may be electrically connected to the display panel 110, and the other side may be electrically connected to the source printed circuit board (SPCB).

[0049] The control printed circuit board (CPCB) may be mounted with a timing controller 140 and a power management circuit 150. The timing controller 140 may control the operation of the data driving circuit 130 and the gate driving circuit 120. The power management circuit 150 may supply driving voltages and currents to the display panel 110, the data driving circuit 130, the gate driving circuit 120, etc., and may control the supplied voltages and currents.

[0050] At least one source printed circuit board (SPCB) and a control printed circuit board (CPCB) are circuit-connected through at least one connecting member, and the connecting member may be, for example, a flexible printed circuit (FPC), a flexible flat cable (FFC), etc. Also, at least one source printed circuit board (SPCB) and a control printed circuit board (CPCB) may be integrated into one printed circuit board.

[0051] The display device 100 may further include a set board 170 electrically connected to the control printed circuit board (CPCB). In this case, the set board 170 may be a power board. The set board 170 may include a main power management circuit 160 that manages the overall power of the display device 100. The main power management circuit 160 may be linked to the power management circuit 150.

[0052] In the display device 100 configured as above, a driving voltage is generated in the set board 170 and transmitted to the power management circuit 150 in the control printed circuit board (CPCB). The power management circuit 150 transmits a driving voltage required for display driving or characteristic value sensing to the source printed circuit board (SPCB) through a flexible printed circuit (FPC) or a flexible flat cable (FFC). The driving voltage transmitted to the source printed circuit board (SPCB) is supplied to a specific sub-pixel (SP) in the display panel 110 for emitting light or sensing through a source driving integrated circuit (SDIC).

[0053] At this time, each sub-pixel (SP) arranged on the display panel 110 in the display device 100 may be composed of a light emitting element and a circuit element such as a driving transistor for driving the light emitting element.

[0054] The type and number of circuit elements constituting each sub-pixel (SP) may be determined in various ways depending on the provided function and design method.

[0055] FIG. 3 is a diagram illustrating a sub-pixel circuit of a display device according to an embodiment of the present disclosure.

[0056] Referring to FIG. 3, a sub-pixel (SP) of a display device 100 according to an embodiment of the present disclosure may include first to seventh switching transistors (T1-T7), a driving transistor (DRT), a storage capacitor (Cst), and a light emitting element (ED).

[0057] Here, the light emitting device (ED) may be a self-emitting device capable of emitting light such as an organic light emitting diode (OLED), for example.

[0058] In the subpixel (SP) according to an embodiment of the present specification, the second to fourth switching transistors (T2-T4), the sixth switching transistor (T6), the seventh switching transistor (T7) and the driving transistor (DRT) may be P-type transistors, and the first switching transistor (T1) and the fifth switching transistor (T5) may be N-type transistors.

[0059] P-type transistors are relatively more reliable than N-type transistors. In the case of P-type transistors, the source electrode can be fixed at a high potential driving voltage (VDD) when emitting light, so the current flowing through the light emitting element (ED) is less likely to fluctuate due to the capacitor (Cst). Therefore, it is easier to supply a stable current.

[0060] When the P-type transistor is connected to the anode electrode of the light emitting element (ED) and operates in a saturation region, it can pass a constant current regardless of changes in threshold voltage, and therefore has relatively high reliability.

[0061] In such a subpixel (SP) structure, the N-type transistors (T1, T5) may be oxide transistors formed using an oxide semiconductor (e.g., transistors having a channel formed from an oxide semiconductor such as indium, gallium, zinc oxide or IGZO), and the other P-type transistors (DRT, T2-T4, T6, T7) may be silicon transistors formed from a semiconductor such as silicon (e.g., transistors having a polysilicon channel formed using a low-temperature process referred to as LTPS or low-temperature polysilicon).

[0062] Since oxide transistors have a relatively low leakage current compared to silicon transistors, when a transistor is formed using oxide transistors, it is possible to prevent current from leaking from the gate electrode of the driving transistor (DRT), thereby reducing image quality defects such as flicker.

[0063] Meanwhile, the remaining P-type transistors (DRT, T2-T4, T6, T7) except for the first switching transistor T1 and the fifth switching transistor T5, which are N-type transistors, may be made of low temperature polysilicon.

[0064] At this time, the names of the source electrode and the drain electrode of the switching transistor may change depending on the input voltage.

[0065] A gate electrode of the first switching transistor T1 receives a first scan signal SCAN1, a drain electrode of the first switching transistor T1 is connected to a gate electrode of the driving transistor DRT, and a source electrode of the first switching transistor T1 is connected to a drain electrode of the driving transistor DRT.

[0066] The first switching transistor T1 is turned on by the first scan signal SCAN1, and maintains the gate voltage of the driving transistor DRT constant by the storage capacitor Cst, one terminal of which is fixed to the high potential driving voltage VDD.

[0067] The first switching transistor T1 is an oxide transistor and can be an N-type MOS transistor. Since an N-type MOS transistor uses electrons, not holes, as carriers, it has a higher mobility than a P-type MOS transistor and can therefore have a faster switching speed.

[0068] The second switching transistor T2 has a gate electrode receiving a second scan signal SCAN2, a source electrode receiving a data voltage Vdata, and a drain electrode connected to a source electrode of the driving transistor DRT.

[0069] The second switching transistor T2 is turned on by the second scan signal SCAN2 to supply the data voltage Vdata to the source electrode of the driving transistor DRT.

[0070] The third switching transistor T3 has a gate electrode receiving the light emitting signal EM, a source electrode receiving the high potential driving voltage VDD, and a drain electrode connected to the source electrode of the driving transistor DRT.

[0071] The third switching transistor (T3) is turned on by the light emission signal (EM) to supply the high potential driving voltage (VDD) to the source electrode of the driving transistor (DRT).

[0072] The fourth switching transistor T4 has a gate electrode receiving the light emitting signal EM, a source electrode connected to the drain electrode of the driving transistor DRT, and a drain electrode connected to the anode electrode of the light emitting element ED.

[0073] The fourth switching transistor T4 is turned on by the light emitting signal EM to supply a driving current to the anode electrode of the light emitting element ED.

[0074] The gate electrode of the fifth switching transistor T5 is supplied with a fourth scan signal SCAN4.

[0075] Here, the fourth scan signal (SCAN4) may have a different phase from the first scan signal (SCAN1) supplied to the sub-pixels (SP) at other positions. For example, when the first scan signal (SCAN1) is applied to the n-th gate line, the fourth scan signal (SCAN4) may use the first scan signal (SCAN1[00n-1]) applied to the n-1-th gate line. That is, the fourth scan signal (SCAN4) may use the first scan signal (SCAN1) that differs in gate line (GL) depending on the phase in which the display panel 110 is driven.

[0076] The drain electrode of the fifth switching transistor T5 is supplied with the stabilizing voltage Vini, and the source electrode of the fifth switching transistor T5 is connected to the gate electrode of the driving transistor DRT and the storage capacitor Cst.

[0077] The fifth switching transistor T5 is turned on by the fourth scan signal SCAN4 to supply the stabilizing voltage Vini to the gate electrode of the driving transistor DRT.

[0078] A third scan signal (SCAN3) is supplied to the gate electrode of the sixth switching transistor (T6).

[0079] The sixth switching transistor T6 has a source electrode supplied with a reset voltage VAR and a drain electrode connected to an anode electrode of the light emitting element ED.

[0080] The sixth switching transistor T6 is turned on by the third scan signal SCAN3 to supply the reset voltage VAR to the anode electrode of the light emitting element ED.

[0081] A fifth scan signal (SCAN5) is supplied to the gate electrode of the seventh switching transistor (T7).

[0082] A bias voltage VOBS is supplied to a source electrode of the seventh switching transistor T7, and a drain electrode of the seventh switching transistor T7 is connected to a source electrode of the driving transistor DRT.

[0083] Here, the fifth scan signal (SCAN5) may have a different phase from the third scan signal (SCAN3) supplied to the sub-pixels (SP) at other positions. For example, when the third scan signal (SCAN3) is applied to the n-th gate line, the fifth scan signal (SCAN5) may be the third scan signal (SCAN3) applied to the (n-1)th gate line. That is, the fifth scan signal (SCAN5) may use the third scan signal (SCAN3) that differs in gate line (GL) depending on the phase in which the display panel 110 is driven.

[0084] Meanwhile, since the fifth scan signal SCAN5 is a signal for applying the bias voltage VOBS to the driving transistor DRT, it is preferable to distinguish it from the second scan signal SCAN2 for applying the data voltage Vdata.

[0085] The gate electrode of the driving transistor DRT is connected to the drain electrode of the first switching transistor T1, the source electrode of the driving transistor DRT is connected to the drain electrode of the second switching transistor T2, and the drain electrode of the driving transistor DRT is connected to the source electrode of the first switching transistor T1.

[0086] The driving transistor (DRT) is turned on by a voltage difference between the gate electrode and the source electrode, and a driving current is applied to the light emitting element (ED).

[0087] The source electrode and drain electrode of the first switching transistor (T1) are respectively connected to the drain electrode and gate electrode of the driving transistor (DRT), and when the first switching transistor (T1) is turned on, the threshold voltage of the driving transistor (DRT) is sampled according to a data voltage (Vdata) applied to the source electrode of the driving transistor (DRT) to perform a compensation operation.

[0088] A high potential drive voltage (VDD) is applied to one electrode of the storage capacitor (Cst), and the other electrode is connected to the gate electrode of the drive transistor (DRT). The storage capacitor (Cst) stores the voltage of the gate electrode of the drive transistor (DRT).

[0089] An anode electrode of the light emitting element ED is connected to a drain electrode of the fourth switching transistor T4 and a drain electrode of the sixth switching transistor T6, and a low potential driving voltage VSS is applied to a cathode electrode of the light emitting element ED.

[0090] The light emitting element (ED) emits light with a predetermined brightness in response to a driving current flowing through the driving transistor (DRT).

[0091] At this time, the stabilization voltage (Vini) is supplied to stabilize the change in the capacitor formed at the gate electrode of the driving transistor (DRT), and the reset voltage (VAR) is supplied to reset the anode electrode of the light emitting element (ED).

[0092] When a reset voltage (VAR) is supplied to the anode electrode of the light emitting element (ED) while a fourth switching transistor (T4) located between the anode electrode of the light emitting element (ED) and the driving transistor (DRT) and controlled by an emission signal (EM) is turned off, the anode electrode of the light emitting element (ED) can be reset.

[0093] A sixth switching transistor T6 for supplying a reset voltage VAR is connected to the anode electrode of the light emitting element ED.

[0094] The fourth scan signal (SCAN4) for driving or stabilizing the driving transistor (DRT) and the third scan signal (SCAN3) for controlling the supply of the reset voltage (VAR) to the anode electrode of the light-emitting element (ED) may be separated from each other so that the driving operation of the driving transistor (DRT) and the operation of resetting the anode electrode of the light-emitting element (ED) may be performed separately.

[0095] At this time, when the switching transistors (T5, T6) which supply the stabilization voltage (Vini) and the reset voltage (VAR) are turned on, the fourth switching transistor (T4) connecting the drain electrode of the driving transistor (DRT) and the anode electrode of the light emitting element (ED) is turned off to block the driving current of the driving transistor (DRT) from flowing to the anode electrode of the light emitting element (ED), thereby configuring the sub-pixel (SP) so that the anode electrode is not affected by voltages other than the reset voltage (VAR).

[0096] In this manner, a subpixel (SP) formed of eight transistors (DRT, T1, T2, T3, T4, T5, T6, T7) and one storage capacitor (Cst) can be referred to as having an 8T1C structure.

[0097] Although an 8T1C structure is shown here as an example of various subpixel (SP) circuits, the structure and number of transistors and capacitors constituting the subpixel (SP) may be variously changed. Meanwhile, each of the multiple subpixels (SP) may have the same structure, or some of the multiple subpixels (SP) may have a different structure.

[0098] FIG. 4 is a plan view showing an example of a display panel.

[0099] Referring to FIG. 4, the display panel 110 may be divided into a display area (DA) for displaying an image and a bezel area (BA) outside the display area (DA) where no image is displayed.

[0100] In the display area (DA), first to m-th gate lines (GL1 to GLm) receiving gate signals in one direction and first to n-th data lines (DL1 to DLn) receiving data signals and intersecting the first to m-th gate lines (GL1 to GLm) to define a plurality of sub-pixels (SP) may be arranged in a matrix form.

[0101] A plurality of transistors (TR) for driving the sub-pixels (SP) are arranged at the intersections of the first through m-th gate lines (GL1 through GLm) and the first through n-th data lines (DL1 through DLn), and pixel electrodes (PE) in contact with the transistors (TR) are arranged to correspond one-to-one to the sub-pixels (SP).

[0102] The first through m-th gate lines (GL1 through GLm) and the first through n-th data lines (DL1 through DLn) are respectively connected to the first through m-th gate pads (GP1 through GPm) and the first through n-th data pads (DP1 through DPn) through the first through m-th gate link lines (GLL1 through GLLm) and the first through n-th data link lines (DLL1 through DLLn) formed in the bezel area (BA).

[0103] At this time, the first to m-th gate pads GP1 to GPm are electrically connected to the gate driving circuit 120, and an area in which the first to m-th gate pads GP1 to GPm are formed may correspond to an area of ​​the gate driving circuit 120.

[0104] In addition, the first to n-th data pads DP1 to DPn are electrically connected to the data driving circuit 230, and the region in which the first to n-th data pads DP1 to DPn are formed may correspond to the region of the data driving circuit 130.

[0105] FIG. 5 is an enlarged view of part A in FIG.

[0106] Referring to FIG. 5, the bezel area (BA) adjacent to the data driving circuit 130 may include a data link area (DLA) in which a plurality of data link lines (DLL1-DLLn) are formed, and a data pad area (DPA) in which a plurality of data pads (DP1-DPn) are formed.

[0107] The first to n-th data pads DP1 to DPn formed in the data pad area DPA are spaced apart at a regular pad pitch P1.

[0108] The first through n-th data link lines DLL1 through DLLn, which correspond one-to-one to the first through n-th data pads DP1 through DPn, serve to apply data signals to the first through n-th data lines DL1 through DLn.

[0109] The width (WDP) of the data pads in which the first to n-th data pads (DP1 to DPn) are arranged in the horizontal direction corresponds to the width of the data driving circuit 130. Since the data driving circuit 130 is formed smaller than the width (WDA) of the display area, the width (WDP) of the data pads is formed smaller than the width (WDA) of the display area.

[0110] Therefore, in the conventional display panel 110, the first to n-th data link lines DLL1 to DLLn may have a diagonal structure in which the first to n-th data pads DP1 to DPn are extended in a diagonal shape toward the display panel 110.

[0111] In this case, the first to n-th data link lines (DLL1 to DLLn) may be designed to have an equal width, and the spacing between the first to n-th data link lines (DLL1 to DLLn) may have a constant link pitch (P2).

[0112] In this diagonal line structure, the length of the data link line increases from the n / 2th data link line (DLLn / 2) to the n / 2-1th data link line (DLLn / 2-1) toward the first data link line (DLL1), and then increases from the n / 2+1th data link line (DLLn / 2+1) toward the nth data link line (DLLn).

[0113] At this time, the thickness of the data link area (DLA) can be determined taking into consideration the difference between the width of the data pad (WDP) and the width of the display area (WDA) and the link pitch (P2) between the data link lines (DLL1 to DLLn).

[0114] For example, the greater the difference between the width of the data pad (WDP) and the width of the display area (WDA), the closer the outermost data link lines (DLL1 and DLLn) are to horizontal, so it is preferable to increase the distance between the data pad and the display area (DA) taking into account the link pitch (P2) between the data link lines (DLL1 to DLLn).

[0115] In particular, as the display device 100 is configured with a larger screen or the resolution increases, the number of data lines (DL) and data link lines (DLL) increases, and as a result, the width of the data link area (DLA) increases, and the size of the bezel area (BA) also increases.

[0116] The display apparatus 100 of the present disclosure may implement a narrow bezel by forming data link lines (DLL) arranged in a display area (DA) of a display panel 110 to have equal lengths, thereby reducing or preventing degradation of image quality.

[0117] FIG. 6 is a plan view illustrating an example structure of a display panel according to an embodiment of the present disclosure.

[0118] Referring to FIG. 6, a display panel 110 according to an embodiment of the present disclosure may be divided into a display area (DA) for displaying an image and a bezel area (BA) outside the display area (DA) where no image is displayed.

[0119] Here, only the data pad (DP) connected to the data driving circuit 130 and the data link line (DLL) extending from the data pad (DP) toward the display panel 110 are shown in the bezel area (BA).

[0120] In the display area (DA), a plurality of data lines (DL) may be arranged, which extend in a first direction (e.g., a column direction) and receive a data voltage (Vdata) output to the data driving circuit 130. Also, a plurality of gate lines (GL in FIG. 4) may be arranged, which extend in a second direction (e.g., a row direction) and receive a gate signal output to the gate driving circuit 120. A plurality of sub-pixels (SP in FIG. 4) may be formed in an area where the gate lines (GL in FIG. 4) and the data lines (DL) intersect.

[0121] For ease of explanation, the gate line (GL in FIG. 4) is omitted and only the data link line (DLL) and data line (DL) are shown.

[0122] A plurality of data lines DL may be arranged in a first direction (column direction) of the display panel 110 in the data driving circuit 130 .

[0123] The multiple data lines (DL) may include a first data line group (DLG1) arranged in a first area (Area 1) corresponding to the data driving circuit 130, and a second data line group (DLG2) arranged in a second area (Area 2) corresponding to the outside of the data driving circuit 130.

[0124] In the display device 100 of the present disclosure, in order to configure the area in which the data driving circuit 130 is located as a narrow bezel, a first data line group (DLG1) arranged in a first area (Area 1) corresponding to the data driving circuit 130 is connected to a first data link line group (DLLG1) having a straight structure, and a second data line group (DLG2) arranged in a second area (Area 2) corresponding to the outside of the data driving circuit 130 is connected to a second data link line group (DLLG2) having a bent structure.

[0125] The first area (Area1) corresponding to the data driving circuit 130 is an area corresponding to the width of the data driving circuit 130 within the display area (DA) of the display panel 110. Since the first area (Area1) is an area corresponding to the data driving circuit 130 in the first direction (column direction), the first data line group (DLG1) arranged in the first area (Area1) can be connected to the data driving circuit 130 using the first data link line group (DLLG1) having a linear structure.

[0126] The first data link line group (DLLG1) is extended to the data driving circuit 130 and is respectively connected to the first data line group (DLG1) in the first area (Area1) corresponding to the data driving circuit 130. Therefore, the first data link line group (DLLG1) can be located in the data link area (DLA).

[0127] The second area (Area2) corresponding to the outside of the data driving circuit 130 corresponds to an outer area outside the width of the data driving circuit 130 within the display area (DA) of the display panel 110. The display device 100 of the present disclosure includes a second data link line group (DLLG2) having a bent structure connecting the data driving circuit 130 and the second data line group (DLG2) arranged in the second area (Area2).

[0128] The second data link line group (DLLG2) may include a straight second data link line (DLLG2_S), a vertical second data link line (DLLG2_V), and a horizontal second data link line (DLLG2_H) to connect the second data line group (DLG2) in the second area (Area2) corresponding to the outside of the data driving circuit 130.

[0129] The straight second data link line (DLLG2_S) extends in a straight line from the data pad (DP) to the first area (Area 1) corresponding to the data driving circuit 130.

[0130] The second vertical data link lines (DLLG2_V) are arranged in a first direction (column direction) parallel to the first data line groups (DLG1) in the first area (Area1) corresponding to the data driving circuit 130. The second vertical data link lines (DLLG2_V) are formed in the display area (DA). In this case, the second vertical data link lines (DLLG2_V) may be arranged one by one in the spaces between the first data line groups (DLG1).

[0131] The straight second data link line DLLG2_S extends in a first direction (column direction) and is connected to the vertical second data link line DLLG2_V in a first area Area1 corresponding to the data driving circuit 130.

[0132] The second horizontal data link line (DLLG2_H) is extended in a second direction (row direction) and connected to a second data line group (DLG2) arranged in a second area (Area2) corresponding to the outside of the data driving circuit 130. The second horizontal data link line (DLLG2_H) may be formed in the display area (DA).

[0133] Therefore, the second data line group (DLG2) arranged in the second area (Area2) corresponding to the outside of the data driving circuit 130 can be connected to the data driving circuit 130 through a straight second data link line (DLLG2_S) extending from the data pad (DP), a vertical second data link line (DLLG2_V) arranged in a first direction (column direction) parallel to the first data line group (DLG1), and a straight second data link line (DLLG2_S) extending in a second direction (row direction).

[0134] In the display device 100 of the present disclosure, the horizontal second data link lines (DLLG2_H) may be formed to have equal lengths in order to reduce parasitic capacitance formed between the horizontal second data link lines (DLLG2_H) and different signal wirings.

[0135] For example, the data line DL1 arranged on the outermost left side of the second data line group DLG2 arranged in the second area is connected to the data link line DLG2_V1 located on the leftmost side of the vertical second data link line DLG2_V arranged in the first area.

[0136] In addition, the data line (DL2) arranged second from the left among the second data line group (DLG2) arranged in the second area (Area) is connected to the data link line (DLLG2_V2) arranged second from the left among the vertical second data link lines (DLLG2_V) located in the first area (Area1).

[0137] In this manner, by forming the second horizontal data link line (DLLG2_H) connecting the second data line group (DLG2) arranged in the second area (Area) and the second vertical data link line (DLLG2_V) arranged in the first area (Area1) with equal lengths, it is possible to reduce parasitic capacitance formed between the second horizontal data link line (DLLG2_H) and different signal wirings.

[0138] Here, a structure in which the horizontal second data link line (DLLG2_H) is disposed on the outer side of the display panel 110 as it is farther away from the data driving circuit 130 is shown as an example.

[0139] In addition, the structure of forming the horizontal second data link lines (DLLG2_H) with equal lengths can be equally applied to the second area (Area2) on the right side of the display panel 110 as well as the second area (Area2) on the left side of the display panel 110.

[0140] In this case, it is preferable that the horizontal second data link line (DLLG2_H1) structure arranged in the second area (Area 2) on the left side of the display panel 110 and the horizontal second data link line (DLLG2_H2) structure arranged in the second area (Area 2) on the right side of the display panel 110 are formed symmetrically based on the center of the display panel 110.

[0141] The second horizontal data link line (DLLG2_H) may be connected to the second vertical data link line (DLLG2_V) and the second data line group (DLG2) through the contact hole (CNT), and may be formed in a layer different from the second vertical data link line (DLLG2_V) and the second data line group (DLG2).

[0142] Meanwhile, in consideration of the capacitance due to the vertical second data link line (DLLG2_V) arranged in the first area (Area 1) corresponding to the data driving circuit 130, a domino data link line (DDLL) may be additionally arranged between the second data line group (DLG2) in the second area (Area 2) corresponding to the outside of the data driving circuit 130.

[0143] In this manner, when the second data line group (DLG2) of the second area (Area2) corresponding to the outside of the data driving circuit 130 is connected using the straight second data link line (DLLG2_S) extended from the data pad (DP), the vertical second data link line (DLLG2_V) arranged parallel to the first data line group (DLG1), and the straight second data link line (DLLG2_S) extended in the second direction (horizontal direction), the link pitch between the data link lines can be secured even if the distance between the data pad (DP) and the display area (DA) is reduced.

[0144] Therefore, the width of the data link area (DLA) can be reduced, allowing a narrow bezel to be configured.

[0145] FIG. 7 is a diagram showing only the connection structure of data lines arranged in a first region corresponding to a data driving circuit in a display device according to an embodiment of the present disclosure, and FIG. 8 is a diagram showing only the connection structure of data lines arranged in a second region corresponding to the outside of the data driving circuit in a display device according to an embodiment of the present disclosure.

[0146] 7 and 8, for ease of understanding, a first area (Area 1) corresponding to the data driving circuit 130 and a second area (Area 2) corresponding to the outside of the data driving circuit 130 are shown separately.

[0147] 7, in the display device 100 according to the embodiment of the present disclosure, a first area (Area1) corresponding to the data driving circuit 130 is an area corresponding to the width of the data driving circuit 130 within the display area (DA) of the display panel 110. Since the first area (Area1) is an area corresponding to the data driving circuit 130 in a first direction (column direction), the first data line group (DLG1) arranged in the first area (Area1) can be connected to the data pad (DP) through a first data link line group (DLLG1) having a linear structure.

[0148] The first data link line group (DLLG1) extends from the data pad (DP) and is directly connected to the first data line group (DLG1) arranged in the first area (Area1) corresponding to the data driving circuit 130. Therefore, the first data link line group (DLLG1) can be located in the data link area (DLA).

[0149] Referring to FIG. 8, in the display device 100 according to an embodiment of the present disclosure, a second area (Area 2) corresponding to the outside of the data driving circuit 130 corresponds to an outer area beyond the width of the data driving circuit 130 in the display area (DA) of the display panel 110.

[0150] The second data line group (DLG2) arranged in the second area (Area2) is connected to the data pad (DP) by a second data link line group (DLLG2) having a bent structure.

[0151] The second data link line group (DLLG2) may include a straight second data link line (DLLG2_S), a vertical second data link line (DLLG2_V), and a horizontal second data link line (DLLG2_H).

[0152] The straight second data link line (DLLG2_S) extends from the data pad (DP) to the first area (Area 1) corresponding to the data driving circuit 130.

[0153] The vertical second data link lines (DLLG2_V) are arranged in parallel with the first data line group (DLG1) in the first area (Area1).

[0154] The straight second data link line (DLLG2_S) is connected to the vertical second data link line (DLLG2_V) in the first area (Area1).

[0155] The second horizontal data link line DLG2_H is extended in a second direction (row direction) and connected to the second data line group DLG2 arranged in a second area Area2 corresponding to the outside of the data driving circuit 130.

[0156] The display device 100 of the present disclosure can form the lengths (LH) of the horizontal second data link lines (DLLG2_H) to be equal in order to reduce the parasitic capacitance formed between the horizontal second data link lines (DLLG2_H) and different signal wirings.

[0157] For example, the data line DL1 arranged on the outermost left side of the second data line group DLG2 arranged in the second area is connected to the data link line DLG2_V1 located on the leftmost side of the vertical second data link line DLG2_V arranged in the first area.

[0158] In addition, the data line (DL2) arranged second from the left among the second data line group (DLG2) arranged in the second area (Area) is connected to the data link line (DLLG2_V2) arranged second from the left among the vertical second data link lines (DLLG2_V) located in the first area (Area1).

[0159] In this manner, by forming the lengths (LH) of the second horizontal data link lines (DLLG2_H1) formed in the second left area (Area2) of the display panel 110 to be all equal, it is possible to reduce the parasitic capacitance formed between the second horizontal data link lines (DLLG2_H) and different signal wirings.

[0160] Similarly, the lengths (LH) of the second horizontal data link lines (DLLG2_H2) formed in the second right area (Area2) of the display panel 110 are all made equal, thereby reducing the parasitic capacitance formed between the second horizontal data link lines (DLLG2_H) and different signal wirings.

[0161] In this case, it is preferable that the horizontal second data link line (DLLG2_H1) structure arranged in the second area (Area 2) on the left side of the display panel 110 and the horizontal second data link line (DLLG2_H2) structure arranged in the second area (Area 2) on the right side of the display panel 110 are formed symmetrically based on the center of the display panel 110.

[0162] FIG. 9 is a diagram illustrating an example of a phenomenon in which stains occur in a certain region when the lengths of the horizontal second data link lines are different in a display device according to an embodiment of the present disclosure.

[0163] Referring to FIG. 9, the display device 100 according to an embodiment of the present disclosure can connect a first data line group (DLG1) arranged in a first area (Area 1) corresponding to the data driving circuit 130 to a first data link line group (DLLG1) having a straight structure, and connect a second data line group (DLG2) arranged in a second area (Area 2) corresponding to the outside of the data driving circuit 130 to a second data link line group (DLLG2) having a bent structure.

[0164] The second data link line group (DLLG2) may include a straight second data link line (DLLG2_S), a vertical second data link line (DLLG2_V), and a horizontal second data link line (DLLG2_H) to connect the second data line group (DLG2) in the second area (Area2) corresponding to the outside of the data driving circuit 130.

[0165] In this case, if the length (LH1-LH3) of the second horizontal data link line (DLLG2_H) connecting the second vertical data link line (DLLG2_V) arranged in the first area (Area1) and the second data line group (DLG2) arranged in the second area (Area2) varies depending on the position, a stain with different brightness may appear along the bending point (VH) where the second data line group (DLG2) and the second horizontal data link line (DLLG2_H) are connected.

[0166] FIG. 10 is a circuit diagram showing a phenomenon in which stains appear due to a second data link line group having a bent structure in a display device according to an embodiment of the present disclosure.

[0167] 10, in the display device 100 according to the embodiment of the present disclosure, a stain with different brightness may appear along a bending point (VH in FIG. 9) where the second data line group (DLG2) and the second horizontal data link line (DLLG2_H) are connected. Experimental results have confirmed that the main cause of this phenomenon is the parasitic capacitance (Cp) formed between the second horizontal data link line (DLLG2_H) and the gate line to which the scan signal (SCAN) is applied.

[0168] In particular, it was confirmed that the first scan signal (SCAN1) applied to the first switching transistor (T1) to maintain the gate voltage of the drive transistor (DRT) constant and the fourth scan signal (SCAN4) controlling the fifth switching transistor (T5) to apply the stabilizing voltage (Vini) to the gate electrode of the drive transistor (DRT) form a large parasitic capacitance (Cp) in the second horizontal data link line (DLLG2_H).

[0169] As a result, a luminance difference occurs along the bending point (VH in FIG. 9) where the second data line group (DLG2) and the horizontal second data link line (DLLG2_H) are connected, and a stain may appear.

[0170] Therefore, the display device 100 of the present disclosure forms the second horizontal data link line (DLLG2_H) connecting the second data line group (DLG2) arranged in the second area (Area) and the second vertical data link line (DLLG2_V) arranged in the first area (Area1) with equal lengths, thereby reducing parasitic capacitance formed between the second horizontal data link line (DLLG2_H) and different signal wirings and improving image quality.

[0171] FIG. 11 is a diagram illustrating a stain in the shape of a horizontal second data link line in a display device according to an embodiment of the present disclosure.

[0172] Referring to FIG. 11, in the display device 100 according to an embodiment of the present disclosure, when the length of the second horizontal data link line (DLLG2_H) connecting the second vertical data link line (DLLG2_V) arranged in the first area (Area1) and the second horizontal data line group (DLG2) arranged in the second area (Area2) varies depending on the position, a stain with different brightness may appear along the bending point (VH) where the second data line group (DLG2) and the second horizontal data link line (DLLG2_H) are connected (case (a)).

[0173] Meanwhile, when the second horizontal data link line (DLLG2_H) connecting the second data line group (DLG2) arranged in the second area (Area) and the second vertical data link line (DLLG2_V) arranged in the first area (Area1) is formed to have the same length, the parasitic capacitance formed between the second horizontal data link line (DLLG2_H) and different signal wirings is reduced, and as a result, the stain generated along the bending point (VH) where the second data line group (DLG2) and the second horizontal data link line (DLLG2_H) are connected can be reduced (case (b)).

[0174] FIG. 12 is a plan view illustrating an example of a display panel structure having different arrangement structures of the horizontal second data link lines in a display device according to an embodiment of the present disclosure.

[0175] Referring to FIG. 12, a display panel 110 according to an embodiment of the present disclosure may be divided into a display area (DA) for displaying an image and a bezel area (BA) outside the display area (DA) where no image is displayed.

[0176] In the display area (DA), a plurality of data lines (DL) may be arranged, which extend in a first direction (e.g., a column direction) and receive a data voltage (Vdata) output from a data driving circuit 130. Also, a plurality of gate lines (GL in FIG. 4) may be arranged, which extend in a second direction (e.g., a row direction) and receive a gate signal output from a gate driving circuit (120 in FIG. 1). A plurality of sub-pixels (SP in FIG. 4) may be formed in areas where the gate lines (GL in FIG. 4) and the data lines (DL) intersect.

[0177] The multiple data lines (DL) may include a first data line group (DLG1) arranged in a first area (Area 1) corresponding to the data driving circuit 130, and a second data line group (DLG2) arranged in a second area (Area 2) corresponding to the outside of the data driving circuit 130.

[0178] In the display device 100 of the present disclosure, in order to configure the area in which the data driving circuit 130 is located as a narrow bezel, a first data line group (DLG1) arranged in a first area (Area 1) corresponding to the data driving circuit 130 is connected to a first data link line group (DLLG1) having a straight structure, and a second data line group (DLG2) arranged in a second area (Area 2) corresponding to the outside of the data driving circuit 130 is connected to a second data link line group (DLLG2) having a bent structure.

[0179] The first area (Area1) corresponding to the data driving circuit 130 is an area corresponding to the width of the data driving circuit 130 within the display area (DA) of the display panel 110. Since the first area (Area1) is an area corresponding to the data driving circuit 130 in a first direction (column direction), the first data line group (DLG1) arranged in the first area (Area1) can be connected to the data driving circuit 130 using the first data link line group (DLLG1) having a linear structure.

[0180] The first data link line group (DLLG1) is extended from the data driving circuit 130 and is respectively connected to the first data line group (DLG1) in the first area (Area1) corresponding to the data driving circuit 130. Thus, the first data link line group (DLLG1) may be located in the data link area (DLA).

[0181] The second area (Area2) corresponding to the outside of the data driving circuit 130 corresponds to an outer area outside the width of the data driving circuit 130 within the display area (DA) of the display panel 110. The display device 100 of the present disclosure includes a second data link line group (DLLG2) having a bent structure connecting the data driving circuit 130 and the second data line group (DLG2) arranged in the second area (Area2).

[0182] The second data link line group (DLLG2) may include a straight second data link line (DLLG2_S), a vertical second data link line (DLLG2_V), and a horizontal second data link line (DLLG2_H) to connect the second data line group (DLG2) in the second area (Area2) corresponding to the outside of the data driving circuit 130.

[0183] The straight second data link line (DLLG2_S) extends in a straight line from the data pad (DP) to the first area (Area 1) corresponding to the data driving circuit 130.

[0184] The second vertical data link lines (DLLG2_V) are arranged in a first direction (column direction) parallel to the first data line groups (DLG1) in the first area (Area1) corresponding to the data driving circuit 130. The second vertical data link lines (DLLG2_V) are formed in the display area (DA). In this case, the second vertical data link lines (DLLG2_V) may be arranged one by one in the spaces between the first data line groups (DLG1).

[0185] The straight second data link line DLLG2_S extends in a first direction (column direction) and is connected to the vertical second data link line DLLG2_V in a first area Area 1 corresponding to the data driving circuit 130 .

[0186] The second horizontal data link line (DLLG2_H) is extended in a second direction (row direction) and connected to the second data line group (DLG2) arranged in a second area (Area2) corresponding to the outside of the data driving circuit 130. The second horizontal data link line (DLLG2_H) may be formed in the display area (DA).

[0187] Therefore, the second data line group (DLG2) arranged in the second area (Area2) corresponding to the outside of the data driving circuit 130 can be connected to the data driving circuit 130 through a straight second data link line (DLLG2_S) extending from the data pad (DP), a vertical second data link line (DLLG2_V) arranged in a first direction (column direction) parallel to the first data line group (DLG1), and a straight second data link line (DLLG2_S) extending in a second direction (row direction).

[0188] The display device 100 of the present disclosure may form the horizontal second data link lines (DLLG2_H) with equal lengths in order to reduce parasitic capacitance formed between the horizontal second data link lines (DLLG2_H) and different signal wirings.

[0189] For example, the data line DL1 arranged on the outermost left side of the second data line group DLG2 arranged in the second area is connected to the data link line DLG2_V1 located on the leftmost side of the vertical second data link line DLG2_V arranged in the first area.

[0190] In addition, the data line (DL2) arranged first from the left among the second data line group (DLG2) arranged in the second area (Area) is connected to the data link line (DLLG2_V2) arranged second from the left among the vertical second data link lines (DLLG2_V) located in the first area (Area1).

[0191] In this manner, by forming the second horizontal data link line (DLLG2_H) connecting the second data line group (DLG2) arranged in the second area (Area) and the second vertical data link line (DLLG2_V) arranged in the first area (Area1) with equal lengths, it is possible to reduce parasitic capacitance formed between the second horizontal data link line (DLLG2_H) and different signal wirings.

[0192] In this case, the second horizontal data link line (DLLG2_H) connecting the second data line group (DLG2) arranged in the second area (Area) and the second vertical data link line (DLLG2_V) arranged in the first area (Area1) can be arranged toward the center of the display panel 110 as it is farther away from the data driving circuit 130.

[0193] In addition, the structure of forming the horizontal second data link lines (DLLG2_H) with equal lengths can be applied not only to the left second area (Area2) of the display panel 110 but also to the right second area (Area2) of the display panel 110 equally.

[0194] In this case, it is preferable that the horizontal second data link line (DLLG2_H1) structure arranged in the second area (Area 2) on the left side of the display panel 110 and the horizontal second data link line (DLLG2_H2) structure arranged in the second area (Area 2) on the right side of the display panel 110 are formed symmetrically based on the center of the display panel 110.

[0195] The second horizontal data link line (DLLG2_H) may be connected to the second vertical data link line (DLLG2_V) and the second data line group (DLG2) through contact holes (CNT), and may be formed in a layer different from the second vertical data link line (DLLG2_V) and the second data line group (DLG2).

[0196] In this manner, when connecting the second data line group (DLG2) in the second area (Area2) corresponding to the outside of the data driving circuit 130 through the second data link line group (DLLG2) having a bent structure, the second data line group (DLG2) arranged in the second area (Area) and the horizontal second data link line (DLLG2_H) connecting the vertical second data link line (DLLG2_V) arranged in the first area (Area1) are formed to have equal lengths, thereby realizing a narrow bezel while reducing stains caused by parasitic capacitance (Cp).

[0197] The above-described embodiment of the present disclosure can be briefly described as follows.

[0198] A display device according to an embodiment of the present disclosure includes a display panel including a plurality of sub-pixels, a plurality of data lines arranged in a column direction, and a plurality of gate lines arranged in a row direction, a data driving circuit that supplies data voltages to the display panel through the plurality of data lines, a gate driving circuit that supplies gate signals to the display panel through the plurality of gate lines, and a timing controller that controls the data driving circuit and the gate driving circuit, and the display panel may include a first data link line group having a straight structure connecting first data line groups arranged in a first region corresponding to the data driving circuit, and a second data link line group having a bent structure connecting a second data line group arranged in a second region corresponding to the outside of the data driving circuit to a horizontal second data link line of the same length.

[0199] The first data link line group may connect the data driving circuit and the first data line group with a straight line.

[0200] The second data link line group of the bent structure may include straight second data link lines extending to the data driving circuit, vertical second data link lines disposed in the first region, and horizontal second data link lines connecting the vertical second data link lines and the second data line group.

[0201] A straight second data link line may be disposed in the bezel area.

[0202] The vertical second data link lines may be disposed parallel to the first data line group in the first region.

[0203] The second horizontal data link lines may be arranged on the outside of the display panel, farther away from the data driving circuit.

[0204] The second horizontal data link lines may be arranged toward the center of the display panel as they are farther away from the data driving circuit.

[0205] The horizontal second data link lines may be formed such that the horizontal second data link lines arranged in the second left region of the display panel and the horizontal second data link lines arranged in the second right region of the display panel are symmetrical with respect to the center of the display panel.

[0206] The second horizontal data link lines may be formed in a layer different from that of the second data line group.

[0207] The display device may further include a domino data link line disposed between the second data line group in the second region.

[0208] In addition, the display panel according to an embodiment of the present disclosure may include a plurality of subpixels, a first data line group arranged in a first region corresponding to a data driving circuit and a second data line group arranged in a second region corresponding to the outside of the data driving circuit, a plurality of data lines arranged in a column direction, a plurality of gate lines arranged in a row direction, a first data link line group having a straight structure connected to the first data line group in the bezel region, and a second data link line group having a bent structure in which horizontal second data link lines of the same length are connected to the second data line group through the display region.

[0209] The above description is merely illustrative of the technical concept of the present invention, and various modifications and variations are possible within the scope of the essential characteristics of the present invention, if one skilled in the art to which the present invention pertains. Furthermore, the embodiments disclosed in the present invention are for the purpose of explanation, not for the purpose of limiting the technical concept of the present invention, and therefore the scope of the technical concept of the present invention is not limited by such embodiments. [Explanation of symbols]

[0210] 100 Display device 110 Display Panel

Claims

1. a display panel including a plurality of sub-pixels, a plurality of data lines arranged in a column direction, and a plurality of gate lines arranged in a row direction; a data driving circuit for supplying a data voltage to the display panel through the plurality of data lines; a gate driving circuit for supplying gate signals to the display panel through the gate lines; a timing controller for controlling the data driving circuit and the gate driving circuit; The display panel comprises: a first data link line group having a linear structure connecting a first data line group arranged in a first region corresponding to the data driving circuit among the plurality of data lines; a second data link line group having a bent structure connecting a second data line group arranged in a second region outside the first region among the plurality of data lines to a second-third data link line having the same length; domino data link lines respectively disposed between the second data line groups in the second region; A display device comprising:

2. The first data link line group is 2. The display device of claim 1, wherein the data driving circuit and the first data line group are connected by a straight line.

3. The second data link line group having a bent structure is a second data link line extending from the data driving circuit; a second-2 data link line disposed in the first region; 2. The display device of claim 1, further comprising: a second-third data link line connecting the second-second data link line and the second data line group.

4. 4. The display device of claim 3, wherein the second-1 data link line is disposed in a bezel area.

5. 4. The display device of claim 3, wherein the second-second data link lines are arranged parallel to the first data line group in the first region.

6. 2. The display device of claim 1, wherein the second and third data link lines are arranged in a direction toward the outside of the display panel as they are farther from the data driving circuit.

7. 2. The display device of claim 1, wherein the second and third data link lines are arranged toward a center of the display panel as they are farther from the data driving circuit.

8. The second-third data link line is 2. The display device of claim 1, wherein a portion of the second-third data link lines arranged in the second left region of the display panel and a portion of the second-third data link lines arranged in the second right region of the display panel are formed symmetrically with respect to the center of the display panel.

9. 2. The display device of claim 1, wherein the second and third data link lines are formed in a layer different from that of the second data line group.

10. 4. The display device of claim 3, wherein the second-second data link lines are mutually arranged with the first data line group in the first region.

11. A plurality of sub-pixels; a plurality of data lines including a first data line group disposed in a first region corresponding to a data driving circuit and a second data line group disposed in a second region located outside the first region; a domino data link line disposed between the second data line group in the second region; A plurality of gate lines; a first data link line group having a straight structure connected to the first data line group in a bezel area; a second data link line group having a bent structure in which second and third data link lines having the same length are connected to the second data line group through a display area; a display panel including

12. The display panel of claim 11, wherein the first data link line group connects the data driving circuit and the first data line group in a straight line.

13. The second data link line group having a bent structure is a second data link line extending from the data driving circuit; a second-2 data link line disposed in the first region; 12. The display panel of claim 11, further comprising: a second-third data link line connecting the second-second data link line and the second data line group.

14. 14. The display panel of claim 13, wherein the second-1 data link line is disposed in a bezel area.

15. 14. The display panel of claim 13, wherein the second-second data link lines are disposed parallel to the first data line group in the first region.

16. 12. The display panel of claim 11, wherein the second and third data link lines are arranged in a direction toward the outside of the display panel as they are farther away from the data driving circuit.

17. 12. The display panel of claim 11, wherein the second and third data link lines are arranged toward a center of the display panel as they are farther from the data driving circuit.

18. The second-third data link line is 12. The display panel of claim 11, wherein a portion of the second-third data link lines arranged in the second left region of the display panel and a portion of the second-third data link lines arranged in the second right region of the display panel are formed symmetrically with respect to the center of the display panel.

19. 12. The display panel of claim 11, wherein the second and third data link lines are formed in a layer different from that of the second data line group.

20. 14. The display panel of claim 13, wherein the second-second data link lines are inter-disposed with the first data line group in the first region.

21. a display panel including a plurality of sub-pixels, a plurality of data lines, and a plurality of gate lines; a data driving circuit for supplying a plurality of data voltages to the plurality of data lines; a gate driving circuit for supplying a plurality of gate signals to the plurality of gate lines; a timing controller for controlling the data driving circuit and the gate driving circuit; The display panel comprises: a first data link line group having a linear structure connected to a first data line group disposed in a first region corresponding to the data driving circuit among the plurality of data lines; a second data link line group connected to a second data line group disposed in a second region located outside the first region among the plurality of data lines, the second data link line group having an equal length to the data link lines disposed in a first direction in the first region and the data link lines extended in a second direction perpendicular to the first direction; domino data link lines respectively disposed between the second data line groups in the second region; A display device comprising:

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