Display device

Abstract

A display device capable of controlling a viewing angle is provided. [Solution] A display device according to an embodiment of the present specification includes a display panel including a display area and a non-display area arranged to surround the display area, the display panel including a plurality of pixels arranged on the display area and a plurality of selection signal generators, and a timing controller for controlling the display panel. Each of the plurality of pixels includes a first light-emitting element, a first optical member that refracts light from the first light-emitting element, a second light-emitting element that emits the same color as the first light-emitting element, and a second optical member that refracts light from the second light-emitting element and has a shape different from that of the first optical member. Each of the plurality of selection signal generators controls one of the first light-emitting element and the second light-emitting element included in at least one corresponding pixel among the plurality of pixels to emit light.

Description

[Technical field]

[0001] The present specification relates to a display device, and more particularly to a display device capable of controlling a viewing angle. [Background technology]

[0002] As technology in modern society develops, display devices are used in a variety of ways to provide information to users. Display devices include not only electronic boards that simply transmit visual information in one direction, but also various electronic devices that require higher technology to confirm user input and provide information corresponding to the confirmed input.

[0003] For example, a display device may be included in a vehicle to provide various information to a vehicle driver and passengers. However, the display device of the vehicle must display content appropriately so as not to interfere with the operation of the vehicle. For example, the display device must limit the display of content that may distract the driver from driving while the vehicle is in operation. Summary of the Invention [Problem to be solved by the invention]

[0004] SUMMARY OF THE DISCLOSURE An object of the present disclosure is to provide a display device capable of dividing a display panel into regions and independently controlling a driving mode for each region.

[0005] Another problem to be solved by the present specification is to provide a display device capable of minimizing the number of wirings and pixel layout arranged on a display panel.

[0006] Still another problem to be solved by the present specification is to provide a display device capable of achieving high resolution.

[0007] The subject of the present specification is not limited to the subject mentioned above, and other subjects not mentioned will be clearly understood by those skilled in the art from the following description. [Means for solving the problem]

[0008] A display device according to an embodiment of the present specification may include a display panel including a display area and a non-display area arranged to surround the display area, the display panel including a plurality of pixels arranged on the display area and a plurality of selection signal generators, and a timing controller for controlling the display panel. Each of the plurality of pixels may include a first light-emitting element, a first optical member for refracting light from the first light-emitting element, a second light-emitting element for emitting the same color as the first light-emitting element, and a second optical member for refracting light from the second light-emitting element and having a shape different from that of the first optical member. Each of the plurality of selection signal generators may control one of the first light-emitting element and the second light-emitting element included in at least one corresponding pixel among the plurality of pixels to emit light.

[0009] Further details of the embodiments are included in the detailed description and the drawings. Effect of the Invention

[0010] The embodiments of the present specification divide the display panel into regions and control the driving mode of each region independently, so that each region can be driven in a first mode that provides content at a wide viewing angle or in a second mode that provides content at a narrow viewing angle.

[0011] The embodiments of the present specification allow the display panel to be configured with high resolution because the display panel can be divided into regions and the driving mode of each region can be controlled independently without increasing the number of wirings and pixel layout arranged on the display panel.

[0012] The effects of the embodiments of the present specification are not limited to those exemplified above, and various other effects are included within the present specification. [Brief description of the drawings]

[0013] [Figure 1] 1 is a diagram illustrating an example of a display device according to an embodiment of the present specification; [Diagram 2]FIG. 1 is a functional block diagram of a display device according to an embodiment of the present specification. [Figure 3a] 3 is a diagram showing an example of a display panel included in the display device of FIG. 2. [Figure 3b] 3 is a diagram showing an example of a display panel included in the display device of FIG. 2. [Figure 3c] 3 is a diagram showing an example of a display panel included in the display device of FIG. 2. [Figure 3d] 3 is a diagram showing an example of a display panel included in the display device of FIG. 2. [Figure 3e] 3 is a diagram showing an example of a display panel included in the display device of FIG. 2. [Figure 4] 3 is a circuit diagram showing an example of a pixel circuit included in the display device of FIG. 2. [Figure 5a] 5 is a waveform diagram for explaining the pixel circuit of FIG. [Figure 5b] 5 is a waveform diagram for explaining the pixel circuit of FIG. [Figure 6] 1 is a cross-sectional view of a portion of a display device according to an embodiment of the present specification. [Figure 7] 1 is a cross-sectional view of a portion of a display device according to an embodiment of the present specification. [Figure 8] 3 is a circuit diagram showing an example of a selection signal generating circuit included in the display device of FIG. 2. [Figure 9] 9 is a diagram for explaining an example of the operation of the selection signal generating circuit in FIG. 8. [Figure 10a] 9 is an equivalent circuit diagram for explaining an example of the operation of the selection signal generating circuit in FIG. 8. [Figure 10b] 9 is an equivalent circuit diagram for explaining an example of the operation of the selection signal generating circuit in FIG. 8. [Figure 10c] 9 is an equivalent circuit diagram for explaining an example of the operation of the selection signal generating circuit in FIG. 8. [Figure 10d] 9 is an equivalent circuit diagram for explaining an example of the operation of the selection signal generating circuit in FIG. 8. [Figure 11] 3 is a circuit diagram showing another example of a pixel circuit included in the display device of FIG. 2. [Figure 12]3 is a circuit diagram showing another example of a selection signal generating circuit included in the display device of FIG. 2. [Figure 13] 13 is a diagram for explaining an example of the operation of the selection signal generating circuit of FIG. 12. [Figure 14a] 13 is an equivalent circuit diagram for explaining an example of the operation of the selection signal generation circuit of FIG. 12. [Figure 14b] 13 is an equivalent circuit diagram for explaining an example of the operation of the selection signal generation circuit of FIG. 12. [Figure 14c] 13 is an equivalent circuit diagram for explaining an example of the operation of the selection signal generation circuit of FIG. 12. [Figure 14d] 13 is an equivalent circuit diagram for explaining an example of the operation of the selection signal generation circuit of FIG. 12. [Figure 15] 4 is a circuit diagram showing another example of a selection signal generating circuit included in the display device of FIG. 2. [Figure 16] 16 is a diagram for explaining an example of the operation of the selection signal generating circuit in FIG. 15. [Figure 17a] 16 is an equivalent circuit diagram for explaining an example of the operation of the selection signal generation circuit of FIG. 15. [Figure 17b] 16 is an equivalent circuit diagram for explaining an example of the operation of the selection signal generation circuit of FIG. 15. [Figure 17c] 16 is an equivalent circuit diagram for explaining an example of the operation of the selection signal generation circuit of FIG. 15. [Figure 17d] 16 is an equivalent circuit diagram for explaining an example of the operation of the selection signal generation circuit of FIG. 15. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0014] The advantages and features of the present specification, and the methods for achieving them, will become clear from the following detailed description of the embodiments in conjunction with the accompanying drawings. However, the present specification is not limited to the embodiments disclosed below, and may be embodied in various different forms, and the embodiments are provided solely to ensure that the disclosure of the present specification is complete and to fully convey the scope of the specification to those skilled in the art to which the present specification pertains.

[0015] The shapes, areas, ratios, angles, numbers, etc. disclosed in the drawings for explaining the embodiments of this specification are illustrative, and the specification is not limited to the matters illustrated. The same reference symbols refer to the same components throughout the specification. In addition, in explaining this specification, if it is determined that a specific description of related known technology may unnecessarily cloud the gist of this specification, the detailed description will be omitted. When "includes," "has," "is made," etc. are used in this specification, other parts may be added since "only" is not used. When a component is expressed in the singular, it includes the case where it includes a plural, unless otherwise expressly stated.

[0016] When interpreting elements, they are interpreted as including a margin of error even if there is no other explicit description.

[0017] When describing a positional relationship, for example when describing the positional relationship of two parts using "on top of," "at the top of," "at the bottom of," "next to," etc., one or more other parts may be located between the two parts, so long as "immediately" or "directly" is not used.

[0018] When an element or layer is referred to as "on" another element or layer, this includes the case where the element or layer is directly on top of the other element, or has other layers or elements interposed therebetween.

[0019] In addition, although the terms "first", "second" and the like are used to describe various components, these components are not limited by these terms. These terms are used merely to distinguish one component from another. Therefore, the first component referred to below may be the second component within the technical concept of this specification.

[0020] Like reference numbers refer to like elements throughout the specification.

[0021] The area and thickness of each component shown in the drawings are shown for convenience of explanation, and the present specification is not necessarily limited to the area and thickness of the components shown.

[0022] The features of the various embodiments of this specification may be combined or combined with each other, either partially or in whole, and may be technically interlocked and driven in various ways, and each embodiment may be implemented independently of each other or may be implemented together in a related relationship.

[0023] In the following, the present specification will be described with reference to the drawings.

[0024] FIG. 1 is a diagram illustrating a display device according to an embodiment of the present specification.

[0025] 1, the display device 100 may be disposed in at least a part of a dashboard of a vehicle. The dashboard of a vehicle may include a configuration disposed in front of a front seat (e.g., a driver's seat, a passenger seat) of the vehicle. For example, an input configuration for operating various functions (e.g., an air conditioner, an audio system, a navigation system) inside the vehicle may be disposed on the dashboard of the vehicle.

[0026] The display device 100 is disposed on the dashboard of a vehicle and can operate as an input unit for operating at least some of the various functions of the vehicle. The display device 100 can provide various information related to the vehicle, such as vehicle operation information (e.g., the current speed of the vehicle, the amount of remaining fuel, the mileage), information on vehicle parts (e.g., the degree of damage to the vehicle tires), etc.

[0027] The display device 100 may be disposed across the driver's seat and the passenger seat disposed in the front seats of the vehicle. Users of the display device 100 may include the driver of the vehicle and the passenger seat passenger. The driver and the passenger seat passenger of the vehicle may all use the display device 100.

[0028] The display device 100 shown in Fig. 1 may be only partially illustrated. The display device 100 shown in Fig. 1 may be an example showing a display panel among various components included in the display device 100. As a specific example, the display device 100 shown in Fig. 1 may show at least a part of a display area and a non-display area of ​​a display panel. The components of the display device 100 other than the parts shown in Fig. 1 may be implemented inside (or at least in part) a vehicle.

[0029] FIG. 2 is a functional block diagram of a display device according to an embodiment of the present specification.

[0030] The display device according to an embodiment of the present specification may be an electroluminescent display device. The electroluminescent display device may be an organic light emitting diode display device, a quantum dot light emitting diode display device, or an inorganic light emitting diode display device.

[0031] Referring to FIG. 2, the display device 100 may include a display panel PN, a data driving circuit DD, a gate driving circuit GD and a timing controller TD.

[0032] The display panel PN can generate an image to be provided to a user. For example, the display panel PN can generate and display an image to be provided to a user through a plurality of pixels PX, each of which includes a pixel circuit.

[0033] The data driving circuit DD, the gate driving circuit GD and the timing controller TD can provide signals for the operation of each pixel PX through signal wirings. For example, the signal wirings for providing signals for the operation of each pixel PX can include a plurality of data wirings DL and a plurality of gate wirings GL.

[0034] The multiple data lines DL can include multiple lines arranged in a column direction and connected to the pixels PX arranged in one column direction, and the multiple gate lines GL can include multiple lines arranged in a row direction and connected to the pixels PX arranged in one row direction.

[0035] In some cases, the display device 100 may further include a power supply unit. In this case, a signal for operating the pixel PX may be provided through a power supply line connecting the power supply unit and the display panel PN. According to an embodiment, the power supply unit may provide power to the data driving circuit DD and the gate driving circuit GD. The data driving circuit DD and the gate driving circuit GD may be driven based on the power provided by the power supply unit.

[0036] As an example, the data driving circuit DD can apply data signals to each pixel PX through a plurality of data lines DL, the gate driving circuit GD can apply gate signals to each pixel PX through a plurality of gate lines GL, and the power supply unit can supply a power supply voltage to each pixel PX through a power supply voltage supply line.

[0037] The timing controller TD can control the data driving circuit DD and the gate driving circuit GD. For example, the timing controller TD can realign digital video data input from the outside to match the resolution of the display panel PN and supply the realigned data to the data driving circuit DD.

[0038] The data driving circuit DD can convert digital video data input from the timing controller TD based on a data control signal into analog data voltages and supply them to a plurality of data lines DL.

[0039] The gate driving circuit GD may generate a scan signal and an emission signal based on the gate control signal. For example, the gate driving circuit GD may include a scan driver and an emission signal driver. The scan driver may generate scan signals in a row sequential manner to drive at least one or more scan lines connected to each row of pixels, and supply the scan signals to the scan lines. The emission signal driver may generate emission signals in a row sequential manner to drive at least one or more emission signal lines connected to each row of pixels, and supply the emission signals to the emission signal lines.

[0040] According to an embodiment, the gate driving circuit GD may be arranged on the display panel PN in a GIP (Gate-driver In Panel) manner. For example, the gate driving circuit GD may be divided into a plurality of parts and arranged on at least two sides of the display panel PN, respectively.

[0041] The display panel PN can include a display area and a non-display area surrounding the display area.

[0042] The display area of ​​the display panel PN may include a plurality of pixels PX arranged in row and column directions. For example, the plurality of pixels PX may be arranged in a region where a plurality of data lines DL and a plurality of gate lines GL intersect.

[0043] One pixel PX may include a plurality of sub-pixels emitting different colors. For example, one pixel PX may express blue, red, and green using three sub-pixels. However, this is not limiting, and in some cases, the pixel PX may further include a sub-pixel for further expressing a specific color, for example, white.

[0044] In the pixel PX, a region expressing blue may be referred to as a blue sub-pixel, a region expressing red may be referred to as a red sub-pixel, and a region expressing green may be referred to as a green sub-pixel.

[0045] Each of the pixels PX may include a first light emitting element and a second light emitting element that emit light of the same color.

[0046] Each of the pixels PX may include a first optical member that refracts light from a first light-emitting element in a specific direction and a second optical member that refracts light from a second light-emitting element in a specific direction. For example, the first optical member and the second optical member may each be configured as a lens, but the embodiments of the present specification are not limited thereto.

[0047] For example, the first optical member may be disposed in an optical region that provides light to a first range to form a first viewing angle, and the second optical member may be disposed in an optical region that provides light to a second range to form a second viewing angle. The first range may be wider than the second range. Thus, the first optical member and the second optical member may limit the viewing angle of each of the pixels PX.

[0048] The first and second optical members will be described in detail below with reference to FIGS.

[0049] The non-display area may be arranged along the periphery of the display area. In the non-display area, various components for driving the pixel circuits arranged in the pixels PX may be arranged. For example, at least a part of the gate drive circuit GD may be arranged in the non-display area. The non-display area may be referred to as a bezel area.

[0050] When the display panel PN is used in the vehicle described with reference to Fig. 1, the field of view of at least a part of the display panel PN needs to be restricted in response to a user request. For example, in the case of an image displayed in an area of ​​the display panel PN that provides entertainment functions and seat information for a passenger in the passenger seat, the image may interfere with the driver's driving of the vehicle, so that it may be necessary to restrict the field of view of the image displayed in the relevant area in response to a user request.

[0051] Thus, each pixel PX included in the display panel PN may be driven in a first mode or a second mode depending on the driving mode. For example, when the pixel PX is driven in the first mode, a first light emitting element included in the pixel PX emits light based on a selection signal, and light from the first light emitting element is provided to a first range through a first optical member to form a first viewing angle, e.g., a wide viewing angle. When the pixel PX is driven in the second mode, a second light emitting element included in the pixel PX emits light based on a selection signal, and light from the second light emitting element is provided to a second range through a second optical member to form a second viewing angle, e.g., a narrow viewing angle. Here, the first mode may correspond to a mode in which the corresponding pixel PX is controlled in a wide viewing mode (Share mode), and the second mode may correspond to a mode in which the corresponding pixel PX is driven in a narrow viewing mode (Private mode).

[0052] Meanwhile, when controlling the driving mode, it is necessary to divide the display panel PN into regions and control the driving mode of each region independently. In this case, when a selection signal for controlling the driving mode of the pixel PX arranged in each region is generated from a driving circuit such as a D-IC and provided to the pixel PX of the corresponding region, the selection signal wiring for providing the selection signal from the driving circuit to the pixel PX of the corresponding region is arranged throughout the display panel PN, so that the number of divided regions may be limited. For example, as the number of divided regions increases, the number of selection signal wirings arranged throughout the display panel PN increases, so that the wirings arranged throughout the display panel PN and the area occupied by the wirings increase. In addition, when the pixel circuit is changed to receive the selection signal in a matrix form within each pixel PX in order to reduce the number of selection signal wirings, a transistor is added within the pixel PX, making the pixel layout complicated, so that it may be difficult to achieve high resolution.

[0053] Therefore, the display device 100 according to the embodiment of the present specification may further include at least one selection signal generator for controlling the driving mode of the pixels PX in each divided region. The selection signal generator is disposed on the display panel PN, and one selection signal generator for commonly controlling the driving mode of the pixels PX in each divided region may be disposed on the display panel PN.

[0054] The selection signal generating unit can control the driving mode of the pixel PX. For example, the selection signal generating unit generates a selection signal and provides it to the pixel PX, and the pixel PX can be driven in a first mode or a second mode based on the selection signal as described above.

[0055] In this way, the selection signal generating unit for controlling the driving mode of the pixel PX may be disposed on the display panel PN. For example, the selection signal generating unit may be disposed in a region of the display region of the display panel PN where the pixel PX is not disposed, and / or may be disposed in a layer different from the configuration included in the pixel PX. As a result, the display panel PN may be divided into regions and the driving mode of each region may be independently controlled without increasing the number of selection signal wirings connected to the pixel PX from the driving circuit or changing the pixel circuit as described above. Therefore, when the display panel PN is divided into regions and the driving mode of each region may be independently controlled, the number of wirings and pixel layout disposed on the display panel PN may be minimized, and high resolution may be realized.

[0056] A detailed description of the selection signal generator will be given below with reference to Figures 3a to 3e, 8 to 10d, and 12 to 17d.

[0057] 3a to 3e are diagrams illustrating examples of a display panel included in the display device of FIG.

[0058] Meanwhile, the first display panel PN1, the second display panel PN2, the third display panel PN3, the fourth display panel PN4 and the fifth display panel PN5 shown in Figures 3a to 3e each represent various embodiments of the display panel PN described with reference to Figure 2.

[0059] Referring to FIG. 3a, the first display panel PN1 may include a plurality of selection signal generating units SLG and a plurality of pixels PX.

[0060] Each of the selection signal generators SLG is disposed for each pixel PX, and can control the driving mode of the corresponding pixel PX. For example, as shown in Fig. 3a, each of the selection signal generators SLG may be disposed on one side of each pixel PX. As an example, on the first display panel PN1, the selection signal generators SLG and the pixels PX may be disposed in a ratio of 1:1.

[0061] Each of the selection signal generators SLG provides a selection signal to a corresponding pixel PX to control the driving mode of the corresponding pixel PX. Thus, the driving mode of each pixel PX included in the first display panel PN1 may be controlled independently. For example, the first display panel PN1 includes a plurality of regions defined as a pixel PX unit, and the driving modes of the corresponding regions may be controlled independently. That is, in the case of a plurality of pixels PX included in the first display panel PN1, the driving mode of each individual pixel PX may be controlled independently. Meanwhile, in this case, one selection signal generator SLG and one corresponding pixel PX may be defined as a pixel block or a pixel unit.

[0062] Referring to FIG. 3b, the second display panel PN2 may include a plurality of selection signal generating units SLG and a plurality of pixels PX.

[0063] Each of the selection signal generating units SLG is disposed for every two pixels PX, and can control the driving modes of the corresponding two pixels PX. For example, as shown in FIG. 3b, each of the selection signal generating units SLG may be disposed on one side along the row direction of one of two pixels PX disposed in the row direction. As an example, on the second display panel PN2, the selection signal generating units SLG and the pixels PX may be disposed in a ratio of 1:2. However, this is not limited thereto, and each of the selection signal generating units SLG may be disposed on one side along the column direction of one of two pixels PX disposed in the column direction.

[0064] Each of the selection signal generating units SLG provides a selection signal to two corresponding pixels PX to commonly control the driving modes of the two corresponding pixels PX. Thus, the driving modes of two pixels PX included in the second display panel PN2 may be independently controlled. For example, the second display panel PN2 includes a plurality of regions defined as two pixel PX units, and the driving modes of the plurality of regions may be independently controlled. That is, in the case of a plurality of pixels PX included in the second display panel PN2, the driving modes of every two pixels PX may be independently controlled. Meanwhile, in such a case, one selection signal generating unit SLG and two corresponding pixels PX may be defined as a pixel block or a pixel unit.

[0065] Referring to FIG. 3c, the third display panel PN3 may include a plurality of selection signal generating units SLG and a plurality of pixels PX.

[0066] Each of the selection signal generating units SLG is arranged for every three pixels PX, and can control the driving modes of the corresponding three pixels PX. For example, as shown in FIG. 3c, each of the selection signal generating units SLG may be arranged on one side along the row direction of one of three pixels PX arranged in the row direction. As an example, on the third display panel PN3, the selection signal generating units SLG and the pixels PX may be arranged in a ratio of 1:3. However, this is not limited thereto, and each of the selection signal generating units SLG may be arranged on one side along the column direction of one of three pixels PX arranged in the column direction.

[0067] Each of the selection signal generators SLG provides a selection signal to three corresponding pixels PX to commonly control the driving modes of the three pixels PX. Thus, the driving modes of the three pixels PX included in the third display panel PN3 may be independently controlled. For example, the third display panel PN3 includes a plurality of regions defined as three pixel PX units, and the driving modes of the plurality of regions may be independently controlled. That is, in the case of the plurality of pixels PX included in the third display panel PN3, the driving modes may be independently controlled for every three pixels PX. Meanwhile, in this case, one selection signal generator SLG and the three corresponding pixels PX may be defined as a pixel block or a pixel unit.

[0068] Referring to FIG. 3d, the fourth display panel PN4 may include a plurality of selection signal generating units SLG and a plurality of pixels PX.

[0069] Each of the selection signal generating units SLG is arranged for every six pixels PX, and can control the driving modes of the corresponding six pixels PX. For example, as shown in FIG. 3d, each of the selection signal generating units SLG may be arranged on one side along the row direction of one of the six pixels PX arranged in the row direction. As an example, on the fourth display panel PN4, the selection signal generating units SLG and the pixels PX may be arranged in a ratio of 1:6. However, this is not limited thereto, and each of the selection signal generating units SLG may be arranged on one side along the column direction of one of the six pixels PX arranged in the column direction.

[0070] Each of the selection signal generators SLG provides a selection signal to the corresponding six pixels PX to commonly control the driving modes of the corresponding six pixels PX. Thus, the driving modes of the six pixels PX included in the fourth display panel PN4 may be independently controlled. For example, the fourth display panel PN4 includes a plurality of regions defined as six pixel PX units, and the driving modes of the corresponding regions may be independently controlled. That is, in the case of the pixels PX included in the fourth display panel PN4, the driving modes of the six pixels PX may be independently controlled. Meanwhile, in this case, one selection signal generator SLG and the six corresponding pixels PX may be defined as a pixel block or a pixel unit.

[0071] Referring to FIG. 3e, the fifth display panel PN5 may include a plurality of selection signal generating units SLG and a plurality of pixels PX.

[0072] Each of the selection signal generating units SLG is arranged for every six pixels PX, and can control the driving modes of the corresponding six pixels PX. For example, as shown in FIG. 3e, each of the selection signal generating units SLG may be arranged on one side in the row direction of two pixels PX arranged in the same column among six pixels PX arranged in two rows, three pixels in each row. As an example, on the fifth display panel PN5, the selection signal generating units SLG and the pixels PX may be arranged in a ratio of 1:6. However, this is not limited thereto, and each of the selection signal generating units SLG may be arranged on one side in the column direction of two pixels PX arranged in the same row among six pixels PX arranged in two columns, three pixels in each row.

[0073] Each of the selection signal generating units SLG provides a selection signal to the corresponding six pixels PX to commonly control the driving modes of the six pixels PX. Thus, the driving modes of the six pixels PX included in the fifth display panel PN5 can be independently controlled. For example, the fifth display panel PN5 includes a plurality of regions defined as six pixel PX units, and the driving modes of the plurality of regions can be independently controlled. That is, in the case of the pixels PX included in the fifth display panel PN5, the driving modes of the six pixels PX can be independently controlled.

[0074] As described above, the arrangement relationship between the selection signal generator SLG and the pixels PX included in the display panel PN of the display device 100 according to the embodiment of the present specification may be designed in various ways. Here, as described above, the regions of the display panel PN may be divided according to the pixels PX commonly controlled by one selection signal generator SLG, and the driving mode may be independently controlled for each region. Thus, the display panel PN may be divided into various regions according to the design of the display device 100, and the corresponding regions may be independently controlled. Meanwhile, in such a case, one selection signal generator SLG and six corresponding pixels PX may be defined as a pixel block or a pixel unit.

[0075] FIG. 4 is a circuit diagram showing an example of a pixel circuit included in the display device of FIG.

[0076] On the other hand, the first pixel circuit PC1 shown in FIG. 4 represents an embodiment of a pixel circuit corresponding to each of the plurality of pixels PX included in the display device 100 described with reference to FIG.

[0077] 4, at least some of the transistors included in the first pixel circuit PC1 may be n-type transistors or p-type transistors. In the case of p-type transistors, the low level voltage of each driving signal may represent a voltage that turns on the TFT, and the high level voltage of each driving signal may represent a voltage that turns off the TFT.

[0078] Here, the low level voltage may correspond to a pre-specified voltage lower than the high level. For example, the low level voltage may include a voltage within a range of -8V to -12V. The high level voltage may correspond to a pre-specified voltage higher than the low level voltage. For example, the high level voltage may include a voltage within a range of 12V to 16V. Depending on the embodiment, the low level voltage may be referred to as a first voltage, and the high level voltage may be referred to as a second voltage. In this case, the first voltage may be lower than the second voltage.

[0079] The first pixel circuit PC1 may include a driving transistor DT, a plurality of switching transistors ST1 to ST6, a plurality of selection transistors TP1 and TP2, a storage capacitor Cst, and a plurality of light emitting elements ED1 and ED2.

[0080] The driving transistor DT can control a driving current applied to the light emitting elements ED1 and ED2 by a source-gate voltage. The driving transistor DT can include a source electrode connected to a high potential power supply line providing a high potential power supply voltage VDD, a gate electrode connected to a second node N2, and a drain electrode connected to a third node N3.

[0081] The first switching transistor ST1 can apply a data voltage Vdata from the data line DL to the first node N1. The first switching transistor ST1 can include a source electrode connected to the data line DL, a drain electrode connected to the first node N1, and a gate electrode connected to a first scan signal line to which a first scan signal SCAN1 is applied. The first switching transistor ST1 can be turned on or off by the first scan signal SCAN1. Thus, the first switching transistor ST1 can apply the data voltage Vdata from the data line DL to the first node N1 in response to the first scan signal SCAN1 of a low level, which is a turn-on level.

[0082] The second switching transistor ST2 can diode-connect the gate electrode and the drain electrode of the driving transistor DT. The second switching transistor ST2 includes a drain electrode connected to a second node N2, a source electrode connected to a third node N3, and a gate electrode connected to a second scan signal line to which a second scan signal SCAN2 is applied. The second switching transistor ST2 can be turned on or off by the second scan signal SCAN2. Thus, the second switching transistor ST2 can diode-connect the gate electrode and the drain electrode of the driving transistor DT in response to the second scan signal SCAN2 of a low level, which is a turn-on level.

[0083] The third switching transistor ST3 can apply a reference voltage Vref to the first node N1. The third switching transistor ST3 can include a source electrode connected to a reference voltage line providing the reference voltage Vref, a drain electrode connected to the first node N1, and a gate electrode connected to an emission signal line to which an emission signal EM is applied. The third switching transistor ST3 can be turned on or off by the emission signal EM. Thus, the third switching transistor ST3 can transfer the reference voltage Vref to the first node N1 in response to the emission signal EM having a low level, which is a turn-on level.

[0084] The fourth switching transistor ST4 may apply a reference voltage Vref to the anode electrode of the first light emitting element ED1. The fourth switching transistor ST4 may include a source electrode connected to a reference voltage line providing the reference voltage Vref, a drain electrode connected to the anode electrode of the first light emitting element ED1, and a gate electrode connected to a second scan signal line to which a second scan signal SCAN2 is applied. The fourth switching transistor ST4 may be turned on or off by the second scan signal SCAN2. Thus, the fourth switching transistor ST4 may apply the reference voltage Vref to the anode electrode of the first light emitting element ED1 in response to the second scan signal SCAN2 having a low level, which is a turn-on level.

[0085] The fifth switching transistor ST5 may apply a reference voltage Vref to the anode electrode of the second light emitting element ED2. The fifth switching transistor ST5 may include a source electrode connected to a reference voltage line providing the reference voltage Vref, a drain electrode connected to the anode electrode of the second light emitting element ED2, and a gate electrode connected to a second scan signal line to which a second scan signal SCAN2 is applied. The fifth switching transistor ST5 may be turned on or off by the second scan signal SCAN2. Thus, the fifth switching transistor ST5 may apply the reference voltage Vref to the anode electrode of the second light emitting element ED2 in response to the second scan signal SCAN2 of a low level, which is a turn-on level.

[0086] The sixth switching transistor ST6 can form a current path between the driving transistor DT and any one of the plurality of light emitting elements ED1 and ED2. The sixth switching transistor ST6 can include a source electrode connected to the third node N3, a drain electrode connected to the fourth node N4, and a gate electrode connected to a light emitting signal wiring to which a light emitting signal EM is applied. The sixth switching transistor ST6 can be turned on or off by the light emitting signal EM. Thus, the sixth switching transistor ST6 can electrically connect the third node N3 and the fourth node N4 in response to the light emitting signal EM of a low level, which is a turn-on level, to form a current path between the driving transistor DT and any one of the plurality of light emitting elements ED1 and ED2.

[0087] The storage capacitor Cst may include a first electrode connected to the first node N1 and a second electrode connected to the second node N2. One electrode of the storage capacitor Cst may be connected to the gate electrode of the driving transistor DT, and the other electrode of the storage capacitor Cst may be connected to the first switching transistor ST1. The storage capacitor Cst stores a constant voltage and can maintain the voltage of the gate electrode of the driving transistor DT constant while any one of the light emitting elements ED1 and ED2 emits light.

[0088] The multiple selection transistors TP1, TP2 may include a first selection transistor TP1 for generating a current path of a first driving current via the first light-emitting element ED1 and a second selection transistor TP2 for generating a current path of a second driving current via the second light-emitting element ED2.

[0089] The first selection transistor TP1 is connected between the fourth node N4 and the first light-emitting element ED1, and the gate electrode of the first selection transistor TP1 may be connected to a first selection signal line that provides a first selection signal Ss. When the pixel PX to which the first pixel circuit PC1 is applied is driven in a first mode that is a wide viewing mode, the first selection signal Ss may be supplied to the gate electrode of the first selection transistor TP1 to turn on the first selection transistor TP1. Thus, a current path of a first driving current passing through the first light-emitting element ED1 is formed, and the first light-emitting element ED1 may emit light. Meanwhile, the first selection transistor TP1 may also be referred to as a first emission control transistor that controls the emission of the first light-emitting element ED1.

[0090] The second selection transistor TP2 is connected between the fourth node N4 and the second light-emitting element ED2, and the gate electrode of the second selection transistor TP2 may be connected to a second selection signal line that provides a second selection signal Ps. When the pixel PX to which the first pixel circuit PC1 is applied is driven in a second mode that is a narrow viewing mode, the second selection signal Ps may be supplied to the gate electrode of the second selection transistor TP2 to turn on the second selection transistor TP2. Thus, a current path of the second driving current passing through the second light-emitting element ED2 is formed, and the second light-emitting element ED2 may emit light. Meanwhile, the second selection transistor TP2 may also be referred to as a second emission control transistor that controls the emission of the second light-emitting element ED2.

[0091] The first light emitting element ED1 may be connected between a first selection transistor TP1 turned on or off by a first selection signal Ss and a low potential power supply line providing a low potential power supply voltage VSS. The second light emitting element ED2 may be connected between a second selection transistor TP2 turned on or off by a second selection signal Ps and a low potential power supply line providing a low potential power supply voltage VSS.

[0092] In this case, the first light emitting element ED1 or the second light emitting element ED2 may be connected to another component of the first pixel circuit PC1, for example, the driving transistor DT, by the first selection transistor TP1 or the second selection transistor TP2 that is turned on depending on the driving mode. For example, the first light emitting element ED1 may be connected to the driving transistor DT via the first selection transistor TP1 that is turned on in the first mode, and may provide light at a wide viewing angle, which is a first viewing angle, in the first mode, i.e., wide viewing mode, by the first driving current. Also, the second light emitting element ED2 may be connected to the driving transistor DT via the second selection transistor TP2 that is turned on in the second mode, and may provide light at a narrow viewing angle, which is a second viewing angle, in the second mode, i.e., narrow viewing mode, by the second driving current. Here, the driving mode may be designated by a user's input or may be determined when a pre-designated condition is satisfied.

[0093] 5a and 5b are waveform diagrams for explaining the pixel circuit of FIG.

[0094] On the other hand, Figure 5a shows a waveform diagram for explaining an example of a case where a pixel PX to which the first pixel circuit PC1 is applied is driven in a first mode, and Figure 5b shows a waveform diagram for explaining an example of a case where a pixel PX to which the first pixel circuit PC1 is applied is driven in a second mode.

[0095] 4 to 5b, in the first mode, only the first light emitting element ED1 can emit light, and in the second mode, only the second light emitting element ED2 can emit light. Here, as shown in Fig. 5a, the second selection signal Ps for controlling the emission of the second light emitting element ED2 can be output only at a high level, which is a turn-off level, so that only the first light emitting element ED1 can emit light in the first mode. Also, as shown in Fig. 5b, the first selection signal Ss for controlling the emission of the first light emitting element ED1 can be output only at a high level (or first level), which is a turn-off level, so that only the second light emitting element ED2 can emit light in the second mode.

[0096] 4 and 5a, the first mode, which is a wide viewing mode, may be considered. In the initialization period P1, the second scan signal SCAN2 at a low level, the first selection signal Ss at a low level, and the light emission signal EM at a low level may be output. The second switching transistor ST2, the fourth switching transistor ST4, and the fifth switching transistor ST5 may be turned on by the second scan signal SCAN2 at a low level, the first selection transistor TP1 may be turned on by the first selection signal Ss at a low level, and the third switching transistor ST3 and the sixth switching transistor ST6 may be turned on by the light emission signal EM at a low level.

[0097] The first node N1 may be initialized to the reference voltage Vref through the turned-on third switching transistor ST3. The voltage of the anode electrode of the first light emitting element ED1 may be initialized to the reference voltage Vref through the turned-on fourth switching transistor ST4, and the voltage of the anode electrode of the second light emitting element ED2 may be initialized to the reference voltage Vref through the turned-on fifth switching transistor ST5. The driving transistor DT may be diode-connected through the turned-on second switching transistor ST2, and the gate electrode and the drain electrode of the driving transistor DT may be shorted, so that the driving transistor DT may operate like a diode. The reference voltage Vref transferred to the anode electrode of the first light emitting element ED1 through the turned-on fourth switching transistor ST4 may be transferred to the third node N3 and the second node N2 through the turned-on first selection transistor TP1 and the turned-on sixth switching transistor ST6, and the third node N3 and the second node N2 may be initialized to the reference voltage Vref.

[0098] Next, in a sampling period P2, the first scan signal SCAN1 of a low level and the second scan signal SCAN2 of a low level may be output, and the first selection signal Ss may be output at a high level. When the light emitting signal EM of a high level is output, the third switching transistor ST3 is turned off, and at the same time, the first switching transistor ST1 is turned on by the first scan signal SCAN1 of a low level (or a second level, the second level having a value lower than the first level), and the data voltage Vdata may be transmitted to the first node N1. Then, the driving transistor DT is diode-connected by the turned-on second switching transistor ST2, and the difference voltage between the high potential power supply voltage VDD and the threshold voltage may be sampled and supplied to the second node N2.

[0099] Meanwhile, during the sampling period P2, the sixth switching transistor ST6 is turned off by the high-level light emitting signal EM, and the first selection transistor TP1 is turned off by the high-level first selection signal Ss.

[0100] In addition, during the holding period P3, the first scan signal SCAN1 and the second scan signal SCAN2 are output at a high level, and the first switching transistor ST1, the second switching transistor ST2, the fourth switching transistor ST4, and the fifth switching transistor ST5 are all turned off. However, even if the first switching transistor ST1 is turned off, the data voltage Vdata input during the previous period (e.g., the sampling period P2) may be maintained by the storage capacitor Cst.

[0101] Finally, in the light emitting period P4, the first selection signal Ss and the light emitting signal EM of a low level are output, and the second selection signal Ps of a high level is output. The reference voltage Vref is applied to the first node N1 through the third switching transistor ST3 that is turned on by the light emitting signal EM of a low level, and the voltage of the first node N1 may become a difference voltage between the reference voltage Vref and the data voltage Vdata, and such a voltage fluctuation may be reflected in the second node N2. The gate-source voltage of the driving transistor DT may be set to a value (Vdata-Vref+Vth) obtained by subtracting the reference voltage Vref from the data voltage Vdata and adding the data voltage Vdata to the data voltage Vdata, thereby controlling the first driving current.

[0102] Then, the first driving current is supplied from the driving transistor DT to the first light emitting element ED1 through the sixth switching transistor ST6 turned on by the low level light emitting signal EM and the first selection transistor TP1 turned on by the low level first selection signal Ss, so that the first light emitting element ED1 can emit light. However, since the second selection signal Ps is output at a high level and the second selection transistor TP2 is turned off, the second driving current cannot be transmitted from the driving transistor DT to the second light emitting element ED2. Therefore, when the first pixel circuit PC1 is driven in the first mode, the first driving current is applied only to the first light emitting element ED1, so that only the first light emitting element ED1 can emit light.

[0103] 4 and 5b, the second mode, which is a narrow viewing mode, may be considered. In the second mode, the first pixel circuit PC1 may be driven in substantially the same manner as the first mode, except that the first selection signal Ss and the second selection signal Ps are output in the opposite manner to the first mode, which is a wide viewing mode. That is, the first selection signal Ss may be output only at a high level, which is a turn-off level, and the second selection signal Ps may be output at a low level, which is a turn-on level, during a light emission period P4 in which the second light emitting element ED2 emits light.

[0104] Specifically, in the initialization period P1, the first scan signal SCAN1 may be output at a high level, and the second scan signal SCAN2 may be output at a low level. Then, the first selection signal Ss may be output at a high level, and the second selection signal Ps and the light emission signal EM may be output at a low level. Thus, the second switching transistor ST2, the fourth switching transistor ST4, and the fifth switching transistor ST5 may be turned on by the second scan signal SCAN2, the second selection transistor TP2 may be turned on by the second selection signal Ps, and the third switching transistor ST3 and the sixth switching transistor ST6 may be turned on by the light emission signal EM.

[0105] The first node N1 is initialized to the reference voltage Vref through the third switching transistor ST3 turned on by the light emitting signal EM, and the anode electrodes of the first light emitting element ED1 and the second light emitting element ED2 can be initialized to the reference voltage Vref through the fourth switching transistor ST4 and the fifth switching transistor ST5 turned on by the second scan signal SCAN2, respectively. And, the driving transistor DT is diode-connected through the second switching transistor ST2 turned on and can operate like a diode. Finally, the reference voltage Vref transferred to the anode electrode of the second light emitting element ED2 through the fifth switching transistor ST5 turned on is transferred to the third node N3 and the second node N2 through the second selection transistor TP2 turned on and the sixth switching transistor ST6 turned on, and the third node N3 and the second node N2 can be initialized to the reference voltage Vref.

[0106] Next, in a sampling period P2, the first scan signal SCAN1 of a low level and the second scan signal SCAN2 of a low level are output, and the second selection signal Ps and the light emission signal EM are output from a low level to a high level. When the light emission signal EM of a high level is output, the third switching transistor ST3 is turned off, and the first switching transistor ST1 is turned on by the first scan signal SCAN1 of a low level, so that the data voltage Vdata can be transmitted to the first node N1. Then, the driving transistor DT is diode-connected by the turned-on second switching transistor ST2, and a difference voltage between the high potential power supply voltage VDD and the threshold voltage can be sampled and supplied to the second node N2.

[0107] Meanwhile, during the sampling period P2, the sixth switching transistor ST6 is turned off by the high-level light emitting signal EM, and the second selection transistor TP2 is turned off by the high-level second selection signal Ps.

[0108] Finally, in the light emitting period P4, the second selection signal Ps and the light emitting signal EM of a low level are output, and the first selection signal Ss of a high level is output. The reference voltage Vref is applied to the first node N1 through the third switching transistor ST3 that is turned on by the light emitting signal EM of a low level, and the voltage of the first node N1 may become a difference voltage between the reference voltage Vref and the data voltage Vdata, and such a voltage fluctuation may be reflected in the second node N2. The gate-source voltage of the driving transistor DT may be set to a value (Vdata-Vref+Vth) obtained by subtracting the reference voltage Vref from the data voltage Vdata and adding the data voltage Vdata to the data voltage Vdata, thereby controlling the second driving current.

[0109] Then, the second driving current is supplied from the driving transistor DT to the second light emitting element ED2 through the sixth switching transistor ST6 turned on by the low level light emitting signal EM and the second selection transistor TP2 turned on by the low level second selection signal Ps, so that the second light emitting element ED2 can emit light. However, since the first selection signal Ss is output at a high level and the first selection transistor TP1 is turned off, the first driving current cannot be transmitted from the driving transistor DT to the first light emitting element ED1. Therefore, when the first pixel circuit PC1 is driven in the second mode, the second driving current is applied only to the second light emitting element ED2, so that only the second light emitting element ED2 can emit light.

[0110] 6 and 7 are cross-sectional views of a portion of a display device according to an embodiment of the present specification.

[0111] FIG. 6 shows a pixel in which a first optical member 161 is disposed, and FIG. 7 shows a pixel in which a second optical member 162 is disposed.

[0112] Referring to Figures 6 and 7, the display device 100 according to an embodiment of the present specification may include a substrate 110, a buffer film 111, a gate insulating film 112, an interlayer insulating film 113, a lower protective film 114, an overcoat layer 115, a bank insulating film 116, a first selection transistor TP1, a second selection transistor TP2, a first light-emitting element ED1, a second light-emitting element ED2, a first optical member 161, a second optical member 162, an optical member protective film 170 and a sealing member 180.

[0113] The substrate 110 may include an insulating material. The substrate 110 may include a transparent material. For example, the substrate 110 may include glass or plastic.

[0114] A buffer film 111 may be disposed on the substrate 110. The buffer film 111 may include an insulating material. For example, the buffer film 111 may include an inorganic insulating material such as silicon oxide (SiOx) and silicon nitride (SiNx). The buffer film 111 may have a multi-layer structure. For example, the buffer film 111 may have a stacked structure of a film made of silicon nitride (SiNx) and a film made of silicon oxide (SiOx).

[0115] The buffer film 111 may be located between the substrate 110 and the driving portion of each pixel PX. The buffer film 111 can prevent contamination by the substrate 110 in a process of forming the driving portion. For example, the upper surface of the substrate 110 facing the driving portion of each pixel PX may be covered by the buffer film 111. The driving portion of each pixel PX may be located on the buffer film 111.

[0116] A gate insulating layer 112 may be disposed on the buffer layer 111. The gate insulating layer 112 may include an insulating material. For example, the gate insulating layer 112 may include an inorganic insulating material such as silicon oxide (SiO) and silicon nitride (SiN). The gate insulating layer 112 may include a material having a high dielectric constant. For example, the gate insulating layer 112 may include a high-K material such as hafnium oxide (HfO). The gate insulating layer 112 may have a multi-layer structure.

[0117] The gate insulating film 112 may extend between the semiconductor layers 121, 221 and the gate electrodes 122, 223 of the selection transistors TP1, TP2. For example, the gate electrodes of the driving transistors and the switching transistors may be insulated from the semiconductor layers of the driving transistors and the switching transistors by the gate insulating film 112. The gate insulating film 112 may cover the semiconductor layers of each pixel PX. The gate electrodes of the driving transistors and the switching transistors may be located on the gate insulating film 112.

[0118] An interlayer insulating film 113 may be disposed on the gate insulating film 112. The interlayer insulating film 113 may include an insulating material. For example, the interlayer insulating film 113 may include an inorganic insulating material such as silicon oxide (SiO) and silicon nitride (SiN). The interlayer insulating film 113 may extend between the gate electrode and the source electrode and between the gate electrode and the drain electrode of each of the driving transistor and the switching transistor. For example, the source electrode and the drain electrode of each of the driving transistor and the switching transistor may be insulated from the gate electrode by the interlayer insulating film 113. The interlayer insulating film 113 may cover the gate electrodes of each of the driving transistor and the switching transistor. The source electrode and the drain electrode of each pixel PX may be located on the interlayer insulating film 113. The gate insulating film 112 and the interlayer insulating film 113 may expose the source region and the drain region of each semiconductor pattern located in each pixel PX.

[0119] A lower protective layer 114 may be disposed on the interlayer insulating layer 113. The lower protective layer 114 may include an insulating material. For example, the lower protective layer 114 may include an inorganic insulating material such as silicon oxide (SiO) and silicon nitride (SiN). The lower protective layer 114 may prevent damage to the driving portion due to external moisture and impact. The lower protective layer 114 may extend along surfaces of the driving transistor and the switching transistor facing the substrate 110. The lower protective layer 114 may contact the interlayer insulating layer 113 outside the driving portion located in each pixel PX.

[0120] An overcoat layer 115 may be disposed on the lower passivation film 114. The overcoat layer 115 may include an insulating material. The overcoat layer 115 may include a material different from that of the lower passivation film 114. For example, the overcoat layer 115 may include an organic insulating material. The overcoat layer 115 may remove steps caused by driving portions of each pixel PX. For example, an upper surface of the overcoat layer 115 facing the substrate 110 may be a flat surface.

[0121] A first selection transistor TP1 and a second selection transistor TP2 may be disposed on the substrate 110. The first selection transistor TP1 may be electrically connected between the drain electrode of the driving transistor DT and the first lower electrode 141 of the first light-emitting element ED1. The second selection transistor TP2 may be electrically connected between the drain electrode of the driving transistor DT and the second lower electrode 151 of the second light-emitting element ED2.

[0122] The first selection transistor TP1 may include a first semiconductor layer 121, a first gate electrode 122, a first source electrode 123, and a first drain electrode 124. The first selection transistor TP1 may have the same structure as the switching transistor and the driving transistor. For example, the first semiconductor layer 121 may be located between the buffer film 111 and the gate insulating film 112, and the first gate electrode 122 may be located between the gate insulating film 112 and the interlayer insulating film 113. The first source electrode 123 and the first drain electrode 124 may be located between the interlayer insulating film 113 and the lower protective film 114. The first gate electrode 122 may overlap with the channel region of the first semiconductor layer 121. The first source electrode 123 may be electrically connected to the source region of the first semiconductor layer 121. The first drain electrode 124 may be electrically connected to the drain region of the first semiconductor layer 121.

[0123] The second selection transistor TP2 may include a second semiconductor layer 221, a second gate electrode 223, a second source electrode 225, and a second drain electrode 227. For example, the second semiconductor layer 221 may be located in the same layer as the first semiconductor layer 121, the second gate electrode 223 may be located in the same layer as the first gate electrode 122, and the second source electrode 225 and the second drain electrode 227 may be located in the same layer as the first source electrode 123 and the first drain electrode 124.

[0124] The first light emitting element ED1 and the second light emitting element ED2 of each pixel PX may be disposed on the overcoat layer 115 of the corresponding pixel PX.

[0125] The first light emitting element ED1 may emit light exhibiting a specific color. For example, the first light emitting element ED1 may include a first lower electrode 141, a first light emitting layer 142, and a first upper electrode 143, which are sequentially stacked on a substrate 110.

[0126] The first lower electrode 141 may include a conductive material. The first lower electrode 141 may include a material having high reflectivity. For example, the first lower electrode 141 may include a metal such as aluminum (Al) and silver (Ag). The first lower electrode 141 may have a multi-layer structure. For example, the first lower electrode 141 may have a structure in which a reflective electrode made of a metal is located between transparent electrodes made of a transparent conductive material such as ITO and IZO. The first lower electrode 141 may be electrically connected to the first drain electrode 124 of the first selection transistor TP1 through a contact hole penetrating the lower passivation film 114 and the overcoat layer 115.

[0127] The first light emitting layer 142 may generate light having a brightness corresponding to a voltage difference between the first lower electrode 141 and the first upper electrode 143. For example, the first light emitting layer 142 may include an emission material layer (EML) including a light emitting material. The light emitting material may include an organic material, an inorganic material, or a hybrid material.

[0128] The first light emitting layer 142 may have a multi-layer structure. For example, the first light emitting layer 142 may further include at least one of a hole injection layer (HIL), a hole transport layer (HTL), an electron transport layer (ETL), and an electron injection layer (EIL).

[0129] The first upper electrode 143 may include a conductive material. The first upper electrode 143 may include a material different from that of the first lower electrode 141. The transmittance of the first upper electrode 143 may be higher than that of the first lower electrode 141. For example, the first upper electrode 143 may be a transparent electrode made of a transparent conductive material such as ITO or IZO. Thus, in the display device 100 according to the embodiment of the present specification, light generated by the first light emitting layer 142 may be emitted through the first upper electrode 143.

[0130] The second light emitting element ED2 may express the same color as the first light emitting element ED1. The second light emitting element ED2 may have the same structure as the first light emitting element ED1. For example, the second light emitting element ED2 may include a second lower electrode 151, a second light emitting layer 152, and a second upper electrode 153, which are sequentially stacked on the substrate 110.

[0131] The second lower electrode 151 may correspond to the first lower electrode 141, the second light emitting layer 152 may correspond to the first light emitting layer 142, and the second upper electrode 153 may correspond to the first upper electrode 143. For example, the second lower electrode 151 may be formed with the same structure as the first lower electrode 141 for the second light emitting element ED2, which is also the same for the second light emitting layer 152 and the second upper electrode 153. For example, the first light emitting element ED1 and the second light emitting element ED2 may be formed to have the same structure. However, this is not limited thereto, and in some cases, at least a part of the configuration of the first light emitting element ED1 and the second light emitting element ED2 may be formed to be different.

[0132] The second light emitting layer 152 may be spaced apart from the first light emitting layer 142. This may prevent light emission due to leakage current in the display device according to the embodiment of the present disclosure.

[0133] According to the embodiment of the present disclosure, in the display device, light may be generated from only one of the first light emitting layer 142 and the second light emitting layer 152 according to a user selection or a pre-specified condition.

[0134] The second lower electrode 151 of each pixel PX may be spaced apart from the first lower electrode 141 of the corresponding pixel PX. For example, a bank insulating layer 116 may be disposed between the first lower electrode 141 and the second lower electrode 151 of each pixel PX. The bank insulating layer 116 may include an insulating material. For example, the bank insulating layer 116 may include an organic insulating material. The bank insulating layer 116 may include a material different from that of the overcoat layer 115.

[0135] The second lower electrode 151 of each pixel PX may be insulated from the first lower electrode 141 of the corresponding pixel PX by the bank insulating film 116. For example, the bank insulating film 116 may cover an edge of the first lower electrode 141 and an edge of the second lower electrode 151 located in each pixel PX. As a result, in the display device 100, an image according to the first optical region of each pixel PX in which the first light-emitting element ED1 is located or an image according to the second optical region of each pixel PX in which the second light-emitting element ED2 is located may be provided to a user.

[0136] The first light emitting layer 142 and the first upper electrode 143 of the first light emitting element ED1 located in each pixel PX may be stacked on a portion of the first lower electrode 141 exposed by the bank insulating film 116. The second light emitting layer 152 and the second upper electrode 153 of the second light emitting element ED2 located in each pixel PX may be stacked on a portion of the second lower electrode 151 exposed by the bank insulating film 116. For example, the bank insulating film 116 may divide each pixel PX into a first light emitting region where light is emitted by the first light emitting element ED1 and a second light emitting region where light is emitted by the second light emitting element ED2. The size of the divided second light emitting region in each pixel PX may be smaller than the size of the first light emitting region.

[0137] The second upper electrode 153 of each pixel PX may be electrically connected to the first upper electrode 143 of the corresponding pixel PX. For example, a voltage applied to the second upper electrode 153 of the second light-emitting element ED2 located in each pixel PX may be the same as a voltage applied to the first upper electrode 143 of the first light-emitting element ED1 located in the corresponding pixel PX. The second upper electrode 153 of each pixel PX may include the same material as the first upper electrode 143 of the corresponding pixel PX. For example, the second upper electrode 153 of each pixel PX may be formed simultaneously with the first upper electrode 143 of the corresponding pixel PX. The second upper electrode 153 of each pixel PX may extend onto the bank insulating film 116 and directly contact the first upper electrode 143 of the corresponding pixel PX. The luminance of the first optical region and the luminance of the second optical region located in each pixel PX may be controlled by a driving current generated in the corresponding pixel PX.

[0138] An encapsulating member 180 may be disposed on the first light emitting element ED1 and the second light emitting element ED2 of each pixel PX. The encapsulating member 180 may prevent the light emitting elements ED1 and ED2 from being damaged by moisture and impact from the outside. The encapsulating member 180 may have a multi-layer structure. For example, the encapsulating member 180 may include, but is not limited to, a first encapsulating layer 181, a second encapsulating layer 182, and a third encapsulating layer 183, which are sequentially stacked. The first encapsulating layer 181, the second encapsulating layer 182, and the third encapsulating layer 183 may include an insulating material. The second encapsulating layer 182 may include a material different from the first encapsulating layer 181 and the third encapsulating layer 183. For example, the first encapsulating layer 181 and the third encapsulating layer 183 may be inorganic encapsulating layers including an inorganic insulating material, and the second encapsulating layer 182 may include an organic encapsulating layer including an organic insulating material. This may more effectively prevent the light emitting elements ED1 and ED2 of the display device 100 from being damaged by moisture and impact from the outside.

[0139] A first optical member 161 and a second optical member 162 may be disposed on the sealing member 180 .

[0140] The first optical member 161 may be disposed on the first light emitting element ED1. Light generated by the first light emitting element ED1 of each pixel PX may be emitted through the first optical member 161 disposed in the first optical region of the corresponding pixel PX. The first optical member 161 may have a shape that does not restrict light in at least one direction. For example, the planar shape of the first optical member 161 located in each pixel PX may have a bar shape extending in one direction.

[0141] In this case, the traveling direction of the corresponding light emitted from the first optical region of each pixel PX does not need to be limited to one direction. For example, the content (or image) provided through the first optical region of each pixel PX can be shared with the user and people nearby in one direction. Thus, the content provided by the light emitted through the first optical member 161 can be provided in a first viewing angle range, which is a wider viewing angle than the content provided by the light emitted through the second optical member 162. For example, the content provided by the light emitted through the first optical member 161 can be provided in a wide viewing mode (Share mode).

[0142] The second optical member 162 may be disposed on the second light-emitting element ED2. Light generated by the second light-emitting element ED2 of each pixel PX may be emitted through the second optical member 162 disposed in the second optical region of the corresponding pixel PX. The second optical member 162 may limit the traveling direction of the light passing therethrough to one direction and / or the other direction. For example, the planar shape of the second optical member 162 located in each pixel PX may have a circular shape.

[0143] In this case, the traveling direction of the light emitted from the second optical region of each pixel PX may be limited to one direction and / or the other direction. For example, the content (or image) provided by the second optical region of each pixel PX does not need to be shared with people around the user. As a result, the content provided by the light emitted through the second optical member 162 may be provided in a second viewing angle range that is a narrower viewing angle than the content provided by the light emitted through the first optical member 161. For example, the content provided by the light emitted through the second optical member 162 may be provided in a narrow viewing mode (Private mode).

[0144] The first light-emitting region of each pixel PX may have a shape corresponding to the first optical member 161 of the corresponding pixel PX. For example, the planar shape of the first light-emitting region of each pixel PX may have a bar shape extending in one direction. The first optical member 161 may have a larger size than the first light-emitting region of the corresponding pixel PX. This may improve the efficiency of light emitted from the first light-emitting region of the pixel PX.

[0145] The second light-emitting region of each pixel PX may have a shape corresponding to the second optical member 162 of the corresponding pixel PX. For example, the planar shape of the second light-emitting region of each pixel PX may be circular. The second optical member 162 may have a larger size than the second light-emitting region of the corresponding pixel PX. This may improve the efficiency of light emitted from the second light-emitting region of the pixel PX.

[0146] An optical member protective film 170 may be positioned on the first optical member 161 and the second optical member 162 of the pixel PX. The optical member protective film 170 may include an insulating material. For example, the optical member protective film 170 may include an organic insulating material. The refractive index of the optical member protective film 170 may be smaller than the refractive index of the first optical member 161 and the second optical member 162 located in each pixel PX. As a result, in the display device 100 according to the embodiment of the present specification, the light passing through the first optical member 161 and the second optical member 162 of each pixel PX is not reflected toward the substrate 110 due to the refractive index difference with the optical member protective film 170.

[0147] FIG. 8 is a circuit diagram showing an example of a selection signal generating circuit included in the display device of FIG.

[0148] Meanwhile, the first selection signal generation circuit SLC1 shown in Fig. 8 illustrates an embodiment of a selection signal generation circuit corresponding to each of the selection signal generation units SLG included in the display device 100 described with reference to Figs. 2 to 3e. The selection signal generation unit SLG including the first selection signal generation circuit SLC1 can provide a selection signal to the pixel PX including the first pixel circuit PC1 described with reference to Fig. 4.

[0149] 8, the transistors included in the first selection signal generating circuit SLC1 may be n-type transistors or p-type transistors. In the case of p-type transistors, a low level voltage of each control signal may mean a voltage that turns on a TFT, and a high level voltage of each control signal may mean a voltage that turns off a TFT. In the following, for convenience of explanation, the transistors T1 to T8 included in the first selection signal generating circuit SLC1 are described as p-type transistors, but at least some of the transistors T1 to T8 included in the first selection signal generating circuit SLC1 may be modified to be n-type transistors.

[0150] Hereinafter, the first electrode or the second electrode of a transistor may mean a source electrode or a drain electrode. However, the terms first electrode and second electrode are merely terms for distinguishing each electrode, and do not limit what each electrode corresponds to. Also, the first electrode may not refer to the same electrode for each electrode.

[0151] The first selection signal generation circuit SLC1 may include a first selection signal output unit SGL1 that generates a first selection signal Ss based on the first to fourth control signals S_V, S_H, P_V, P_H, the first power supply voltage VGH and the second power supply voltage VGL, and a second selection signal output unit SGL2 that generates a second selection signal Ps based on the first to fourth control signals S_V, S_H, P_V, P_H, the first power supply voltage VGH and the second power supply voltage VGL.

[0152] The first power supply voltage VGH and the second power supply voltage VGL are driving voltages for driving the first selection signal generating circuit SLC1, and the voltage level of the second power supply voltage VGL may be lower than the voltage level of the first power supply voltage VGH. For example, the first power supply voltage VGH may be a positive voltage, and the second power supply voltage VGL may be a negative voltage.

[0153] The first selection signal output unit SGL1 controls the voltage of the first output node NC1 to be the first power supply voltage VGH at a high level or the second power supply voltage VGL at a low level, thereby outputting the first selection signal Ss at a high level or a low level, i.e., the first selection signal Ss at a turn-off level or a turn-on level, through the first output node NC1. To this end, the first selection signal output unit SGL1 includes first to fourth transistors T1 to T4.

[0154] The first transistor T1 may be connected between a second power supply voltage wiring providing a second power supply voltage VGL and a first output node NC1. For example, a first electrode of the first transistor T1 may be connected to the second power supply voltage wiring, and a second electrode of the first transistor T1 may be connected to the first output node NC1. A gate electrode of the first transistor T1 may be connected to a first control signal wiring providing a first control signal S_V. When a turn-on level, for example, a first control signal S_V of a low level is supplied, the first transistor T1 is turned on to electrically connect the first output node NC1 and the second power supply voltage wiring. In this case, the second power supply voltage VGL is provided to the first output node NC1, and the first selection signal output unit SGL1 may output a first selection signal Ss of a low level.

[0155] The second transistor T2 may be connected between a second power supply voltage wiring providing a second power supply voltage VGL and the first output node NC1. For example, a first electrode of the second transistor T2 may be connected to the second power supply voltage wiring, and a second electrode of the second transistor T2 may be connected to the first output node NC1. A gate electrode of the second transistor T2 may be connected to a second control signal wiring providing a second control signal S_H. When a turn-on level, for example, a low level second control signal S_H is supplied, the second transistor T2 is turned on to electrically connect the first output node NC1 and the second power supply voltage wiring. In this case, the second power supply voltage VGL is provided to the first output node NC1, and the first selection signal output unit SGL1 may output a low level first selection signal Ss.

[0156] The third transistor T3 may be connected between a first power supply voltage wiring providing a first power supply voltage VGH and a first output node NC1. For example, a first electrode of the third transistor T3 may be connected to the fourth transistor T4, and a second electrode of the third transistor T3 may be connected to the first output node NC1. A gate electrode of the third transistor T3 may be connected to a third control signal wiring providing a third control signal P_V. When a third control signal P_V of a turn-on level, for example, a low level, is supplied, the third transistor T3 is turned on to electrically connect the first output node NC1 and the fourth transistor T4.

[0157] The fourth transistor T4 may be connected between the third transistor T3 and a first power supply voltage wiring providing a first power supply voltage VGH. For example, a first electrode of the fourth transistor T4 may be connected to the first power supply voltage wiring, and a second electrode of the fourth transistor T4 may be connected to a first electrode of the third transistor T3. A gate electrode of the fourth transistor T4 may be connected to a fourth control signal wiring providing a fourth control signal P_H. When a turn-on level, for example, a low level fourth control signal P_H is supplied, the fourth transistor T4 is turned on to electrically connect the third transistor T3 to the second power supply voltage wiring.

[0158] The first transistor T1 and the second transistor T2 may be connected in parallel between a second power supply voltage line providing a second power supply voltage VGL and a first output node NC1. Thus, when at least one of the first transistor T1 and the second transistor T2 is turned on, the first output node NC1 and the second power supply voltage line providing the second power supply voltage VGL are electrically connected to each other, and a first selection signal Ss of a low level may be output through the first output node NC1.

[0159] In addition, the third transistor T3 and the fourth transistor T4 may be connected in series between a first power supply voltage line providing the first power supply voltage VGH and a first output node NC1. Thus, when both the third transistor T3 and the fourth transistor T4 are turned on, the first output node NC1 and the first power supply voltage line providing the first power supply voltage VGH are electrically connected to each other, and a first selection signal Ss of a high level may be output through the first output node NC1.

[0160] In this manner, the first transistor T1 and the second transistor T2 can function as a pull-up section of the first selection signal output section SGL1, and the third transistor T3 and the fourth transistor T4 can function as a pull-down section of the first selection signal output section SGL1. For example, the first transistor T1 and the second transistor T2 can be defined as a first pull-up section, and the third transistor T3 and the fourth transistor T4 can be defined as a first pull-down section.

[0161] The second selection signal output unit SGL2 controls the voltage of the second output node NC2 to the first power supply voltage VGH at a high level or the second power supply voltage VGL at a low level, thereby outputting the second selection signal Ps at a high level or a low level, i.e., the second selection signal Ps at a turn-off level or a turn-on level, through the second output node NC2. To this end, the second selection signal output unit SGL2 may include fifth to eighth transistors T5 to T8.

[0162] The fifth transistor T5 may be connected between a second power supply voltage wiring providing a second power supply voltage VGL and a second output node NC2. For example, a first electrode of the fifth transistor T5 may be connected to the second power supply voltage wiring, and a second electrode of the fifth transistor T5 may be connected to the sixth transistor T6. A gate electrode of the fifth transistor T5 may be connected to a fourth control signal wiring providing a fourth control signal P_H. When a turn-on level, e.g., a low level fourth control signal P_H is supplied, the fifth transistor T5 is turned on to electrically connect the second power supply voltage wiring and the sixth transistor T6.

[0163] The sixth transistor T6 may be connected between the fifth transistor T5 and the second output node NC2. For example, a first electrode of the sixth transistor T6 may be connected to a second electrode of the fifth transistor T5, and a second electrode of the sixth transistor T6 may be connected to the second output node NC2. A gate electrode of the sixth transistor T6 may be connected to a third control signal wiring that provides a third control signal P_V. When a third control signal P_V of a turn-on level, for example, a low level, is supplied, the sixth transistor T6 is turned on to electrically connect the fifth transistor T5 and the second output node NC2.

[0164] The seventh transistor T7 may be connected between a first power supply voltage wiring providing a first power supply voltage VGH and a second output node NC2. For example, a first electrode of the seventh transistor T7 may be connected to the first power supply voltage wiring, and a second electrode of the seventh transistor T7 may be connected to the second output node NC2. A gate electrode of the seventh transistor T7 may be connected to a first control signal wiring providing a first control signal S_V. When a turn-on level, for example, a first control signal S_V of a low level is supplied, the seventh transistor T7 is turned on to electrically connect the second output node NC2 and the first power supply voltage wiring. In this case, the first power supply voltage VGH is provided to the second output node NC2, and the second selection signal output unit SGL2 may output a second selection signal Ps of a high level.

[0165] The eighth transistor T8 may be connected between a first power supply voltage wiring providing a first power supply voltage VGH and a second output node NC2. For example, a first electrode of the eighth transistor T8 may be connected to the first power supply voltage wiring, and a second electrode of the eighth transistor T8 may be connected to the second output node NC2. A gate electrode of the eighth transistor T8 may be connected to a second control signal wiring providing a second control signal S_H. When a turn-on level, for example, a low level second control signal S_H is supplied, the eighth transistor T8 is turned on to electrically connect the second output node NC2 and the first power supply voltage wiring. In this case, the first power supply voltage VGH is provided to the second output node NC2, and the second selection signal output unit SGL2 may output a high level second selection signal Ps.

[0166] The fifth transistor T5 and the sixth transistor T6 may be connected in series between a second power supply voltage line providing the second power supply voltage VGL and a second output node NC2. Thus, when the fifth transistor T5 and the sixth transistor T6 are both turned on, the second output node NC2 and the second power supply voltage line providing the second power supply voltage VGL are electrically connected to each other, and a low level second selection signal Ps may be output through the second output node NC2.

[0167] In addition, the seventh transistor T7 and the eighth transistor T8 may be connected in parallel between a first power supply voltage line providing the first power supply voltage VGH and a second output node NC2. Thus, when at least one of the seventh transistor T7 and the eighth transistor T8 is turned on, the second output node NC2 and the first power supply voltage line providing the first power supply voltage VGH are electrically connected to each other, and a second selection signal Ps of a high level may be output through the second output node NC2.

[0168] In this way, the fifth transistor T5 and the sixth transistor T6 can function as a pull-up unit of the second selection signal output unit SGL2, and the seventh transistor T7 and the eighth transistor T8 can function as a pull-down unit of the second selection signal output unit SGL2. For example, the fifth transistor T5 and the sixth transistor T6 can be defined as a second pull-up unit, and the seventh transistor T7 and the eighth transistor T8 can be defined as a second pull-down unit.

[0169] FIG. 9 is a diagram for explaining an example of the operation of the selection signal generating circuit of FIG.

[0170] 10a to 10d are equivalent circuit diagrams for explaining an example of the operation of the selection signal generating circuit of FIG.

[0171] 8 and 9, the first selection signal generation circuit SLC1 can output a first selection signal Ss of a low level and a second selection signal Ps of a high level, or output a first selection signal Ss of a high level and a second selection signal Ps of a low level, based on the first to fourth control signals S_V, S_H, P_V, and P_H. That is, the first selection signal generation circuit SLC1 can output the first selection signal Ss and the second selection signal Ps having voltage levels opposite to each other.

[0172] For example, referring further to FIG. 10a, when the first control signal S_V and the second control signal S_H are at a low level, i.e., a turn-on level, and the third control signal P_V and the fourth control signal P_H are at a high level, i.e., a turn-off level, the first transistor T1, the second transistor T2, the seventh transistor T7, and the eighth transistor T8 can be turned on, and the third transistor T3, the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6 can be turned off.

[0173] In this case, the second power supply voltage VGL provided from the second power supply voltage wiring is provided to the first output node NC1 through the turned-on first transistor T1 or the turned-on second transistor T2, and a first selection signal Ss having a low level, i.e., a turn-on level, of the second power supply voltage VGL may be output. Also, the first power supply voltage VGH provided from the first power supply voltage wiring is provided to the second output node NC2 through the turned-on seventh transistor T7 or the turned-on eighth transistor T8, and a second selection signal Ps having a high level, i.e., a turn-off level, of the first power supply voltage VGH may be output.

[0174] Next, referring further to FIG. 10b, when the second control signal S_H and the third control signal P_V are at a low level, i.e., a turn-on level, and the first control signal S_V and the fourth control signal P_H are at a high level, i.e., a turn-off level, the second transistor T2, the third transistor T3, the sixth transistor T6 and the eighth transistor T8 can be turned on, and the first transistor T1, the fourth transistor T4, the fifth transistor T5 and the seventh transistor T7 can be turned off.

[0175] In this case, the second power supply voltage VGL provided from the second power supply voltage line is provided to the first output node NC1 through the turned-on second transistor T2, and a first selection signal Ss having a low level, i.e., a turn-on level, of the second power supply voltage VGL may be output. Also, the first power supply voltage VGH provided from the first power supply voltage line is provided to the second output node NC2 through the turned-on eighth transistor T8, and a second selection signal Ps having a high level, i.e., a turn-off level, of the first power supply voltage VGH may be output.

[0176] Meanwhile, even if the third transistor T3 is turned on, the fourth transistor T4 connected in series with the third transistor T3 is turned off, so that the first power supply voltage VGH cannot be provided to the first output node NC1. Similarly, even if the sixth transistor T6 is turned on, the fifth transistor T5 connected in series with the sixth transistor T6 is turned off, so that the second power supply voltage VGL cannot be provided to the second output node NC2.

[0177] Next, referring further to FIG. 10c, when the second control signal S_H and the third control signal P_V are at a high level, i.e., a turn-off level, and the first control signal S_V and the fourth control signal P_H are at a low level, i.e., a turn-on level, the second transistor T2, the third transistor T3, the sixth transistor T6 and the eighth transistor T8 can be turned off, and the first transistor T1, the fourth transistor T4, the fifth transistor T5 and the seventh transistor T7 can be turned on.

[0178] In this case, the second power supply voltage VGL provided from the second power supply voltage line is provided to the first output node NC1 through the turned-on first transistor T1, and a first selection signal Ss having a low level, i.e., a turn-on level, of the second power supply voltage VGL may be output. Also, the first power supply voltage VGH provided from the first power supply voltage line is provided to the second output node NC2 through the turned-on seventh transistor T7, and a second selection signal Ps having a high level, i.e., a turn-off level, of the first power supply voltage VGH may be output.

[0179] Meanwhile, even if the fourth transistor T4 is turned on, the third transistor T3 connected in series with the fourth transistor T4 is turned off, so that the first power supply voltage VGH cannot be provided to the first output node NC1. Similarly, even if the fifth transistor T5 is turned on, the sixth transistor T6 connected in series with the fifth transistor T5 is turned off, so that the second power supply voltage VGL cannot be provided to the second output node NC2.

[0180] Finally, referring further to FIG. 10d, when the first control signal S_V and the second control signal S_H are at a high level, i.e., a turn-off level, and the third control signal P_V and the fourth control signal P_H are at a low level, i.e., a turn-on level, the first transistor T1, the second transistor T2, the seventh transistor T7 and the eighth transistor T8 can be turned off, and the third transistor T3, the fourth transistor T4, the fifth transistor T5 and the sixth transistor T6 can be turned on.

[0181] In this case, the first power supply voltage VGH provided from the first power supply voltage wiring is connected in series to each other and provided to the first output node NC1 through the turned-on third transistor T3 and the turned-on fourth transistor T4, and a first selection signal Ss having a high level, i.e., a turn-off level, of the first power supply voltage VGH may be output. Also, the second power supply voltage VGL provided from the second power supply voltage wiring is connected in series to each other and provided to the second output node NC2 through the turned-on fifth transistor T5 and the turned-on sixth transistor T6, and a second selection signal Ps having a low level, i.e., a turn-on level, of the second power supply voltage VGL may be output.

[0182] In this manner, the first selection signal generation circuit SLC1 can provide the first selection signal Ss and the second selection signal Ps having mutually opposing voltage levels to the pixel PX to control the driving mode of the pixel PX.

[0183] For example, when a first selection signal Ss of a low level and a second selection signal Ps of a high level are provided to the pixel PX, the first selection transistor TP1 is turned on and the second selection transistor TP2 is turned off, so that a first driving current is provided to the first light emitting element ED1. In this case, the first light emitting element ED1 can provide light through the first optical member 161 at a wide viewing angle, which is a first viewing angle.

[0184] In addition, when the first selection signal Ss of a high level and the second selection signal Ps of a low level are provided to the pixel PX, the first selection transistor TP1 is turned off and the second selection transistor TP2 is turned on, so that the second driving current is provided to the second light emitting element ED2. In this case, the second light emitting element ED2 can provide light through the second optical member 162 at a second viewing angle, which is a narrow viewing angle.

[0185] In this manner, the selection signal generating unit SLG to which the first selection signal generating circuit SLC1 is applied can provide a first selection signal Ss and a second selection signal Ps having opposite voltage levels to the pixel PX, thereby controlling at least one corresponding pixel PX to a first mode or a second mode.

[0186] FIG. 11 is a circuit diagram showing another example of a pixel circuit included in the display device of FIG.

[0187] Meanwhile, the second pixel circuit PC2 shown in Fig. 11 shows another embodiment of a pixel circuit corresponding to each of the plurality of pixels PX included in the display device 100 described with reference to Fig. 2. For example, Fig. 11 shows a modified embodiment of the embodiment of Fig. 4 in relation to the selection transistors TP3 and TP4, and therefore, in Fig. 11, differences from the embodiment of Fig. 4 will be mainly described to avoid redundant description.

[0188] Referring to FIG. 11, the second pixel circuit PC2 may include a driving transistor DT, a plurality of switching transistors ST1 to ST6, a plurality of selection transistors TP3 and TP4, a storage capacitor Cst, and a plurality of light emitting elements ED1 and ED2.

[0189] The multiple selection transistors TP3, TP4 may include a third selection transistor TP3 for generating a current path for a first driving current via the first light-emitting element ED1, and a fourth selection transistor TP4 for generating a current path for a second driving current via the second light-emitting element ED2.

[0190] The third selection transistor TP3 is connected between the fourth node N4 and the first light emitting element ED1, and the gate electrode of the third selection transistor TP3 may be connected to a selection signal line that provides a selection signal MS.

[0191] The fourth selection transistor TP4 is connected between the fourth node N4 and the second light emitting element ED2, and the gate electrode of the fourth selection transistor TP4 may be connected to a selection signal line that provides a selection signal MS.

[0192] The third selection transistor TP3 may be an n-type transistor, and the fourth selection transistor TP4 may be a p-type transistor. Thus, when a low-level selection signal MS is supplied to the selection signal wiring, the third selection transistor TP3 may be turned off and the fourth selection transistor TP4 may be turned on in response to the low-level selection signal MS. Also, when a high-level selection signal MS is supplied to the selection signal wiring, the third selection transistor TP3 may be turned on and the fourth selection transistor TP4 may be turned off in response to the high-level selection signal MS.

[0193] When the pixel PX to which the second pixel circuit PC2 is applied is driven in the first mode, which is a wide viewing mode, a high-level selection signal MS is supplied to the gate electrodes of the third and fourth selection transistors TP3 and TP4, respectively, to turn on the third and fourth selection transistors TP3 and TP4, respectively, and the first and fourth selection transistors TP4 and ED1 are turned on and off, respectively. Thus, a current path for the first driving current passing through the first light-emitting element ED1 is formed, and the first light-emitting element ED1 can emit light. Meanwhile, the second driving current is not formed due to the fourth selection transistor TP4 being turned off, and the second light-emitting element ED2 cannot emit light.

[0194] Also, when the pixel PX to which the second pixel circuit PC2 is applied is driven in the second mode, which is a narrow viewing mode, a low-level selection signal MS is supplied to the gate electrodes of the third selection transistor TP3 and the fourth selection transistor TP4, respectively, to turn off the third selection transistor TP3 and turn on the fourth selection transistor TP4. Thus, a current path for the second driving current passing through the second light-emitting element ED2 is formed, and the second light-emitting element ED2 can emit light. Meanwhile, since the first driving current is not formed due to the turned-off third selection transistor TP3, the first light-emitting element ED1 cannot emit light.

[0195] The first light emitting element ED1 may be connected between a third selection transistor TP3 that is turned on or off by a selection signal MS and a low potential power supply line that provides a low potential power supply voltage VSS. The second light emitting element ED2 may be connected between a fourth selection transistor TP4 that is turned on or off by a selection signal MS and a low potential power supply line that provides a low potential power supply voltage VSS.

[0196] In this case, the first light emitting element ED1 or the second light emitting element ED2 may be connected to another component of the second pixel circuit PC2, for example, the driving transistor DT, by the third selection transistor TP3 or the fourth selection transistor TP4 that is turned on depending on the driving mode. For example, the first light emitting element ED1 may be connected to the driving transistor DT via the third selection transistor TP3 that is turned on in the first mode, and may provide light at a wide viewing angle, which is a first viewing angle, in the first mode, i.e., wide viewing mode, by the first driving current. Also, the second light emitting element ED2 may be connected to the driving transistor DT via the fourth selection transistor TP4 that is turned on in the second mode, and may provide light at a narrow viewing angle, which is a second viewing angle, in the second mode, i.e., narrow viewing mode, by the second driving current. Here, the driving mode may be designated by a user's input or may be determined when a pre-designated condition is satisfied.

[0197] FIG. 12 is a circuit diagram showing another example of the selection signal generating circuit included in the display device of FIG.

[0198] On the other hand, the second selection signal generation circuit SLC2 shown in FIG. 12 shows another embodiment of a selection signal generation circuit corresponding to each of the multiple selection signal generation units SLG included in the display device 100 described with reference to FIG. 2 to FIG. 3e, and the selection signal generation unit SLG including the second selection signal generation circuit SLC2 can provide a selection signal to the pixel PX including the second pixel circuit PC2 described with reference to FIG. 11.

[0199] 12, the multiple transistors included in the second selection signal generation circuit SLC2 may be n-type transistors or p-type transistors. For convenience of explanation, the following description will be given on the basis that the multiple transistors T9 to T12 included in the second selection signal generation circuit SLC2 are p-type transistors, but at least some of the multiple transistors T9 to T12 included in the second selection signal generation circuit SLC2 may be modified to be n-type transistors.

[0200] The second selection signal generation circuit SLC2 can generate a selection signal MS based on the first to fourth control signals S_V, S_H, P_V, P_H, the first power supply voltage VGH, and the second power supply voltage VGL.

[0201] The second selection signal generation circuit SLC2 can output a high-level or low-level selection signal MS through the third output node NC3 by controlling the voltage of the third output node NC3 to the first power supply voltage VGH at a high level or the second power supply voltage VGL at a low level. For this purpose, the second selection signal generation circuit SLC2 can include ninth to twelfth transistors T9 to T12.

[0202] The ninth transistor T9 may be connected between a second power supply voltage wiring providing a second power supply voltage VGL and a third output node NC3. For example, a first electrode of the ninth transistor T9 may be connected to the second power supply voltage wiring, and a second electrode of the ninth transistor T9 may be connected to the third output node NC3. A gate electrode of the ninth transistor T9 may be connected to a first control signal wiring providing a first control signal S_V. When a turn-on level, for example, a first control signal S_V of a low level is supplied, the ninth transistor T9 is turned on to electrically connect the third output node NC3 and the second power supply voltage wiring. In this case, the second power supply voltage VGL is provided to the third output node NC3, and the second selection signal generation circuit SLC2 may output a selection signal MS of a low level.

[0203] The tenth transistor T10 may be connected between a second power supply voltage wiring providing a second power supply voltage VGL and a third output node NC3. For example, a first electrode of the tenth transistor T10 may be connected to the second power supply voltage wiring, and a second electrode of the tenth transistor T10 may be connected to the third output node NC3. A gate electrode of the tenth transistor T10 may be connected to a second control signal wiring providing a second control signal S_H. When a turn-on level, for example, a low level second control signal S_H is supplied, the tenth transistor T10 is turned on to electrically connect the third output node NC3 and the second power supply voltage wiring. In this case, the second power supply voltage VGL is provided to the third output node NC3, and the second selection signal generation circuit SLC2 may output a low level selection signal MS.

[0204] The eleventh transistor T11 may be connected between a first power supply voltage wiring providing a first power supply voltage VGH and a third output node NC3. For example, a first electrode of the eleventh transistor T11 may be connected to the twelfth transistor T12, and a second electrode of the eleventh transistor T11 may be connected to the third output node NC3. A gate electrode of the eleventh transistor T11 may be connected to a third control signal wiring providing a third control signal P_V. When a third control signal P_V of a turn-on level, for example, a low level, is supplied, the eleventh transistor T11 is turned on to electrically connect the third output node NC3 and the twelfth transistor T12.

[0205] The twelfth transistor T12 may be connected between the eleventh transistor T11 and a first power supply voltage wiring that provides a first power supply voltage VGH. For example, a first electrode of the twelfth transistor T12 may be connected to the first power supply voltage wiring, and a second electrode of the twelfth transistor T12 may be connected to a first electrode of the eleventh transistor T11. A gate electrode of the twelfth transistor T12 may be connected to a fourth control signal wiring that provides a fourth control signal P_H. When a fourth control signal P_H of a turn-on level, for example, a low level, is supplied, the twelfth transistor T12 is turned on to electrically connect the eleventh transistor T11 to the second power supply voltage wiring.

[0206] The ninth transistor T9 and the tenth transistor T10 may be connected in parallel between a second power supply voltage line providing the second power supply voltage VGL and a third output node NC3. Thus, when at least one of the ninth transistor T9 and the tenth transistor T10 is turned on, the third output node NC3 and the second power supply voltage line providing the second power supply voltage VGL are electrically connected to each other, and a low level selection signal MS may be output through the third output node NC3.

[0207] In addition, the eleventh transistor T11 and the twelfth transistor T12 may be connected in series between a first power supply voltage line providing the first power supply voltage VGH and a third output node NC3. Thus, when both the eleventh transistor T11 and the twelfth transistor T12 are turned on, the third output node NC3 and the first power supply voltage line providing the first power supply voltage VGH are electrically connected to each other, and a high level selection signal MS may be output through the third output node NC3.

[0208] In this manner, the ninth transistor T9 and the tenth transistor T10 can function as a pull-up unit of the second selection signal generating circuit SLC2, and the eleventh transistor T11 and the twelfth transistor T12 can function as a pull-down unit of the second selection signal generating circuit SLC2. For example, the ninth transistor T9 and the tenth transistor T10 can be defined as a third pull-up unit, and the eleventh transistor T11 and the twelfth transistor T12 can be defined as a third pull-down unit.

[0209] FIG. 13 is a diagram for explaining an example of the operation of the selection signal generating circuit of FIG.

[0210] 14a to 14d are equivalent circuit diagrams for explaining an example of the operation of the selection signal generating circuit of FIG.

[0211] 12 and 13, the second selection signal generation circuit SLC2 can output a low level selection signal MS or a high level selection signal MS based on the first to fourth control signals S_V, S_H, P_V, and P_H.

[0212] For example, referring further to FIG. 14a, when the first control signal S_V and the second control signal S_H are at a low level, i.e., a turn-on level, and the third control signal P_V and the fourth control signal P_H are at a high level, i.e., a turn-off level, the ninth transistor T9 and the tenth transistor T10 can be turned on, and the eleventh transistor T11 and the twelfth transistor T12 can be turned off.

[0213] In this case, the second power supply voltage VGL provided from the second power supply voltage wiring is provided to the third output node NC3 through the turned-on ninth transistor T9 or the turned-on tenth transistor T10, and a selection signal MS having a low level of the second power supply voltage VGL can be output.

[0214] Next, referring further to FIG. 14b, when the second control signal S_H and the third control signal P_V are at a low level, i.e., a turn-on level, and the first control signal S_V and the fourth control signal P_H are at a high level, i.e., a turn-off level, the tenth transistor T10 and the eleventh transistor T11 can be turned on, and the ninth transistor T9 and the twelfth transistor T12 can be turned off.

[0215] In this case, the second power supply voltage VGL provided from the second power supply voltage line is provided to the third output node NC3 through the turned-on tenth transistor T10, and a selection signal MS having a low level of the second power supply voltage VGL can be output.

[0216] On the other hand, even if the eleventh transistor T11 is turned on, the twelfth transistor T12 connected in series with the eleventh transistor T11 is turned off, so that the first power supply voltage VGH cannot be provided to the third output node NC3.

[0217] Next, referring further to FIG. 14c, when the second control signal S_H and the third control signal P_V are at a high level, i.e., a turn-off level, and the first control signal S_V and the fourth control signal P_H are at a low level, i.e., a turn-on level, the ninth transistor T9 and the twelfth transistor T12 can be turned off, and the tenth transistor T10 and the eleventh transistor T11 can be turned on.

[0218] In this case, the second power supply voltage VGL provided from the second power supply voltage line is provided to the third output node NC3 through the turned-on ninth transistor T9, and a selection signal MS having a low level of the second power supply voltage VGL can be output.

[0219] On the other hand, even if the twelfth transistor T12 is turned on, the eleventh transistor T11 connected in series with the twelfth transistor T12 is turned off, so that the first power supply voltage VGH cannot be provided to the third output node NC3.

[0220] Finally, referring further to FIG. 14d, when the first control signal S_V and the second control signal S_H are at a high level, i.e., a turn-off level, and the third control signal P_V and the fourth control signal P_H are at a low level, i.e., a turn-on level, the ninth transistor T9 and the tenth transistor T10 can be turned off, and the eleventh transistor T11 and the twelfth transistor T12 can be turned on.

[0221] In this case, the first power supply voltage VGH provided from the first power supply voltage wiring is connected in series with each other and provided to the third output node NC3 through the turned-on eleventh transistor T11 and the turned-on twelfth transistor T12, and a selection signal MS having a high level of the first power supply voltage VGH can be output.

[0222] In this way, the second selection signal generation circuit SLC2 can control the driving mode of the pixel PX by providing a selection signal MS having a high level to the pixel PX in the first mode and providing a selection signal MS having a low level to the pixel PX in the second mode.

[0223] For example, when a high level selection signal MS is provided to the pixel PX, the third selection transistor TP3 is turned on and the fourth selection transistor TP4 is turned off, so that a first driving current is provided to the first light emitting element ED1. In this case, the first light emitting element ED1 can provide light through the first optical member 161 at a wide viewing angle, which is a first viewing angle.

[0224] In addition, when a low level selection signal MS is provided to the pixel PX, the third selection transistor TP3 is turned off and the fourth selection transistor TP4 is turned on, so that the second driving current is provided to the second light emitting element ED2. In this case, the second light emitting element ED2 can provide light through the second optical member 162 at a second viewing angle, which is a narrow viewing angle.

[0225] In this manner, the selection signal generation unit SLG to which the second selection signal generation circuit SLC2 is applied can provide a selection signal MS having a different voltage level in each mode to the pixel PX, thereby controlling at least one corresponding pixel PX to the first mode or the second mode.

[0226] Furthermore, as explained with reference to Figures 11 to 14d, by commonly connecting the gate electrodes of the selection transistors TP3 and TP4 included in the pixel circuit of the pixel PX to the same selection signal MS and controlling the voltage level of the selection signal MS by the drive mode, the number of selection signal wirings for controlling the selection transistors TP3 and TP4 can be reduced, and the number of transistors in the selection signal generation circuit of the selection signal generation unit SLG can be reduced, thereby simplifying the selection signal generation circuit for generating the selection signal.

[0227] FIG. 15 is a circuit diagram showing another example of the selection signal generating circuit included in the display device of FIG.

[0228] Meanwhile, the third selection signal generating circuit SLC3 shown in FIG. 15 shows another embodiment of a selection signal generating circuit corresponding to each of the multiple selection signal generating units SLG included in the display device 100 described with reference to FIG. 2 to FIG. 3e, and the selection signal generating unit SLG including the third selection signal generating circuit SLC3 can provide a selection signal to the pixel PX including the second pixel circuit PC2 described with reference to FIG. 11.

[0229] 15, the multiple transistors included in the third selection signal generation circuit SLC3 may be n-type transistors or p-type transistors. In the following, for convenience of explanation, the multiple transistors T13-T16 included in the third selection signal generation circuit SLC3 are described as p-type transistors, but at least some of the multiple transistors T13-T16 included in the third selection signal generation circuit SLC3 may be modified to be n-type transistors.

[0230] The third selection signal generation circuit SLC3 can generate a selection signal MS based on the first to fourth control signals S_V, S_H, P_V, P_H, the first power supply voltage VGH, and the second power supply voltage VGL.

[0231] The third selection signal generation circuit SLC3 can output a high-level or low-level selection signal MS through the fourth output node NC4 by controlling the voltage of the fourth output node NC4 to the first power supply voltage VGH at a high level or the second power supply voltage VGL at a low level. To this end, the third selection signal generation circuit SLC3 can include thirteenth to sixteenth transistors T13 to T16.

[0232] The thirteenth transistor T13 may be connected between a second power supply voltage wiring providing a second power supply voltage VGL and a fourth output node NC4. For example, a first electrode of the thirteenth transistor T13 may be connected to the second power supply voltage wiring, and a second electrode of the thirteenth transistor T13 may be connected to the fourteenth transistor T14. A gate electrode of the thirteenth transistor T13 may be connected to a fourth control signal wiring providing a fourth control signal P_H. When a fourth control signal P_H of a turn-on level, for example, a low level, is supplied, the thirteenth transistor T13 is turned on to electrically connect the second power supply voltage wiring and the fourteenth transistor T14.

[0233] The fourteenth transistor T14 may be connected between the thirteenth transistor T13 and the fourth output node NC4. For example, a first electrode of the fourteenth transistor T14 may be connected to a second electrode of the thirteenth transistor T13, and a second electrode of the fourteenth transistor T14 may be connected to the fourth output node NC4. A gate electrode of the fourteenth transistor T14 may be connected to a third control signal wiring that provides a third control signal P_V. When a third control signal P_V of a turn-on level, for example, a low level, is supplied, the fourteenth transistor T14 is turned on to electrically connect the thirteenth transistor T13 and the fourth output node NC4.

[0234] The fifteenth transistor T15 may be connected between a first power supply voltage wiring providing a first power supply voltage VGH and a fourth output node NC4. For example, a first electrode of the fifteenth transistor T15 may be connected to the first power supply voltage wiring, and a second electrode of the fifteenth transistor T15 may be connected to the fourth output node NC4. A gate electrode of the fifteenth transistor T15 may be connected to a first control signal wiring providing a first control signal S_V. When a turn-on level, for example, a first control signal S_V of a low level is supplied, the fifteenth transistor T15 is turned on to electrically connect the fourth output node NC4 and the first power supply voltage wiring. In this case, the first power supply voltage VGH is provided to the fourth output node NC4, and the third selection signal generation circuit SLC3 may output a high level selection signal MS.

[0235] The sixteenth transistor T16 may be connected between a first power supply voltage wiring providing a first power supply voltage VGH and a fourth output node NC4. For example, a first electrode of the sixteenth transistor T16 may be connected to the first power supply voltage wiring, and a second electrode of the sixteenth transistor T16 may be connected to the fourth output node NC4. A gate electrode of the sixteenth transistor T16 may be connected to a second control signal wiring providing a second control signal S_H. When a turn-on level, for example, a low level second control signal S_H is supplied, the sixteenth transistor T16 is turned on to electrically connect the fourth output node NC4 and the first power supply voltage wiring. In this case, the first power supply voltage VGH is provided to the fourth output node NC4, and the third selection signal generation circuit SLC3 may output a high level selection signal MS.

[0236] The thirteenth transistor T13 and the fourteenth transistor T14 may be connected in series between a second power supply voltage line providing the second power supply voltage VGL and a fourth output node NC4. Thus, when both the thirteenth transistor T13 and the fourteenth transistor T14 are turned on, the fourth output node NC4 and the second power supply voltage line providing the second power supply voltage VGL are electrically connected to each other, and a low level selection signal MS may be output through the fourth output node NC4.

[0237] In addition, the fifteenth transistor T15 and the sixteenth transistor T16 may be connected in parallel between a first power supply voltage line providing the first power supply voltage VGH and a fourth output node NC4. Thus, when at least one of the fifteenth transistor T15 and the sixteenth transistor T16 is turned on, the fourth output node NC4 and the first power supply voltage line providing the first power supply voltage VGH are electrically connected to each other, and a high level selection signal MS may be output through the fourth output node NC4.

[0238] In this way, the thirteenth transistor T13 and the fourteenth transistor T14 can function as a pull-up unit of the third selection signal generation circuit SLC3, and the fifteenth transistor T15 and the sixteenth transistor T16 can function as a pull-down unit of the third selection signal generation circuit SLC3. For example, the thirteenth transistor T13 and the fourteenth transistor T14 can be defined as a fourth pull-up unit, and the fifteenth transistor T15 and the sixteenth transistor T16 can be defined as a fourth pull-down unit.

[0239] FIG. 16 is a diagram for explaining an example of the operation of the selection signal generating circuit of FIG.

[0240] 17a to 17d are equivalent circuit diagrams for explaining an example of the operation of the selection signal generating circuit of FIG.

[0241] 15 and 16, the third selection signal generation circuit SLC3 can output a low level selection signal MS or a high level selection signal MS based on the first to fourth control signals S_V, S_H, P_V, and P_H.

[0242] For example, referring further to FIG. 17a, when the first control signal S_V and the second control signal S_H are at a low level, i.e., a turn-on level, and the third control signal P_V and the fourth control signal P_H are at a high level, i.e., a turn-off level, the fifteenth transistor T15 and the sixteenth transistor T16 can be turned on, and the thirteenth transistor T13 and the fourteenth transistor T14 can be turned off.

[0243] In this case, the first power supply voltage VGH provided from the first power supply voltage wiring is provided to the fourth output node NC4 through the turned-on 15th transistor T15 or the turned-on 16th transistor T16, and a selection signal MS having a high level of the first power supply voltage VGH can be output.

[0244] Next, referring further to FIG. 17b, when the second control signal S_H and the third control signal P_V are at a low level, i.e., a turn-on level, and the first control signal S_V and the fourth control signal P_H are at a high level, i.e., a turn-off level, the fourteenth transistor T14 and the sixteenth transistor T16 can be turned on, and the thirteenth transistor T13 and the fifteenth transistor T15 can be turned off.

[0245] In this case, the first power supply voltage VGH provided from the first power supply voltage line is provided to the fourth output node NC4 through the turned-on sixteenth transistor T16, and a selection signal MS having a high level of the first power supply voltage VGH can be output.

[0246] On the other hand, even if the fourteenth transistor T14 is turned on, the thirteenth transistor T13 connected in series with the fourteenth transistor T14 is turned off, so that the second power supply voltage VGL cannot be provided to the fourth output node NC4.

[0247] Next, referring further to FIG. 17c, when the second control signal S_H and the third control signal P_V are at a high level, i.e., a turn-off level, and the first control signal S_V and the fourth control signal P_H are at a low level, i.e., a turn-on level, the fourteenth transistor T14 and the sixteenth transistor T16 can be turned off, and the thirteenth transistor T13 and the fifteenth transistor T15 can be turned on.

[0248] In this case, the first power supply voltage VGH provided from the first power supply voltage line is provided to the fourth output node NC4 through the turned-on fifteenth transistor T15, and a selection signal MS having a high level of the first power supply voltage VGH can be output.

[0249] On the other hand, even if the thirteenth transistor T13 is turned on, the fourteenth transistor T14 connected in series with the thirteenth transistor T13 is turned off, so that the second power supply voltage VGL cannot be provided to the fourth output node NC4.

[0250] Finally, referring further to FIG. 17d, when the first control signal S_V and the second control signal S_H are at a high level, i.e., a turn-off level, and the third control signal P_V and the fourth control signal P_H are at a low level, i.e., a turn-on level, the fifteenth transistor T15 and the sixteenth transistor T16 can be turned off, and the thirteenth transistor T13 and the fourteenth transistor T14 can be turned on.

[0251] In this case, the second power supply voltage VGL provided from the second power supply voltage wiring is connected in series with each other and provided to the fourth output node NC4 through the turned-on 13th transistor T13 and the turned-on 14th transistor T14, and a selection signal MS having a low level of the second power supply voltage VGL can be output.

[0252] In this way, the third selection signal generation circuit SLC3 can control the driving mode of the pixel PX by providing a selection signal MS having a high level to the pixel PX in the first mode and providing a selection signal MS having a low level to the pixel PX in the second mode.

[0253] For example, when a high level selection signal MS is provided to the pixel PX, the third selection transistor TP3 is turned on and the fourth selection transistor TP4 is turned off, so that a first driving current is provided to the first light emitting element ED1. In this case, the first light emitting element ED1 can provide light through the first optical member 161 at a wide viewing angle, which is a first viewing angle.

[0254] In addition, when a low level selection signal MS is provided to the pixel PX, the third selection transistor TP3 is turned off and the fourth selection transistor TP4 is turned on, so that the second driving current is provided to the second light emitting element ED2. In this case, the second light emitting element ED2 can provide light through the second optical member 162 at a second viewing angle, which is a narrow viewing angle.

[0255] In this manner, the selection signal generation unit SLG to which the third selection signal generation circuit SLC3 is applied can provide a selection signal MS having a different voltage level in each mode to the pixel PX, thereby controlling at least one corresponding pixel PX to the first mode or the second mode.

[0256] Furthermore, as explained with reference to Figures 11 and 15 to 17d, by commonly connecting the gate electrodes of the selection transistors TP3 and TP4 included in the pixel circuit of the pixel PX to the same selection signal MS and controlling the voltage level of the selection signal MS by the drive mode, the number of selection signal wirings for controlling the selection transistors TP3 and TP4 can be reduced, and the number of transistors in the selection signal generation circuit of the selection signal generation unit SLG can be reduced, thereby simplifying the selection signal generation circuit for generating the selection signal.

[0257] A display device according to an embodiment of the present specification can be described as follows.

[0258] A display device according to an embodiment of the present specification may include a display panel including a display area and a non-display area arranged to surround the display area, the display panel including a plurality of pixels arranged on the display area and a plurality of selection signal generators, and a timing controller for controlling the display panel. Each of the plurality of pixels may include a first light-emitting element, a first optical member for refracting light from the first light-emitting element, a second light-emitting element for emitting the same color as the first light-emitting element, and a second optical member for refracting light from the second light-emitting element and having a shape different from that of the first optical member. Each of the plurality of selection signal generators may control one of the first light-emitting element and the second light-emitting element included in at least one corresponding pixel among the plurality of pixels to emit light.

[0259] According to another feature of the present specification, each of the plurality of pixels may further include a drive transistor that generates a first drive current flowing from a high potential power supply wiring that provides a high potential power supply voltage through a first light emitting element to a low potential power supply wiring that provides a low potential power supply voltage and a second drive current flowing from the high potential power supply wiring to the low potential power supply wiring through a second light emitting element, a first selection transistor connected between the drive transistor and the first light emitting element and turned on in response to a first selection signal supplied to a first selection signal wiring, and a second selection transistor connected between the drive transistor and the second light emitting element and turned on in response to a second selection signal supplied to a second selection signal wiring.

[0260] According to another feature of the present specification, each of the multiple selection signal generation units includes a first selection signal output unit that outputs a first selection signal through a first output node based on the first to fourth control signals, the first power supply voltage, and the second power supply voltage, and a second selection signal output unit that outputs a second selection signal through a second output node based on the first to fourth control signals, the first power supply voltage, and the second power supply voltage.

[0261] According to still another feature of the present specification, the first selection signal output unit may include a first transistor connected between a second power supply voltage wiring providing a second power supply voltage and a first output node and turned on in response to a first control signal, a second transistor connected between the second power supply voltage wiring and the first output node and turned on in response to the second control signal, a third transistor connected between the first output node and a first power supply voltage wiring providing the first power supply voltage and turned on in response to a third control signal, and a fourth transistor connected between the third transistor and the first power supply voltage wiring and turned on in response to a fourth control signal.

[0262] According to still another feature of the present specification, the first transistor and the second transistor may be connected in parallel between the second power supply voltage wiring and the first output node, and the third transistor and the fourth transistor may be connected in series between the first power supply voltage wiring and the first output node.

[0263] According to another feature of the present specification, the second selection signal output unit may include a fifth transistor connected between a second power supply voltage wiring providing a second power supply voltage and a second output node and turned on in response to a fourth control signal, a sixth transistor connected between the fifth transistor and the second output node and turned on in response to a third control signal, a seventh transistor connected between the second output node and a first power supply voltage wiring providing the first power supply voltage and turned on in response to the first control signal, and an eighth transistor connected between the second output node and the first power supply voltage wiring and turned on in response to the second control signal.

[0264] According to still another feature of the present specification, the fifth transistor and the sixth transistor may be connected in series between the second power supply voltage wiring and the second output node, and the seventh transistor and the eighth transistor may be connected in parallel between the first power supply voltage wiring and the second output node.

[0265] According to another feature of the present specification, each of the plurality of pixels may further include a driving transistor that generates a first driving current flowing from a high potential power wiring that provides a high potential power voltage through a first light emitting element to a low potential power wiring that provides a low potential power voltage and a second driving current flowing from the high potential power wiring to the low potential power wiring through a second light emitting element, a third selection transistor connected between the driving transistor and the first light emitting element and turned on in response to a selection signal supplied to the selection signal wiring, and a fourth selection transistor connected between the driving transistor and the second light emitting element and turned on in response to the selection signal.

[0266] According to still other features herein, the third select transistor may be an n-type transistor and the fourth select transistor may be a p-type transistor.

[0267] According to still another feature of the present specification, each of the multiple selection signal generating units can output a selection signal having a high level or a low level based on the first to fourth control signals, the first power supply voltage, and the second power supply voltage.

[0268] According to still another feature of the present specification, each of the selection signal generating units may include a ninth transistor connected between a second power supply voltage wiring providing a second power supply voltage and a third output node and turned on in response to a first control signal, a tenth transistor connected between the second power supply voltage wiring and the third output node and turned on in response to the second control signal, an eleventh transistor connected between the third output node and a first power supply voltage wiring providing the first power supply voltage and turned on in response to the third control signal, and a twelfth transistor connected between the eleventh transistor and the first power supply voltage wiring and turned on in response to a fourth control signal.

[0269] According to still another feature of the present specification, the ninth transistor and the tenth transistor may be connected in parallel between the second power supply voltage wiring and the third output node, and the eleventh transistor and the twelfth transistor may be connected in series between the first power supply voltage wiring and the third output node.

[0270] According to another feature of the present specification, each of the plurality of selection signal generating units may include a 13th transistor connected between a second power supply voltage wiring providing a second power supply voltage and a fourth output node and turned on in response to a fourth control signal, a 14th transistor connected between the 13th transistor and the fourth output node and turned on in response to a third control signal, a 15th transistor connected between the fourth output node and a first power supply voltage wiring providing a first power supply voltage and turned on in response to the first control signal, and a 16th transistor connected between the fourth output node and the first power supply voltage wiring and turned on in response to the second control signal.

[0271] According to still another feature of the present specification, the thirteenth transistor and the fourteenth transistor may be connected in series between the second power supply voltage wiring and the fourth output node, and the fifteenth transistor and the sixteenth transistor may be connected in parallel between the first power supply voltage wiring and the fourth output node.

[0272] According to another feature of the present specification, each of the multiple selection signal generation units can control one of a first light-emitting element and a second light-emitting element included in one pixel among the multiple pixels to emit light.

[0273] According to another feature of the present specification, each of the multiple selection signal generation units can control one of a first light-emitting element and a second light-emitting element included in each of at least two pixels among the multiple pixels to emit light.

[0274] Although the embodiments of the present specification have been described in more detail with reference to the accompanying drawings, the present specification is not necessarily limited to such embodiments, and various modifications can be made within the scope of the technical idea of ​​the present specification. Therefore, the embodiments disclosed in the present specification are for illustration purposes, not for limiting the technical idea of ​​the present specification, and the scope of the technical idea of ​​the present specification is not limited by such embodiments. Therefore, it should be understood that the embodiments described above are illustrative in all respects and not restrictive.

Claims

1. a display panel including a display area and a non-display area arranged so as to surround the display area, the display panel including a plurality of pixels and a plurality of selection signal generating units arranged on the display area; a timing controller for controlling the display panel; Each of the plurality of pixels is A first light-emitting element; a first optical member that refracts light from the first light emitting element; A second light emitting element that emits light of the same color as the first light emitting element; a second optical member that refracts light from the second light emitting element and has a shape different from that of the first optical member; A display device, wherein each of the plurality of selection signal generation units controls one of the first light-emitting element and the second light-emitting element included in at least one corresponding pixel among the plurality of pixels to emit light.

2. Each of the plurality of pixels is a driving transistor that generates a first driving current flowing from a high potential power supply wiring that provides a high potential power supply voltage through the first light emitting element to a low potential power supply wiring that provides a low potential power supply voltage, and a second driving current flowing from the high potential power supply wiring to the low potential power supply wiring through the second light emitting element; a first selection transistor connected between the driving transistor and the first light emitting element and turned on in response to a first selection signal supplied to a first selection signal line; 2. The display device of claim 1, further comprising: a second selection transistor connected between the driving transistor and the second light emitting element and turned on in response to a second selection signal supplied to a second selection signal line.

3. Each of the plurality of selection signal generation units a first selection signal output unit that outputs the first selection signal through a first output node based on the first to fourth control signals, a first power supply voltage, and a second power supply voltage; 3. The display device of claim 2, further comprising: a second selection signal output section that outputs the second selection signal through a second output node based on the first to fourth control signals, the first power supply voltage, and the second power supply voltage.

4. The first selection signal output unit is a first transistor connected between a second power supply voltage line providing the second power supply voltage and the first output node, the first transistor being turned on in response to the first control signal; a second transistor connected between the second power supply voltage wiring and the first output node and turned on in response to the second control signal; a third transistor connected between the first output node and a first power supply voltage line for providing the first power supply voltage, the third transistor being turned on in response to the third control signal; 4. The display device of claim 3, further comprising: a fourth transistor connected between the third transistor and the first power supply voltage wiring and turned on in response to the fourth control signal.

5. the first transistor and the second transistor are connected in parallel between the second power supply voltage wiring and the first output node, The display device according to claim 4 , wherein the third transistor and the fourth transistor are connected in series between the first power supply voltage wiring and the first output node.

6. The second selection signal output unit is a fifth transistor connected between a second power supply voltage line providing the second power supply voltage and the second output node, and turned on in response to the fourth control signal; a sixth transistor connected between the fifth transistor and the second output node and turned on in response to the third control signal; a seventh transistor connected between the second output node and a first power supply voltage line providing the first power supply voltage, the seventh transistor being turned on in response to the first control signal; 4. The display device according to claim 3, further comprising: an eighth transistor connected between the second output node and the first power supply voltage wiring and turned on in response to the second control signal.

7. the fifth transistor and the sixth transistor are connected in series between the second power supply voltage wiring and the second output node, The display device according to claim 6 , wherein the seventh transistor and the eighth transistor are connected in parallel between the first power supply voltage wiring and the second output node.

8. Each of the plurality of pixels is a driving transistor that generates a first driving current flowing from a high potential power supply wiring that provides a high potential power supply voltage through the first light emitting element to a low potential power supply wiring that provides a low potential power supply voltage, and a second driving current flowing from the high potential power supply wiring to the low potential power supply wiring through the second light emitting element; a third selection transistor connected between the driving transistor and the first light emitting element and turned on in response to a selection signal provided to a selection signal line; 2. The display device of claim 1, further comprising a fourth selection transistor connected between the driving transistor and the second light emitting element and turned on in response to the selection signal.

9. The display device according to claim 8 , wherein the third selection transistor is an n-type transistor, and the fourth selection transistor is a p-type transistor.

10. 9. The display device according to claim 8, wherein each of the plurality of selection signal generating units outputs the selection signal having a high level or a low level based on the first to fourth control signals, the first power supply voltage, and the second power supply voltage.

11. Each of the plurality of selection signal generation units a ninth transistor connected between a second power supply voltage line providing the second power supply voltage and a third output node, the ninth transistor being turned on in response to the first control signal; a tenth transistor connected between the second power supply voltage wiring and the third output node and turned on in response to the second control signal; an eleventh transistor connected between the third output node and a first power supply voltage line providing the first power supply voltage, and turned on in response to the third control signal; 11. The display device of claim 10, further comprising: a twelfth transistor connected between the eleventh transistor and the first power supply voltage wiring and turned on in response to the fourth control signal.

12. the ninth transistor and the tenth transistor are connected in parallel between the second power supply voltage wiring and the third output node, The display device according to claim 11 , wherein the eleventh transistor and the twelfth transistor are connected in series between the first power supply voltage wiring and the third output node.

13. Each of the plurality of selection signal generation units a thirteenth transistor connected between a second power supply voltage line for providing the second power supply voltage and a fourth output node, and turned on in response to the fourth control signal; a fourteenth transistor connected between the thirteenth transistor and the fourth output node and turned on in response to the third control signal; a fifteenth transistor connected between the fourth output node and a first power supply voltage line providing the first power supply voltage, the fifteenth transistor being turned on in response to the first control signal; 11. The display device of claim 10, further comprising: a sixteenth transistor connected between the fourth output node and the first power supply voltage wiring and turned on in response to the second control signal.

14. the thirteenth transistor and the fourteenth transistor are connected in series between the second power supply voltage wiring and the fourth output node, The display device according to claim 13 , wherein the fifteenth transistor and the sixteenth transistor are connected in parallel between the first power supply voltage wiring and the fourth output node.

15. The display device according to claim 1 , wherein each of the plurality of selection signal generating sections controls either the first light emitting element or the second light emitting element included in one pixel of the plurality of pixels to emit light.

16. The display device according to claim 1 , wherein each of the selection signal generating sections controls either one of the first light emitting element and the second light emitting element included in each of at least two pixels among the plurality of pixels to emit light.

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