API for Recurrent Neural Networks

Abstract

In at least one embodiment, an application programming interface receives one or more API calls that include a graph definition and a recursion attribute, and executes a recursive neural network based on the graph definition.

Description

[Technical field]

[0001] This application claims priority to U.S. patent application Ser. No. 16 / 719,718, filed Dec. 18, 2019, entitled “API FOR RECURRENT NEURAL NETWORKS,” the entire contents of which are incorporated herein by reference in their entirety and for all purposes.

[0002] At least one embodiment relates to an application programming interface for implementing a recurrent neural network. [Background technology]

[0003] Code for implementing recurrent neural networks can be complex and can result in inefficient code. Application programming interfaces ("APIs") for implementing recurrent neural networks could be improved. Summary of the Invention [Problem to be solved by the invention]

[0004] Provides an API for recurrent neural networks. [Brief description of the drawings]

[0005] [Figure 1] FIG. 1 illustrates an example of implementing a recurrent neural network, according to at least one embodiment. [Diagram 2] FIG. 1 illustrates an example application programming interface for defining and executing a recurrent neural network using the application programming interface, according to at least one embodiment. [Diagram 3] FIG. 13 illustrates an example of restricted access to tensors during the execution of a recurrent neural network, according to at least one embodiment. [Figure 4]FIG. 1 illustrates an example process for defining and executing a recurrent neural network, according to at least one embodiment. [Diagram 5] FIG. 1 illustrates an example embodiment of implementing a bidirectional recurrent neural network, according to at least one embodiment. [Figure 6] FIG. 1 illustrates an example implementation of a ragged recurrent neural network, according to at least one embodiment. [Figure 7] FIG. 1 illustrates an example of a running chain of a bidirectional recurrent neural network, according to at least one embodiment. [Figure 8] FIG. 1 illustrates an example process for defining and executing a recurrent neural network using an application programming interface, according to at least one embodiment. [Figure 9A] FIG. 1 illustrates inference and / or training logic, according to at least one embodiment. [Figure 9B] FIG. 1 illustrates inference and / or training logic, according to at least one embodiment. [Figure 10] FIG. 1 illustrates training and deployment of a neural network, according to at least one embodiment. [Figure 11] FIG. 1 illustrates an example data center system in accordance with at least one embodiment. [Figure 12A] FIG. 1 illustrates an example of an autonomous vehicle, according to at least one embodiment. [Figure 12B] 12B is a diagram illustrating example camera locations and fields of view for the autonomous vehicle of FIG. 12A, according to at least one embodiment. [Figure 12C] FIG. 12B is a block diagram illustrating an example system architecture for the autonomous vehicle of FIG. 12A, according to at least one embodiment. [Figure 12D] FIG. 12B illustrates a system for communication between a cloud-based server and the autonomous vehicle of FIG. 12A, according to at least one embodiment. [Figure 13]FIG. 1 is a block diagram illustrating a computer system according to at least one embodiment. [Figure 14] FIG. 1 is a block diagram illustrating a computer system according to at least one embodiment. [Figure 15] FIG. 1 illustrates a computer system according to at least one embodiment. [Figure 16] FIG. 1 illustrates a computer system according to at least one embodiment. [Figure 17A] FIG. 1 illustrates a computer system according to at least one embodiment. [Figure 17B] FIG. 1 illustrates a computer system according to at least one embodiment. [Figure 17C] FIG. 1 illustrates a computer system according to at least one embodiment. [Figure 17D] FIG. 1 illustrates a computer system according to at least one embodiment. [Figure 17E] FIG. 1 illustrates a shared programming model, according to at least one embodiment. [Figure 17F] FIG. 1 illustrates a shared programming model, according to at least one embodiment. [Figure 18] FIG. 1 illustrates an exemplary integrated circuit and associated graphics processor according to at least one embodiment. [Figure 19A] FIG. 1 illustrates an exemplary integrated circuit and associated graphics processor according to at least one embodiment. [Figure 19B] FIG. 1 illustrates an exemplary integrated circuit and associated graphics processor according to at least one embodiment. [Figure 20A] FIG. 13 illustrates additional exemplary graphics processor logic in accordance with at least one embodiment. [Figure 20B] FIG. 13 illustrates additional exemplary graphics processor logic in accordance with at least one embodiment. [Figure 21] FIG. 1 illustrates a computer system according to at least one embodiment. [Figure 22A] FIG. 1 illustrates a parallel processor, according to at least one embodiment. [Figure 22B] A diagram illustrating a partition unit according to at least one embodiment. [Figure 22C] FIG. 2 illustrates a processing cluster, according to at least one embodiment. [Figure 22D] FIG. 1 illustrates a graphics multiprocessor according to at least one embodiment. [Diagram 23] FIG. 1 illustrates a multi-graphics processing unit (GPU) system in accordance with at least one embodiment. [Figure 24] FIG. 1 illustrates a graphics processor according to at least one embodiment. [Diagram 25] FIG. 1 is a block diagram illustrating a processor micro-architecture for a processor according to at least one embodiment. [Figure 26] FIG. 1 illustrates a deep learning application processor according to at least one embodiment. [Figure 27] FIG. 1 is a block diagram illustrating an exemplary neuromorphic processor in accordance with at least one embodiment. [Figure 28] A diagram illustrating at least a portion of a graphics processor in accordance with one or more embodiments. [Figure 29] A diagram illustrating at least a portion of a graphics processor in accordance with one or more embodiments. [Diagram 30] A diagram illustrating at least a portion of a graphics processor in accordance with one or more embodiments. [Diagram 31] FIG. 1 is a block diagram of a graphics processing engine of a graphics processor in accordance with at least one embodiment. [Diagram 32] 1 is a block diagram of at least a portion of a graphics processor core according to at least one embodiment. [Figure 33A]A diagram illustrating thread execution logic including an array of processing elements of a graphics processor core, in accordance with at least one embodiment. [Figure 33B] A diagram illustrating thread execution logic including an array of processing elements of a graphics processor core, in accordance with at least one embodiment. [Diagram 34] FIG. 2 illustrates a parallel processing unit ("PPU"), according to at least one embodiment. [Diagram 35] FIG. 1 illustrates a general purpose processing cluster ("GPC"), according to at least one embodiment. [Diagram 36] FIG. 2 illustrates a memory partition unit of a parallel processing unit ("PPU") according to at least one embodiment. [Figure 37] FIG. 1 illustrates a streaming multiprocessor according to at least one embodiment. [Figure 38] FIG. 1 is an example data flow diagram for an advanced computing pipeline, according to at least one embodiment. [Figure 39] A system diagram of an example system for training, adapting, instantiating, and deploying machine learning models in an advanced computing pipeline, according to at least one embodiment. [Diagram 40] A diagram including an example of an advanced computing pipeline 3910A for processing imaging data, according to at least one embodiment. [Figure 41A] FIG. 13 is a diagram including an example data flow of a virtual instrument supporting an ultrasound device, according to at least one embodiment. [Figure 41B] FIG. 13 is a diagram including an example data flow of a virtual instrument supporting a CT scanner, according to at least one embodiment. [Figure 42A] FIG. 1 is a data flow diagram of a process for training a machine learning model, according to at least one embodiment. [Figure 42B]FIG. 1 illustrates an example client-server architecture for extending annotation tools with pre-trained annotation models, according to at least one embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0006] FIG. 1 illustrates an example of implementing a recurrent neural network, according to at least one embodiment.

[0007] In at least one embodiment, an example process 100 for executing a recurrent neural network includes utilization of an application programming interface. In at least one embodiment, the graph-based application programming interface includes functions for defining a graph to represent the neural network structure. In at least one embodiment, tensors and operations that operate on these tensors are added to the graph. In at least one embodiment, example operations include operations such as convolution, generalized matrix multiplication ("GEMM"), point-wise operations, and activation. In at least one embodiment, one or more tensors associated with the graph definition are marked as input tensors. In at least one embodiment, one or more tensors associated with the graph definition are marked as output tensors.

[0008] In at least one embodiment, the application programming interface includes functions for defining nested graphs. In an embodiment, a graph can be added to another graph using functions of the programming interface.

[0009] In at least one embodiment, a graph comprises nodes and associated edges. In at least one embodiment, the nodes are associated with operations and tensors. In at least one embodiment, the operations include operations such as convolution, generalized matrix multiplication ("GEMM"), point-wise operations, and activation. In at least one embodiment, the tensors represent data referenced by one or more operations. In at least one embodiment, edges associated with graph nodes correspond to data flows between nodes.

[0010] In at least one embodiment, a graph is created to represent a recursive neural network by associating a recursion attribute 110 with the graph. In at least one embodiment, the graph is a nested graph. In at least one embodiment, associating the recursion property with the graph effectively makes the graph recursive or looping over the attributes of the graph. In at least one embodiment, the use of the recursion property in an application programming interface provides a technical advantage over the use of a while loop, or similar programming construct, which may require the construction of separate graphs to represent the header, body, and exit portions of the while loop.

[0011] In at least one embodiment, the recursion attribute is associated with a trip count that may represent a number of iterations to perform. In at least one embodiment, the trip count includes at least one of a scalar value or a scalar tensor. In at least one embodiment, the application programming interface takes a scalar tensor and registers it as a loop count for the recursive graph. In at least one embodiment, if the trip count is represented as an immutable value, such as a scalar integer or a scalar tensor of an immutable integer type, the trip count at compile time is used to determine the number of iterations of the associated recursive graph.

[0012] In at least one embodiment, to support variable length recurrent neural networks, the application programming interface takes a tensor whose value is calculated after every iteration. In at least one embodiment, a Boolean tensor is used. In at least one embodiment, if the tensor evaluates to true, another iteration occurs, and if false, evaluation of the associated loop ends. In at least one embodiment, the tensor is represented as a control tensor.

[0013] In at least one embodiment, the trip count is not explicitly specified. In at least one embodiment, the trip count for a recursive graph is assumed to be equal to the outer dimension of the input sequence to the recursive graph.

[0014] In at least one embodiment, an example process 100 for implementing a recurrent neural network comprises a definition phase 102 and an execution phase 104 .

[0015] In an embodiment, the example process 100 includes a definition phase 102 in which one or more graphs are defined. In at least one embodiment, the graph comprises one or more of an input layer 104, a hidden layer 106, and an output layer 108. In at least one embodiment, any one of the input layer 104, the hidden layer 106, and the output layer 108 constitutes a graph. In at least one embodiment, a recurrent attribute 110 is associated with the graph. In at least one embodiment, the recurrent attribute 110 is associated with a trip count.

[0016] In an embodiment, the example process 100 includes an execution phase 104. In at least one embodiment, a recurrent neural network takes a sequence of inputs, where an element t of the input sequence is used in a corresponding iteration t of a corresponding graph. Execution of the graph may generate a corresponding sequence of outputs, including the output produced by the final iteration.

[0017] In at least one embodiment, an iteration attribute is associated with a tensor to indicate an association with an iteration of a recursive graph. In at least one embodiment, the association with an iteration attribute indicates that access to a tensor is limited, at a given iteration, to a slice corresponding to said iteration. In at least one embodiment, a slice associated with an iteration corresponds to a slice defined by a fixed outer dimension, such slice being defined by an element t of said outer dimension during iteration t. In at least one embodiment, the limitation on access is such that the embodiment does not allow, based on limitations imposed by the application programming interface and / or compiler of the embodiment, to read or write elements that do not match the current iteration index. In at least one embodiment, access to other elements is allowed, but is controlled or otherwise limited. In at least one embodiment, immutable offsets are allowed. For example, in at least one embodiment, immutable offsets are specified via an application programming interface and are interpreted as allowing access to data from a previous iteration.

[0018] In at least one embodiment, the repeat attribute may indicate the direction of the repeat, such as forward or reverse. In at least one embodiment, the repeat attribute may be associated with a transpose attribute.

[0019] In at least one embodiment, a recurrent neural network is associated with recurrent data. For example, a recurrent neural network may have hidden states, and a long short-term memory (LSTM) may have additional cell states. In at least one embodiment, the recurrent data is typically read at iteration t, updated with new values ​​in this same iteration, and read again at iteration t+1. In at least one embodiment, the recurrent data tensors are marked as input or live-in to identify them as associated with hidden or cell states.

[0020] In at least one embodiment, the compiler identifies output data. In at least one embodiment, the recurrent tensor is not an output for the recurrent graph, but instead is only an output across iterations. For example, the cell states of some LSTM's may be stored in a recurrent tensor that serves as an output across iterations, but is not an output for the recurrent graph.

[0021] In at least one embodiment, the execution phase 104 includes unrolling the defined recurrent neural network 120 into corresponding neural networks 122, 124, 126 where the inputs to the network are based on the outputs of a previous network. In at least one embodiment, the execution phase 104 includes evaluation of a first unrolled neural network 122 based on an initial set of inputs to generate outputs that are fed to a subsequent neural network 124. The outputs from this neural network 124 are then fed as inputs to a subsequent neural network 126, and so on, until the requisite number of iterations has been completed.

[0022] FIG. 2 illustrates an example application programming interface 200 for defining and executing recurrent neural networks using the application programming interface, according to at least one embodiment.

[0023] In at least one embodiment, source code 202 includes calls to functions defined by an application programming interface for implementing a recurrent neural network. In at least one embodiment, source code 202 references an API definition 204. In at least one embodiment, API definition 204 may include additional source code, such as header files or other files or metadata, that may provide definitions of associated application programming interface functions.

[0024] In at least one embodiment, the API definition 204 comprises one or more of functions such as graph_create, create_operation, create_sensor, set_graph, set_recurrent, set_recurrent_count_tensor, and set_recurrent_control_tensor, set_input, and set_output.

[0025] In at least one embodiment, lexical and semantic analysis 206 is performed by a compiler to generate an intermediate representation 208 of the instructions defined by the source code 202. In at least one embodiment, the intermediate representation 208 represents the corresponding source code 202 in a format that facilitates subsequent translation into executable instructions 214.

[0026] In at least one embodiment, the compiler optimizes the intermediate representation 208 to generate an optimized representation 210. In at least one embodiment, the optimized representation 210 represents a functional equivalent of a program described by the corresponding source code 202, but that has been rearranged or restructured to improve performance. In at least one embodiment, the optimizations include one or more of loop fusion, loop splitting, loop unrolling, data flow analysis, parallelization, auto-vectorization, and the like. These examples are intended to be illustrative and thus should not be construed as limiting the scope of any potential embodiments to those that include the specific examples provided.

[0027] In at least one embodiment, a compiler generates executable instructions 214 from optimized representation 210. In at least one embodiment, the compiler also generates executable instructions 214 that are based on or include those defined in API library 212. In at least one embodiment, API library 212 comprises intermediate or executable instructions that implement functions described in API definition 204.

[0028] In at least one embodiment, executable instructions 214 are executed by a compatible computing system. In at least one embodiment, execution of executable instructions 214 results in the definition and evaluation of a recurrent neural network according to instructions provided in source code 202. In at least one embodiment, the evaluation is optimized based on various techniques just described with respect to FIG.

[0029] 3 illustrates an example 300 of restricted access to tensors during execution of a recurrent neural network, according to at least one embodiment. In at least one embodiment, in example 310, a recurrent neural network is executed based on a graph defined via an embodiment of an application programming interface. In at least one embodiment, the definition includes an association between the graph and a recurrent property and an association with a tensor 302. In at least one embodiment, the tensor 302 is an input tensor. In at least one embodiment, the tensor 302 is at least one of an input tensor, an output tensor, a tensor for storing a hidden state, or a tensor for storing a cell state.

[0030] In at least one embodiment, tensor access constraints 306 are imposed such that access to tensor 302 is limited, at a given iteration, to slice 304 corresponding to the current iteration. For example, in FIG. 3, iteration t of the graph is represented by unrolled neural network 308. During evaluation of unrolled neural network 308, access to tensor 302 is limited to slices 304 corresponding to the outer dimensions of tensor 302, such slices being defined by elements t of said outer dimensions during iteration t. In at least one embodiment, tensor access constraints 306 are imposed by an application programming interface and / or a compiler to prevent reading or writing of elements that do not match the current iteration t. In at least one embodiment, access to other elements is allowed to be limited, for example, by specifying an immutable offset. For example, in at least one embodiment, an immutable offset is specified via an application programming interface and is interpreted to allow access to data from a previous iteration, such as iteration t-1.

[0031] FIG. 4 illustrates an example process for defining and executing a recurrent neural network, according to at least one embodiment. In at least one embodiment, an example 400 for defining and executing a recurrent neural network comprises the elements depicted in FIG. 4. Although depicted as a sequence of steps, the depicted sequence should not be construed as limiting the scope of potential embodiments to only those embodiments conforming to the depicted sequence. For example, depicted steps may be rearranged or performed in parallel, except where logically necessary. In at least some embodiments, certain steps may be omitted. In at least some embodiments, additional steps may be added.

[0032] In at least one embodiment, a graph is defined at 402 such that the structure of the graph corresponds to a neural network. For example, the graph may be defined with nodes that make up the input, hidden, and output layers of the neural network.

[0033] In at least one embodiment, a recursive property is associated with the defined graph at 404. In at least one embodiment, a corresponding trip count is also associated with the defined graph at 404. In at least one embodiment, the trip count comprises a scalar-valued tensor. In at least one embodiment, the defined graph is associated with a control tensor instead of a trip count. In at least one embodiment, neither a trip count nor a control tensor is provided, and instead the trip count is inferred based on the size of an outer dimension of an input tensor.

[0034] In at least one embodiment, at 406, the input and output tensors are associated with the defined graph.

[0035] In at least one embodiment, at 408, scan attributes are associated with the input and output tensors. In at least one embodiment, the association between a tensor and an iteration attribute indicates that access to the tensor is limited, at a given iteration, to the slice corresponding to the iteration. In at least one embodiment, during a given iteration t, access to other slices is allowed, such as slice t-1 or t+1. In at least one embodiment, the access is declared to a compiler, such that the compiler can optimize based on assumptions about which slices of a tensor will be accessed during a given iteration. In at least one embodiment, the scan attributes correspond to or are expressed as iteration attributes.

[0036] In at least one embodiment, the defined neural network is executed as a recurrent neural network based on the provided input / output tensors at 410. In at least one embodiment, the number of iterations for execution of the recurrent neural network is based on the trip count, control tensor, or geometry of the input tensor, as described with respect to element 404.

[0037] 5 illustrates an example embodiment 500 of a bidirectional recurrent neural network implementation, according to at least one embodiment. In at least one embodiment, a bidirectional recurrent neural network connects one or more layers of a unidirectional recurrent neural network with one or more equivalent layers of the recurrent neural network in a reverse direction. In at least one embodiment, a bidirectional recurrent neural network is used in conjunction with applications involving contextual recognition or analysis of sequences in both forward and reverse time directions.

[0038] In at least one embodiment, sequence 502 includes a series of invocations of application programming interface functions, potentially including other functions and operations, and in at least one embodiment, the sequence includes an operation 506 for executing a graph, an operation 508 for inverting a graph, and an operation 510 for executing the inverted graph.

[0039] In at least one embodiment, a compiler detects a sequence 502 that includes operations of executing a graph, inverting the graph, and executing the inverted graph. In at least one embodiment, these operations correspond to a pattern 504 for executing a bidirectional recurrent neural network. In at least one embodiment, a compiler detects pattern 504 and optimizes execution of the bidirectional recurrent neural network based on the detection of pattern 504.

[0040] 6 illustrates an example of an implementation of an incomplete recurrent neural network, according to at least one embodiment. In at least one embodiment, an implementation 600 of an incomplete neural network includes using an input tensor 602 paired with a validity tensor 604.

[0041] In at least one embodiment, an incomplete recurrent neural network is a recurrent neural network in which an input tensor, such as the depicted input tensor 602, has variable sequence lengths for a given batch. For example, in at least one embodiment, each batch 606 of input tensor 602 has sequences 608 of different lengths. Thus, in the example, batch b 1 has sequence length 5, and batch b 2 has sequence length 6, and batch b 3 has sequence length 4, and batch b 4 has a sequence length of 3. In at least one embodiment, elements of the input tensor 602 that exceed the sequence length for a given batch are invalid.

[0042] In at least one embodiment, a validity tensor 604 is associated with the input tensor 602. In at least one embodiment, application programming interface functions are used to provide an input tensor with an associated validity tensor 604 or to associate an existing input tensor with an validity tensor. In at least one embodiment, the functionality provided by the validity tensor 604 is substituted with a function that returns a validity indicator based on batch number and iteration number parameters.

[0043] In at least one embodiment, validity tensor 604 comprises Boolean entries whose values ​​indicate whether the corresponding entry in the input tensor is valid. For example, (b 2 ,t 1 The entries in (b 2 ,t 1 ) is set to true to indicate that the corresponding entry is also valid.2 ,t 6 ) may be set to false to indicate that the corresponding entry in the input tensor 602 is invalid.

[0044] 7 illustrates an example of a running chain of a bidirectional recurrent neural network, according to at least one embodiment. In at least one embodiment, example 700 comprises application of an input sequence "I AM HERE" to a bidirectional recurrent neural network. In at least one embodiment, the bidirectional recurrent neural network is implemented according to the techniques described with respect to the embodiments depicted in FIGS. 5 and 6.

[0045] In at least one embodiment, a forward application of a bidirectional recurrent neural network utilizes a forward input sequence 702, and an inverse application of the bidirectional recurrent neural network utilizes a corresponding inverse input sequence 704. These respectively produce a forward output sequence 706 and an inverse output sequence 708. Concatenation of the forward output sequence 706 and the inverse output sequence 708 produces a bidirectional output sequence 710, as shown in FIG.

[0046] In at least one embodiment, the application programming interface includes a chaining function for combining forward and inverted outputs of the incomplete bidirectional recurrent neural network.

[0047] In at least one embodiment, source code for using an embodiment of the application programming interface to implement an incomplete bidirectional recurrent neural network includes calls to programming language and application programming interface functions to implement a reduce operation, provide a trip count, provide an input tensor and associated iteration attributes, implement a select operation, and implement a ensure operation. In at least one embodiment, the reduce operation finds a maximum sequence length in a batch. In at least one embodiment, the ensure operation ensures an order of elements in a tensor to construct the bidirectional recurrent neural network.

[0048] In at least one embodiment, the chaining operation takes a scalar axis as input and indicates the axis to chain along. In at least one embodiment, subsequent inputs to the chaining operation are chained to produce an output tensor. In at least one embodiment, the chaining operation moves elements from an input tensor to an output tensor without performing a calculation on the elements of the input tensor.

[0049] In at least one embodiment, a compiler optimizes performance of chained operations. In at least one embodiment, the optimization includes avoiding data movement by having definitions or views of input tensors that are written to output tensors without copying the underlying data. In at least one embodiment, a location alias relationship is created between the output tensor and the input tensor. In at least one embodiment, a compiler identifies conditions under which chained optimizations may be applied. In at least one embodiment, a compiler identifies conditions under which chained operations may be eliminated. In at least one embodiment, a compiler performs optimizations to eliminate chained operations on outputs of iterations of a recurrent neural network.

[0050] FIG. 8 illustrates an example process for defining and executing a recurrent neural network using an application programming interface, according to at least one embodiment. In at least one embodiment, an example 800 for defining and executing a recurrent neural network comprises the elements depicted in FIG. 8. Although depicted as a sequence of steps, the depicted sequence should not be construed as limiting the scope of potential embodiments to only those embodiments conforming to the depicted sequence. For example, depicted steps may be rearranged or performed in parallel, except where logically necessary. In at least some embodiments, certain steps may be omitted. In at least some embodiments, additional steps may be added.

[0051] In at least one embodiment, an application programming interface receives one or more API calls including a graph definition and a recursion attribute at 802. In at least one embodiment, the API calls correspond to function calls.

[0052] In at least one embodiment, the one or more API calls are received by a declaration or invocation of the API calls in source code, in at least one embodiment, the API calls are received by execution of code to invoke the API calls, in at least one embodiment, the API calls are received by a runtime library that implements API functions corresponding to the one or more API calls.

[0053] In at least one embodiment, the one or more API calls include an API call to associate the graph with a recursive attribute.

[0054] In at least one embodiment, the one or more API calls include an API call to set a trip count.

[0055] In at least one embodiment, the one or more API calls include an API call to set a control tensor.

[0056] In at least one embodiment, the effects of executing functions of the API for defining and executing recurrent neural networks are localized to the function's respective environment. In at least one embodiment, this restriction on the effects can be described as conforming to a functional programming paradigm. In at least one embodiment, a compiler bases optimizations of the execution of the recurrent neural network on assumptions imposed by this restriction on the effects.

[0057] In at least one embodiment, an application programming interface receives one or more API calls to associate tensors with a graph at 804. In at least one embodiment, an input tensor is associated with the graph. In at least one embodiment, an input / output tensor is associated with the graph.

[0058] In at least one embodiment, a tensor corresponds to a one-dimensional, two-dimensional, three-dimensional, or n-dimensional array. In at least one embodiment, one or more of the input data, hidden outputs, hidden inputs, cell states, hidden states, and output data are stored in a tensor.

[0059] In at least one embodiment, the application programming interface assumes that access to the tensor is limited to a particular slice during each iteration for purposes of compilation and optimization at 806. In at least one embodiment, a recurrent neural network is executed based at least in part on the tensor, and access to the tensor is limited to a slice of the tensor corresponding to the iteration during an iteration of execution of the recurrent neural network. In at least one embodiment, the slice of the tensor assumed to be accessible by the compiler is advanced after each iteration.

[0060] In at least one embodiment, at 808, the application programming interface generates optimized instructions for executing the recurrent neural network based on the graph definition. In at least one embodiment, a compiler optimizes the instructions. In at least one embodiment, optimizing the instructions includes minimizing consumption of computational capacity or resources, such as processor time or memory, used while executing the recurrent neural network. In at least one embodiment, optimizing the instructions includes minimizing the time required to execute the recurrent neural network.

[0061] In at least one embodiment, execution of a recurrent neural network is optimized over multiple iterations. In at least one embodiment, the execution optimization is based at least in part on a compiler assumption that accesses to tensors are limited to slices of the tensors during an iteration of execution. In at least one embodiment, this assumption enables the compiler to perform optimizations such as loop fusion, loop splitting, loop unrolling, data flow analysis, parallelization, and auto-vectorization.

[0062] In at least one embodiment, the application programming interface executes the recurrent neural network at 810. In at least one embodiment, executing the recurrent neural network includes evaluating the recurrent neural network according to the received API calls.

[0063] In at least one embodiment, the application programming interface, when implemented by one or more processors, causes the one or more processors to determine that the recurrent neural network is a bidirectional recurrent neural network and optimize performance of the bidirectional recurrent neural network based at least in part on detecting the ability to invert a graph.

[0064] In at least one embodiment, the application programming interface, when executed by the one or more processors, causes the one or more processors to execute the incomplete recurrent neural network. In at least one embodiment, an API call is received to associate the recurrent neural network with a significance tensor, as depicted in FIG.

[0065] In at least one embodiment, the application programming interface, when executed by one or more processors, causes the one or more processors to execute a bidirectional incomplete recurrent neural network. In at least one embodiment, an API call is received to associate the recurrent neural network with a validity tensor, as depicted in Figure 6. In at least one embodiment, the chaining operations are optimized using a technique consistent with that depicted in Figure 7 to minimize data movement.

[0066] Logic of inference and training 9A illustrates inference and / or training logic 915 that may be used to perform inference and / or training operations for one or more embodiments. More details regarding inference and / or training logic 915 are provided below in conjunction with FIGs. 9A and / or 9B.

[0067] In at least one embodiment, the inference and / or training logic 915 may include, without limitation, code and / or data storage 901 for storing forward and / or output weights, and / or input / output data, and / or other parameters for configuring neurons or layers of a neural network that are trained and / or used to infer in one or more aspects of the embodiment. In at least one embodiment, the training logic 915 may include or be coupled to code and / or data storage 901 for storing graph code or other software for controlling the timing and / or ordering of the weights and / or other parameter information to configure logic including integer and / or floating point units (collectively arithmetic logic units (ALUs)). In at least one embodiment, code such as graph code loads the weights or other parameter information into a processor ALU based on the architecture of the neural network to which such code corresponds. In at least one embodiment, code and / or data storage 901 stores weight parameters and / or input / output data for each layer of a neural network trained or used in conjunction with one or more embodiments during forward propagation of the input / output data and / or weight parameters during training and / or inference using aspects of one or more embodiments. In at least one embodiment, any portion of code and / or data storage 901 may be included with other on-chip or off-chip data storage, including L1, L2, or L3 caches of a processor, or system memory.

[0068] In at least one embodiment, any portion of the code and / or data storage 901 may be internal or external to one or more processors or other hardware logic devices or circuits. In at least one embodiment, the code and / or code and / or data storage 901 may be cache memory, dynamic randomly addressable memory (“DRAM”), static randomly addressable memory (“SRAM”), non-volatile memory (e.g., flash memory), or other storage. In at least one embodiment, the choice of whether the code and / or code and / or data storage 901 is internal or external to the processor, for example, or includes DRAM, SRAM, flash, or some other type of storage, may depend on the storage available on-chip versus off-chip, the latency requirements of the training and / or inference functions being performed, the batch size of data used in the inference and / or training of the neural network, or any combination of these factors.

[0069] In at least one embodiment, the inference and / or training logic 915 may include, without limitation, code and / or data storage 905 for storing backpropagation and / or output weights and / or input / output data corresponding to neurons or layers of a neural network trained and / or used to infer with one or more aspects of an embodiment. In at least one embodiment, the code and / or data storage 905 stores weight parameters and / or input / output data for each layer of a neural network trained or used in conjunction with one or more embodiments while backpropagating input / output data and / or weight parameters during training and / or inference using one or more aspects of an embodiment. In at least one embodiment, the training logic 915 may include or be coupled to code and / or data storage 905 for storing graph code or other software for controlling the timing and / or sequence into which weights and / or other parameter information are loaded to configure logic including integer and / or floating point units (collectively arithmetic logic units (ALUs)).

[0070] In at least one embodiment, code such as graph code causes the processor ALU to load weights or other parameter information based on the architecture of the neural network to which such code corresponds. In at least one embodiment, any portion of code and / or data storage 905 may be included with other on-chip or off-chip data storage, including L1, L2, or L3 cache of a processor, or system memory. In at least one embodiment, any portion of code and / or data storage 905 may be internal or external to one or more processors, or other hardware logic devices or circuits. In at least one embodiment, code and / or data storage 905 may be cache memory, DRAM, SRAM, non-volatile memory (e.g., flash memory), or other storage. In at least one embodiment, the choice of whether the code and / or data storage 905 is internal or external to the processor, for example, or includes DRAM, SRAM, flash memory, or some other type of storage, may depend on the storage available on-chip versus off-chip, the latency requirements of the training and / or inference functions being performed, the batch size of data used in inference and / or training of the neural network, or any combination of these factors.

[0071] In at least one embodiment, code and / or data storage 901 and code and / or data storage 905 may be separate storage structures. In at least one embodiment, code and / or data storage 901 and code and / or data storage 905 may be combined storage structures. In at least one embodiment, code and / or data storage 901 and code and / or data storage 905 may be partially combined and partially separate. In at least one embodiment, any portion of code and / or data storage 901 and code and / or data storage 905 may be included with other on-chip or off-chip data storage, including a processor's L1, L2, or L3 cache, or system memory.

[0072] In at least one embodiment, the inference and / or training logic 915 may include one or more arithmetic logic units ("ALUs") 910, including, without limitation, integer and / or floating point units, for performing logical and / or arithmetic operations based at least in part on or indicated by the training and / or inference code (e.g., graph code), the results of which may generate activations (e.g., output values ​​from layers or neurons in a neural network) that are stored in activation storage 920 and that are functions of input / output and / or weight parameter data stored in code and / or data storage 901 and / or code and / or data storage 905. In at least one embodiment, the activations stored in activation storage 920 are generated according to linear algebra and / or matrix based calculations performed by ALU 910 in response to executing instructions or other code, where weight values ​​stored in code and / or data storage 905 and / or data 901 are used as operands along with other values, such as bias values, gradient information, momentum values, or other parameters or hyperparameters, any or all of which may be stored in code and / or data storage 905, or code and / or data storage 901, or in another storage, on-chip or off-chip.

[0073] In at least one embodiment, ALU 910 is included within one or more processors or other hardware logic devices or circuits, while in other embodiments ALU 910 may be external to the processors or other hardware logic devices or circuits that use them (e.g., a coprocessor). In at least one embodiment, ALU 910 may be included within an execution unit of a processor, or may be otherwise included within an ALU bank accessible by execution units of a processor, either within the same processor or distributed among different processors of different types (e.g., central processing units, graphics processing units, fixed function units, etc.). In at least one embodiment, code and / or data storage 901, code and / or data storage 905, and activation storage 920 may share a processor or other hardware logic device or circuit, while in other embodiments they may be in different processors or other hardware logic devices or circuits, or some combination of the same processor or other hardware logic device or circuit and different processors or other hardware logic devices or circuits. In at least one embodiment, any portion of activation storage 920 may be included with other on-chip or off-chip data storage, including L1, L2, or L3 caches of the processor, or system memory. Additionally, inference and / or training code may be stored with other code accessible to the processor or other hardware logic or circuitry, and may be fetched and / or processed using the fetch, decode, schedule, execute, retire, and / or other logic circuitry of the processor.

[0074] In at least one embodiment, activation storage 920 may be cache memory, DRAM, SRAM, non-volatile memory (e.g., flash memory), or other storage. In at least one embodiment, activation storage 920 may be fully or partially internal or external to one or more processors or other logic circuits. In at least one embodiment, the choice of whether activation storage 920 is internal or external to a processor, for example, or includes DRAM, SRAM, flash memory, or some other type of storage, may depend on available on-chip versus off-chip storage, latency requirements of the training and / or inference functions being performed, batch sizes of data used in inference and / or training of the neural network, or any combination of these factors.

[0075] In at least one embodiment, the inference and / or training logic 915 shown in Figure 9A may be used in conjunction with an application-specific integrated circuit ("ASIC"), such as a TensorFlow® processing unit from Google, an inference processing unit (IPU) from Graphcore™, or a Nervana® (e.g., "Lake Crest") processor from Intel Corp. In at least one embodiment, the inference and / or training logic 915 shown in Figure 9A may be used in conjunction with other hardware, such as central processing unit ("CPU") hardware, graphics processing unit ("GPU") hardware, or a field programmable gate array ("FPGA").

[0076] FIG. 9B illustrates inference and / or training logic 915 according to at least one embodiment. In at least one embodiment, the inference and / or training logic 915 may include, without limitation, hardware logic in which computational resources are dedicated to or otherwise used only in conjunction with weight values ​​or other information corresponding to one or more layers of neurons in a neural network. In at least one embodiment, the inference and / or training logic 915 illustrated in FIG. 9B may be used in conjunction with an application specific integrated circuit (ASIC), such as a TensorFlow® processing unit from Google, an inference processing unit (IPU) from Graphcore™, or a Nervana® (e.g., “Lake Crest”) processor from Intel Corporation. In at least one embodiment, the inference and / or training logic 915 illustrated in FIG. 9B may be used in conjunction with other hardware, such as central processing unit (CPU) hardware, graphics processing unit ("GPU") hardware, or field programmable gate arrays (FPGAs). In at least one embodiment, the inference and / or training logic 915 may include, without limitation, code and / or data storage 901 and code and / or data storage 905, which may be used to store code (e.g., graph code), weight values, and / or other information including bias values, gradient information, momentum values, and / or other parameter or hyperparameter information. In at least one embodiment shown in FIG. 9B, each of the code and / or data storage 901 and code and / or data storage 905 is associated with dedicated computational resources, such as computational hardware 902 and computational hardware 906, respectively. In at least one embodiment, each of the computational hardware 902 and computational hardware 906 includes one or more ALUs that perform mathematical functions, such as linear algebraic functions, only on the information stored in the code and / or data storage 901 and code and / or data storage 905, respectively, with the results stored in activation storage 920.

[0077] In at least one embodiment, each of the code and / or data storage 901 and 905 and corresponding computational hardware 902 and 906 correspond to a different layer of a neural network, such that activations resulting from one storage / computation pair 901 / 902 with the code and / or data storage 901 and computational hardware 902 are provided as input to a storage / computation pair 905 / 906 with the next code and / or data storage 905 and computational hardware 906 to reflect the conceptual organization of the neural network. In at least one embodiment, the storage / computation pairs 901 / 902 and 905 / 906 may correspond to two or more layers of the neural network. In at least one embodiment, additional storage / computation pairs (not shown) may be included in the inference and / or training logic 915 after or in parallel with the storage / computation pairs 901 / 902 and 905 / 906.

[0078] Training and deployment of neural networks FIG. 10 illustrates training and deployment of a deep neural network, according to at least one embodiment. In at least one embodiment, an untrained neural network 1006 is trained using a training data set 1002. In at least one embodiment, the training framework 1004 is the PyTorch framework, while in other embodiments, the training framework 1004 is TensorFlow, Boost, Caffe, Microsoft Cognitive Toolkit / CNTK, MXNet, Chainer, Keras, Deeplearning4j, or other training frameworks. In at least one embodiment, the training framework 1004 trains the untrained neural network 1006 and enables it to be trained using processing resources described herein to generate a trained neural network 1008. In at least one embodiment, the weights may be selected randomly or by pre-training using a deep belief network. In at least one embodiment, the training may be performed in a supervised, semi-supervised, or unsupervised manner.

[0079] In at least one embodiment, the untrained neural network 1006 is trained using supervised learning, where the training data set 1002 includes inputs paired with desired outputs for the inputs, or the training data set 1002 includes inputs with known outputs and the outputs of the neural network 1006 are manually scored. In at least one embodiment, the untrained neural network 1006 is trained in a supervised manner, processing inputs from the training data set 1002 and comparing the resulting outputs to a set of expected or desired outputs. In at least one embodiment, errors are then back-propagated through the untrained neural network 1006. In at least one embodiment, the training framework 1004 adjusts weights that control the untrained neural network 1006. In at least one embodiment, the training framework 1004 includes tools to monitor how well the untrained neural network 1006 is converging towards a model, such as a trained neural network 1008, suitable for generating correct answers, such as in results 1014, based on input data, such as a new data set 1012. In at least one embodiment, the training framework 1004 iteratively trains the untrained neural network 1006 while adjusting weights to refine the output of the untrained neural network 1006 using a loss function and a tuning algorithm, such as stochastic gradient descent. In at least one embodiment, the training framework 1004 trains the untrained neural network 1006 until it reaches a desired accuracy. In at least one embodiment, the trained neural network 1008 can then be deployed to implement any number of machine learning operations.

[0080] In at least one embodiment, the untrained neural network 1006 is trained using unsupervised learning, where the untrained neural network 1006 attempts to train itself using unlabeled data. In at least one embodiment, the training data set 1002 for unsupervised learning includes input data without any associated output data or "ground truth" data. In at least one embodiment, the untrained neural network 1006 can learn groupings within the training data set 1002 and determine how individual inputs relate to the untrained data set 1002. In at least one embodiment, unsupervised training can be used within the trained neural network 1008 to generate self-organizing maps that can perform operations useful for reducing the dimensionality of the new data set 1012. In at least one embodiment, unsupervised training can also be used to perform anomaly detection, which allows for identifying data points in the new data set 1012 that deviate from normal patterns in the new data set 1012.

[0081] In at least one embodiment, semi-supervised learning may be used, which is a technique in which labeled and unlabeled data are mixed in the training data set 1002. In at least one embodiment, the training framework 1004 may be used to perform incremental learning, such as by transfer learning techniques. In at least one embodiment, incremental learning allows the trained neural network 1008 to adapt to new data sets 1012 without forgetting the knowledge instilled in the trained neural network 1008 during initial training.

[0082] Data Center 11 illustrates an example data center 1100 in which at least one embodiment may be used. In at least one embodiment, the data center 1100 includes a data center infrastructure layer 1110, a framework layer 1120, a software layer 1130, and an application layer 1140.

[0083] As shown in FIG. 11 , in at least one embodiment, a data center infrastructure layer 1110 may include a resource orchestrator 1112, grouped computing resources 1114, and node computing resources (“node CRs”) 1116(1) through 1116(N), where “N” represents a positive integer (and may be a different integer “N” than used in other figures). In at least one embodiment, nodes CR 1116(1)-1116(N) may include, but are not limited to, any number of central processing units ("CPUs") or other processors (including accelerators, field programmable gate arrays (FPGAs), graphics processors, etc.), memory storage devices 1118(1)-1118(N) (e.g., dynamic read-only memory, solid-state storage drives or disk drives), network input / output ("NW I / O") devices, network switches, virtual machines ("VMs"), power modules, and cooling modules. In at least one embodiment, one or more of nodes CR 1116(1)-1116(N) may be a server having one or more of the computing resources described above.

[0084] In at least one embodiment, the grouped computing resources 1114 may include separate groups of node CRs housed in one or more racks (not shown), or multiple racks housed in a data center at various graphical locations (also not shown). In at least one embodiment, the separate groups of node CRs in the grouped computing resources 1114 may include grouped compute resources, network resources, memory resources, or storage resources that may be configured or allocated to support one or more workloads. In at least one embodiment, several node CRs including CPUs or processors may be grouped in one or more racks to provide compute resources to support one or more workloads. In at least one embodiment, the one or more racks may also include any number of power supply modules, cooling modules, and network switches in any combination.

[0085] In at least one embodiment, the resource orchestrator 1112 may configure or otherwise control one or more nodes CR 1116(1)-1116(N) and / or grouped computing resources 1114. In at least one embodiment, the resource orchestrator 1112 may include a software design infrastructure ("SDI") management entity for the data center 1100. In at least one embodiment, the resource orchestrator 912 may include hardware, software, or some combination thereof.

[0086] In at least one embodiment shown in FIG. 11 , framework layer 1120 includes a job scheduler 1122, a configuration manager 1124, a resource manager 1126, and a distributed file system 1128. In at least one embodiment, framework layer 1120 may include a framework for supporting software 1132 in software layer 1130 and / or one or more applications 1142 in application layer 1140. In at least one embodiment, software 1132 or applications 1142 may each include web-based service software or applications, such as those offered by Amazon Web Services, Google Cloud, and Microsoft Azure. In at least one embodiment, framework layer 1120 may be a type of free and open source software web application framework, such as, but not limited to, Apache Spark® (hereinafter “Spark”), which can use distributed file system 1128 for large-scale data processing (e.g., “big data”). In at least one embodiment, the job scheduler 1132 may include a Spark driver to facilitate scheduling of workloads supported by various tiers of the data center 1100. In at least one embodiment, the configuration manager 1124 may be capable of configuring different tiers, such as the software tier 1130, as well as the framework tier 1120 including Spark and a distributed file system 1128 to support large scale data processing. In at least one embodiment, the resource manager 1126 may be capable of managing clustered or grouped computing resources that are mapped or allocated to support the distributed file system 1128 and the job scheduler 1122. In at least one embodiment, the clustered or grouped computing resources may include grouped computing resources 1114 in the data center infrastructure tier 1110.In at least one embodiment, resource manager 1126 may cooperate with resource orchestrator 1112 to manage these mappings or allocated computing resources.

[0087] In at least one embodiment, the software 1132 included in the software layer 1130 may include software used by at least a portion of the nodes CRs 1116(1)-1116(N), the grouped computing resources 1114, and / or the distributed file system 1128 of the framework layer 1120. In at least one embodiment, the one or more types of software may include, but are not limited to, Internet web page searching software, email virus scanning software, database software, and streaming video content software.

[0088] In at least one embodiment, the applications 1142 included in the application layer 1140 may include one or more types of applications used by at least a portion of the nodes CRs 1116(1)-1116(N), the grouped computing resources 1114, and / or the distributed file system 1128 of the framework layer 1120. In at least one embodiment, the one or more types of applications may include, but are not limited to, any number of genomics applications, cognitive compute, and applications including training or inference software, machine learning framework software (e.g., PyTorch, TensorFlow, Caffe, etc.) and machine learning applications, or other machine learning applications used in conjunction with one or more embodiments.

[0089] In at least one embodiment, any of configuration manager 1124, resource manager 1126, and resource orchestrator 1112 may implement any number and type of self-correcting actions based on any amount and type of data obtained in any technically feasible manner. In at least one embodiment, the self-correcting actions may enable data center operators of data center 1100 to avoid determining potentially poor configurations and eliminate underutilized and / or underperforming portions of the data center.

[0090] In at least one embodiment, data center 1100 may include tools, services, software, or other resources for training one or more machine learning models or predicting or inferring information using one or more machine learning models according to one or more embodiments described herein. For example, in at least one embodiment, a machine learning model may be trained by calculating weight parameters according to a neural network architecture using the software and computing resources described above with respect to data center 1100. In at least one embodiment, a trained machine learning model corresponding to one or more neural networks may be used to infer or predict information using the resources described above with respect to data center 1100 by using weight parameters calculated by one or more techniques described herein.

[0091] In at least one embodiment, the data center may use a CPU, application specific integrated circuit (ASIC), GPU, FPGA, or other hardware to perform training and / or inference using the resources described above. Additionally, one or more of the software and / or hardware resources described above may be configured as a service to enable a user to train or perform inference on information, such as image recognition, speech recognition, or other artificial intelligence services.

[0092] Inference and / or training logic 915 is used to perform inference and / or training operations associated with one or more embodiments. More details regarding the inference and / or training logic 915 are provided herein in conjunction with Figures 9A and / or 9B. In at least one embodiment, the inference and / or training logic 915 may be used in the system of Figure 11 for inference or prediction operations based at least in part on weight parameters calculated using neural network training operations, neural network functionality and / or architecture, or neural network use cases described herein.

[0093] In at least one embodiment, an application programming interface is adapted to receive an application programming interface call including a graph definition and a recursion attribute in association with the diagram, and to execute a recursive neural network based on the graph definition.

[0094] Autonomous Vehicles 12A illustrates an example of an autonomous vehicle 1200 according to at least one embodiment. In at least one embodiment, the autonomous vehicle 1200 (alternatively referred to herein as “vehicle 1200”) may be a passenger vehicle, such as, without limitation, a car, truck, bus, and / or another type of vehicle that accommodates one or more passengers. In at least one embodiment, the vehicle 1200 may be a semi-tractor trailer truck for hauling cargo. In at least one embodiment, the vehicle 1200 may be an aircraft, a robotic vehicle, or other type of vehicle.

[0095] Autonomous vehicles may be described in terms of levels of automation as defined by the National Highway Traffic Safety Administration ("NHTSA"), a division of the U.S. Department of Transportation, and the Society of Automotive Engineers' ("SAE") "Taxonomy and Definitions for Terms Related to Driving Automation Systems for On-Road Motor Vehicles" (e.g., Standard No. J3016-201806, issued June 15, 2018, Standard No. J3016-201609, issued September 30, 2016, and previous and new versions of this standard). In one or more embodiments, vehicle 1200 may be capable of functionality according to one or more of autonomous driving levels 1 through 5. For example, in at least one embodiment, vehicle 1200 may be capable of conditional automation (Level 3), high automation (Level 4), and / or full automation (Level 5), depending on the embodiment.

[0096] In at least one embodiment, the vehicle 1200 may include components such as, without limitation, a chassis, a vehicle body, wheels (2, 4, 6, 8, 18, etc.), tires, axles, and other vehicle components. In at least one embodiment, the vehicle 1200 may include a propulsion system 1250 such as, without limitation, an internal combustion engine, a hybrid power plant, a fully electric engine, and / or another type of propulsion system. In at least one embodiment, the propulsion system 1250 may be coupled to a drive train of the vehicle 1200, which may include, without limitation, a transmission to enable propulsion of the vehicle 1200. In at least one embodiment, the propulsion system 1250 may be controlled in response to receiving a signal from a throttle / accelerator 1252.

[0097] In at least one embodiment, steering system 1254, which may include without limitation a steering wheel, is used to steer vehicle 1200 (e.g., along a desired path or route) when propulsion system 1250 is operating (e.g., when vehicle 1200 is moving). In at least one embodiment, steering system 1254 may receive signals from steering actuator 1256. In at least one embodiment, the steering wheel may be optional for fully automated (Level 5) functionality. In at least one embodiment, brake sensor system 1246 may be used to operate vehicle brakes in response to receiving signals from brake actuator 1248 and / or brake sensor.

[0098] In at least one embodiment, controller 1236, which may include without limitation one or more system on chip ("SoC") (not shown in FIG. 12A) and / or graphics processing unit ("GPU"), provides signals (e.g., representing commands) to one or more components and / or systems of vehicle 1200. For example, in at least one embodiment, controller 1236 may send signals to operate vehicle brakes via brake actuator 1248, to operate steering system 1254 via steering actuator 1256, and to operate propulsion system 1250 via throttle / accelerator 1252. In at least one embodiment, controller 1236 may include one or more on-board (e.g., integrated) computing devices (e.g., supercomputers) that process sensor signals and output operational commands (e.g., signals representing commands) to enable autonomous driving and / or assist a human driver in driving vehicle 1200. In at least one embodiment, controller 1236 may include a first controller for autonomous driving functions, a second controller for functional safety functions, a third controller for artificial intelligence functions (e.g., computer vision), a fourth controller for infotainment functions, a fifth controller for redundancy in emergency situations, and / or other controllers. In at least one embodiment, a single controller may handle two or more of the above functionalities, two or more controllers may handle a single functionality, and / or some combination thereof.

[0099] In at least one embodiment, controller 1236 provides signals to control one or more components and / or systems of vehicle 1200 in response to sensor data (e.g., sensor inputs) received from one or more sensors. In at least one embodiment, sensor data may be received from, for example, without limitation, global navigation satellite system ("GNSS") sensors 1258 (e.g., global positioning system sensors), RADAR sensors 1260, ultrasonic sensors 1262, LIDAR sensors 1264, inertial measurement units ("IMUs"), or other sensors. 12A ), a long-range camera (not shown in FIG. 12A ), a mid-range camera (not shown in FIG. 12A ), a speed sensor 1244 (e.g., for measuring the speed of the vehicle 1200), a vibration sensor 1242, a steering sensor 1240, a brake sensor (e.g., as part of a brake sensor system 1246), and / or other types of sensors.

[0100] In at least one embodiment, one or more of the controllers 1236 may receive input (e.g., represented by input data) from the instrument cluster 1232 of the vehicle 1200 and provide output (e.g., represented by output data, display data, etc.) via a human-machine interface ("HMI") display 1234, an audible annunciator, a loudspeaker, and / or via other components of the vehicle 1200. In at least one embodiment, the output may include information such as vehicle speed, speed, time, map data (e.g., a high definition map (not shown in FIG. 12A )), location data (e.g., location of the vehicle 1200 on a map, etc.), direction, locations of other vehicles (e.g., occupancy grid), information about objects and object conditions sensed by the controller 1236, etc. For example, in at least one embodiment, the HMI display 1234 may display information about the presence of one or more objects (e.g., road signs, warning signs, traffic light changes, etc.) and / or information about a driving maneuver that the vehicle has performed, is performing, or will perform (e.g., currently changing lanes, exiting at exit 34B in 2 miles, etc.).

[0101] In at least one embodiment, vehicle 1200 further includes a network interface 1224, which may use a wireless antenna 1226 and / or a modem for communicating over one or more networks. For example, in at least one embodiment, network interface 1224 may be capable of communicating over a Long-Term Evolution ("LTE"), Wideband Code Division Multiple Access ("WCDMA"), Universal Mobile Telecommunications System ("UMTS"), Global System for Mobile communications ("GSM"), IMT-CDMA Multi-Carrier ("CDMA2000") network, etc. Additionally, in at least one embodiment, the wireless antenna 1226 may enable communication between objects in the environment (e.g., vehicles, mobile devices, etc.) using local area network ("LE") protocols such as Bluetooth, Bluetooth Low Energy ("Z"), Z-Wave, ZigBee, etc., and / or low power wide-area network ("LPWAN") protocols such as LoRaWAN, SigFox, etc.

[0102] Inference and / or training logic 915 is used to perform inference and / or training operations associated with one or more embodiments. More details regarding the inference and / or training logic 915 are provided herein in conjunction with Figures 9A and / or 9B. In at least one embodiment, the inference and / or training logic 915 may be used in the system of Figure 12A for inference or prediction operations based at least in part on weight parameters calculated using neural network training operations, neural network functionality and / or architecture, or neural network use cases described herein.

[0103] In at least one embodiment, an application programming interface is adapted to receive an application programming interface call including a graph definition and a recursion attribute in association with the diagram, and to execute a recursive neural network based on the graph definition.

[0104] 12B illustrates example camera locations and fields of view for the autonomous vehicle 1200 of FIG. 12A according to at least one embodiment. In at least one embodiment, the cameras and their respective fields of view are an example implementation and are not limiting. For example, in at least one embodiment, additional and / or alternative cameras may be included and / or cameras may be positioned at different locations on the vehicle 1200.

[0105] In at least one embodiment, the camera type may include, but is not limited to, a digital camera that may be adapted for use with components and / or systems of vehicle 1200. In at least one embodiment, the camera may operate at automotive safety integrity level ("ASIL") B and / or another ASIL. In at least one embodiment, the camera type may be capable of any image capture rate, such as 60 frames per second (fps), 1220 fps, 240 fps, etc., depending on the embodiment. In at least one embodiment, the camera may be capable of using a rolling shutter, a global shutter, another type of shutter, or a combination thereof. In at least one embodiment, the color filter array may include a red, clear, clear, clear ("RCCC") color filter array, a red, clear, clear, blue ("RCCB") color filter array, a red, blue, green, clear ("RBGC") color filter array, a Foveon X3 color filter array, a Bayer sensor (RGGB) color filter array, a monochrome sensor color filter array, and / or another type of color filter array. In at least one embodiment, a clear pixel camera may be used, such as a camera having a RCCC, RCCB, and / or RBGC color filter array, to increase light sensitivity.

[0106] In at least one embodiment, one or more of the cameras may be used to perform advanced driver assistance systems ("ADAS") functions (e.g., as part of a redundant or fail-safe design). For example, in at least one embodiment, a multi-function mono camera may be installed to provide functions including lane departure warning, traffic sign assist, and intelligent headlight control. In at least one embodiment, one or more of the cameras (e.g., all of the cameras) may simultaneously record and provide image data (e.g., video).

[0107] In at least one embodiment, the camera or cameras may be mounted on a mounting assembly, such as a custom designed (e.g., three-dimensional ("3D") printed) assembly, to eliminate stray light and reflections from inside the vehicle 1200 (e.g., reflections reflected from the dashboard onto the windshield) that may interfere with the camera's image data capture capabilities. With reference to a door mirror mounting assembly, in at least one embodiment, the door mirror assembly may be custom 3D printed such that the camera mounting plate conforms to the shape of the door mirror. In at least one embodiment, the camera may be integral with the door mirror. For side view cameras, in at least one embodiment, the cameras may again be integrated into the four pillars at each corner of the cabin.

[0108] In at least one embodiment, a camera (e.g., a front-facing camera) having a field of view that includes a portion of the environment in front of the vehicle 1200 may be used for a surrounding view to help identify the path and obstacles ahead, and may be used in conjunction with the controller 1236 and / or one or more of the control SoCs to assist in generating an occupancy grid and / or providing information essential to determining a preferred vehicle path. In at least one embodiment, the front-facing camera may be used to perform many of the ADAS functions similar to LIDAR, including, without limitation, emergency braking, pedestrian detection, and collision avoidance. In at least one embodiment, the front-facing camera may also be used for ADAS functions and systems, including, without limitation, Lane Departure Warnings ("LDW"), Autonomous Cruise Control ("ACC"), and / or other functions such as traffic sign recognition.

[0109] In at least one embodiment, a variety of cameras may be used in a front-facing configuration, including, for example, a monocular camera platform including a complementary metal oxide semiconductor (CMOS) color imager. In at least one embodiment, a wide-angle camera 1270 may be used to sense objects (e.g., pedestrians, cross traffic, or bicycles) coming into view from the surroundings. Although only one wide-angle camera 1270 is shown in FIG. 12B, in other embodiments, there may be any number (including zero) of wide-angle cameras on the vehicle 1200. In at least one embodiment, any number of long-range cameras 1298 (e.g., a pair of long-range view stereo cameras) may be used for depth-based object detection, especially for objects for which a neural network has not yet been trained. In at least one embodiment, the long-range cameras 1298 may also be used for object detection and classification, as well as basic object tracking.

[0110] In at least one embodiment, any number of stereo cameras 1268 may also be included in a front-facing configuration. In at least one embodiment, one or more of the stereo cameras 1268 may include an integrated control unit with a scalable processing unit, which may provide a programmable logic ("FPGA") and a multi-core microprocessor with an integrated controller area network ("CAN") or Ethernet interface on a single chip. In at least one embodiment, such a unit may be used to generate a 3D map of the vehicle's 1200 environment, including distance estimates for all points in the image. In at least one embodiment, one or more of the stereo cameras 1268 may include, without limitation, a compact stereo vision sensor, which may include, without limitation, two camera lenses (one on the left and one on the right) and an image processing chip that can measure distances from the vehicle 1200 to target objects and use the generated information (e.g., metadata) to activate autonomous emergency braking and lane departure warning features. In at least one embodiment, other types of stereo cameras 1268 may be used in addition to or instead of those described herein.

[0111] In at least one embodiment, a camera having a field of view that includes a portion of the environment to the side of the vehicle 1200 (e.g., a side view camera) may be used for a view of the surroundings to provide information used for creating and updating the occupancy grid and generating side collision warnings. For example, in at least one embodiment, surrounding cameras 1274 (e.g., four surrounding cameras as shown in FIG. 12B ) may be disposed on the vehicle 1200. In at least one embodiment, the surrounding cameras 1274 may include, without limitation, any number and combination of wide-angle cameras, fisheye cameras, 360-degree cameras, and / or the like. For example, in at least one embodiment, four fisheye cameras may be disposed in front, behind, and on the sides of the vehicle 1200. In at least one embodiment, the vehicle 1200 may use three surrounding cameras 1274 (e.g., left, right, and rear) and may utilize one or more other cameras (e.g., a front camera) as a fourth surrounding camera.

[0112] In at least one embodiment, a camera having a field of view that includes a portion of the environment behind the vehicle 1200 (e.g., a rear view camera) may be used for parking assistance, surrounding view, rear collision warning, and to create and update the occupancy grid. In at least one embodiment, a wide variety of cameras may be used, including, but not limited to, cameras suitable as front cameras as described herein (e.g., long-range camera 1298, and / or mid-range camera 1276, stereo camera 1268, infrared camera 1272, etc.).

[0113] Inference and / or training logic 915 is used to perform inference and / or training operations associated with one or more embodiments. More details regarding the inference and / or training logic 915 are provided herein in conjunction with Figures 9A and / or 9B. In at least one embodiment, the inference and / or training logic 915 may be used in the system of Figure 12B for inference or prediction operations based at least in part on weight parameters calculated using neural network training operations, neural network functionality and / or architecture, or neural network use cases described herein.

[0114] In at least one embodiment, an application programming interface is adapted to receive an application programming interface call including a graph definition and a recursion attribute in association with the diagram, and to execute a recursive neural network based on the graph definition.

[0115] FIG. 12C is a block diagram illustrating an example system architecture of the autonomous vehicle 1200 of FIG. 12A according to at least one embodiment. In at least one embodiment, each of the components, features, and systems of the vehicle 1200 of FIG. 12C is shown as being connected via a bus 1202. In at least one embodiment, the bus 1202 may include, without limitation, a CAN data interface (alternatively referred to herein as a (CAN bus)). In at least one embodiment, the CAN may be a network internal to the vehicle 1200 that is used to help control various features and functions of the vehicle 1200, such as brake application, acceleration, brake control, steering, windshield wipers, etc. In at least one embodiment, the bus 1202 may be configured to have dozens or even hundreds of nodes, each with its own unique identifier (e.g., a CAN ID). In at least one embodiment, the bus 1202 may be read to find steering wheel angle, ground speed, engine revolutions per minute ("RPM"), button position, and / or other vehicle status indicators. In at least one embodiment, bus 1202 may be an ASIL B compliant CAN bus.

[0116] In at least one embodiment, FlexRay and / or Ethernet protocols may be used in addition to or instead of CAN. In at least one embodiment, there may be any number of buses forming bus 1202, including, without limitation, zero or more CAN buses, zero or more FlexRay buses, zero or more Ethernet buses, and / or zero or more other types of buses using other protocols. In at least one embodiment, two or more buses may be used to perform different functions and / or provide redundancy. For example, a first bus may be used for collision avoidance functions and a second bus may be used for actuation control. In at least one embodiment, each bus of bus 1202 may communicate with any of the components of vehicle 1200, and two or more of buses of bus 1202 may communicate with corresponding components. In at least one embodiment, each of any number of systems-on-chip (“SoC”) 1204 (e.g., SoC 1204(A) and SoC 1204(B)), each of the controllers 1236, and / or each computer in the vehicle may have access to the same input data (e.g., input from sensors in vehicle 1200) and may be connected to a common bus, such as a CAN bus.

[0117] In at least one embodiment, vehicle 1200 may include one or more controllers 1236, such as those described herein with respect to FIGURE 12A. In at least one embodiment, controller 1236 may be used for a variety of functions. In at least one embodiment, controller 1236 may be coupled to any of a variety of other components and systems of vehicle 1200 and may be used to control vehicle 1200, artificial intelligence of vehicle 1200, infotainment and / or other functions of vehicle 1200.

[0118] In at least one embodiment, vehicle 1200 may include any number of SoCs 1204. In at least one embodiment, each of SoCs 1204 may include, without limitation, a central processing unit ("CPU") 1206, a graphics processing unit ("GPU") 1208, a processor 1210, a cache 1212, an accelerator 1214, a data store 1216, and / or other components and features not shown. In at least one embodiment, SoCs 1204 may be used to control vehicle 1200 in a variety of platforms and systems. For example, in at least one embodiment, SoC 1204 may be incorporated into a system (e.g., that of vehicle 1200) having a high definition ("HD") map 1222 that can obtain map refreshes and / or updates via a network interface 1224 from one or more servers (not shown in FIG. 12C ).

[0119] In at least one embodiment, CPU 1206 may include a CPU cluster, or CPU complex (alternatively referred to herein as a “CCPLEX”). In at least one embodiment, CPU 1206 may include multiple cores and / or level 2 (“L2”) caches. For example, in at least one embodiment, CPU 1206 may include eight cores in a coherent multiprocessor configuration. In at least one embodiment, CPU 1206 may include four dual-core clusters, where each cluster has a dedicated L2 cache (e.g., 2 megabytes (MB) of L2 cache). In at least one embodiment, CPU 1206 (e.g., CCPLEX) may be configured to support simultaneous cluster operation allowing any combination of clusters of CPU 1206 to be active at any given time.

[0120] In at least one embodiment, one or more of the CPUs 1206 may implement power management features including, without limitation, one or more of the following features: individual hardware blocks may be automatically clock gated when idle to conserve dynamic power; each core clock may be gated when the core is not actively executing instructions due to execution of a Wait for Interrupt ("WFI") / Wait for Event ("WFE") instruction; each core may be independently power gated; each core cluster may be independently clock gated when all cores are clock gated or power gated; and / or each core cluster may be independently power gated when all cores are power gated. In at least one embodiment, the CPUs 1206 may further implement an advanced algorithm for managing power states, where, given allowed power states and expected wake-up times, the hardware / microcode determines what is the best power state for the cores, clusters, and CCPLEXes to enter. In at least one embodiment, a processing core may support in software a simple sequence of entering power states with work offloaded to microcode.

[0121] In at least one embodiment, GPU 1208 may include an integrated GPU (alternatively referred to herein as an “iGPU”). In at least one embodiment, GPU 1208 may be programmable and efficient for parallel workloads. In at least one embodiment, GPU 1208 may use an extended tensor instruction set. In one embodiment, GPU 1208 may include one or more streaming microprocessors, where each streaming microprocessor may include a level 1 (“L1”) cache (e.g., an L1 cache having at least 96 KB of storage capacity) and two or more streaming microprocessors may share an L2 cache (e.g., an L2 cache having 512 KB of storage capacity). In at least one embodiment, GPU 1208 may include at least eight streaming microprocessors. In at least one embodiment, GPU 1208 may use a compute application programming interface (API). In at least one embodiment, the GPU 1208 may use one or more parallel computing platforms and / or programming modules (e.g., NVIDIA's CUDA model).

[0122] In at least one embodiment, one or more of the GPUs 1208 may be power optimized for best performance in automotive and embedded use cases. For example, in one embodiment, the GPUs 1208 may be fabricated on Fin field-effect transistor ("FinFET") circuitry. In at least one embodiment, each streaming microprocessor may incorporate multiple mixed-precision processing cores partitioned into multiple blocks. For example, without limitation, 64 PF32 cores and 32 PF64 cores may be partitioned into four processing blocks. In at least one embodiment, each processing block may be allocated 16 FP32 cores, 8 FP64 cores, 16 INT32 cores, two mixed-precision NVIDIA Tensor cores for deep learning matrix operations, a level-zero ("L0") instruction cache, a warp scheduler, a dispatch unit, and / or a 64KB register file. In at least one embodiment, the streaming microprocessor includes independent parallel integer and floating point data paths to achieve efficient execution of workloads by mixing computation and addressing calculations. In at least one embodiment, the streaming microprocessor may include independent thread scheduling to allow finer grained synchronization and coordination between parallel threads. In at least one embodiment, the streaming microprocessor may include a combination of an L1 data cache and a shared memory unit to improve performance while simplifying programming.

[0123] In at least one embodiment, one or more of the GPUs 1208 may include high bandwidth memory ("HBM") and / or a 16 GB HBM2 memory subsystem, providing, in some examples, a peak memory bandwidth of approximately 900 GB / sec. In at least one embodiment, synchronous graphics random-access memory ("SGRAM"), such as graphics double data rate type five ("GDDR5"), may be used in addition to or in place of the HBM memory.

[0124] In at least one embodiment, the GPU 1208 may include unified memory technology. In at least one embodiment, address translation services ("ATS") support may be used to allow the GPU 1208 to directly access the page tables of the CPU 1206. In at least one embodiment, an address translation request may be sent to the CPU 1206 when the GPU in the GPU 1208 memory management unit ("MMU") experiences a miss. In at least one embodiment, in response, two of the CPUs 1206 may look up the virtual-to-physical address mapping in their own page tables and send the translation back to the GPU 1208. In at least one embodiment, the unified memory technology allows for a single unified virtual address space for both the CPU 1206 and the GPU 1208 memory, thereby simplifying programming the GPU 1208 and porting applications to the GPU 1208.

[0125] In at least one embodiment, the GPU 1208 may include any number of access counters that can record the frequency of accesses of the GPU 1208 to the memory of other processors. In at least one embodiment, the access counters may help ensure that memory pages are moved to the physical memory of the processor that is accessing the pages most frequently, thereby improving the efficiency of memory ranges shared between processors.

[0126] In at least one embodiment, one or more of the SoCs 1204 may include any number of caches 1212, including those described herein. For example, in at least one embodiment, the caches 1212 may include a level 3 ("L3") cache available to both the CPU 1206 and the GPU 1208 (e.g., connected to both the CPU 1206 and the GPU 1208). In at least one embodiment, the caches 1212 may include a write-back cache that can record line state by using a cache coherence protocol or the like (e.g., MEI, MESI, MSI, etc.). In at least one embodiment, the L3 cache may include 4 MB of memory or more, depending on the embodiment, although smaller cache sizes may be used.

[0127] In at least one embodiment, one or more of the SoCs 1204 may include one or more accelerators 1214 (e.g., hardware accelerators, software accelerators, or a combination thereof). In at least one embodiment, the SoCs 1204 may include a hardware acceleration cluster, which may include optimized hardware accelerators and / or large on-chip memory. In at least one embodiment, the large on-chip memory (e.g., 4MB of SRAM) may enable the hardware acceleration cluster to accelerate neural networks and other calculations. In at least one embodiment, the hardware acceleration cluster may be used to complement the GPU 1208 and offload some of the GPU 1208's tasks (e.g., freeing up more cycles for the GPU 1208 to perform other tasks). In at least one embodiment, accelerator 1214 may be used for target workloads that are stable enough to accommodate acceleration (e.g., perception, convolutional neural networks ("CNNs"), recurrent neural networks ("RNNs"), etc.). In at least one embodiment, CNNs may include region-based or regional convolutional neural networks ("RCNNs"), and Fast RCNNs (e.g., used for object detection), or other types of CNNs.

[0128] In at least one embodiment, the accelerator 1214 (e.g., a hardware accelerated cluster) may include one or more deep learning accelerators ("DLAs"). In at least one embodiment, the DLAs may include, without limitation, one or more tensor processing units ("TPUs"), which may be further configured to provide tens of trillion operations per second for deep learning applications and inference. In at least one embodiment, the TPUs may be accelerators configured and optimized to perform image processing functions (e.g., CNN, RCNN, etc.). In at least one embodiment, the DLAs may be further optimized for a specific set of neural network types and floating point operations, as well as inference. In at least one embodiment, the design of the DLAs allows for improved performance per millimeter over a typical general-purpose GPU, and typically greatly exceeds the performance of a CPU. In at least one embodiment, the TPU may execute several functions, including, for example, single instance convolution functions supporting INT8, INT16, and FP16 data types for both features and weights, as well as post-processing functions. In at least one embodiment, the DLA may quickly and efficiently execute neural networks, in particular CNNs, on the processed or unprocessed data for any of a variety of functions, including, for example, without limitation, CNNs for object identification and detection using data from a camera sensor, CNNs for distance estimation using data from a camera sensor, CNNs for emergency vehicle detection and identification using data from a microphone, CNNs for face recognition and vehicle owner identification using data from a camera sensor, and / or CNNs for security and / or safety related events.

[0129] In at least one embodiment, the DLA may perform any function of the GPU 1208, and a designer may target either the DLA or the GPU 1208 for any function, such as by using an inference accelerator. For example, in at least one embodiment, a designer may centralize processing of CNNs and floating point operations in the DLA and offload other functions to the GPU 1208 and / or other accelerators 1214.

[0130] In at least one embodiment, the accelerator 1214 may include a programmable vision accelerator (“PVA”), which may alternatively be referred to herein as a computer vision accelerator. In at least one embodiment, the PVA may be designed and configured to accelerate computer vision algorithms for advanced driver assistance systems (“ADAS”) 1238, autonomous driving, augmented reality (“AR”) applications, and / or virtual reality (“VR”) applications. In at least one embodiment, the PVA may balance performance and versatility. For example, in at least one embodiment, each PVA may include, for example and without limitation, any number of reduced instruction set computer (“RISC”) cores, direct memory access (“DMA”) cores, and / or any number of vector processors.

[0131] In at least one embodiment, the RISC core may interact with an image sensor (e.g., an image sensor of any camera described herein), an image signal processor, etc. In at least one embodiment, each RISC core may include any amount of memory. In at least one embodiment, the RISC core may use any of a number of protocols depending on the embodiment. In at least one embodiment, the RISC core may execute a real-time operating system ("RTOS"). In at least one embodiment, the RISC core may be implemented using one or more integrated circuit devices, application specific integrated circuits ("ASICs"), and / or memory devices. For example, in at least one embodiment, the RISC core may include an instruction cache and / or tightly coupled RAM.

[0132] In at least one embodiment, the DMA may allow components of the PVA to access system memory independent of the CPU 1206. In at least one embodiment, the DMA may support any number of features used to provide optimizations to the PVA, including, but not limited to, multi-dimensional addressing and / or circular addressing. In at least one embodiment, the DMA may support up to six or more addressing dimensions, which may include, without limitation, block width, block height, block depth, horizontal block stepping, vertical block stepping, and / or depth stepping.

[0133] In at least one embodiment, the vector processor may be a programmable processor that may be designed to efficiently and flexibly execute programming for computer vision algorithms and provide signal processing capabilities. In at least one embodiment, the PVA may include a PVA core and two vector processing subsystem partitions. In at least one embodiment, the PVA core may include a processor subsystem, a DMA engine (e.g., two DMA engines), and / or other peripherals. In at least one embodiment, the vector processing subsystem may operate as the primary processing engine of the PVA and may include a vector processing unit ("VPU"), an instruction cache, and / or a vector memory (e.g., "VMEM"). In at least one embodiment, the VPU may include a digital signal processor, such as, for example, a single instruction, multiple data ("SIMD"), very long instruction word ("VLIW") digital signal processor. In at least one embodiment, the combination of SIMD and VLIW may improve throughput and speed.

[0134] In at least one embodiment, each of the vector processors may include an instruction cache and may be coupled to dedicated memory. As a result, in at least one embodiment, each of the vector processors may be configured to execute independently of the other vector processors. In at least one embodiment, the vector processors included in a particular PVA may be configured to use data parallelism. For example, in at least one embodiment, multiple vector processors included in a single PVA may execute a common computer vision algorithm on different regions of an image. In at least one embodiment, the vector processors included in a particular PVA may execute different computer vision algorithms simultaneously on an image, or even execute different algorithms on successive images or portions of an image. In at least one embodiment, among other things, any number of PVAs may be included in a hardware accelerated cluster, and any number of vector processors may be included in each PVA. In at least one embodiment, the PVA may include additional Error Correction Code ("ECC") memory to enhance the overall security of the system.

[0135] In at least one embodiment, the accelerator 1214 may include an on-chip computer vision network and static random access memory ("SRAM") to provide high bandwidth, low latency SRAM for the accelerator 1214. In at least one embodiment, the on-chip memory may include at least 4 MB of SRAM including, for example, without limitation, eight field configurable memory blocks, which may be accessible from both the PVA and the DLA. In at least one embodiment, each pair of memory blocks may include an advanced peripheral bus ("APB") interface, configuration circuitry, a controller, and a multiplexer. In at least one embodiment, any type of memory may be used. In at least one embodiment, the PVA and DLA may access the memory through a backbone that provides the PVA and DLA with high speed access to the memory. In at least one embodiment, the backbone may include an on-chip computer vision network that interconnects the PVA and DLA to the memory (e.g., using the APB).

[0136] In at least one embodiment, the on-chip computer vision network may include an interface that determines that both the PVA and DLA provide ready and enable signals before transmitting any control signals / addresses / data. In at least one embodiment, the interface may provide separate phases and separate channels for transmitting control signals / addresses / data, as well as burst-based communication for continuous data transfer. In at least one embodiment, the interface may conform to International Organization for Standardization ("ISO") 26262 or International Electrotechnical Commission ("IEC") 61508 standards, although other standards and protocols may be used.

[0137] In at least one embodiment, one or more of the SoCs 1204 may include a real-time ray tracing hardware accelerator that may be used to quickly and efficiently determine the location and range of objects (e.g., within a world model) to generate real-time visualization simulations for RADAR signal interpretation, sound propagation synthesis and / or analysis, simulation of SONAR systems, general waveform propagation simulation, comparison with LIDAR data for localization and / or other functions, and / or other uses.

[0138] In at least one embodiment, the accelerator 1214 can have a variety of uses for autonomous driving. In at least one embodiment, the PVA can be used for key processing stages in ADAS and autonomous vehicles. In at least one embodiment, the performance of the PVA is well suited to algorithm domains that require predictable processing with low power and low latency. In other words, the PVA works well for small data sets for semi-dense or dense regular computations that may require predictable run times with low latency and low power. In at least one embodiment, the PVA can be designed to run traditional computer vision algorithms, such as in the vehicle 1200, as they may be useful for object detection and integer number operations.

[0139] For example, according to at least one embodiment of the technology, computer stereo vision may be performed using the PVA. In at least one embodiment, algorithms based on semi-global matching may be used in some examples, but are not limited to this. In at least one embodiment, applications for Level 3-5 autonomous driving use motion estimation / stereo matching (e.g., structure from motion, pedestrian recognition, lane detection, etc.) on the fly. In at least one embodiment, the PVA may perform computer stereo vision functions on input from two monocular cameras.

[0140] In at least one embodiment, the PVA may be used to perform dense optical flow. For example, in at least one embodiment, the PVA may process raw RADAR data (e.g., using a 4D Fast Fourier Transform) to provide processed RADAR data. In at least one embodiment, the PVA is used for time-of-flight depth processing, e.g., by processing raw time-of-flight data to provide processed time-of-flight data.

[0141] In at least one embodiment, the DLA may be used to implement any type of network for enhancing control and driving safety, including, for example and without limitation, a neural network that outputs a confidence measure for each object detection. In at least one embodiment, the confidence may be expressed or interpreted as a probability of each detection compared to other detections, or as providing its relative "weight". In at least one embodiment, the confidence measure allows the system to make further decisions regarding which detections should be considered positive detections rather than false positives. In at least one embodiment, the system may set a threshold for the confidence and only consider detections that exceed the threshold as positive detections. In embodiments where automatic emergency braking ("AEB") is used, a false positive may cause the vehicle to automatically apply emergency braking, which is clearly undesirable. In at least one embodiment, a highly confident detection may be considered as a trigger for AEB. In at least one embodiment, the DLA may implement a neural network to regress the confidence value. In at least one embodiment, the neural network may take as its input at least some subset of parameters, such as, among others, bounding box dimensions, a ground estimate obtained (e.g., from another subsystem), an output from an IMU sensor 1266 that correlates with the orientation of the vehicle 1200, distance, and a 3D location estimate of the object obtained from the neural network and / or other sensors (e.g., a LIDAR sensor 1264 or a RADAR sensor 1260).

[0142] In at least one embodiment, one or more of the SoCs 1204 may include a data store 1216 (e.g., a memory). In at least one embodiment, the data store 1216 may be an on-chip memory of the SoC 1204, which may store the neural network executed on the GPU 1208 and / or DLA. In at least one embodiment, the capacity of the data store 1216 may be large enough to store multiple instances of the neural network for redundancy and safety. In at least one embodiment, the data store 1216 may comprise an L2 or L3 cache.

[0143] In at least one embodiment, one or more of the SoCs 1204 may include any number of processors 1210 (e.g., embedded processors). In at least one embodiment, the processors 1210 may include a boot and power management processor, which may be a dedicated processor and subsystem for handling boot power and management functions and associated security enforcement. In at least one embodiment, the boot and power management processor may be part of the boot sequence of the SoC 1204 and may provide run-time power management services. In at least one embodiment, the boot power and management processor may provide programming of clocks and voltages, assisting in transitioning the system into a low power state, managing thermal and temperature sensors of the SoC 1204, and / or managing the power state of the SoC 1204. In at least one embodiment, each temperature sensor may be implemented as a ring oscillator whose output frequency is proportional to temperature, and the SoC 1204 may use the ring oscillator to detect the temperature of the CPU 1206, the GPU 1208, and / or the accelerator 1214. In at least one embodiment, if it is determined that the temperature exceeds a threshold, the boot and power management processor may enter a temperature fault routine, place SoC 1204 in a low power state, and / or place vehicle 1200 in a driver-safety shutdown mode (e.g., bring vehicle 1200 to a safety shutdown).

[0144] In at least one embodiment, processor 1210 may further include a set of embedded processors that can act as an audio processing engine, which may be an audio subsystem that allows full hardware support for multiple channels of audio over multiple interfaces, and a wide and flexible variety of audio I / O interfaces. In at least one embodiment, the audio processing engine is a dedicated processor core that has a digital signal processor with dedicated RAM.

[0145] In at least one embodiment, the processor 1210 may further include an always-on processor engine capable of providing the necessary hardware features to support low power sensor management and bring-up use cases. In at least one embodiment, the always-on processor engine may include, without limitation, a processor core, tightly-coupled RAM, supporting peripherals (e.g., timers and interrupt controllers), various I / O controller peripherals, and routing logic.

[0146] In at least one embodiment, the processor 1210 may further include a safety cluster engine, which may include, without limitation, a dedicated processor subsystem for handling safety management of automotive applications. In at least one embodiment, the safety cluster engine may include, without limitation, two or more processor cores, tightly coupled RAM, supporting peripherals (e.g., timers, interrupt controllers, etc.), and / or routing logic. In a safety mode, in at least one embodiment, two or more cores may operate in a lock-step mode and function as a single core with comparison logic to detect any differences between their operations. In at least one embodiment, the processor 1210 may further include a real-time camera engine, which may include, without limitation, a dedicated processor subsystem for handling real-time camera management. In at least one embodiment, the processor 1210 may further include a high dynamic range signal processor, which may include, without limitation, an image signal processor, which is a hardware engine that is part of a camera processing pipeline.

[0147] In at least one embodiment, the processor 1210 may include a video image composer, which may be a processing block (e.g., implemented in a microprocessor) that implements video post-processing functions required by a video playback application to generate a final image in a playback device window. In at least one embodiment, the video image composer may perform lens distortion correction for the wide-angle camera 1270, the surrounding camera 1274, and / or the in-cabin surveillance camera sensor. In at least one embodiment, the in-cabin surveillance camera sensor is preferably monitored by a neural network running on another instance of the SoC 1204 that is configured to identify events in the cabin and respond accordingly. In at least one embodiment, the in-cabin system may perform lip reading, without limitation, to activate cellular service, make calls, write emails, change the vehicle's destination, activate or change the vehicle's infotainment system and settings, and provide voice-activated web surfing. In at least one embodiment, certain functions are available to the driver when the vehicle is operating in an autonomous mode and are unavailable at other times.

[0148] In at least one embodiment, the video image combiner may include extended temporal noise reduction for both spatial and temporal noise reduction. For example, in at least one embodiment, when motion occurs in the video, the noise reduction appropriately weights the spatial information and de-weights the information provided by adjacent frames. In at least one embodiment, when an image or portion of an image does not contain motion, the temporal noise reduction performed by the video image combiner may use information from previous images to reduce noise in the current image.

[0149] In at least one embodiment, the video image composer may also be configured to perform stereo rectification on the input stereo lens frames. In at least one embodiment, the video image composer may also be used to composite a user interface when the operating system desktop is in use, eliminating the need for the GPU 1208 to continually render new surfaces. In at least one embodiment, the video image composer may be used to offload the GPU 1208 when it is powered on and actively performing 3D rendering, to improve performance and responsiveness.

[0150] In at least one embodiment, one or more of the SoCs 1204 may further include a mobile industry processor interface ("MIPI") camera serial interface for receiving input from video and cameras, a high-speed interface, and / or a video input block that may be used for camera and associated pixel input functions. In at least one embodiment, one or more of the SoCs 1204 may further include an input / output controller that may be controlled by software and may be used to receive I / O signals that are not tied to a specific role.

[0151] In at least one embodiment, one or more of the SoCs 1204 may further include peripherals, audio encoders / decoders ("codecs"), power management, and / or a wide range of peripheral interfaces to enable communication with other devices. In at least one embodiment, the SoC 1204 may be used to process data from cameras (e.g., connected via a gigabit multimedia serial link and an Ethernet channel), data from sensors (e.g., LIDAR sensor 1264, RADAR sensor 1260, etc., which may be connected via an Ethernet channel), data from the bus 1202 (e.g., speed of the vehicle 1200, steering wheel position, etc.), data from the GNSS sensor 1258 (e.g., connected via an Ethernet bus or a CAN bus), etc. In at least one embodiment, one or more of the SoCs 1204 may further include a dedicated high-performance mass storage controller, which may include its own DMA engine and may be used to offload the CPU 1206 from routine data management tasks.

[0152] In at least one embodiment, the SoC 1204 may be an end-to-end platform with a flexible architecture spanning levels 3-5 of automation, providing a comprehensive functional safety architecture that leverages and efficiently uses computer vision and ADAS techniques for diversity and redundancy, and providing a flexible, reliable driving software stack along with deep learning tools. In at least one embodiment, the SoC 1204 is faster, more reliable, and more energy and space efficient than traditional systems. For example, in at least one embodiment, the accelerator 1214, when combined with the CPU 1206, GPU 1208, and data store 1216, may provide a fast and efficient platform for levels 3-5 of autonomous vehicles.

[0153] In at least one embodiment, computer vision algorithms may be executed on a CPU, which may be configured using a high-level programming language, such as C, to perform various processing algorithms across various visual data. However, in at least one embodiment, CPUs often cannot meet the performance requirements of many computer vision applications, such as requirements related to execution time and power consumption. In at least one embodiment, many CPUs cannot run in real time the complex object detection algorithms used in in-vehicle ADAS applications and realistic Level 3-5 autonomous vehicles.

[0154] The embodiments described herein allow multiple neural networks to run simultaneously and / or sequentially, and the results can be combined to enable Level 3-5 autonomous driving capabilities. For example, in at least one embodiment, the CNN running on the DLA or a separate GPU (e.g., GPU1220) may include text and word recognition to enable reading and understanding traffic signs, including signs for which the neural network has not been specifically trained. In at least one embodiment, the DLA may further include a neural network that can identify and interpret signs and provide a semantic understanding of the signs, which can then be passed on to a route planning module running on the CPU complex.

[0155] In at least one embodiment, multiple neural networks may be run simultaneously for level 3, 4, or 5 driving. For example, in at least one embodiment, a warning sign that displays "Caution: Frozen Conditions When Flashing" in conjunction with a light may be interpreted separately or collectively by several neural networks. In at least one embodiment, such a warning sign itself may be identified as a traffic sign by a first deployed neural network (e.g., a neural network that has been trained), and the words "Frozen Conditions When Flashing" may be interpreted by a second deployed neural network, which notifies the vehicle's route planning software (preferably running on the CPU complex) that icy conditions exist if a flashing light is detected. In at least one embodiment, the flashing light may be identified by running a third deployed neural network over multiple frames, and the presence (or absence) of the flashing light is notified to the vehicle's route planning software. In at least one embodiment, all three neural networks may be run simultaneously, such as within the DLA and / or on the GPU 1208.

[0156] In at least one embodiment, a CNN for facial recognition and vehicle owner identification may use data from the camera sensor to identify the presence of an authorized driver and / or owner of the vehicle 1200. In at least one embodiment, an always-on sensor processing engine may be used to unlock the vehicle and turn on the lights when the owner approaches the driver's door, and to disable such vehicle in security mode when the owner leaves such vehicle. Thus, the SoC 1204 provides security against theft and / or carjacking.

[0157] In at least one embodiment, a CNN for emergency vehicle detection and identification may use data from microphone 1296 to detect and identify emergency vehicle sirens. In at least one embodiment, SoC 1204 uses a CNN to classify environmental and urban sounds as well as visual data. In at least one embodiment, the CNN running on the DLA is trained to identify the relative speed at which an emergency vehicle is approaching (e.g., by using the Doppler effect). In at least one embodiment, the CNN may also be trained to identify emergency vehicles specific to the region in which the vehicle is operating, as identified by GNSS sensor 1258. In at least one embodiment, when operating in Europe, the CNN attempts to detect European sirens, and when in North America, it attempts to identify only North American sirens. In at least one embodiment, when an emergency vehicle is detected, a control program to execute an emergency vehicle safety routine may be used to slow the vehicle, pull over to the side of the road, stop the vehicle, and / or idle the vehicle in conjunction with ultrasonic sensor 1262 until the emergency vehicle has passed.

[0158] In at least one embodiment, the vehicle 1200 may include a CPU 1218 (e.g., a discrete CPU or dCPU), which may be coupled to the SoC 1204 via a high-speed interconnect (e.g., PCIe). In at least one embodiment, the CPU 1218 may include, for example, an X86 processor. The CPU 1218 may be used to perform any of a variety of functions, including, for example, reconciling potentially inconsistent results between the ADAS sensors and the SoC 1204, and / or monitoring the status and health of the controller 1236 and / or the infotainment system on a chip ("infotainment SoC") 1230.

[0159] In at least one embodiment, vehicle 1200 may include a GPU 1220 (e.g., a discrete GPU or a dGPU), which may be coupled to SoC 1204 via a high-speed interconnect (e.g., NVIDIA's NVLINK channel). In at least one embodiment, GPU 1220 may provide additional artificial intelligence functionality, such as by running redundant and / or different neural networks, and may be used to train and / or update neural networks based at least in part on inputs (e.g., sensor data) from sensors of vehicle 1200.

[0160] In at least one embodiment, vehicle 1200 may further include a network interface 1224, which may include, without limitation, a wireless antenna 1226 (e.g., one or more wireless antennas for different communication protocols, such as a cellular antenna, a Bluetooth antenna, etc.). In at least one embodiment, network interface 1224 may be used to enable wireless connections to Internet cloud services (e.g., servers and / or other network devices) with other vehicles and / or computing devices (e.g., passenger client devices). In at least one embodiment, to communicate with other vehicles, a direct link may be established between vehicle 120 and the other vehicles and / or an indirect link (e.g., across a network and via the Internet) may be established. In at least one embodiment, the direct link may be provided using a vehicle-to-vehicle communication link. In at least one embodiment, the vehicle-to-vehicle communication link may provide vehicle 1200 with information about vehicles in its vicinity (e.g., vehicles in front of, to the sides of, and / or behind vehicle 1200). In at least one embodiment, these aforementioned features may be part of a cooperative adaptive cruise control function of the vehicle 1200.

[0161] In at least one embodiment, the network interface 1224 may include a SoC that provides modulation and demodulation functionality and enables the controller 1236 to communicate over a wireless network. In at least one embodiment, the network interface 1224 may include a radio frequency front end for up-conversion from baseband to radio frequency and down-conversion from radio frequency to baseband. In at least one embodiment, the frequency conversion may be performed in any technically feasible manner. For example, the frequency conversion may be performed by well-known processes and / or using a super-heterodyne process. In at least one embodiment, the radio frequency front end functionality may be provided by a separate chip. In at least one embodiment, the network interface may include wireless functionality for communicating via LTE, WCDMA, UMTS, GSM, CDMA2000, Bluetooth, Bluetooth LE, Wi-Fi, Z-Wave, ZigBee, LoRaWAN, and / or other wireless protocols.

[0162] In at least one embodiment, vehicle 1200 may further include a data store 1228, which may include, without limitation, off-chip (e.g., not on SoC 1204) storage. In at least one embodiment, data store 1228 may include one or more storage elements, including, without limitation, RAM, SRAM, dynamic random access memory ("DRAM"), video random-access memory ("VRAM"), flash memory, a hard disk, and / or other components and / or devices capable of storing at least one bit of data.

[0163] In at least one embodiment, vehicle 1200 may further include GNSS sensors 1258 (e.g., GPS and / or assisted GPS sensors) to assist in mapping, perception, occupancy grid generation, and / or route planning functions. In at least one embodiment, any number of GNSS sensors 1258 may be used, including, for example, without limitation, a GPS using a USB connector with an Ethernet to serial (e.g., RS-232) bridge.

[0164] In at least one embodiment, the vehicle 1200 may further include a RADAR sensor 1260. In at least one embodiment, the RADAR sensor 1260 may be used by the vehicle 1200 to perform long-range vehicle detection, even in darkness and / or severe weather conditions. In at least one embodiment, the RADAR functional safety level may be ASIL B. In at least one embodiment, the RADAR sensor 1260 may use a CAN bus and / or bus 1202 for control (e.g., to transmit data generated by the RADAR sensor 1260) and to access object tracking data, and in some examples may have access to an Ethernet channel to access raw data. In at least one embodiment, various types of RADAR sensors may be used. For example, without limitation, the RADAR sensor 1260 may be suitable for forward, rearward, and side RADAR use. In at least one embodiment, one or more of the RADAR sensors 1260 are pulse-Doppler RADAR sensors.

[0165] In at least one embodiment, the RADAR sensor 1260 may include different configurations, such as long range with narrow field of view, short range with wide field of view, and short range with side coverage. In at least one embodiment, the long range RADAR may be used for adaptive cruise control functions. In at least one embodiment, the long range RADAR system may provide a wide field of view, such as within a 250m (meter) range, achieved by two or more independent scans. In at least one embodiment, the RADAR sensor 1260 may help distinguish between static and moving objects and may be used by the ADAS system 1238 to provide emergency braking assistance and forward collision warning. In at least one embodiment, the sensor 1260 included in the long range RADAR system may include, without limitation, multiple (e.g., six or more) fixed RADAR antennas, as well as monostatic multi-mode RADAR with high speed CAN and FlexRay interfaces. In at least one embodiment, where there are six antennas, the center four antennas may generate a focused beam pattern designed to record the surroundings of vehicle 1200 at higher speeds with minimal interference from adjacent lanes. In at least one embodiment, the other two antennas may provide an extended field of view, allowing for quick detection of vehicles entering or exiting vehicle 1200's lane.

[0166] In at least one embodiment, the mid-range RADAR system may include, by way of example, a range of up to 160 meters (forward) or 80 meters (backward) and a field of view of up to 42 degrees (forward) or 150 degrees (backward). In at least one embodiment, the short-range RADAR system may include, without limitation, any number of RADAR sensors 1260 designed to be mounted on either end of the rear bumper. When mounted on either end of the rear bumper, in at least one embodiment, the RADAR sensor system may generate two beams that constantly monitor the blind spots behind and adjacent to the vehicle. In at least one embodiment, the short-range RADAR system may be used in an ADAS system 1238 to perform blind spot detection and / or lane change assistance.

[0167] In at least one embodiment, the vehicle 1200 may further include ultrasonic sensors 1262. In at least one embodiment, the ultrasonic sensors 1262 may be located at the front, rear, and / or side positions of the vehicle 1200 and may be used for parking assistance and / or to generate and update an occupancy grid. In at least one embodiment, multiple ultrasonic sensors 1262 may be used, and different ultrasonic sensors 1262 may be used for different detection ranges (e.g., 2.5 m, 4 m). In at least one embodiment, the ultrasonic sensors 1262 may operate at functional safety level ASIL B.

[0168] In at least one embodiment, the vehicle 1200 may include a LIDAR sensor 1264. In at least one embodiment, the LIDAR sensor 1264 may be used for object and pedestrian detection, emergency braking, collision avoidance, and / or other functions. In at least one embodiment, the LIDAR sensor 1264 may operate at a functional safety level ASIL B. In at least one embodiment, the vehicle 1200 may include multiple LIDAR sensors 1264 (e.g., two, four, six, etc.), which may use an Ethernet channel (e.g., to provide data to a Gigabit Ethernet switch).

[0169] In at least one embodiment, the LIDAR sensor 1264 may be capable of providing a list of objects and their distances for a 360 degree field of view. In at least one embodiment, a commercially available LIDAR sensor 1264 may, for example, have an advertised range of approximately 100m, an accuracy of 2cm to 3cm, and support a 100Mbps Ethernet connection. In at least one embodiment, one or more non-protruding LIDAR sensors may be used. In such embodiments, the LIDAR sensor 1264 may include small devices that may be integrated into the front, rear, side, and / or corner positions of the vehicle 1200. In at least one embodiment, the LIDAR sensor 1264 of such embodiments may provide a horizontal field of view of up to 120 degrees and a vertical field of view of 35 degrees, with a range of 200m, even for low-reflectivity objects. In at least one embodiment, a front-mounted LIDAR sensor 1264 may be configured to provide a horizontal field of view of 45 degrees to 135 degrees.

[0170] In at least one embodiment, LIDAR technology such as 3D flash LIDAR may also be used. In at least one embodiment, the 3D flash LIDAR uses a flash of a laser as a transmission source to illuminate the surroundings of the vehicle 1200 up to approximately 200 meters. In at least one embodiment, the flash LIDAR unit includes, without limitation, a receptor that records the transit time of the laser pulse and the reflected light at each pixel, which corresponds to the range from the vehicle 1200 to the object. In at least one embodiment, the flash LIDAR allows a very accurate and undistorted image of the surroundings to be generated with each flash of the laser. In at least one embodiment, four flash LIDARs may be deployed, one on each side of the vehicle 1200. In at least one embodiment, the 3D flash LIDAR system includes, without limitation, a solid-state 3D staring array LIDAR camera (e.g., a non-scanning LIDAR device) with no moving parts other than a fan. In at least one embodiment, the flash LIDAR device may use Class I (eye-safe) laser pulses of 5 nanoseconds per frame and may capture the reflected laser light as a 3D range point cloud and co-registered intensity data.

[0171] In at least one embodiment, the vehicle 1200 may further include an IMU sensor 1266. In at least one embodiment, the IMU sensor 1266 may be positioned at the center of the rear axle of the vehicle 1200. In at least one embodiment, the IMU sensor 1266 may include, for example, without limitation, an accelerometer, a magnetometer, a gyroscope, a magnetic compass, multiple magnetic compasses, and / or other types of sensors. In at least one embodiment, such as in a 6-axis application, the IMU sensor 1266 may include, without limitation, an accelerometer and a gyroscope. In at least one embodiment, such as in a 9-axis application, the IMU sensor 1266 may include, without limitation, an accelerometer, a gyroscope, and a magnetometer.

[0172] In at least one embodiment, the IMU sensor 1266 may be implemented as a compact, high-performance GPS-Aided Inertial Navigation System ("GPS / INS") that combines micro-electro-mechanical systems ("MEMS") inertial sensors, a highly sensitive GPS receiver, and advanced Kalman filtering algorithms to provide estimates of position, velocity, and attitude. In at least one embodiment, the IMU sensor 1266 allows the vehicle 1200 to estimate the orientation of the vehicle 1200 without requiring input from a magnetic sensor by directly observing velocity changes and correlating them from the GPS to the IMU sensor 1266. In at least one embodiment, the IMU sensor 1266 and the GNSS sensor 1258 may be combined into a single integrated unit.

[0173] In at least one embodiment, vehicle 1200 may include microphones 1296 located in and / or around vehicle 1200. In at least one embodiment, microphones 1296 may be used for, among other things, detection and identification of emergency vehicles.

[0174] In at least one embodiment, vehicle 1200 may further include any number of camera types including stereo camera 1268, wide angle camera 1270, infrared camera 1272, surrounding camera 1274, long range camera 1298, mid range camera 1276, and / or other camera types. In at least one embodiment, the cameras may be used to capture image data around the entire perimeter of vehicle 1200. In at least one embodiment, which type of camera is used depends on vehicle 1200. In at least one embodiment, any combination of camera types may be used to provide the required coverage around vehicle 1200. In at least one embodiment, the number of cameras deployed may vary depending on the embodiment. For example, in at least one embodiment, vehicle 1200 may include 6 cameras, 7 cameras, 10 cameras, 12 cameras, or another number of cameras. In at least one embodiment, the cameras may support, by way of example and not limitation, Gigabit Multimedia Serial Link ("GMSL") and / or Gigabit Ethernet communications. In at least one embodiment, each camera may be as described in further detail herein above with respect to Figures 12A and 12B.

[0175] In at least one embodiment, the vehicle 1200 may further include a vibration sensor 1242. In at least one embodiment, the vibration sensor 1242 may measure vibration of a component of the vehicle 1200, such as an axle. For example, in at least one embodiment, a change in vibration may indicate a change in the road surface. In at least one embodiment, if more than one vibration sensor 1242 is used, the difference in vibration may be used to determine the amount of friction or slippage of the road surface (e.g., if there is a vibration difference between a powered axle and a free-wheeling axle).

[0176] In at least one embodiment, the vehicle 1200 may include an ADAS system 1238. In at least one embodiment, the ADAS system 1238 may include, in some examples, without limitation, a SoC. In at least one embodiment, the ADAS system(s) 1238 may include, without limitation, any number and any combination of autonomous / adaptive / automatic cruise control ("ACC") systems, cooperative adaptive cruise control ("CACC") systems, forward crash warning ("FCW") systems, automatic emergency braking ("AEB") systems, lane departure warning ("LDW") systems, lane keep assist ("LKA") systems, blind spot warning ("BSW") systems, rear cross-traffic warning ("RCTW") systems, collision warning ("CW") systems, lane centering ("LC") systems, and / or other systems, features, and / or functions.

[0177] In at least one embodiment, the ACC system may use a RADAR sensor 1260, a LIDAR sensor 1264, and / or any number of cameras. In at least one embodiment, the ACC system may include a longitudinal ACC system and / or a lateral ACC system. In at least one embodiment, the longitudinal ACC system monitors and controls the distance to another vehicle immediately in front of the vehicle 1200 and automatically adjusts the speed of the vehicle 1200 to maintain a safe distance from the vehicle in front. In at least one embodiment, the lateral ACC system performs distance maintenance and notifies the vehicle 1200 to change lanes when necessary. In at least one embodiment, the lateral ACC is related to other ADAS applications such as LC and CW.

[0178] In at least one embodiment, the CACC system uses information from other vehicles, which may be received by the network interface 1224 and / or wireless antenna 1226 from other vehicles via a wireless link or indirectly via a network connection (e.g., via the Internet). In at least one embodiment, a direct link may be provided by a vehicle-to-vehicle ("V2V") communication link, while an indirect link may be provided by an infrastructure-to-vehicle ("I2V") communication link. Generally, V2V communication provides information about the preceding vehicle (e.g., the vehicle immediately in front of the vehicle 1200 and in the same lane), and I2V communication provides information about the traffic ahead. In at least one embodiment, the CACC system may include either or both of I2V and V2V information sources. In at least one embodiment, information about the vehicle in front of the vehicle 1200 may make the CACC system more reliable, potentially allowing for smoother traffic flow and less congestion on the roads.

[0179] In at least one embodiment, the FCW system is designed to alert drivers to hazards so that such drivers can take corrective action. In at least one embodiment, the FCW system uses a front camera and / or RADAR sensor 1260 coupled to a dedicated processor, DSP, FPGA, and / or ASIC that is electrically coupled to provide feedback to the driver, such as a display, speaker, and / or vibration components. In at least one embodiment, the FCW system may provide warnings in the form of sound, visual warnings, vibrations, and / or quick brake pulses.

[0180] In at least one embodiment, the AEB system may detect an imminent frontal collision with another vehicle or other object and automatically apply the brakes if the driver does not take corrective action within a specified time or distance parameter. In at least one embodiment, the AEB system may use a frontal camera and / or RADAR sensor 1260 coupled to a dedicated processor, DSP, FPGA, and / or ASIC. In at least one embodiment, when the AEB system detects a hazard, the AEB system typically first advises the driver to take corrective action to avoid the collision, and if the driver does not take corrective action, the AEB system may automatically apply the brakes to prevent or at least mitigate the impact of the predicted collision. In at least one embodiment, the AEB system may include techniques such as dynamic brake support and / or pre-collision braking.

[0181] In at least one embodiment, the LDW system provides visual, audio, and / or tactile warnings, such as vibrations of the steering wheel or seat, to advise the driver when the vehicle 1200 crosses a lane marker. In at least one embodiment, the LDW system does not operate if the driver indicates an intentional lane departure, such as by activating a turn signal. In at least one embodiment, the LDW system may use a front-facing camera, which is coupled to a dedicated processor, DSP, FPGA, and / or ASIC that can be electrically coupled to provide feedback to the driver, such as a display, speaker, and / or vibration components. In at least one embodiment, the LKA system is a variation of the LDW system. In at least one embodiment, the LKA system provides steering inputs or brake controls to correct the vehicle 1200 if the vehicle 1200 begins to stray from the vehicle 1200's lane.

[0182] In at least one embodiment, the BSW system detects vehicles in the vehicle's blind spot and warns the driver. In at least one embodiment, the BSW system may provide visual, audio, and / or haptic alerts to indicate that it is unsafe to merge or change lanes. In at least one embodiment, the BSW system may provide an additional warning when the driver uses a turn signal. In at least one embodiment, the BSW system may use a rear camera and / or RADAR sensor 1260 coupled to dedicated processors, DSPs, FPGAs, and / or ASICs that are electrically coupled to feedback to the driver, such as displays, speakers, and / or vibration components.

[0183] In at least one embodiment, the RCTW system may provide visual, audio, and / or tactile notifications when an object is detected outside the range of the rear camera when reversing the vehicle 1200. In at least one embodiment, the RCTW system includes an AEB system to ensure vehicle braking is applied to avoid a collision. In at least one embodiment, the RCTW system may use one or more rear RADAR sensors 1260 coupled to dedicated processors, DSPs, FPGAs, and / or ASICs that are electrically coupled to provide feedback to the driver, such as displays, speakers, and / or vibration components.

[0184] In at least one embodiment, conventional ADAS systems may be prone to false positive results, which may be annoying and distracting to the driver, but are usually not of major concern because conventional ADAS systems advise the driver and allow the driver to determine whether a safety condition truly exists and respond accordingly. In at least one embodiment, in the case of conflicting results, the vehicle 1200 itself determines whether to follow the results from the primary computer (e.g., the first controller of the controller 1236) or the secondary computer (e.g., the second controller of the controller 1236). For example, in at least one embodiment, the ADAS system 1238 may be a backup and / or secondary computer to resist perception information to a rationality module of the backup computer. In at least one embodiment, the rationality monitor of the backup computer may run a variety of redundant software on hardware components to detect perception errors and dynamic driving tasks. In at least one embodiment, the output from the ADAS system 1238 may be provided to a supervisory MCU. In at least one embodiment, if the output from the primary computer and the output from the secondary computer conflict, the supervisory MCU determines how to reconcile the conflict to ensure safe operation.

[0185] In at least one embodiment, the primary computer may be configured to provide a reliability score to the monitor MCU that indicates the reliability of the primary computer's selected result. In at least one embodiment, if the reliability score exceeds a threshold, the monitor MCU may follow the instructions of the primary computer regardless of whether the secondary computers are providing conflicting or inconsistent results. In at least one embodiment, if the reliability score does not meet the threshold and the primary and secondary computers indicate different results (e.g., conflicting), the monitor MCU may arbitrate between the computers to determine an appropriate result.

[0186] In at least one embodiment, the monitoring MCU may be configured to execute a neural network that is trained and configured to determine conditions under which the secondary computer will provide a false alarm based at least in part on the output from the primary computer and the output from the secondary computer. In at least one embodiment, the neural network of the monitoring MCU may learn when the output of the secondary computer may be trusted and when it may not be trusted. For example, in at least one embodiment, if the secondary computer is a RADAR-based FCW system, the neural network of the monitoring MCU may learn when the FCW system identifies a metal object that is not actually a hazard, such as a drain grate or manhole cover that triggers an alarm. In at least one embodiment, if the secondary computer is a camera-based LDW system, the neural network of the monitoring MCU may learn to disable the LDW when a bicyclist or pedestrian is present and lane departure is actually the safest maneuver. In at least one embodiment, the monitoring MCU may include at least one of a DLA or a GPU suitable for executing the neural network along with associated memory. In at least one embodiment, the supervisory MCU may comprise and / or be included as a component of the SoC1204.

[0187] In at least one embodiment, the ADAS system 1238 may include a secondary computer that performs ADAS functions using traditional rules of computer vision. In at least one embodiment, the secondary computer may use traditional computer vision rules (if-then rules) and a neural network may reside in the supervisory MCU to improve reliability, safety, and performance. For example, in at least one embodiment, diverse implementations and intentional non-identity may increase the overall system's error tolerance, especially to errors caused by the functionality of the software (or software-hardware interface). For example, in at least one embodiment, if there is a bug or error in the software running on the primary computer and the non-identical software code running on the secondary computer provides globally consistent results, the supervisory MCU may have higher confidence that the overall results are correct and that a bug in the software or hardware on the primary computer has not caused a critical error.

[0188] In at least one embodiment, the output of the ADAS system 1238 may be provided to a perception block of the primary computer and / or a dynamic driving task block of the primary computer. For example, in at least one embodiment, if the ADAS system 1238 indicates a frontal collision warning due to an immediately preceding object, the perception block may use this information when identifying the object. In at least one embodiment, the secondary computer may have its own neural network that is pre-trained as described herein, thus reducing the risk of false positives.

[0189] In at least one embodiment, vehicle 1200 may further include an infotainment SoC 1230 (e.g., an in-vehicle infotainment system (IVI)). Although infotainment system 1230 is shown and described as an SoC, in at least one embodiment, it may not be an SoC and may include, without limitation, two or more separate components. In at least one embodiment, infotainment SoC 1230 may include, without limitation, a combination of hardware and software that may be used to provide audio (e.g., music, personal digital assistant, navigation instructions, news, radio, etc.), video (e.g., TV, movies, streaming, etc.), telephony (e.g., hands-free calling), network connectivity (e.g., LTE, Wi-Fi, etc.), and / or information services (e.g., navigation systems, rear parking assist, wireless data systems, vehicle-related information such as fuel level, total mileage, brake fuel level, oil level, door opening and closing, air filter information, etc.) to vehicle 1200. For example, infotainment SoC 1230 may include a radio, a disc player, a navigation system, a video player, USB and Bluetooth connectivity, a car computer, in-car entertainment, Wi-Fi, steering wheel audio controls, hands-free voice controls, a heads-up display ("HUD"), an HMI display 1234, telematics devices, a control panel (e.g., for controlling and / or interacting with various components, features, and / or systems), and / or other components. In at least one embodiment, infotainment SoC 1230 may also be used to provide information (e.g., visual and / or auditory) to a user of vehicle 1200, such as information from ADAS system 1238, autonomous driving information such as vehicle maneuver plans, trajectories, surrounding environment information (e.g., intersection information, vehicle information, road information, etc.), and / or other information.

[0190] In at least one embodiment, infotainment SoC 1230 may include any amount and type of GPU functionality. In at least one embodiment, infotainment SoC 1230 may communicate with other devices, systems, and / or components of vehicle 1200 via bus 1202. In at least one embodiment, infotainment SoC 1230 may be coupled to a supervisory MCU such that the infotainment system's GPU may perform some self-driving functions when primary controller 1236 (e.g., vehicle 1200's primary and / or backup computer) fails. In at least one embodiment, infotainment SoC 1230 may place vehicle 1200 in a driver-safety shutdown mode as described herein.

[0191] In at least one embodiment, the vehicle 1200 may further include an instrument cluster 1232 (e.g., a digital dashboard, an electronic instrument cluster, a digital instrument panel, etc.). In at least one embodiment, the instrument cluster 1232 may include, without limitation, a controller and / or a supercomputer (e.g., a separate controller or a supercomputer). In at least one embodiment, the instrument cluster 1232 may include any number and combination of instrument sets, such as, without limitation, a speedometer, a fuel level, an oil pressure, a tachometer, an odometer, a turn signal, a shift lever position indicator, a seat belt warning light, a parking brake warning light, an engine malfunction light, supplemental restraint system (e.g., airbag) information, light control, safety system control, navigation information, etc. In some examples, information may be displayed and / or shared between the infotainment SoC 1230 and the instrument cluster 1232. In at least one embodiment, the instrument cluster 1232 may be included as part of the infotainment SoC 1230 or vice versa.

[0192] Inference and / or training logic 915 is used to perform inference and / or training operations associated with one or more embodiments. More details regarding the inference and / or training logic 915 are provided herein in conjunction with Figures 9A and / or 9B. In at least one embodiment, the inference and / or training logic 915 may be used in the system of Figure 12C for inference or prediction operations based at least in part on weight parameters calculated using neural network training operations, neural network functionality and / or architecture, or neural network use cases described herein.

[0193] In at least one embodiment, an application programming interface is adapted to receive an application programming interface call including a graph definition and a recursion attribute in association with the diagram, and to execute a recursive neural network based on the graph definition.

[0194] 12D is a diagram of a system 1276 for communicating between a cloud-based server and the autonomous vehicle 1200 of FIG. 12A, according to at least one embodiment. In at least one embodiment, the system may include any number and type of vehicles, including, without limitation, a server 1278, a network 1290, and a vehicle 1200. In at least one embodiment, the server 1278 may include, without limitation, a number of GPUs 1284(A)-1284(H) (collectively referred to herein as GPUs 1284), PCIe switches 1282(A)-1282(D) (collectively referred to herein as PCIe switches 1282), and / or CPUs 1280(A)-1280(B) (collectively referred to herein as CPUs 1280). In at least one embodiment, the GPUs 1284, CPUs 1280, and PCIe switches 1282 may be interconnected by a high speed interconnect, such as, for example and without limitation, an NVLink interface 1288 developed by NVIDIA, and / or a PCIe connection 1286. In at least one embodiment, the GPUs 1284 are connected to each other via an NVLink and / or NVS switch SoC, and the GPUs 1284 and PCIe switches 1282 are connected via a PCIe interconnect. Although eight GPUs 1284, two CPUs 1280, and four PCIe switches 1282 are illustrated, this is not intended to be limiting. In at least one embodiment, each of the servers 1278 may include any number of GPUs 1284, CPUs 1280, and / or PCIe switches 1282 in any combination, without limitation. For example, in at least one embodiment, the servers 1278 may each include 8, 16, 32, and / or more GPUs 1284.

[0195] In at least one embodiment, server 1278 may receive image data from a vehicle over network 1290 representing images showing unexpected or changed road conditions, such as recently begun road construction. In at least one embodiment, server 1278 may transmit updated or not neural network 1292 and / or map information 1294, including without limitation information regarding traffic and road conditions, to the vehicle over network 1290. In at least one embodiment, updates to map information 1294 may include without limitation updates to HD map 1222, such as information regarding construction sites, potholes, detours, flooding, and / or other obstacles. In at least one embodiment, neural network 1292 and / or map information 1294 may be derived from new training and / or experience represented in data received from any number of vehicles in the environment and / or may be derived based at least in part on training performed at a data center (e.g., using server 1278 and / or other servers).

[0196] In at least one embodiment, server 1278 may be used to train a machine learning model (e.g., a neural network) based at least in part on the training data. In at least one embodiment, the training data may be generated by the vehicle and / or generated in a simulation (e.g., using a game engine). In at least one embodiment, any amount of the training data may be tagged and / or otherwise pre-processed (e.g., if the associated neural network would benefit from supervised learning). In at least one embodiment, any amount of the training data may not be tagged and / or pre-processed (e.g., if the associated neural network does not require supervised learning). In at least one embodiment, once the machine learning model is trained, it may be used by the vehicle (e.g., transmitted to the vehicle via network 1290 and / or used by server 1278 to remotely monitor the vehicle.

[0197] In at least one embodiment, server 1278 may receive data from vehicles and apply the data to state-of-the-art real-time neural networks to enable real-time intelligent inference. In at least one embodiment, server 1278 may include a deep learning supercomputer and / or special purpose AI computer powered by GPU 1284, such as the DGX and DGX Station machines developed by NVIDIA. However, in at least one embodiment, server 1278 may include a deep learning infrastructure using a CPU powered data center.

[0198] In at least one embodiment, the deep learning infrastructure of server 1278 may be capable of rapid real-time inference and may use that capability to assess and verify the health of the processor, software, and / or associated hardware of vehicle 1200. For example, in at least one embodiment, the deep learning infrastructure may receive periodic updates from vehicle 1200, such as a series of images and / or objects that vehicle 1200 has located in the series of images (e.g., via computer vision and / or other machine learning object classification techniques). In at least one embodiment, the deep learning infrastructure may run its own neural network to identify objects and compare them to the objects identified by vehicle 1200, and if the results do not match and the deep learning infrastructure concludes that the AI ​​of vehicle 1200 has failed, server 1278 may send a signal to vehicle 1200 to instruct the fail-safe computer of vehicle 1200 to take control, notify the occupants, and complete a safe stop maneuver.

[0199] In at least one embodiment, server 1278 may include GPU 1284 and one or more programmable inference accelerators (e.g., NVIDIA's TensorRT3 devices). In at least one embodiment, the combination of GPU-driven servers and inference acceleration may enable real-time response. In at least one embodiment, CPU, FPGA, and other processor-driven servers may be used for inference, such as when performance is less critical. In at least one embodiment, a hardware structure 915 is used to execute one or more embodiments. Details regarding hardware structure 915 are provided herein in conjunction with FIG. 9A and / or FIG. 9B.

[0200] Computer Systems 13 is a block diagram illustrating an exemplary computer system, which may be a system having interconnected devices and components formed with a processor that may include an execution unit for executing instructions, a system on a chip (SoC), or any combination thereof, according to at least one embodiment. In at least one embodiment, computer system 1300 may include components such as, without limitation, processor 1302 for using an execution unit that includes logic for executing algorithms for processing data in accordance with the present disclosure, such as in the embodiments described herein. In at least one embodiment, computer system 1300 may include a processor such as the PENTIUM® processor family, Xeon™, Itanium®, XScale™ and / or StrongARM™, Intel® Core™, or Intel® Nervana™ microprocessors available from Intel Corporation, Santa Clara, Calif., although other systems may be used (including PCs with other microprocessors, engineering workstations, set-top boxes, etc.). In at least one embodiment, computer system 1300 may run a version of the WINDOWS® operating system available from Microsoft Corporation of Redmond, Washington, although other operating systems (e.g., UNIX® and Linux®), embedded software, and / or graphical user interfaces may be used.

[0201] Embodiments may be used in other devices, such as portable devices and embedded applications. Some examples of portable devices include cellular phones, Internet protocol devices, digital cameras, personal digital assistants ("PDAs"), and portable PCs. In at least one embodiment, embedded applications may include microcontrollers, digital signal processors ("DSPs"), systems-on-chips, network computers ("NetPCs"), set-top boxes, network hubs, wide area network ("WAN") switches, or any other system capable of executing one or more instructions according to at least one embodiment.

[0202] In at least one embodiment, computer system 1300 may include, without limitation, a processor 1302, which may include one or more execution units 1308 for performing training and / or inference of machine learning models according to the techniques described herein. In at least one embodiment, computer system 1300 is a single processor desktop or server system, while in other embodiments, computer system 1300 may be a multiprocessor system. In at least one embodiment, processor 1302 may include, without limitation, a complex instruction set computer ("CISC") microprocessor, a reduced instruction set computing ("RISC") microprocessor, a very long instruction word ("VLIW") microprocessor, a processor implementing a combination of instruction sets, or any other processor device, such as a digital signal processor. In at least one embodiment, processor 1302 may be coupled to a processor bus 1310, which may transmit digital signals between processor 1302 and other components within computer system 1300.

[0203] In at least one embodiment, the processor 1302 may include, without limitation, a level 1 ("L1") internal cache memory ("cache") 1304. In at least one embodiment, the processor 1302 may have a single internal cache or multiple levels of internal cache. In at least one embodiment, the cache memory may be external to the processor 1302. Other embodiments may include a combination of both internal and external cache depending on the particular implementation and needs. In at least one embodiment, the register file 1306 may store different types of data in various registers, including, without limitation, integer registers, floating point registers, status registers, and an instruction pointer register.

[0204] In at least one embodiment, the processor 1302 also includes an execution unit 1308, including, without limitation, logic for performing integer and floating point operations. In at least one embodiment, the processor 1302 may also include a microcode ("u-code") read only memory ("ROM") that stores microcode for certain macroinstructions. In at least one embodiment, the execution unit 1308 may include logic to accommodate a packed instruction set 1309. In at least one embodiment, by including the packed instruction set 1309 in the instruction set of a general purpose processor along with associated circuitry for executing the instructions, operations used by many multimedia applications may be performed using packed data in the processor 1302. In one or more embodiments, many multimedia applications may be accelerated and executed more efficiently by performing operations on packed data using the full width of the processor's data bus, thereby eliminating the need to transfer smaller units of data between the processor's data bus to perform one or more operations on one data element at a time.

[0205] In at least one embodiment, the execution unit 1308 may also be used in a microcontroller, an embedded processor, a graphics device, a DSP, and other types of logic circuits. In at least one embodiment, the computer system 1300 may include, without limitation, a memory 1320. In at least one embodiment, the memory 1320 may be a dynamic random access memory ("DRAM") device, a static random access memory ("SRAM") device, a flash memory device, or other memory device. In at least one embodiment, the memory 1320 may store instructions 1319 and / or data 1321 represented by data signals that may be executed by the processor 1302.

[0206] In at least one embodiment, a system logic chip may be coupled to the processor bus 1310 and the memory 1320. In at least one embodiment, the system logic chip may include, without limitation, a memory controller hub ("MCH") 1316, and the processor 1302 may communicate with the MCH 1316 via the processor bus 1310. In at least one embodiment, the MCH 1316 may provide a high bandwidth memory path 1318 to the memory 1320 for storing instructions and data, and for storing graphics commands, data, and textures. In at least one embodiment, the MCH 1316 may route data signals between the processor 1302, the memory 1320, and other components of the computer system 1300, and may bridge data signals between the processor bus 1310, the memory 1320, and the system I / O interface 1322. In at least one embodiment, the system logic chip may provide a graphics port for coupling to a graphics controller. In at least one embodiment, the MCH 1316 may be coupled to memory 1320 via a high-bandwidth memory path 1318, and the graphics / video card 1312 may be coupled to the MCH 1316 via an Accelerated Graphics Port ("AGP") interconnect 1314.

[0207] In at least one embodiment, computer system 1300 may use system I / O interface 1322 as a proprietary hub interface bus to couple MCH 1316 to an I / O controller hub ("ICH") 1330. In at least one embodiment, ICH 1330 may provide direct connections to some I / O devices via a local I / O bus. In at least one embodiment, the local I / O bus may include, without limitation, a high-speed I / O bus for connecting peripherals to memory 1320, a chipset, and processor 1302. Examples may include, without limitation, audio controller 1329, firmware hub ("Flash BIOS") 1328, wireless transceiver 1326, data storage 1324, legacy I / O controller 1323 including user input and keyboard interfaces, serial expansion ports 1327 such as Universal Serial Bus ("USB") ports, and network controller 1334. In at least one embodiment, data storage 1324 may comprise a hard disk drive, a floppy disk drive, a CD-ROM device, a flash memory device, or other mass storage device.

[0208] In at least one embodiment, Figure 13 illustrates a system including interconnected hardware devices or "chips," while in other embodiments, Figure 13 may illustrate an exemplary SoC. In at least one embodiment, the devices illustrated in Figure 13 may be interconnected with proprietary interconnects, standard interconnects (e.g., PCIe), or some combination thereof. In at least one embodiment, one or more components of computer system 1300 may be interconnected using a Compute Express Link (CXL) interconnect.

[0209] Inference and / or training logic 915 is used to perform inference and / or training operations associated with one or more embodiments. More details regarding the inference and / or training logic 915 are provided herein in conjunction with Figures 9A and / or 9B. In at least one embodiment, the inference and / or training logic 915 may be used in the system of Figure 13 for inference or prediction operations based at least in part on weight parameters calculated using neural network training operations, neural network functionality and / or architecture, or neural network use cases described herein.

[0210] In at least one embodiment, an application programming interface is adapted to receive an application programming interface call including a graph definition and a recursion attribute in association with the diagram, and to execute a recursive neural network based on the graph definition.

[0211] 14 is a block diagram illustrating an electronic device 1400 for utilizing a processor 1410, according to at least one embodiment. In at least one embodiment, electronic device 1400 may be, for example, without limitation, a notebook, a tower server, a rack server, a blade server, a laptop, a desktop, a tablet, a mobile device, a phone, an embedded computer, or any other suitable electronic device.

[0212] In at least one embodiment, electronic device 1400 may include a processor 1410 communicatively coupled to any suitable number or type of components, peripherals, modules, or devices, without limitation. 2The devices may be coupled using a bus or interface, such as a C bus, a System Management Bus (“SMBus”), a Low Pin Count (LPC) bus, a Serial Peripheral Interface (“SPI”), a High Definition Audio (“HDA”) bus, a Serial Advance Technology Attachment (“SATA”) bus, a Universal Serial Bus (“USB”) (versions 1, 2, 3, etc.), or a Universal Asynchronous Receiver / Transmitter (“UART”) bus. In at least one embodiment, FIG. 14 illustrates a system including interconnected hardware devices or “chips,” while in other embodiments, FIG. 14 may illustrate an exemplary SoC. In at least one embodiment, the devices illustrated in FIG. 14 may be interconnected with proprietary interconnects, standard interconnects (e.g., PCIe), or some combination thereof. In at least one embodiment, one or more of the components of FIG. 14 may be interconnected using a Compute Express Link (CXL) interconnect.

[0213] In at least one embodiment, FIG. 14 illustrates a display 1424, a touch screen 1425, a touch pad 1430, a Near Field Communications unit ("NFC") 1445, a sensor hub 1440, a thermal sensor 1446, an Express Chipset ("EC") 1435, a Trusted Platform Module ("TPM") 1438, a BIOS / firmware / flash memory ("BIOS, FW flash") 1422, a DSP 1460, a drive 1420, such as a Solid State Disk ("SSD") or a Hard Disk Drive ("HDD"), a wireless local area network unit ("WLAN") 1450, a Bluetooth unit 1452, a wireless wide area network unit ("WWAN") 1454, a Bluetooth® unit 1456, a Bluetooth® unit 1458, a Bluetooth® unit 1459, a Bluetooth® unit 1460, a Bluetooth® unit 1470, a Bluetooth® unit 1472, a Bluetooth® unit 1474, a Bluetooth® unit 1476, a Bluetooth® unit 1478, a Bluetooth® unit 1478, a Bluetooth® unit 1478, a Bluetooth® unit 1479, a Bluetooth® unit 1480, a Bluetooth® unit 1482, a Bluetooth® unit 1484, a Bluetooth® unit 1486, a Bluetooth® unit 1488, a Bluetooth® unit 1488, a Bluetooth® unit 1488, a Bluetooth® unit 1488, a Bluetooth® unit 1489, a Bluetooth® unit 1490, a Bluetooth® unit 1491, a Bluetooth® unit 1492, a Bluetooth® unit 1494, a Bluetooth® unit 1496, a Bluetooth® unit 1498, a Bluetooth® unit 1499, a Bluetooth® unit 1500, a Bluetooth® unit 1501 The memory may include a GPS (Global Positioning System) unit 1456, a Global Positioning System (GPS) unit 1455, a camera, such as a USB 3.0 camera ("USB 3.0 Camera") 1454, and / or a Low Power Double Data Rate ("LPDDR") memory unit ("LPDDR3") 1415, implemented, for example, to the LPDDR3 standard. Each of these components may be implemented in any suitable manner.

[0214] In at least one embodiment, other components may be communicatively coupled to the processor 1410 via the components described above. In at least one embodiment, an accelerometer 1441, an ambient light sensor ("ALS") 1442, a compass 1443, and a gyroscope 1444 may be communicatively coupled to the sensor hub 1440. In at least one embodiment, a thermal sensor 1439, a fan 1437, a keyboard 1436, and a touch pad 1430 may be communicatively coupled to the EC 1435. In at least one embodiment, a speaker 1463, a headphone 1464, and a microphone ("mic") 1465 may be communicatively coupled to an audio unit ("audio codec and class D amplifier") 1462, which may be communicatively coupled to the DSP 1460. In at least one embodiment, the audio unit 1462 may include, for example, without limitation, an audio coder / decoder ("codec") and a class D amplifier. In at least one embodiment, a SIM card ("SIM") 1457 may be communicatively coupled to the WWAN unit 1456. In at least one embodiment, components such as the WLAN unit 1450 and the Bluetooth unit 1452, as well as the WWAN unit 1456, may be implemented in a Next Generation Form Factor ("NGFF").

[0215] Inference and / or training logic 915 is used to perform inference and / or training operations associated with one or more embodiments. More details regarding the inference and / or training logic 915 are provided herein in conjunction with Figures 9A and / or 9B. In at least one embodiment, the inference and / or training logic 915 may be used in the system of Figure 14 for inference or prediction operations based at least in part on weight parameters calculated using neural network training operations, neural network functionality and / or architecture, or neural network use cases described herein.

[0216] In at least one embodiment, an application programming interface is adapted to receive an application programming interface call including a graph definition and a recursion attribute in association with the diagram, and to execute a recursive neural network based on the graph definition.

[0217] 15 illustrates a computer system 1500, according to at least one embodiment. In at least one embodiment, the computer system 1500 is configured to implement the various processes and methods described throughout this disclosure.

[0218] In at least one embodiment, computer system 1500 includes at least one central processing unit ("CPU") 1502 connected to a communications bus 1510 implemented using any suitable protocol, such as, without limitation, PCI (Peripheral Component Interconnect), Peripheral Component Interconnect Express ("PCI-Express"), AGP (Accelerated Graphics Port), HyperTransport, or any other bus or point-to-point communications protocol. In at least one embodiment, computer system 1500 includes main memory 1504, control logic (e.g., implemented as hardware, software, or a combination thereof), and data is stored in main memory 1504, which may take the form of random access memory ("RAM"). In at least one embodiment, network interface subsystem (“network interface”) 1522 provides an interface with other computing devices and networks to receive data from other systems, including computer system 1500, and to transmit data to other systems, including computer system 1500.

[0219] In at least one embodiment, computer system 1500 includes, at least in one embodiment, without limitation, input device 1508, parallel processing system 1512, and display device 1506, which may be implemented using a conventional cathode ray tube ("CRT"), liquid crystal display ("LCD"), light emitting diode ("LED") display, plasma display, or other suitable display technology. In at least one embodiment, user input is received from input device 1508, such as a keyboard, mouse, touch pad, microphone, or the like. In at least one embodiment, each of the modules described herein may be located on a single semiconductor platform to form a processing system.

[0220] Inference and / or training logic 915 is used to perform inference and / or training operations associated with one or more embodiments. More details regarding the inference and / or training logic 915 are provided herein in conjunction with Figures 9A and / or 9B. In at least one embodiment, the inference and / or training logic 915 may be used in the system of Figure 15 for inference or prediction operations based at least in part on weight parameters calculated using neural network training operations, neural network functionality and / or architecture, or neural network use cases described herein.

[0221] In at least one embodiment, an application programming interface is adapted to receive an application programming interface call including a graph definition and a recursion attribute in association with the diagram, and to execute a recursive neural network based on the graph definition.

[0222] 16 illustrates a computer system 1600, according to at least one embodiment. In at least one embodiment, computer system 1600 includes, without limitation, a computer 1610 and a USB stick 1620. In at least one embodiment, computer 1610 may include, without limitation, any number and type of processor (not shown), and memory (not shown). In at least one embodiment, computer 1610 includes, without limitation, a server, a cloud instance, a laptop, and a desktop computer.

[0223] In at least one embodiment, the USB stick 1620 includes, without limitation, a processing unit 1630, a USB interface 1640, and USB interface logic 1650. In at least one embodiment, the processing unit 1630 may be any instruction execution system, apparatus, or device capable of executing instructions. In at least one embodiment, without limitation, the processing unit 1630 may include any number and type of processing cores (not shown). In at least one embodiment, the processing unit 1630 comprises an application specific integrated circuit ("ASIC") optimized to perform any amount and type of operations related to machine learning. For example, in at least one embodiment, the processing unit 1630 is a tensor processing unit ("TPC") optimized to perform machine learning inference operations. In at least one embodiment, the processing unit 1630 is a vision processing unit ("VPU") optimized to perform machine vision and machine learning inference operations.

[0224] In at least one embodiment, USB interface 1640 may be any type of USB connector or socket. For example, in at least one embodiment, USB interface 1640 is a USB 3.0 Type-C socket for data and power. In at least one embodiment, USB interface 1640 is a USB 3.0 Type-A connector. In at least one embodiment, USB interface logic 1650 may include any amount and type of logic that enables processing unit 1630 to interface with a device (e.g., computer 1610) via USB connector 1640.

[0225] Inference and / or training logic 915 is used to perform inference and / or training operations associated with one or more embodiments. More details regarding inference and / or training logic 915 are provided herein in conjunction with Figures 9A and / or 9B. In at least one embodiment, inference and / or training logic 915 may be used in the system of Figure 16 for inference or prediction operations based at least in part on weight parameters calculated using neural network training operations, neural network functionality and / or architecture, or neural network use cases described herein.

[0226] In at least one embodiment, an application programming interface is adapted to receive an application programming interface call including a graph definition and a recursion attribute in association with the diagram, and to execute a recursive neural network based on the graph definition.

[0227] FIG. 17A illustrates an exemplary architecture in which multiple GPUs 1710(1)-1710(N) are communicatively coupled to multiple multi-core processors 1705(1)-1705(M) via high-speed links 1740(1)-1740(N) (e.g., buses, point-to-point interconnects, etc.). In at least one embodiment, the high-speed links 1740(1)-1740(N) support communication throughputs of 4 GB / s, 30 GB / s, 80 GB / s, or more. Various interconnect protocols may be used, including, but not limited to, 1740(1)-1740(N) PCIe 4.0 or 5.0, and NVLink 2.0. In the various figures, "N" and "M" represent positive integers, the values ​​of which may vary from figure to figure.

[0228] Further, in one embodiment, two or more of the GPUs 1710 are interconnected via high speed links 1729(1)-1729(2), which may be implemented using similar or different protocols / links as used for high speed links 1740(1)-1740(N). Similarly, two or more of the multi-core processors 1705 may be connected via high speed link 1728, which may be a symmetric multi-processor (SMP) bus operating at 20 GB / s, 30 GB / s, 120 GB / s, or more. Alternatively, all communications between the various system components shown in FIG. 17A may be accomplished using similar protocols / links (e.g., via a common interconnect fabric).

[0229] In one embodiment, each multi-core processor 1705 is communicatively coupled to processor memory 1701(1)-1701(M) via a memory interconnect 1726(1)-1726(M), respectively, and each GPU 1710(1)-1710(N) is communicatively coupled to GPU memory 1720(1)-1720(N), respectively, via GPU memory interconnect 1750(1)-1750(N). In at least one embodiment, memory interconnects 1726 and 1750 may utilize similar or different memory access technologies. By way of example, and not limitation, processor memory 1701(1)-1701(M) and GPU memory 1720 may be volatile memory, such as dynamic random access memory (DRAM) (including stacked DRAM), graphics DDR SDRAM (GDDR) (e.g., GDDR5, GDDR6), or high bandwidth memory (HBM), and / or non-volatile memory, such as 3D XPoint or Nano-Ram. In at least one embodiment, some portions of processor memory 1701 may be volatile memory and other portions may be non-volatile memory (e.g., using a two-level memory (2LM) hierarchy).

[0230] As described herein, the various multi-core processors 1705 and GPUs 1710 may each be physically coupled to a specific memory 1701, 1720, and / or a unified memory architecture may be implemented in which a virtual system address space (also referred to as an "effective address" space) is distributed among various physical memories. For example, processor memories 1701(1)-1701(M) may each have a system memory address space of 64 GB, and GPU memories 1720(1)-1720(N) may each have a system memory address space of 32 GB, resulting in a total addressable memory of 256 GB when M=2 and N=4. Other values ​​for N and M are contemplated.

[0231] 17B illustrates further details of the interconnection between multi-core processor 1707 and graphics acceleration module 1746 according to one example embodiment. In at least one embodiment, graphics acceleration module 1746 may include one or more GPU chips integrated into a line card that is coupled to processor 1707 via a high-speed link 1740 (e.g., a PCIe bus, an NVLink, etc.). Alternatively, in at least one embodiment, graphics acceleration module 1746 may be integrated into the package or chip with processor 1707.

[0232] In at least one embodiment, the processor 1707 includes multiple cores 1760A-1760D, each having a translation lookaside buffer ("TLB") 1761A-1761D and one or more caches 1762A-1762D. In at least one embodiment, the cores 1760A-1760D may include various other components, not shown, for executing instructions and processing data. In at least one embodiment, the caches 1762A-1762D may comprise a level 1 (L1) and a level 2 (L2) cache. Additionally, one or more shared caches 1756 may be included in the caches 1762A-1762D and shared by the set of cores 1760A-1760D. For example, one embodiment of the processor 1707 includes 24 cores, each having its own L1 cache, 12 shared L2 caches, and 12 shared L3 caches. In this embodiment, one or more L2 and L3 caches are shared by two adjacent cores. In at least one embodiment, the processor 1707 and the graphics acceleration module 1746 are coupled to a system memory 1714, which may include the processor memories 1701(1)-1701(M) of FIG. 17A.

[0233] In at least one embodiment, coherency is maintained for data and instructions stored in the various caches 1762A-1762D, 1756, and system memory 1714 by inter-core communication via a coherence bus 1764. In at least one embodiment, for example, each cache may have cache coherence logic / circuitry associated therewith for communicating over the coherence bus 1764 in response to detecting a read or write to a particular cache line. In at least one embodiment, a cache snooping protocol is implemented over the coherence bus 1764 to monitor cache accesses.

[0234] In at least one embodiment, proxy circuit 1725 communicatively couples graphics acceleration module 1746 to coherence bus 1764 to enable graphics acceleration module 1746 to participate in cache coherence protocols as a peer of cores 1760A-1760D. In particular, in at least one embodiment, interface 1735 provides a connection to proxy circuit 1725 over high-speed link 1740, and interface 1737 connects graphics acceleration module 1746 to high-speed link 1740.

[0235] In at least one embodiment, the accelerator integrated circuit 1736 provides cache management, memory access, content management, and interrupt management services on behalf of the multiple graphics processing engines 1731(1)-1731(N) of the graphics acceleration module 1746. In at least one embodiment, the graphics processing engines 1731(1)-1731(N) may each comprise a separate graphics processing unit (GPU). In at least one embodiment, the graphics processing engines 1731(1)-1731(N) may alternatively comprise different types of graphics processing engines within a GPU, such as graphics execution units, media processing engines (e.g., video encoders / decoders), samplers, and blit engines. In at least one embodiment, the graphics acceleration module 1746 may be a GPU having multiple graphics processing engines 1731(1)-1731(N), or the graphics processing engines 1731(1)-1731(N) may be individual GPUs integrated into a common package, line card, or chip.

[0236] In at least one embodiment, accelerator integrated circuitry 1736 includes a memory management unit (MMU) 1739 for performing various memory management functions, such as virtual-to-physical memory translation (also referred to as effective-to-real memory translation), and a memory access protocol for accessing system memory 1714. In at least one embodiment, MMU 1739 may also include a translation lookaside buffer (TLB) (not shown) for caching virtual / effective to physical / real address translations. In at least one embodiment, cache 1738 may store commands and data for efficient access by graphics processing engines 1731(1)-1731(N). In at least one embodiment, data stored in cache 1738 and graphics memory 1733(1)-1733(M) is kept coherent with core caches 1762A-1762D, 1756, and system memory 1714, possibly using fetch unit 1744. As noted, this may be accomplished via proxy circuitry 1725 (e.g., sending updates to cache 1738 and receiving updates from cache 1738 regarding modifications / accesses of cache lines in processor caches 1762A-1762D, 1756) on behalf of cache 1738 and memory 1733(1)-1733(M).

[0237] In at least one embodiment, a set of registers 1745 stores context data for threads executed by the graphics processing engines 1731(1)-1731(N), and a context management circuit 1748 manages thread contexts. For example, the context management circuit 1748 may perform save and restore operations to save and restore the context of various threads during a context switch (e.g., where a first thread is saved and a second thread is stored so that the second thread can be executed by the graphics processing engine). For example, upon a context switch, the context management circuit 1748 may store current register values ​​in a designated area of ​​memory (e.g., identified by a context pointer). Then, upon returning to the context, the context management circuit 1748 may restore the register values. In at least one embodiment, the interrupt management circuit 1747 receives and processes interrupts received from system devices.

[0238] In one embodiment, virtual / effective addresses from the graphics processing engine 1731 are translated by the MMU 1739 to real / physical addresses in the system memory 1714. In at least one embodiment, an embodiment of the accelerator integrated circuitry 1736 supports multiple (e.g., 4, 8, 16) graphics accelerator modules 1746 and / or other accelerator devices. In at least one embodiment, the graphics accelerator modules 1746 may be dedicated to a single application executing on the processor 1707 or may be shared among multiple applications. In at least one embodiment, there is a virtualized graphics execution environment in which the resources of the graphics processing engines 1731(1)-1731(N) are shared with multiple applications or virtual machines (VMs). In at least one embodiment, the resources may be subdivided into "slices" that are allocated to different VMs and / or applications based on the processing requirements and priorities associated with the VMs and / or applications.

[0239] In at least one embodiment, the accelerator integrated circuitry 1736 acts as a bridge to the system for the graphics acceleration module 1746 and provides address translation and system memory caching services. Additionally, in at least one embodiment, the accelerator integrated circuitry 1736 may provide a virtualization facility for a host processor to manage virtualization, interrupts, and memory management of the graphics processing engines 1731(1)-1731(N).

[0240] In at least one embodiment, the hardware resources of the graphics processing engines 1731(1)-1731(N) are explicitly mapped into the real address space seen by the host processor 1707, so that any host processor can directly address these resources using effective address values. In at least one embodiment, one function of the accelerator integrated circuitry 1736 is to physically separate the graphics processing engines 1731(1)-1731(N) so that they appear to the system as independent units.

[0241] In at least one embodiment, one or more graphics memories 1733(1)-1733(M) are each coupled to a respective one of the graphics processing engines 1731(1)-1731(N), where N=M. In at least one embodiment, the graphics memories 1733(1)-1733(M) store instructions and data to be processed by the respective graphics processing engines 1731(1)-1731(N). In at least one embodiment, the graphics memories 1733(1)-1733(M) may be volatile memory, such as DRAM (including stacked DRAM), GDDR memory, (e.g., GDDR5, GDDR6), or HBM, and / or may be non-volatile memory, such as 3D XPoint or Nano-Ram.

[0242] In one embodiment, to reduce data traffic over high-speed link 1740, biasing techniques are used to ensure that the data stored in graphics memory 1733(1)-1733(M) is data that will be used most frequently by graphics processing engines 1731(1)-1731(N) and preferably is not used (or at least is used less frequently) by cores 1760A-1760D. Similarly, in at least one embodiment, the biasing mechanisms attempt to keep data needed by the cores (and thus preferably not needed by graphics processing engines 1731(1)-1731(N)) in the cores' caches 1762A-1762D, 1756, and system memory 1714.

[0243] 17C illustrates another exemplary embodiment in which the accelerator integrated circuit 1736 is integrated within the processor 1707. In at least this embodiment, the graphics processing engines 1731(1)-1731(N) communicate with the accelerator integrated circuit 1736 directly via high speed link 1740 (which again may be any form of bus or interface protocol) through interface 1737 and interface 1735. In at least one embodiment, the accelerator integrated circuit 1736 may perform operations similar to those described with respect to FIG. 17B, but may potentially operate at a higher throughput given its proximity to the coherence bus 1764 and caches 1762A-1762D, 1756. One embodiment supports different programming models, including a dedicated process programming model (without graphics acceleration module virtualization) and a shared programming model (with virtualization), which may include a programming model controlled by the accelerator integrated circuitry 1736 and a programming model controlled by the graphics acceleration module 1746.

[0244] In at least one embodiment, graphics processing engines 1731(1)-1731(N) are dedicated to a single application or process under a single operating system. In at least one embodiment, a single application can centralize other application requests to graphics processing engines 1731(1)-1731(N) to achieve virtualization within a VM / partition.

[0245] In at least one embodiment, graphics processing engines 1731(1)-1731(N) may be shared by multiple VM / application partitions. In at least one embodiment, the sharing model may use a system hypervisor to virtualize graphics processing engines 1731(1)-1731(N) to allow access by each operating system. In at least one embodiment, in a single partition system without a hypervisor, graphics processing engines 1731(1)-1731(N) are owned by the operating system. In at least one embodiment, the operating system may virtualize graphics processing engines 1731(1)-1731(N) to provide access to each process or application.

[0246] In at least one embodiment, the graphics acceleration module 1746 or an individual graphics processing engine 1731(1)-1731(N) selects a process element using a process handle. In at least one embodiment, the process element is stored in system memory 1714 and is addressable using the effective address to real address translation techniques described herein. In at least one embodiment, the process handle may be an implementation-specific value provided to a host process when registering the host process's context with the graphics processing engine 1731(1)-1731(N) (i.e., calling system software to add the process element to the process element linked list). In at least one embodiment, the low-order 16 bits of the process handle may be the offset of the process element within the process element linked list.

[0247] FIG. 17D illustrates an exemplary accelerator integration slice 1790. In at least one embodiment, a “slice” comprises a designated portion of the processing resources of accelerator integration circuitry 1736. In at least one embodiment, application effective address space 1782 in system memory 1714 stores process elements 1783. In at least one embodiment, process elements 1783 are stored in response to GPU calls 1781 from an application 1780 executing on processor 1707. In at least one embodiment, process elements 1783 contain the process state of the corresponding application 1780. In at least one embodiment, work descriptors (WDs) 1784 contained in process elements 1783 can be single jobs requested by the application or may contain a pointer to a queue of jobs. In at least one embodiment, WDs 1784 are pointers to a job request queue in application effective address space 1782.

[0248] In at least one embodiment, the graphics acceleration module 1746 and / or the individual graphics processing engines 1731(1)-1731(N) may be shared by all or a subset of the processes in the system. In at least one embodiment, an infrastructure may be included for setting process state and sending a WD 1784 to the graphics acceleration module 1746 to start a job in a virtualized environment.

[0249] In at least one embodiment, the dedicated process programming model is implementation specific. In at least one embodiment, in this model, a single process owns the graphics acceleration module 1746 or an individual graphics processing engine 1731. In at least one embodiment, when the graphics acceleration module 1746 is owned by a single process, the hypervisor initializes the accelerator integration circuitry 1736 for the owning partition and the operating system initializes the accelerator integration circuitry 1736 for the owning process when the graphics acceleration module 1746 is allocated.

[0250] In at least one embodiment, in operation, a WD fetch unit 1791 in the accelerator integrated slice 1790 fetches a next WD 1784 that includes an indication of work to be performed by one or more graphics processing engines of the graphics acceleration module. In at least one embodiment, as shown, data from the WD 1784 may be stored in registers 1745 and used by the MMU 1739, the interrupt management circuitry 1747, and / or the context management circuitry 1748. For example, one embodiment of the MMU 1739 includes a segment / page walk circuit for accessing a segment / page table 1786 in the OS virtual address space 1785. In at least one embodiment, the interrupt management circuitry 1747 may process an interrupt event 1792 received from the graphics acceleration module 1746. In at least one embodiment, when performing graphics operations, effective addresses 1793 generated by the graphics processing engines 1731(1)-1731(N) are translated to real addresses by the MMU 1739.

[0251] In at least one embodiment, registers 1745 may be replicated for each graphics processing engine 1731(1)-1731(N) and / or graphics acceleration module 1746 and initialized by the hypervisor or operating system. In at least one embodiment, each of these replicated registers may be included in accelerator integration slice 1790. Exemplary registers that may be initialized by the hypervisor are shown in Table 1. [Table 1]

[0252] Exemplary registers that may be initialized by the operating system are shown in Table 2. [Table 2]

[0253] In at least one embodiment, each WD 1784 is specific to a particular graphics acceleration module 1746 and / or graphics processing engine 1731(1)-1731(N). In at least one embodiment, WD 1784 may contain all the information that graphics processing engine 1731(1)-1731(N) needs to do work, or may be a pointer to a memory location where an application has set up a command queue for work to be completed.

[0254] 17E illustrates further details of an exemplary embodiment of the sharing model, including a hypervisor real address space 1798 in which a process element list 1799 is stored. In at least one embodiment, the hypervisor real address space 1798 is accessible via a hypervisor 1796 that virtualizes the graphics acceleration module engine of an operating system 1795.

[0255] In at least one embodiment, the shared programming model allows all or a subset of processes from all or a subset of partitions in a system to use the graphics acceleration module 1746. In at least one embodiment, there are two programming models in which the graphics acceleration module 1746 is shared by multiple processes and partitions: timeslice shared and graphics-directed shared.

[0256] In at least one embodiment, in this model, the system hypervisor 1796 owns the graphics acceleration module 1746 and makes its functionality available to all operating systems 1795. In at least one embodiment, in order for the graphics acceleration module 1746 to support virtualization by the system hypervisor 1796, the graphics acceleration module 1746 may comply with several requirements, such as: 1) the application's job requests must be autonomous (i.e., no state needs to be maintained between jobs) or the graphics acceleration module 1746 must provide a mechanism for saving and restoring context, 2) the application's job requests must be guaranteed by the graphics acceleration module 1746 to complete in a specified amount of time, including any translation errors, or the graphics acceleration module 1746 must provide the ability to preempt the processing of jobs, and 3) the graphics acceleration module 1746 must ensure fairness between processes when operating in a specified shared programming model.

[0257] In at least one embodiment, the application 1780 needs to make a system call to the operating system 1795 with the graphics acceleration module type, a work descriptor (WD), an authority mask register (AMR) value, and a context save / restore area pointer (CSRP). In at least one embodiment, the graphics acceleration module type describes the acceleration function that is the target of the system call. In at least one embodiment, the graphics acceleration module type may be a system specific value. In at least one embodiment, the WD is formatted specifically for the graphics acceleration module 1746 and may be in the form of graphics acceleration module 1746 commands, an effective address pointer to a user defined structure, an effective address pointer to a queue of commands, or any other data structure to describe the work to be done by the graphics acceleration module 1746.

[0258] In at least one embodiment, the AMR value is the AMR state to use for the current process. In at least one embodiment, the value passed to the operating system is the same as the application setting the AMR. In at least one embodiment, if the implementation of the accelerator integrated circuitry 1736 (not shown) and the graphics acceleration module 1746 does not support a user authority mask override register (UAMOR), the operating system may apply the current UAMOR value to the AMR value before passing the AMR to the hypervisor call. In at least one embodiment, the hypervisor 1796 may optionally apply the current authority mask override register (AMOR) value before placing the AMR in the process element 1783. In at least one embodiment, the CSRP is one of the registers 1745 that contains the effective address of an area in the application's effective address space 1782 for the graphics acceleration module 1746 to save and restore context state. In at least one embodiment, this pointer is optional if no state needs to be saved between jobs or when a job is preempted. In at least one embodiment, the context save / restore area may be pinned system memory.

[0259] Upon receiving the system call, the operating system 1795 may verify that the application 1780 is registered and authorized to use the graphics acceleration module 1746. In at least one embodiment, the operating system 1795 then calls the hypervisor 1796 with the information shown in Table 3. [Table 3]

[0260] In at least one embodiment, upon receiving the hypervisor call, the hypervisor 1796 verifies that the operating system 1795 is registered and authorized to use the graphics acceleration module 1746. In at least one embodiment, the hypervisor 1796 then places the process element 1783 into a process element linked list of the corresponding graphics acceleration module 1746 type. In at least one embodiment, the process element may include the information shown in Table 4. [Table 4]

[0261] In at least one embodiment, the hypervisor initializes registers 1745 of multiple accelerator integrated slices 1790.

[0262] As shown in FIG. 17F, at least one embodiment uses a unified memory that is addressable via a common virtual memory address space used to access physical processor memory 1701(1)-1701(N) and GPU memory 1720(1)-1720(N). In this implementation, operations performed on GPUs 1710(1)-1710(N) utilize the same virtual / effective memory address space that accesses processor memory 1701(1)-1701(N), and vice versa, thereby simplifying programmability. In at least one embodiment, a first portion of the virtual / effective address space is allocated to processor memory 1701(1), a second portion is allocated to second processor memory 1701(N), a third portion is allocated to GPU memory 1720(1), and so on. In at least one embodiment, the entire virtual / effective memory space (sometimes referred to as the effective address space) is thereby distributed across each of the processor memory 1701 and GPU memory 1720, allowing either processor or GPU to access either physical memory with virtual addresses mapped to physical memory.

[0263] In one embodiment, bias / coherence management circuits 1794A-1794E in one or more of the MMUs 1739A-1739E ensure cache coherence between caches of one or more host processors (e.g., 1705) and caches of the GPU 1710 and implement biasing techniques to indicate the physical memory in which certain types of data should be stored. In at least one embodiment, multiple instances of bias / coherence management circuits 1794A-1794E are shown in FIG. 17F, however, the bias / coherence circuits may be implemented within the MMUs of one or more host processors 1705 and / or within the accelerator integration circuit 1736.

[0264] One embodiment allows the GPU memory 1720 to be mapped as part of system memory and accessible using shared virtual memory (SVM) techniques, but without the performance penalty associated with full system cache coherence. In at least one embodiment, the GPU memory 1720 being accessible as system memory without cumbersome cache coherence overhead provides a beneficial operating environment for GPU offload. In at least one embodiment, this configuration allows the host processor 1705 software to set up operands and access computation results without the overhead of traditional I / O DMA data copies. In at least one embodiment, such traditional copies require driver calls, interrupts, and memory-mapped I / O (MMIO) accesses, all of which are less efficient than simple memory accesses. In at least one embodiment, the ability to access the GPU memory 1720 without cache coherence overhead can be critical to the execution time of the offloaded computation. In at least one embodiment, for example, in the presence of significant streaming write memory traffic, cache coherence overhead can significantly reduce the effective write bandwidth seen by the GPU 1710. In at least one embodiment, the efficiency of operand setup, the efficiency of result access, and the efficiency of GPU computation can help in determining the effectiveness of GPU offloading.

[0265] In at least one embodiment, the selection of the GPU bias and the host processor bias is determined by a bias tracker data structure. In at least one embodiment, for example, a bias table may be used, which may be a page granular structure including one or two bits per GPU-attached memory page (e.g., controlled at memory page granularity). In at least one embodiment, the bias table may be implemented in a stolen memory range of one or more GPU memories 1720, with or without a bias cache in GPU 1710 (e.g., for caching frequently / recently used entries of the bias table). Alternatively, in at least one embodiment, the bias table may be maintained entirely within the GPU.

[0266] In at least one embodiment, a bias table entry associated with each access to GPU-biased memory 1720 is accessed prior to the actual access to the GPU memory, resulting in the following actions: In at least one embodiment, a local request from the GPU 1710 to find its page in the GPU bias is forwarded directly to the corresponding GPU memory 1720. In at least one embodiment, a local request from the GPU to find its page in the host bias is forwarded to the processor 1705 (e.g., via the high-speed link described above). In at least one embodiment, a request from the processor 1705 to find the requested page in the host processor bias completes the request as if it were a normal memory read. Alternatively, a request directed to a GPU-biased page may be forwarded to the GPU 1710. In at least one embodiment, the GPU may then migrate the page to the host processor bias if it is not currently using the page. In at least one embodiment, the bias state of a page may be changed by either a software-based mechanism, a hardware-assisted software-based mechanism, or for a limited set of cases, simply a hardware-based mechanism.

[0267] In at least one embodiment, one mechanism for changing the bias state utilizes an API call (e.g., OpenCL) that calls the GPU's device driver, which sends a message (or queues a command descriptor) to the GPU to change the bias state and, for some transitions, directs the GPU to perform a cache flushing operation in the host. In at least one embodiment, a cache flushing operation is used for transitions from host processor 1705 bias to GPU bias, but not for transitions in the opposite direction.

[0268] In one embodiment, cache coherence is maintained by temporarily rendering GPU-biased pages that are not cacheable by the host processor 1705. In at least one embodiment, to access these pages, the processor 1705 may request access from the GPU 1710, which may or may not immediately grant the access. In at least one embodiment, therefore, to reduce communication between the processor 1705 and the GPU 1710, it is beneficial for the GPU-biased pages to be requested by the GPU but not by the host processor 1705, or vice versa.

[0269] To implement one or more embodiments, a hardware structure 915 is used, details regarding the hardware structure 915 may be provided herein in conjunction with Figures 9A and / or 9B.

[0270] 18 illustrates an exemplary integrated circuit and associated graphics processor that may be fabricated using one or more IP cores in accordance with various embodiments described herein. In addition to what is illustrated, in at least one embodiment, other logic and circuitry may be included, including additional graphics processors / cores, peripheral device interface controllers, or general purpose processor cores.

[0271] 18 is a block diagram illustrating an exemplary system-on-chip integrated circuit 1800 that can be fabricated using one or more IP cores according to at least one embodiment. In at least one embodiment, integrated circuit 1800 includes one or more application processors 1805 (e.g., a CPU), at least one graphics processor 1810, and may further include an image processor 1815 and / or a video processor 1820, any of which may be modular IP cores. In at least one embodiment, integrated circuit 1800 includes a USB controller 1825, a UART controller 1830, an SPI / SDIO controller 1835, and an I / O controller 1840. 2 2S / I 2 2C controller 1840. In at least one embodiment, the integrated circuit 1800 may include a display device 1845 coupled to one or more of a high-definition multimedia interface (HDMI) controller 1850 and a mobile industry processor interface (MIPI) display interface 1855. In at least one embodiment, storage may be provided by a flash memory subsystem 1860 including a flash memory and a flash memory controller. In at least one embodiment, a memory interface may be provided via a memory controller 1865 to access an SDRAM or SRAM memory device. In at least one embodiment, some integrated circuits further include an embedded security engine 1870.

[0272] Inference and / or training logic 915 is used to perform inference and / or training operations associated with one or more embodiments. More details regarding inference and / or training logic 915 are provided herein in conjunction with Figures 9A and / or 9B. In at least one embodiment, inference and / or training logic 915 may be used in integrated circuit 1800 for inference or prediction operations based at least in part on weight parameters calculated using neural network training operations, neural network functionality and / or architecture, or neural network use cases described herein.

[0273] In at least one embodiment, an application programming interface is adapted to receive an application programming interface call including a graph definition and a recursion attribute in association with the diagram, and to execute a recursive neural network based on the graph definition.

[0274] 19A-19B illustrate an example integrated circuit and associated graphics processor that can be fabricated using one or more IP cores according to various embodiments described herein. In addition to what is shown, at least one embodiment may include other logic and circuitry, including additional graphics processors / cores, peripheral device interface controllers, or general purpose processor cores.

[0275] 19A-19B are block diagrams illustrating an example graphics processor for use in an SoC, according to embodiments described herein. FIG. 19A illustrates an example graphics processor 1910 of a system-on-chip integrated circuit that can be fabricated using one or more IP cores, according to at least one embodiment. FIG. 19B illustrates a further example graphics processor 1940 of a system-on-chip integrated circuit that can be fabricated using one or more IP cores, according to at least one embodiment. In at least one embodiment, the graphics processor 1910 of FIG. 19A is a low-power graphics processor core. In at least one embodiment, the graphics processor 1940 of FIG. 19B is a high-performance graphics processor core. In at least one embodiment, each of the graphics processors 1910, 1940 can be a variation of the graphics processor 1810 of FIG. 18.

[0276] In at least one embodiment, the graphics processor 1910 includes a vertex processor 1905 and one or more fragment processors 1915A-1915N (e.g., 1915A, 1915B, 1915C, 1915D-1, and 1915N). In at least one embodiment, the graphics processor 1910 can execute different shader programs via separate logic, such that the vertex processor 1905 is optimized to perform operations for vertex shader programs, while one or more fragment processors 1915A-1915N perform fragment (e.g., pixel) shading operations for fragment or pixel shader programs. In at least one embodiment, the vertex processor 1905 executes the vertex processing stage of a 3D graphics pipeline, generating primitive and vertex data. In at least one embodiment, the fragment processors 1915A-1915N generate frame buffers that are displayed on a display device using the primitive and vertex data generated by the vertex processor 1905. In at least one embodiment, the fragment processors 1915A-1915N are optimized to execute fragment shader programs provided in an OpenGL API, which may be used to perform operations similar to pixel shader programs provided in a Direct 3D API.

[0277] In at least one embodiment, the graphics processor 1910 further includes one or more memory management units (MMUs) 1920A-1920B, caches 1925A-1925B, and circuit interconnects 1930A-1930B. In at least one embodiment, the one or more MMUs 1920A-1920B provide virtual-to-physical address mapping for the graphics processor 1910, including the vertex processor 1905 and / or fragment processors 1915A-1915N, which may reference vertex or image / text data stored in memory in addition to vertex or image / text data stored in one or more caches 1925A-1925B. In at least one embodiment, one or more MMUs 1920A-1920B may be synchronized with other MMUs in the system, including one or more MMUs associated with one or more application processors 1805, image processor 1815, and / or video processor 1820 of FIG. 18, such that each processor 1805-1820 may participate in a shared or unified virtual memory system. In at least one embodiment, one or more circuit interconnects 1930A-1930B enable the graphics processor 1910 to interface with other IP cores in the SoC via an internal bus of the SoC or via a direct connection.

[0278] In at least one embodiment, as shown in FIG. 19B, the graphics processor 1940 includes one or more shader cores 1955A-1955N (e.g., 1955A, 1955B, 1955C, 1955D, 1955E, 1955F-1955N-1, and 1955N) that provide a unified shader core architecture in which a single core, or type, or cores can execute all types of programmable shader code, including shader program code for implementing vertex shaders, fragment shaders, and / or compute shaders. In at least one embodiment, the number of shader cores can vary. In at least one embodiment, the graphics processor 1940 includes an inter-core task manager 1945 that acts as a thread dispatcher for dispatching execution threads to one or more shader cores 1955A-1955N, and a tiling unit 1958 for accelerating tiling operations for tile-based rendering, where rendering operations of a scene are subdivided in image space, e.g., to exploit local spatial coherence within a scene or to optimize internal cache usage.

[0279] Inference and / or training logic 915 is used to perform inference and / or training operations associated with one or more embodiments. More details regarding the inference and / or training logic 915 are provided herein in conjunction with Figures 9A and / or 9B. In at least one embodiment, the inference and / or training logic 915 may be used in the integrated circuit of Figures 19A and / or 19B for inference or prediction operations based at least in part on weight parameters calculated using neural network training operations, neural network functionality and / or architecture, or neural network use cases described herein.

[0280] In at least one embodiment, an application programming interface is adapted to receive an application programming interface call including a graph definition and a recursion attribute in association with the diagram, and to execute a recursive neural network based on the graph definition.

[0281] Figures 20A and 20B illustrate further exemplary graphics processor logic according to embodiments described herein. Figure 20A illustrates a graphics core 2000, which in at least one embodiment may be included in graphics processor 1810 of Figure 18, or in at least one embodiment may be integrated shader cores 1955A-1955N as in Figure 19B. Figure 20B illustrates a highly parallel general purpose graphics processing unit ("GPGPU") 2030 suitable for incorporation into a multi-chip module in at least one embodiment.

[0282] In at least one embodiment, graphics core 2000 includes a shared instruction cache 2002, a texture unit 2018, and a cache / shared memory 2020, which are common to execution resources within graphics core 2000. In at least one embodiment, graphics core 2000 may include multiple slices 2001A-2001N, or partitions per core, and a graphics processor may include multiple instances of graphics core 2000. In at least one embodiment, slices 2001A-2001N may include supporting logic including local instruction caches 2004A-2004N, thread schedulers 2006A-2006N, thread dispatchers 2008A-2008N, and sets of registers 2010A-2010N. In at least one embodiment, slices 2001A-2001N may include a set of additional functional units (AFUs 2012A-2012N), floating point units (FPUs 2014A-2014N), integer arithmetic logic units (ALUs 2016A-2016N), address calculation units (ACUs 2013A-2013N), double precision floating point units (DPFPUs 2015A-2015N), and matrix processing units (MPUs 2017A-2017N).

[0283] In at least one embodiment, the FPUs 2014A-2014N can perform single precision (32-bit) and half precision (16-bit) floating point operations, while the DPFPUs 2015A-2015N perform double precision (64-bit) floating point operations. In at least one embodiment, the ALUs 2016A-2016N can perform variable precision integer operations with 8-bit, 16-bit, and 32-bit precision and can be configured for mixed precision operations. In at least one embodiment, the MPUs 2017A-2017N can also be configured for mixed precision matrix operations, including half precision floating point and 8-bit integer operations. In at least one embodiment, the MPUs 2017-2017N can perform various matrix operations for accelerating machine learning application frameworks, including being able to support acceleration of general matrix-matrix multiplication (GEMM). In at least one embodiment, the AFUs 2012A-2012N can perform additional logical operations not supported by the floating-point or integer units, including trigonometric operations (e.g., sine, cosine, etc.).

[0284] Inference and / or training logic 915 is used to perform inference and / or training operations associated with one or more embodiments. More details regarding inference and / or training logic 915 are provided herein in conjunction with FIGURES 9A and / or 9B. In at least one embodiment, inference and / or training logic 915 may be used in graphics core 2000 for inference or prediction operations based at least in part on weight parameters calculated using neural network training operations, neural network functionality and / or architecture, or neural network use cases described herein.

[0285] In at least one embodiment, an application programming interface is adapted to receive an application programming interface call including a graph definition and a recursion attribute in association with the diagram, and to execute a recursive neural network based on the graph definition.

[0286] FIG. 20B illustrates a general purpose processing unit (GPGPU) 2030, which in at least one embodiment can be configured to enable highly parallel computational operations by an array of graphics processing units. In at least one embodiment, the GPGPU 2030 can be directly linked to other instances of the GPGPU 2030 to create multiple GPU clusters to improve training speed for deep neural networks. In at least one embodiment, the GPGPU 2030 includes a host interface 2032 to enable connection to a host processor. In at least one embodiment, the host interface 2032 is a PCI Express interface. In at least one embodiment, the host interface 2032 can be a vendor-specific communications interface or fabric. In at least one embodiment, the GPGPU 2030 receives commands from the host processor and distributes execution threads associated with those commands to a set of compute clusters 2036A-2036H using a global scheduler 2034. In at least one embodiment, the compute clusters 2036A-2036H share a cache memory 2038. In at least one embodiment, the cache memory 2038 can act as a higher level cache for the cache memories in the compute clusters 2036A-2036H.

[0287] In at least one embodiment, the GPGPU 2030 includes memory 2044A-2044B coupled to the compute clusters 2036A-2036H via a set of memory controllers 2042A-2042B. In at least one embodiment, the memory 2044A-2044B can include various types of memory devices, including dynamic random access memory (DRAM) or graphics random access memory, such as synchronous graphics random access memory (SGRAM), including graphics double data rate (GDDR) memory.

[0288] In at least one embodiment, each of the compute clusters 2036A-2036H includes a set of graphics cores, such as graphics core 2000 of FIG. 20A, that may include multiple types of integer and floating point logic units capable of performing computational operations with various precisions, including those suitable for machine learning computations. For example, in at least one embodiment, at least a subset of the floating point units in each of the compute clusters 2036A-2036H may be configured to perform 16-bit or 32-bit floating point operations, while another subset of the floating point units may be configured to perform 64-bit floating point operations.

[0289] In at least one embodiment, multiple instances of GPGPU 2030 can be configured to operate as a compute cluster. In at least one embodiment, the communications used by compute clusters 2036A-2036H for synchronization and data exchange vary across embodiments. In at least one embodiment, multiple instances of GPGPU 2030 communicate through host interface 2032. In at least one embodiment, GPGPU 2030 includes an I / O hub 2039 that couples GPGPU 2030 to GPU links 2040 that allow direct connections to other instances of GPGPU 2030. In at least one embodiment, GPU links 2040 are coupled to a dedicated GPU-to-GPU bridge that allows communication and synchronization between multiple instances of GPGPU 2030. In at least one embodiment, GPU links 2040 are coupled to a high-speed interconnect for sending and receiving data to other GPGPUs or parallel processors. In at least one embodiment, multiple instances of GPGPU 2030 are located in separate data processing systems and communicate via a network device accessible via host interface 2032. In at least one embodiment, GPU link 2040 can be configured to allow connection to a host processor in addition to, or instead of, host interface 2032.

[0290] In at least one embodiment, the GPGPU 2030 can be configured to train a neural network. In at least one embodiment, the GPGPU 2030 can be used within an inference platform. In at least one embodiment, where the GPGPU 2030 is used for inference, the GPGPU 2030 may include fewer compute clusters 2036A-H than when the GPGPU 2030 is used to train a neural network. In at least one embodiment, the memory technology associated with the memories 2044A-B may differ between the inference configuration and the training configuration, with a high bandwidth memory technology being devoted to the training configuration. In at least one embodiment, the inference configuration of the GPGPU 2030 may support inference specific instructions. For example, in at least one embodiment, the inference configuration may support one or more 8-bit integer dot product instructions, which may be used during inference operations of the deployed neural network.

[0291] Inference and / or training logic 915 is used to perform inference and / or training operations associated with one or more embodiments. More details regarding the inference and / or training logic 915 are provided herein in conjunction with Figures 9A and / or 9B. In at least one embodiment, the inference and / or training logic 915 may be used in the GPGPU 2030 for inference or prediction operations based at least in part on weight parameters calculated using neural network training operations, neural network functionality and / or architecture, or neural network use cases described herein.

[0292] In at least one embodiment, an application programming interface is adapted to receive an application programming interface call including a graph definition and a recursion attribute in association with the diagram, and to execute a recursive neural network based on the graph definition.

[0293] 21 is a block diagram illustrating a computing system 2100 according to at least one embodiment. In at least one embodiment, the computing system 2100 includes a processing subsystem 2101 having one or more processors 2102 and a system memory 2104 that communicate via an interconnect path that may include a memory hub 2105. In at least one embodiment, the memory hub 2105 may be a separate component within a chipset component or may be integrated within the one or more processors 2102. In at least one embodiment, the memory hub 2105 is coupled to an I / O subsystem 2111 via a communication link 2106. In at least one embodiment, the I / O subsystem 2111 includes an I / O hub 2107 that can enable the computing system 2100 to receive input from one or more input devices 2108. In at least one embodiment, the I / O hub 2107 can enable a display controller, which may be included in the one or more processors 2102 and provide output to one or more display devices 2110A. In at least one embodiment, the one or more display devices 2110A coupled to the I / O hub 2107 can include local, internal, or embedded display devices.

[0294] In at least one embodiment, the processing subsystem 2101 includes one or more parallel processors 2112 coupled to the memory hub 2105 via a bus or other communication link 2113. In at least one embodiment, the communication link 2113 may use one of any number of standard based communication link technologies or protocols, such as, but not limited to, PCI Express, or may be a vendor-specific communication interface or fabric. In at least one embodiment, the one or more parallel processors 2112 form a computationally intensive parallel or vector processing system that may include multiple processing cores and / or processing clusters, such as a many integrated core (MIC) processor. In at least one embodiment, some or all of the parallel processors 2112 form a graphics processing subsystem that may output pixels to one of one or more display devices 2110A coupled via the I / O hub 2107. In at least one embodiment, the parallel processors 2112 may also include a display controller and display interface (not shown) that allows for direct connection to one or more display devices 2110B.

[0295] In at least one embodiment, a system storage unit 2114 may be connected to the I / O hub 2107 to provide a storage mechanism for the computing system 2100. In at least one embodiment, an I / O switch 2116 may be used to provide an interface mechanism to enable communication between the I / O hub 2107 and other components, such as a network adapter 2118 and / or a wireless network adapter 2119, which may be integrated into the platform, as well as various other devices that may be added via one or more add-in devices 2120. In at least one embodiment, the network adapter 2118 may be an Ethernet adapter or another wired network adapter. In at least one embodiment, the wireless network adapter 2119 may include one or more of Wi-Fi, Bluetooth, Near Field Communication (NFC), or other network devices including one or more wireless radios.

[0296] In at least one embodiment, computing system 2100 can include other components not shown, including USB or other port connections, optical storage drives, video capture devices, etc., which may also be connected to I / O hub 2107. In at least one embodiment, the communication paths interconnecting the various components of FIG. 21 may be implemented using any suitable protocol, such as a Peripheral Component Interconnect (PCI) based protocol (e.g., PCI-Express), or other bus or point-to-point communication interface and / or protocol, such as the NV-Link high speed interconnect, or interconnection protocol.

[0297] In at least one embodiment, the parallel processor 2112 incorporates circuitry optimized for graphics and video processing, including, for example, video output circuitry, forming a graphics processing unit (GPU). In at least one embodiment, the parallel processor 2112 incorporates circuitry optimized for general purpose processing. In at least one embodiment, the components of the computing system 2100 may be integrated with one or more other system elements on a single integrated circuit. For example, in at least one embodiment, the parallel processor 2112, the memory hub 2105, the processor 2102, and the I / O hub 2107 may be integrated into a system-on-chip (SoC) integrated circuit. In at least one embodiment, the components of the computing system 2100 may be integrated into a single package to form a system in package (SIP) configuration. In at least one embodiment, at least a portion of the components of computing system 2100 can be integrated into a multi-chip module (MCM), which can be interconnected with other multi-chip modules to form a modular computing system.

[0298] Inference and / or training logic 915 is used to perform inference and / or training operations associated with one or more embodiments. More details regarding the inference and / or training logic 915 are provided herein in conjunction with Figures 9A and / or 9B. In at least one embodiment, the inference and / or training logic 915 may be used in the system of Figure 2100 for inference or prediction operations based at least in part on weight parameters calculated using neural network training operations, neural network functionality and / or architecture, or neural network use cases described herein.

[0299] In at least one embodiment, an application programming interface is adapted to receive an application programming interface call including a graph definition and a recursion attribute in association with the diagram, and to execute a recursive neural network based on the graph definition.

[0300] Processor 22A illustrates a parallel processor 2200 according to at least one embodiment. In at least one embodiment, various components of the parallel processor 2200 may be implemented using one or more integrated circuit devices, such as a programmable processor, an application specific integrated circuit (ASIC), or a field programmable gate array (FPGA). In at least one embodiment, the illustrated parallel processor 2200 is a variation of the one or more parallel processors 2112 shown in FIG. 21 according to an example embodiment.

[0301] In at least one embodiment, parallel processor 2200 includes parallel processing units 2202. In at least one embodiment, parallel processing units 2202 include I / O units 2204 that enable communication with other devices, including other instances of parallel processing units 2202. In at least one embodiment, I / O units 2204 may be directly connected to other devices. In at least one embodiment, I / O units 2204 are connected to other devices through the use of a hub or switch interface, such as memory hub 2205. In at least one embodiment, the connection between memory hub 2205 and I / O units 2204 forms communication link 2213. In at least one embodiment, I / O units 2204 are connected to host interface 2206 and memory crossbar 2216, where host interface 2206 receives commands directed to the execution of processing operations and memory crossbar 2216 receives commands directed to the execution of memory operations.

[0302] In at least one embodiment, when the host interface 2206 receives command buffers via the I / O unit 2204, the host interface 2206 can direct work operations to the front end 2208 to execute these commands. In at least one embodiment, the front end 2208 is coupled to a scheduler 2210, which is configured to distribute commands or other work items to the processing cluster array 2212. In at least one embodiment, the scheduler 2210 ensures that the processing cluster array 2212 is properly configured and in a valid state before tasks are distributed to the clusters of the processing cluster array 2212. In at least one embodiment, the scheduler 2210 is implemented via firmware logic running on a microcontroller. In at least one embodiment, the microcontroller-implemented scheduler 2210 can be configured to perform complex scheduling and work distribution operations at both coarse and fine granularity, allowing for rapid preemption and context switching of threads running in the processing array 2212. In at least one embodiment, host software can initiate scheduling workload on processing cluster array 2212 via one of multiple graphics processing paths. In at least one embodiment, the workload can then be automatically distributed across processing cluster array 2212 by scheduler 2210 logic in a microcontroller that includes scheduler 2210.

[0303] In at least one embodiment, the processing cluster array 2212 may include up to “N” processing clusters (e.g., cluster 2214A, cluster 2214B through cluster 2214N), where “N” represents a positive integer (which may be a different integer “N” than that used in other figures). In at least one embodiment, each cluster 2214A through 2214N of the processing cluster array 2212 may be capable of executing a large number of concurrent threads. In at least one embodiment, the scheduler 2210 may allocate work to the clusters 2214A through 2214N of the processing cluster array 2212 using various scheduling and / or work distribution algorithms, which may vary depending on the workload incurred by each program or type of computation. In at least one embodiment, the scheduling may be dynamically addressed by the scheduler 2210, or may be assisted in part by compiler logic during compilation of program logic configured to be executed by the processing cluster array 2212. In at least one embodiment, different clusters 2214A-2214N of processing cluster array 2212 may be allocated to process different types of programs or perform different types of calculations.

[0304] In at least one embodiment, processing cluster array 2212 may be configured to perform various types of parallel processing operations. In at least one embodiment, processing cluster array 2212 may be configured to perform general-purpose parallel compute operations. For example, in at least one embodiment, processing cluster array 2212 may include logic for performing processing tasks including filtering video and / or audio data, performing modeling operations including physics operations, and performing data transformations.

[0305] In at least one embodiment, the processing cluster array 2212 is configured to perform parallel graphics processing operations. In at least one embodiment, the processing cluster array 2212 may include additional logic to support the execution of such graphics processing operations, including, but not limited to, texture sampling logic for performing texture operations, as well as mosaic logic and other vertex processing logic. In at least one embodiment, the processing cluster array 2212 may be configured to execute graphics processing related shader programs, such as, but not limited to, vertex shaders, mosaic shaders, geometry shaders, and pixel shaders. In at least one embodiment, the parallel processing units 2202 may transfer data from system memory via the I / O units 2204 for processing. In at least one embodiment, the transferred data may be stored in on-chip memory (e.g., parallel processor memory 2222) during processing and then written back to the system memory.

[0306] In at least one embodiment, when graphics processing is performed using parallel processing units 2202, scheduler 2210 may be configured to divide the processing workload into roughly equal sized tasks to better distribute graphics processing operations among multiple clusters 2214A-2214N of processing cluster array 2212. In at least one embodiment, portions of processing cluster array 2212 may be configured to perform different types of processing. For example, in at least one embodiment, to generate and display a rendered image, a first portion may be configured to perform vertex shading and topology generation, a second portion may be configured to perform mosaic and geometry shading, and a third portion may be configured to perform pixel shading or other screen space operations. In at least one embodiment, intermediate data generated by one or more of clusters 2214A-2214N may be stored in a buffer so that the intermediate data can be transmitted between clusters 2214A-2214N for further processing.

[0307] In at least one embodiment, the processing cluster array 2212 can receive processing tasks to be performed via a scheduler 2210, which receives commands from the front end 2208 defining the processing tasks. In at least one embodiment, a processing task can include an index of the data to be processed, e.g., surface (patch) data, primitive data, vertex data, and / or pixel data, as well as state parameters and commands defining how the data should be processed (e.g., which program to execute). In at least one embodiment, the scheduler 2210 can be configured to fetch an index corresponding to the task or can receive the index from the front end 2208. In at least one embodiment, the front end 2208 can be configured to ensure that the processing cluster array 2212 is configured in a valid state before a workload specified by an incoming command buffer (e.g., a batch buffer, a push buffer, etc.) is initiated.

[0308] In at least one embodiment, each of one or more instances of parallel processing unit 2202 can be coupled to a parallel processor memory 2222. In at least one embodiment, parallel processor memory 2222 can be accessed via memory crossbar 2216, which can receive memory requests from processing cluster array 2212 as well as I / O unit 2204. In at least one embodiment, memory crossbar 2216 can access parallel processor memory 2222 via memory interface 2218. In at least one embodiment, memory interface 2218 can include multiple partition units (e.g., partition unit 2220A, partition unit 2220B through partition unit 2220N), each of which can be coupled to a portion (e.g., a memory unit) of parallel processor memory 2222. In at least one embodiment, the number of partition units 2220A-2220N is configured to be equal to the number of memory units, such that a first partition unit 2220A has a corresponding first memory unit 2224A, a second partition unit 2220B has a corresponding memory unit 2224B, and an Nth partition unit 2220N has a corresponding Nth memory unit 2224N. In at least one embodiment, the number of partition units 2220A-2220N does not have to be equal to the number of memory devices.

[0309] In at least one embodiment, the memory units 2224A-2224N may include various types of memory devices, including dynamic random access memory (DRAM) or graphics random access memory, such as synchronous graphics random access memory (SGRAM), including graphics double data rate (GDDR) memory. In at least one embodiment, the memory units 2224A-2224N may also include 3D stacked memory, including but not limited to high bandwidth memory (HBM). In at least one embodiment, to efficiently use the available bandwidth of the parallel processor memory 2222, render targets, such as frame buffers or texture maps, may be stored across the memory units 2224A-2224N, allowing the partition units 2220A-2220N to write portions of each render target in parallel. In at least one embodiment, local instances of the parallel processor memory 2222 may be omitted in favor of a unified memory design that uses a combination of system memory and local cache memory.

[0310] In at least one embodiment, any one of the clusters 2214A-2214N of the processing cluster array 2212 can process data that is to be written to any one of the memory units 2224A-2224N in the parallel processor memory 2222. In at least one embodiment, the memory crossbar 2216 can be configured to forward the output of each cluster 2214A-2214N to any partition unit 2220A-2220N or to another cluster 2214A-2214N that can perform further processing operations on the output. In at least one embodiment, each cluster 2214A-2214N can communicate with a memory interface 2218 through the memory crossbar 2216 to read from or write to various external memory devices. In at least one embodiment, memory crossbar 2216 has connections to memory interfaces 2218 for communicating with I / O units 2204, as well as connections to local instances of parallel processor memory 2222 to allow processing units in different processing clusters 2214A-2214N to communicate with system memory or other memory that is not local to the parallel processing units 2202. In at least one embodiment, memory crossbar 2216 can use virtual channels to separate traffic streams between clusters 2214A-2214N and partition units 2220A-2220N.

[0311] In at least one embodiment, multiple instances of parallel processing unit 2202 may be provided on a single add-in card, or multiple add-in cards may be interconnected. In at least one embodiment, different instances of parallel processing unit 2202 may be configured to interoperate, even if the different instances have different numbers of processing cores, different amounts of local parallel processor memory, and / or other different configurations. For example, in at least one embodiment, some instances of parallel processing unit 2202 may include higher precision floating point units than other instances. In at least one embodiment, systems incorporating one or more instances of parallel processing unit 2202 or parallel processor 2200 may be implemented in a variety of configurations and form factors, including, but not limited to, desktop, laptop, or portable personal computers, servers, workstations, game consoles, and / or embedded systems.

[0312] FIG. 22B is a block diagram of a partition unit 2220 according to at least one embodiment. In at least one embodiment, partition unit 2220 is an instance of one of partition units 2220A-2220N of FIG. 22A. In at least one embodiment, partition unit 2220 includes an L2 cache 2221, a frame buffer interface 2225, and a raster operations unit (ROP) 2226. In at least one embodiment, L2 cache 2221 is a read / write cache configured to execute load and store operations received from memory crossbar 2216 and ROP 2226. In at least one embodiment, read misses and urgent writeback requests are output by L2 cache 2221 to frame buffer interface 2225 to be processed. In at least one embodiment, updates are also sent to the frame via frame buffer interface 2225 to be processed. In at least one embodiment, frame buffer interface 2225 interfaces with one of the memory units of a parallel processor memory, such as memory units 2224A-2224N (eg, in parallel processor memory 2222) of FIG.

[0313] In at least one embodiment, ROP2226 is a processing unit that performs raster operations such as stencil, z-test, blending, etc. In at least one embodiment, ROP2226 then outputs the processed graphics data stored in graphics memory. In at least one embodiment, ROP2226 includes compression logic for compressing depth or color data written to memory and decompressing depth or color data read from memory. In at least one embodiment, the compression logic may be lossless compression logic that utilizes one or more of a number of compression algorithms. In at least one embodiment, the type of compression performed by ROP2226 may vary based on statistical characteristics of the data being compressed. For example, in at least one embodiment, delta color compression is performed on the depth and color data on a tile-by-tile basis.

[0314] In at least one embodiment, ROP 2226 is included within each processing cluster (e.g., clusters 2214A-2214N of FIG. 22A ) rather than within partition unit 2220. In at least one embodiment, read and write requests for pixel data, rather than pixel fragment data, are transmitted through memory crossbar 2216. In at least one embodiment, the processed graphics data may be displayed on a display device, such as one of one or more display devices 2110 of FIG. 21 , may be routed for further processing by processor 2102, or may be routed for further processing by one of the processing entities in parallel processor 2200 of FIG. 22A .

[0315] FIG. 22C is a block diagram of a processing cluster 2214 in a parallel processing unit according to at least one embodiment. In at least one embodiment, the processing cluster is an instance of one of the processing clusters 2214A-2214N of FIG. 22A. In at least one embodiment, the processing cluster 2214 may be configured to execute multiple threads in parallel, where a "thread" refers to an instance of a particular program executing on a particular set of input data. In at least one embodiment, single-instruction, multiple-data (SIMD) instruction issue techniques are used to support parallel execution of multiple threads without providing multiple independent instruction units. In at least one embodiment, single-instruction, multiple-thread (SIMT) techniques are used to support parallel execution of multiple threads that are generally synchronized using a common instruction unit configured to issue instructions to a set of processing engines in each processing cluster.

[0316] In at least one embodiment, the operation of the processing clusters 2214 may be controlled via a pipeline manager 2232 that distributes processing tasks to the SIMT parallel processors. In at least one embodiment, the pipeline manager 2232 receives instructions from the scheduler 2210 of FIG. 22A and manages the execution of those instructions via the graphics multiprocessor 2234 and / or the texture unit 2236. In at least one embodiment, the graphics multiprocessor 2234 is an exemplary instance of a SIMT parallel processor. However, in at least one embodiment, various types of SIMT parallel processors with different architectures may be included in the processing clusters 2214. In at least one embodiment, one or more instances of the graphics multiprocessor 2234 may be included in the processing clusters 2214. In at least one embodiment, the graphics multiprocessor 2234 may process data, and a data crossbar 2240 may be used to distribute the processed data to one of several possible destinations, including other shader units. In at least one embodiment, pipeline manager 2232 can facilitate distribution of the processed data by specifying destinations for the processed data to be distributed through data crossbar 2240.

[0317] In at least one embodiment, each graphics multiprocessor 2234 in a processing cluster 2214 may include an identical set of function execution logic (e.g., arithmetic logic units, load store units, etc.). In at least one embodiment, the function execution logic may be configured in a pipelined manner such that new instructions can be issued before previous instructions are completed. In at least one embodiment, the function execution logic supports a variety of operations including integer and floating point arithmetic, comparison operations, Boolean operations, bit shifts, and calculation of various algebraic functions. In at least one embodiment, the same functional unit hardware may be utilized to perform different operations, and any combination of functional units may be present.

[0318] In at least one embodiment, instructions sent to processing cluster 2214 constitute threads. In at least one embodiment, a set of threads executing across a set of parallel processing engines is a thread group. In at least one embodiment, the thread groups execute a common program on different input data. In at least one embodiment, each thread in a thread group can be assigned to a different processing engine in graphics multiprocessor 2234. In at least one embodiment, a thread group may include fewer threads than the number of processing engines in graphics multiprocessor 2234. In at least one embodiment, if a thread group includes fewer threads than the number of processing engines, one or more of the processing engines may be idle during a cycle in which the thread group is being processed. In at least one embodiment, a thread group may also include more threads than the number of processing engines in graphics multiprocessor 2234. In at least one embodiment, if a thread group includes more threads than the number of processing engines in graphics multiprocessor 2234, processing may be performed over consecutive clock cycles. In at least one embodiment, multiple thread groups may be executed simultaneously on graphics multiprocessor 2234.

[0319] In at least one embodiment, the graphics multiprocessor 2234 includes an internal cache memory for performing load and store operations. In at least one embodiment, the graphics multiprocessor 2234 can forego the internal cache and use a cache memory (e.g., L1 cache 2248) in the processing cluster 2214. In at least one embodiment, each graphics multiprocessor 2234 can also access an L2 cache in a partition unit (e.g., partition units 2220A-2220N in FIG. 22A), which may be shared among all processing clusters 2214 and used to transfer data between threads. In at least one embodiment, the graphics multiprocessor 2234 can also access an off-chip global memory, which may include one or more of the local parallel processor memories and / or system memories. In at least one embodiment, any memory external to the parallel processing units 2202 may be used as global memory. In at least one embodiment, processing cluster 2214 may include multiple instances of graphics multiprocessor 2234 and share common instructions and data, which may be stored in L1 cache 2248.

[0320] In at least one embodiment, each processing cluster 2214 may include a memory management unit (MMU) 2245 configured to map virtual addresses to physical addresses. In at least one embodiment, one or more instances of MMU 2245 may be in memory interface 2218 of FIG. 22A. In at least one embodiment, MMU 2245 includes a set of page table entries (PTEs) used to map virtual addresses to physical addresses of tiles and optionally cache line indexes. In at least one embodiment, MMU 2245 may include a translation lookaside buffer (TLB) or cache of addresses, which may be in the graphics multiprocessor 2234 or L1 2248 caches, or in the processing cluster 2214. In at least one embodiment, physical addresses are processed to locally distribute surface data accesses, allowing efficient interleaving of requests across partition units. In at least one embodiment, the cache line index may be used to determine whether a request for a cache line is a hit or a miss.

[0321] In at least one embodiment, the processing clusters 2214 may be configured such that each graphics multiprocessor 2234 is coupled to a texture unit 2236 to perform texture mapping operations, such as determining texture sample locations, reading texture data, and filtering the texture data. In at least one embodiment, texture data is read from an internal texture L1 cache (not shown) or from an L1 cache in the graphics multiprocessor 2234 and fetched from an L2 cache, local parallel processor memory, or system memory as needed. In at least one embodiment, each graphics multiprocessor 2234 outputs processed tasks to the data crossbar 2240 to provide the processed tasks to another processing cluster 2214 for further processing, or stores the processed tasks in the L2 cache, local parallel processor memory, or system memory via the memory crossbar 2216. In at least one embodiment, a pre-ROP 2242 (pre-raster operation unit) is configured to receive data from the graphics multiprocessor 2234 and direct the data to a ROP unit, which may be located within a partition unit (e.g., partition units 2220A-2220N of FIG. 22A ), as described herein. In at least one embodiment, the pre-ROP 2242 unit can perform color blending optimizations, organize pixel color data, and perform address translation.

[0322] Inference and / or training logic 915 is used to perform inference and / or training operations associated with one or more embodiments. More details regarding the inference and / or training logic 915 are provided herein in conjunction with Figures 9A and / or 9B. In at least one embodiment, the inference and / or training logic 915 may be used in the graphics processing cluster 2214 for inference or prediction operations based at least in part on weight parameters calculated using neural network training operations, neural network functionality and / or architecture, or neural network use cases described herein.

[0323] In at least one embodiment, an application programming interface is adapted to receive an application programming interface call including a graph definition and a recursion attribute in association with the diagram, and to execute a recursive neural network based on the graph definition.

[0324] 22D illustrates a graphics multiprocessor 2234 according to at least one embodiment. In at least one embodiment, the graphics multiprocessor 2234 couples with a pipeline manager 2232 of the processing cluster 2214. In at least one embodiment, the graphics multiprocessor 2234 has an execution pipeline including, but not limited to, an instruction cache 2252, an instruction unit 2254, an address mapping unit 2256, a register file 2258, one or more general purpose graphics processing unit (GPGPU) cores 2262, and one or more load / store units 2266. In at least one embodiment, the GPGPU cores 2262 and the load / store units 2266 are coupled to a cache memory 2272 and a shared memory 2270 via a memory and cache interconnect 2268.

[0325] In at least one embodiment, instruction cache 2252 receives a stream of instructions to be executed from pipeline manager 2232. In at least one embodiment, instructions are cached in instruction cache 2252 and dispatched for execution by instruction unit 2254. In at least one embodiment, instruction unit 2254 can dispatch instructions as thread groups (e.g., warps), with each thread of a thread group being assigned to a different execution unit in GPGPU core 2262. In at least one embodiment, instructions can access either local, shared, or global address spaces by specifying an address in the unified address space. In at least one embodiment, address mapping unit 2256 can be used to translate addresses in the unified address space into individual memory addresses accessible by load / store unit 2266.

[0326] In at least one embodiment, register file 2258 provides a set of registers to the functional units of graphics multiprocessor 2234. In at least one embodiment, register file 2258 provides temporary storage for operands connected to the data paths of the functional units (e.g., GPGPU cores 2262, load / store unit 2266) of graphics multiprocessor 2234. In at least one embodiment, register file 2258 is partitioned among the respective functional units such that each functional unit is allocated a dedicated portion of register file 2258. In one embodiment, register file 2258 is partitioned among the different warps being executed by graphics multiprocessor 2234.

[0327] In at least one embodiment, GPGPU cores 2262 may each include a floating point unit (FPU) and / or an integer arithmetic logic unit (ALU) used to execute instructions for graphics multiprocessor 2234. In at least one embodiment, GPGPU cores 2262 may be of similar architecture or may be of different architectures. In at least one embodiment, a first portion of GPGPU cores 2262 includes a single precision FPU and an integer ALU, and a second portion of GPGPU cores includes a double precision FPU. In at least one embodiment, the FPU may implement IEEE 754-2008 standard floating point arithmetic or may enable variable precision floating point arithmetic. In at least one embodiment, graphics multiprocessor 2234 may further include one or more fixed function units or special function units for performing specific functions, such as rectangle copy or pixel blending operations. In at least one embodiment, one or more of GPGPU cores 2262 may also include fixed or special function logic.

[0328] In at least one embodiment, GPGPU core 2262 includes SIMD logic capable of executing a single instruction on multiple data sets. In at least one embodiment, GPGPU core 2262 can physically execute SIMD4, SIMD8, and SIMD16 instructions and logically execute SIMD1, SIMD2, and SIMD32 instructions. In at least one embodiment, SIMD instructions for the GPGPU core may be generated at compile time by a shader compiler or may be generated automatically when executing a program written and compiled for a single program multiple data (SPMD) or SIMT architecture. In at least one embodiment, multiple threads of a program configured for a SIMT execution model may be executed via a single SIMD instruction. For example, in at least one embodiment, eight SIMT threads performing the same or similar operations may be executed in parallel via a single SIMD8 logical unit.

[0329] In at least one embodiment, memory and cache interconnect 2268 is an interconnect network connecting each functional unit of graphics multiprocessor 2234 to register file 2258 and shared memory 2270. In at least one embodiment, memory and cache interconnect 2268 is a crossbar interconnect that allows load / store unit 2266 to implement load and store operations between shared memory 2270 and register file 2258. In at least one embodiment, register file 2258 can operate at the same frequency as GPGPU core 2262, and therefore data transfers between GPGPU core 2262 and register file 2258 can have very low latency. In at least one embodiment, shared memory 2270 can be used to enable communication between threads executing in functional units within graphics multiprocessor 2234. In at least one embodiment, cache memory 2272 can be used, for example, as a data cache to cache texture data communicated between the functional units and texture unit 2236. In at least one embodiment, shared memory 2270 can also be used as a program-managed cache. In at least one embodiment, threads executing on GPGPU cores 2262 can programmatically store data in the shared memory in addition to automatically caching data stored in cache memory 2272.

[0330] In at least one embodiment, a parallel processor or GPGPU as described herein is communicatively coupled to a host / processor core to accelerate graphics operations, machine learning operations, pattern analysis operations, and various general purpose GPU (GPGPU) functions. In at least one embodiment, the GPU may be communicatively coupled to the host processor / core via a bus or other interconnect (e.g., a high speed interconnect such as PCIe or NVLink). In at least one embodiment, the GPU may be integrated into a package or chip as a core, or may be communicatively coupled to the core via an internal processor bus / interconnect inside the package or chip. In at least one embodiment, regardless of how the GPU is connected, the processor core may allocate work to such GPU in the form of a sequence of commands / instructions contained in a work descriptor. In at least one embodiment, the GPU then uses dedicated circuitry / logic to efficiently process these commands / instructions.

[0331] Inference and / or training logic 915 is used to perform inference and / or training operations associated with one or more embodiments. More details regarding inference and / or training logic 915 are provided herein in conjunction with Figures 9A and / or 9B. In at least one embodiment, inference and / or training logic 915 may be used in graphics multiprocessor 2234 for inference or prediction operations based at least in part on weight parameters calculated using neural network training operations, neural network functionality and / or architecture, or neural network use cases described herein.

[0332] In at least one embodiment, an application programming interface is adapted to receive an application programming interface call including a graph definition and a recursion attribute in association with the diagram, and to execute a recursive neural network based on the graph definition.

[0333] FIG. 23 illustrates a multi-GPU computing system 2300, according to at least one embodiment. In at least one embodiment, the multi-GPU computing system 2300 can include a processor 2302 coupled to a plurality of general purpose graphics processing units (GPGPUs) 2306A-2306D via a host interface switch 2304. In at least one embodiment, the host interface switch 2304 is a PCI Express switch device that couples the processor 2302 to a PCI Express bus via which the processor 2302 can communicate with the GPGPUs 2306A-2306D. In at least one embodiment, the GPGPUs 2306A-2306D can be interconnected via a set of high speed point-to-point GPU-to-GPU links 2316. In at least one embodiment, the GPU-to-GPU links 2316 are connected to each of the GPGPUs 2306A-2306D via dedicated GPU links. In at least one embodiment, the P2P GPU link 2316 allows direct communication between each of the GPGPUs 2306A-2306D without requiring communication via the host interface bus 2304 to which the processor 2302 is connected. In at least one embodiment, when there is GPU-to-GPU traffic directed to the P2P GPU link 2316, the host interface bus 2304 remains available to allow access to system memory or to communicate with other instances of the multi-GPU computing system 2300, for example, via one or more network devices. In at least one embodiment, the GPGPUs 2306A-2306D are connected to the processor 2302 via the host interface switch 2304, and in at least one embodiment, the processor 2302 includes direct support for the P2P GPU link 2316 and can be directly connected to the GPGPUs 2306A-2306D.

[0334] Inference and / or training logic 915 is used to perform inference and / or training operations associated with one or more embodiments. More details regarding the inference and / or training logic 915 are provided herein in conjunction with Figures 9A and / or 9B. In at least one embodiment, the inference and / or training logic 915 may be used in the multi-GPU computing system 2300 for inference or prediction operations based at least in part on weight parameters calculated using neural network training operations, neural network functionality and / or architecture, or neural network use cases described herein.

[0335] In at least one embodiment, an application programming interface is adapted to receive an application programming interface call including a graph definition and a recursion attribute in association with the diagram, and to execute a recursive neural network based on the graph definition.

[0336] 24 is a block diagram of a graphics processor 2400, according to at least one embodiment. In at least one embodiment, graphics processor 2400 includes a ring interconnect 2402, a pipeline front end 2404, a media engine 2437, and graphics cores 2480A-2480N. In at least one embodiment, ring interconnect 2402 couples graphics processor 2400 to other processing units, including other graphics processors or one or more general-purpose processor cores. In at least one embodiment, graphics processor 2400 is one of many processors integrated within a multi-core processing system.

[0337] In at least one embodiment, graphics processor 2400 receives batches of commands via ring interconnect 2402. In at least one embodiment, the incoming commands are interpreted by command streamer 2403 in pipeline front end 2404. In at least one embodiment, graphics processor 2400 includes scalable execution logic for performing 3D geometry processing and media processing via graphics cores 2480A-2480N. In at least one embodiment, for 3D geometry processing commands, command streamer 2403 supplies commands to geometry pipeline 2436. In at least one embodiment, for at least some media processing commands, command streamer 2403 supplies commands to video front end 2434, which is coupled to media engine 2437. In at least one embodiment, the media engine 2437 includes a Video Quality Engine (VQE) 2430 for video and image post-processing and a Multi-Format Encode / Decode (MFX) 2433 engine that provides hardware accelerated encoding and decoding of media data. In at least one embodiment, the geometry pipeline 2436 and the media engine 2437 each spawn execution threads for thread execution resources provided by at least one graphics core 2480.

[0338] In at least one embodiment, the graphics processor 2400 includes a scalable thread execution resource characterized by graphics cores 2480A-2480N (which may be modular and sometimes referred to as core slices), each of which has multiple sub-cores 2450A-50N, 2460A-2460N (sometimes referred to as core sub-slices). In at least one embodiment, the graphics processor 2400 may have any number of graphics cores 2480A. In at least one embodiment, the graphics processor 2400 includes a graphics core 2480A having at least a first sub-core 2450A and a second sub-core 2460A. In at least one embodiment, the graphics processor 2400 is a low power processor having a single sub-core (e.g., 2450A). In at least one embodiment, the graphics processor 2400 includes a plurality of graphics cores 2480A-2480N, each of which includes a first set of sub-cores 2450A-2450N and a second set of sub-cores 2460A-2460N. In at least one embodiment, each of the first sub-cores 2450A-2450N includes at least a first set of execution units 2452A-2452N and media / texture samplers 2454A-2454N. In at least one embodiment, each of the second sub-cores 2460A-2460N includes at least a second set of execution units 2462A-2462N and samplers 2464A-2464N. In at least one embodiment, each sub-core 2450A-2450N, 2460A-2460N shares a set of shared resources 2470A-2470N. In at least one embodiment, the shared resources include shared cache memory and pixel operating logic.

[0339] Inference and / or training logic 915 is used to perform inference and / or training operations associated with one or more embodiments. More details regarding inference and / or training logic 915 are provided herein in conjunction with Figures 9A and / or 9B. In at least one embodiment, inference and / or training logic 915 may be used in graphics processor 2400 for inference or prediction operations based at least in part on weight parameters calculated using neural network training operations, neural network functionality and / or architecture, or neural network use cases described herein.

[0340] In at least one embodiment, an application programming interface is adapted to receive an application programming interface call including a graph definition and a recursion attribute in association with the diagram, and to execute a recursive neural network based on the graph definition.

[0341] FIG. 25 is a block diagram illustrating a micro-architecture of a processor 2500 that may include logic circuits for executing instructions, according to at least one embodiment. In at least one embodiment, the processor 2500 may execute instructions including x86 instructions, AMR instructions, special instructions for application specific integrated circuits (ASICs), and the like. In at least one embodiment, the processor 2500 may include registers for storing packed data, such as 64-bit wide MMXTM registers in a microprocessor enabled with MMX technology by Intel Corporation of Santa Clara, Calif. In at least one embodiment, MMX registers available in both integer and floating-point formats may operate on packed data elements with Single Instruction Multiple Data ("SIMD") and streaming SIMD extensions ("SSE") instructions. In at least one embodiment, 128-bit wide XMM registers for SSE2, SSE3, SSE4, AVX, or higher (collectively referred to as "SSEx") technologies may hold such packed data operands. In at least one embodiment, the processor 2500 may execute instructions to accelerate machine learning or deep learning algorithms, training, or inference.

[0342] In at least one embodiment, processor 2500 includes an in-order front end ("front end") 2501 that fetches instructions to be executed and prepares the instructions for later use in the processor pipeline. In at least one embodiment, front end 2501 may include several units. In at least one embodiment, instruction prefetcher 2526 fetches instructions from memory and provides the instructions to instruction decoder 2528, which decodes or interprets the instructions. For example, in at least one embodiment, instruction decoder 2528 decodes received instructions into one or more operations, called "microinstructions" or "micro-operations" (also called "micro-ops" or "uops"), that the machine can execute. In at least one embodiment, instruction decoder 2528 parses instructions into opcodes and corresponding data and control fields that may be used by the micro-architecture to perform operations in accordance with at least one embodiment. In at least one embodiment, trace cache 2530 may assemble the decoded uops into program-order sequences, or traces, in uop queue 2534 for execution. In at least one embodiment, when trace cache 2530 encounters a complex instruction, microcode ROM 2532 provides the uops necessary to complete the operation.

[0343] In at least one embodiment, some instructions can be converted into a single micro-op, while other instructions require several micro-ops to complete the entire operation. In at least one embodiment, if an instruction requires more than four micro-ops to complete, the instruction decoder 2528 may access the microcode ROM 2532 to execute the instruction. In at least one embodiment, the instruction may be decoded into a small number of micro-ops for processing in the instruction decoder 2528. In at least one embodiment, if a large number of micro-ops are required to complete such an operation, the instruction may be stored in the microcode ROM 2532. In at least one embodiment, the trace cache 2530 references an entry point programmable logic array ("PLA") to determine the correct microinstruction pointer to read the microcode sequence to complete one or more instructions from the microcode ROM 2532 in accordance with at least one embodiment. In at least one embodiment, after the microcode ROM 2532 has finished sequencing micro-ops for an instruction, the machine front end 2501 may resume fetching micro-ops from the trace cache 2530.

[0344] In at least one embodiment, out-of-order execution engine ("out-of-order engine") 2503 may prepare instructions for execution. In at least one embodiment, the out-of-order execution logic has multiple buffers to smooth and reorder the flow of instructions to optimize performance as instructions are scheduled for execution down the pipeline. In at least one embodiment, out-of-order execution engine 2503 includes, without limitation, allocator / register renamer 2540, memory uop queue 2542, integer / floating point uop queue 2544, memory scheduler 2546, fast scheduler 2502, slow / general purpose floating point scheduler ("slow / general purpose FP scheduler") 2504, and simple floating point scheduler ("simple FP scheduler") 2506. In at least one embodiment, fast scheduler 2502, slow / general purpose floating point scheduler 2504, and simple floating point scheduler 2506 are also collectively referred to herein as "uop schedulers 2502, 2504, 2506." In at least one embodiment, allocator / register renamer 2540 allocates machine buffers and resources required by each uop to execute. In at least one embodiment, allocator / register renamer 2540 renames logical registers upon entry into the register file. In at least one embodiment, allocator / register renamer 2540 also allocates entries for each uop to one of two uop queues, memory uop queue 2542 for memory operations and integer / floating point uop queue 2544 for non-memory operations, before memory scheduler 2546 and uop schedulers 2502, 2504, 2506. In at least one embodiment, uop schedulers 2502, 2504, 2506 determine when uops are ready to execute based on the sources of their dependent input register operands being ready and the execution resources required by the uops to complete their operations being available.In at least one embodiment, the fast scheduler 2502 may schedule every half of the main clock cycle, and the slow / general purpose floating point scheduler 2504 and the simple floating point scheduler 2506 may schedule once per main processor clock cycle. In at least one embodiment, the uop schedulers 2502, 2504, 2506 arbitrate for dispatch ports to schedule uops for execution.

[0345] In at least one embodiment, execution block 2511 includes, without limitation, integer register file / bypass network 2508, floating point register file / bypass network (“FP register file / bypass network”) 2510, address generation units (“AGU”) 2512 and 2514, high speed arithmetic logic units (ALUs) (“fast ALUs”) 2516 and 2518, slower arithmetic logic unit (“slower ALU”) 2520, floating point ALU (“FP”) 2522, and floating point move unit (“FP move”) 2524. In at least one embodiment, integer register file / bypass network 2508 and floating point register file / bypass network 2510 are also referred to herein as “register files 2508, 2510.” In at least one embodiment, AGUs 2512 and 2514, fast ALUs 2516 and 2518, slow ALU 2520, floating point ALU 2522, and floating point move unit 2524 are also referred to herein as "execution units 2512, 2514, 2516, 2518, 2520, 2522, and 2524." In at least one embodiment, execution block 2511 may include any number and type of register files (including zero), bypass networks, address generation units, and execution units in any combination, without limitation.

[0346] In at least one embodiment, the register networks 2508, 2510 may be disposed between the uop schedulers 2502, 2504, 2506 and the execution units 2512, 2514, 2516, 2518, 2520, 2522, and 2524. In at least one embodiment, the integer register file / bypass network 2508 performs integer operations. In at least one embodiment, the floating point register file / bypass network 2510 performs floating point operations. In at least one embodiment, each of the register networks 2508, 2510 may include, without limitation, a bypass network that may bypass or forward just completed results that have not yet been written to the register file to new dependent uops. In at least one embodiment, the register networks 2508, 2510 may communicate data to each other. In at least one embodiment, integer register file / bypass network 2508 may include, without limitation, two separate register files, one register file for the lower 32 bits of data and a second register file for the higher 32 bits of data. In at least one embodiment, floating point register file / bypass network 2510 may include, without limitation, 128-bit wide entries since floating point instructions typically have operands that are 64-128 bits wide.

[0347] In at least one embodiment, the execution units 2512, 2514, 2516, 2518, 2520, 2522, 2524 may execute instructions. In at least one embodiment, the register networks 2508, 2510 store integer and floating point data operand values ​​that microinstructions need to execute. In at least one embodiment, the processor 2500 may include any number and combination of execution units 2512, 2514, 2516, 2518, 2520, 2522, 2524, without limitation. In at least one embodiment, the floating point ALU 2522 and floating point move unit 2524 may execute floating point, MMX, SIMD, AVX, and SEE, or other operations, including special machine learning instructions. In at least one embodiment, the floating point ALU 2522 may include, without limitation, a 64-bit floating point divider to perform division, square root, and remaining micro-ops. In at least one embodiment, instructions involving floating point values ​​may be handled by floating point hardware. In at least one embodiment, ALU operations may be passed to the fast ALU 2516, 2518. In at least one embodiment, the fast ALU 2516, 2518 may perform high speed operations with an effective latency of half a clock cycle. In at least one embodiment, most complex integer operations go to the slow ALU 2520, which may include, without limitation, integer execution hardware for long latency type operations such as multipliers, shifts, flag logic, and branching. In at least one embodiment, memory load / store operations may be performed by the AGUS 2512, 2514. In at least one embodiment, fast ALU 2516, fast ALU 2518, and slow ALU 2520 may perform integer arithmetic on 64-bit data operands. In at least one embodiment, fast ALU 2516, fast ALU 2518, and slow ALU 2520 may be implemented to support various data bit sizes, including 16, 32, 128, 256, etc.In at least one embodiment, floating-point ALU 2522 and floating-point move unit 2524 may be implemented to support a wide range of operands having various bit widths, such as 128-bit wide packed data operands in conjunction with SIMD and multimedia instructions.

[0348] In at least one embodiment, the uop schedulers 2502, 2504, 2506 dispatch dependent operations before the parent load finishes execution. In at least one embodiment, since uops may be speculatively scheduled and executed in the processor 2500, the processor 2500 may also include logic to handle memory misses. In at least one embodiment, if a data load misses in the data cache, there may be dependent operations in progress in the pipeline past the scheduler that have temporarily inaccurate data. In at least one embodiment, a replay mechanism tracks and re-executes instructions that use the inaccurate data. In at least one embodiment, dependent operations may need to be replayed and independent operations may be allowed to complete. In at least one embodiment, the scheduler and replay mechanism of at least one embodiment of the processor may also be designed to capture instruction sequences for text string comparison operations.

[0349] In at least one embodiment, a "register" may refer to an on-board processor storage location that may be used as part of an instruction to identify an operand. In at least one embodiment, a register may be available externally to the processor (from a programmer's perspective). In at least one embodiment, a register may not be limited to a particular type of circuit. Rather, in at least one embodiment, a register may store data, provide data, and perform functions described herein. In at least one embodiment, the registers described herein may be implemented by circuits within the processor using any number of different techniques, such as dedicated physical registers, dynamically allocated physical registers using register renaming, or a combination of dedicated and dynamically allocated physical registers. In at least one embodiment, an integer register stores 32-bit integer data. The register file of at least one embodiment also includes eight multimedia SIMD registers for packed data.

[0350] Inference and / or training logic 915 is used to perform inference and / or training operations associated with one or more embodiments. Details regarding the inference and / or training logic 915 are provided herein in conjunction with FIG. 9A and / or FIG. 9B. In at least one embodiment, some or all of the inference and / or training logic 915 may be incorporated into the execution block 2511 and other memories or registers, shown or not shown. For example, in at least one embodiment, the training and / or inference techniques described herein may use one or more of the ALUs shown in the execution block 2511. Additionally, the weight parameters may be stored in on-chip or off-chip memories and / or registers (shown or not shown) that configure the ALUs of the execution block 2511 to execute one or more machine learning algorithms, neural network architectures, use cases, or training techniques described herein.

[0351] In at least one embodiment, an application programming interface is adapted to receive an application programming interface call including a graph definition and a recursion attribute in association with the diagram, and to execute a recursive neural network based on the graph definition.

[0352] FIG. 26 illustrates a deep learning application processor 2600 according to at least one embodiment. In at least one embodiment, the deep learning application processor 2600 uses instructions that, when executed by the deep learning application processor 2600, cause the deep learning application processor 2600 to perform some or all of the processes and techniques described throughout this disclosure. In at least one embodiment, the deep learning application processor 2600 is an application specific integrated circuit (ASIC). In at least one embodiment, the application processor 2600 performs a matrix multiplication operation, both of which are "hardwired" into hardware, as a result of executing one or more instructions or both. In at least one embodiment, the deep learning application processor 2600 may include, without limitation, processing clusters 2610(1)-2610(12), inter-chip links (“ICLs”) 2620(1)-2620(12), inter-chip controllers (“ICCs”) 2630(1)-2630(2), high bandwidth memory second generation (“HBM2”) 2640(1)-2640(4), memory controllers (“Mem Ctrlrs”) 2642(1)-2642(4), high bandwidth memory physical layers (“HBM 2644(1) through 2644(4), a management-controller central processing unit ("management-controller CPU") 2650, a serial peripheral interface, inter-integrated circuit, and general purpose input / output block ("SPI, I2C, GPIO") 2660, a peripheral component interconnect express controller and direct memory access block ("PCIe Controller and DMA") 2670, and a 16-lane peripheral component interconnect express port ("PCI Express x16") 2680.

[0353] In at least one embodiment, the processing clusters 2610 may perform deep learning operations, including inference or prediction operations, based on weight parameters calculated using one or more training techniques, including those described herein. In at least one embodiment, each processing cluster 2610 may include any number and type of processors, without limitation. In at least one embodiment, the deep learning application processor 2600 may include any number and type of processing clusters 2600. In at least one embodiment, the inter-chip link 2620 is bidirectional. In at least one embodiment, the inter-chip link 2620 and the inter-chip controller 2630 enable the multiple deep learning application processors 2600 to exchange information, including activation information resulting from execution of one or more machine learning algorithms embodied in one or more neural networks. In at least one embodiment, the deep learning application processor 2600 may include any number and type (including zero) of ICLs 2620 and ICCs 2630.

[0354] In at least one embodiment, the HBM2 2640 provides a total of 32 Gigabytes (GB) of memory. In at least one embodiment, an HBM2 2640(i) is associated with both a memory controller 2642(i) and an HBM PHY 2644(i), where "i" is any integer. In at least one embodiment, any number of HBM2 2640s may provide any type and total amount of high bandwidth memory and may be associated with any number and type of memory controllers 2642 and HBM PHYs 2644 (including zero). In at least one embodiment, the SPI, I2C, GPIO 2660, PCIe controller and DMA 2670, and / or PCIe 2680 may be replaced with any number and type of blocks enabling any number and type of communication standards in any technically feasible manner.

[0355] Inference and / or training logic 915 is used to perform inference and / or training operations associated with one or more embodiments. More details regarding the inference and / or training logic 915 are provided herein in conjunction with FIG. 9A and / or FIG. 9B. In at least one embodiment, the deep learning application processor 2600 is used to train a machine learning model, such as a neural network, to predict or infer information provided to the deep learning application processor 2600. In at least one embodiment, the deep learning application processor 2600 is used to infer or predict information based on a trained machine learning model (e.g., a neural network) that has been trained by another processor or system or by the deep learning application processor 2600. In at least one embodiment, the processor 2600 may be used to perform one or more neural network use cases described herein.

[0356] In at least one embodiment, an application programming interface is adapted to receive an application programming interface call including a graph definition and a recursion attribute in association with the diagram, and to execute a recursive neural network based on the graph definition.

[0357] FIG. 27 is a block diagram of a neuromorphic processor 2700, according to at least one embodiment. In at least one embodiment, the neuromorphic processor 2700 receives one or more inputs from a source external to the neuromorphic processor 2700. In at least one embodiment, these inputs may be sent to one or more neurons 2702 within the neuromorphic processor 2700. In at least one embodiment, the neurons 2702 and their components may be implemented using circuitry or logic including one or more arithmetic logic units (ALUs). In at least one embodiment, the neuromorphic processor 2700 may include, without limitation, thousands or millions of instances of neurons 2702, although any suitable number of neurons 2702 may be used. In at least one embodiment, each instance of a neuron 2702 may include a neuron input 2704 and a neuron output 2706. In at least one embodiment, the neuron 2702 may generate an output, which may be sent to an input of another instance of the neuron 2702. For example, in at least one embodiment, neuron input 2704 and neuron output 2706 may be interconnected via synapse 2708.

[0358] In at least one embodiment, neurons 2702 and synapses 2708 may be interconnected such that neuromorphic processor 2700 operates to process or analyze information received by neuromorphic processor 2700. In at least one embodiment, neuron 2702 may send an output pulse (or "fire" or "spike") when an input received via neuron input 2704 exceeds a threshold. In at least one embodiment, neuron 2702 may sum or integrate signals received at neuron input 2704. For example, in at least one embodiment, neuron 2702 may be implemented as a leaky integrate-and-fire neuron, where if the sum (called the "membrane potential") exceeds a threshold, neuron 2702 may generate an output (or "fire") using a transfer function such as a sigmoid function or a threshold function. In at least one embodiment, the leaky integrate-and-fire neuron may sum signals received at neuron input 2704 into a membrane potential and may apply a decay factor (or leakage) to reduce the membrane potential. In at least one embodiment, the leaky integrate-and-fire neuron may fire if multiple input signals are received at neuron input 2704 quickly enough to exceed a threshold (i.e., before the membrane potential decays too little to fire). In at least one embodiment, neuron 2702 may be implemented using circuitry or logic that receives inputs, integrates the inputs into a membrane potential, and decays the membrane potential. In at least one embodiment, the inputs may be averaged, or any other suitable transfer function may be used. Additionally, in at least one embodiment, neuron 2702 may include, without limitation, a comparator circuit or logic that generates an output spike at neuron 2706 when the result of applying the transfer function to neuron 2704 exceeds a threshold. In at least one embodiment, neuron 2702 may ignore previously received input information when it fires, for example, by resetting the membrane potential to 0 or other suitable default value.In at least one embodiment, once the membrane potential has been reset to zero, neuron 2702 may resume normal operation after a suitable period (or refractory period).

[0359] In at least one embodiment, neurons 2702 may be interconnected through synapses 2708. In at least one embodiment, synapses 2708 may operate to transmit a signal from an output of a first neuron 2702 to an input of a second neuron 2702. In at least one embodiment, neurons 2702 may transmit information through two or more instances of synapses 2708. In at least one embodiment, one or more instances of neuron outputs 2706 may be connected to instances of neuron inputs 2704 of the same neuron 2702 through instances of synapses 2708. In at least one embodiment, an instance of neuron 2702 that generates an output to be transmitted through an instance of synapse 2708 may be referred to as a “pre-synaptic neuron” with respect to that instance of synapse 2708. In at least one embodiment, an instance of neuron 2702 that receives an input to be transmitted through an instance of synapse 2708 may be referred to as a “post-synaptic neuron” with respect to that instance of synapse 2708. In at least one embodiment, an instance of neuron 2702 may receive input from one or more instances of synapse 2708 and may send output via one or more instances of synapse 2708, so that a single instance of neuron 2702 may be both a “pre-synaptic neuron” and a “post-synaptic neuron” with respect to various instances of synapse 2708.

[0360] In at least one embodiment, neurons 2702 may be organized into one or more layers. In at least one embodiment, each instance of neuron 2702 may have one neuron output 2706 that may fan out to one or more neuron inputs 2704 through one or more synapses 2708. In at least one embodiment, neuron output 2706 of neuron 2702 in a first layer 2710 may be connected to neuron input 2704 of neuron 2702 in a second layer 2712. In at least one embodiment, layer 2710 may be referred to as a "feed forward" layer. In at least one embodiment, each instance of neuron 2702 in an instance of first layer 2710 may fan out to each instance of neuron 2702 in the second layer 2712. In at least one embodiment, first layer 2710 may be referred to as a "fully connected feed forward layer." In at least one embodiment, each instance of a neuron 2702 in the second layer 2712 may fan out to fewer than all instances of neurons 2702 in the third layer 2714. In at least one embodiment, the second layer 2712 may be referred to as a "sparsely connected feed forward layer." In at least one embodiment, the neurons 2702 in the second layer 2712 may fan out to neurons 2702 in multiple other layers, including the neurons 2702 in the second layer 2712. In at least one embodiment, the second layer 2712 may be referred to as a "recurrent layer." In at least one embodiment, the neuromorphic processor 2700 may include, without limitation, any suitable combination of recurrent layers and feed forward layers, including, without limitation, both sparsely connected feed forward layers and fully connected feed forward layers.

[0361] In at least one embodiment, the neuromorphic processor 2700 may include, without limitation, a reconfigurable interconnect architecture or dedicated hardwired interconnects for connecting the synapses 2708 to the neurons 2702. In at least one embodiment, the neuromorphic processor 2700 may include, without limitation, circuitry or logic that allows synapses to be allocated to different neurons 2702 as needed based on the neural network topology and the fan-in / fan-out of the neurons. For example, in at least one embodiment, the synapses 2708 may be connected to the neurons 2702 using an interconnect fabric such as a network-on-chip or using dedicated connections. In at least one embodiment, the synapse interconnects and their components may be implemented using circuitry or logic.

[0362] In at least one embodiment, an application programming interface is adapted to receive an application programming interface call including a graph definition and a recursion attribute in association with the diagram, and to execute a recursive neural network based on the graph definition.

[0363] 28 is a block diagram of a processing system according to at least one embodiment. In at least one embodiment, system 2800 includes one or more processors 2802 and one or more graphics processors 2808 and may be a single processor desktop system, a multiprocessor workstation system, or a server system having multiple processors 2802 or processor cores 2807. In at least one embodiment, system 2800 is a processing platform integrated into a system-on-chip (SoC) integrated circuit for use in a mobile, portable, or embedded device.

[0364] In at least one embodiment, system 2800 may include or be incorporated into a server-based gaming platform, a game console including a game and media console, a mobile gaming console, a handheld game console, or an online game console. In at least one embodiment, system 2800 is a mobile phone, a smart phone, a tablet computing device, or a mobile Internet device. In at least one embodiment, processing system 2800 may also include, be coupled to, or be integrated into a wearable device, such as a smart watch wearable device, a smart eyewear device, an augmented reality device, or a virtual reality device. In at least one embodiment, processing system 2800 is a television or set-top box device having one or more processors 2802 and a graphical interface generated by one or more graphics processors 2808.

[0365] In at least one embodiment, the one or more processors 2802 each include one or more processor cores 2807 for processing instructions that, when executed, perform operations for system and user software. In at least one embodiment, each of the one or more processor cores 2807 is configured to process a particular instruction sequence 2809. In at least one embodiment, the instruction sequence 2809 may facilitate computing via Complex Instruction Set Computing (CISC), Reduced Instruction Set Computing (RISC), or Very Long Instruction Word (VLIW). In at least one embodiment, the processor cores 2807 each may process a different instruction sequence 2809, which instruction set may include instructions that facilitate emulation of other instruction sequences. In at least one embodiment, the processor cores 2807 may also include other processing devices, such as a digital signal processor (DSP).

[0366] In at least one embodiment, the processor 2802 includes a cache memory 2804. In at least one embodiment, the processor 2802 may have a single internal cache or multiple levels of internal cache. In at least one embodiment, the cache memory is shared among various components of the processor 2802. In at least one embodiment, the processor 2802 also uses an external cache (e.g., a level 3 (L3) cache or a last level cache (LLC)) (not shown), which may be shared among the processor cores 2807 using known cache coherence techniques. In at least one embodiment, the processor 2802 further includes a register file 2806, which may include different types of registers (e.g., integer registers, floating point registers, status registers, and an instruction pointer register) for storing different types of data. In at least one embodiment, the register file 2806 may include general purpose registers or other registers.

[0367] In at least one embodiment, the one or more processors 2802 are coupled to one or more interface buses 2810 to transmit communication signals, such as address, data, or control signals, between the processors 2802 and other components in the system 2800. In at least one embodiment, the interface bus 2810 may be a processor bus, such as, in one embodiment, a version of a Direct Media Interface (DMI) bus. In at least one embodiment, the interface 2810 is not limited to a DMI bus, but may include one or more peripheral component interconnect buses (e.g., PCI, PCI Express), a memory bus, or other types of interface buses. In at least one embodiment, the processor 2802 includes an integrated memory controller 2816 and a platform controller hub 2830. In at least one embodiment, the memory controller 2816 facilitates communication between memory devices and other components of the system 2800, while the platform controller hub (PCH) 2830 provides connectivity to I / O devices via a local I / O bus.

[0368] In at least one embodiment, memory device 2820 may be a dynamic random access memory (DRAM) device, a static random access memory (SRAM) device, a flash memory device, a phase change memory device, or any other memory device having suitable performance to serve as process memory. In at least one embodiment, memory device 2820 may operate as system memory for system 2800 to store data 2822 and instructions 2821 for use by one or more processors 2802 in executing applications or processes. In at least one embodiment, memory controller 2816 is also coupled to an optional external graphics processor 2812, which may communicate with one or more graphics processors 2808 within processor 2802 to perform graphics and media operations. In at least one embodiment, a display device 2811 may be connected to processor 2802. In at least one embodiment, display device 2811 may include one or more of an internal display device, such as a mobile electronic device or laptop device, or an external display device attached via a display interface (e.g., a display port, etc.). In at least one embodiment, display device 2811 may include a head mounted display (HMD), such as a stereoscopic display device for use in virtual reality (VR) or augmented reality (AR) applications.

[0369] In at least one embodiment, the platform controller hub 2830 allows peripherals to connect to the memory device 2820 and the processor 2802 via a high-speed I / O bus. In at least one embodiment, the I / O peripherals include, but are not limited to, an audio controller 2846, a network controller 2834, a firmware interface 2828, a wireless transceiver 2826, a touch sensor 2825, and a data storage device 2824 (e.g., hard disk drive, flash memory, etc.). In at least one embodiment, the data storage device 2824 can be connected via a storage interface (e.g., SATA) or via a peripheral bus such as a peripheral component interconnect bus (e.g., PCI, PCI Express). In at least one embodiment, the touch sensor 2825 can include a touch screen sensor, a pressure sensor, or a fingerprint sensor. In at least one embodiment, wireless transceiver 2826 may be a WiFi transceiver, a Bluetooth transceiver, or a mobile network transceiver such as a 3G, 4G, or Long Term Evolution (LTE) transceiver. In at least one embodiment, firmware interface 2828 enables communication with system firmware and may be, for example, a Unified Extensible Firmware Interface (UEFI). In at least one embodiment, network controller 2834 may enable network connectivity to a wired network. In at least one embodiment, a high performance network controller (not shown) couples to interface bus 2810. In at least one embodiment, audio controller 2846 is a multi-channel high definition audio controller. In at least one embodiment, system 2800 includes an optional legacy I / O controller 2840 for coupling legacy (e.g., Personal System 2 (PS / 2)) devices to system 2800.In at least one embodiment, platform controller hub 2830 may also connect to one or more universal serial bus (USB) controllers 2842 connected input devices, such as a keyboard and mouse 2843 combination, a camera 2844, or other USB input devices.

[0370] In at least one embodiment, instances of memory controller 2816 and platform controller hub 2830 may be integrated into a separate external graphics processor, such as external graphics processor 2812. In at least one embodiment, platform controller hub 2830 and / or memory controller 2816 may be external to one or more processors 2802. For example, in at least one embodiment, system 2800 may include an external memory controller 2816 and platform controller hub 2830, which may be configured as a memory controller hub and a peripheral controller hub in a system chipset that communicates with processor 2802.

[0371] Inference and / or training logic 915 is used to perform inference and / or training operations associated with one or more embodiments. Details regarding the inference and / or training logic 915 are provided herein in conjunction with FIG. 9A and / or FIG. 9B. In at least one embodiment, some or all of the inference and / or training logic 915 may be incorporated into the graphics processor 2800. For example, in at least one embodiment, the training and / or inference techniques described herein may use one or more of the ALUs embodied in the 3D pipeline. Furthermore, in at least one embodiment, the inference and / or training operations described herein may be performed using logic other than that shown in FIG. 8A or FIG. 8B. In at least one embodiment, the weight parameters may be stored in on-chip or off-chip memory and / or registers (shown or not shown) that configure the ALUs of the graphics processor 2800 to perform one or more machine learning algorithms, neural network architectures, use cases, or training techniques described herein.

[0372] In at least one embodiment, an application programming interface is adapted to receive an application programming interface call including a graph definition and a recursion attribute in association with the diagram, and to execute a recursive neural network based on the graph definition.

[0373] 29 is a block diagram of a processor 2900 having one or more processor cores 2902A-2902N, an integrated memory controller 2914, and an integrated graphics processor 2908, according to at least one embodiment. In at least one embodiment, the processor 2900 may include a smaller number of additional cores, including additional core 2902N, represented by a dashed box. In at least one embodiment, each of the processor cores 2902A-2902N includes one or more internal cache units 2904A-2904N. In at least one embodiment, each processor core also has access to one or more shared cache units 2906.

[0374] In at least one embodiment, the internal cache units 2904A-2904N and the shared cache unit 2906 represent a cache memory hierarchy within the processor 2900. In at least one embodiment, the cache memory units 2904A-2904N may include at least one level of instruction and data cache within each processor core, as well as one or more levels of shared mid-level cache, such as level 2 (L2), level 3 (L3), level 4 (L4), or other levels of cache, where the highest level of cache before external memory is classified as an LLC. In at least one embodiment, cache coherence logic maintains coherency between the various cache units 2906 and 2904A-2904N.

[0375] In at least one embodiment, the processor 2900 may also include a set of one or more bus controller units 2916 and a system agent core 2910. In at least one embodiment, the bus controller unit 2916 manages a set of peripheral buses, such as one or more PCI or PCI Express buses. In at least one embodiment, the system agent core 2910 provides management functions for the various processor components. In at least one embodiment, the system agent core 2910 includes one or more integrated memory controllers 2914 for managing access to various external memory devices (not shown).

[0376] In at least one embodiment, one or more of the processor cores 2902A-2902N include support for simultaneous multithreading. In at least one embodiment, the system agent core 2910 includes components for coordinating and operating the cores 2902A-2902N during multithreaded processing. In at least one embodiment, the system agent core 2910 may further include a power control unit (PCU), which includes logic and components for coordinating the power state of one or more of the processor cores 2902A-2902N and the graphics processor 2908.

[0377] In at least one embodiment, the processor 2900 further includes a graphics processor 2908 for performing graphics processing operations. In at least one embodiment, the graphics processor 2908 couples to a shared cache unit 2906 and to a system agent core 2910 that includes one or more integrated memory controllers 2914. In at least one embodiment, the system agent core 2910 also includes a display controller 2911 for directing output of the graphics processor to one or more coupled displays. In at least one embodiment, the display controller 2911 may also be a separate module coupled to the graphics processor 2908 via at least one interconnect or may be integrated within the graphics processor 2908.

[0378] In at least one embodiment, a ring-based interconnect unit 2912 is used to couple the internal components of processor 2900. In at least one embodiment, alternative interconnect units such as a point-to-point interconnect, a switched interconnect, or other techniques may be used. In at least one embodiment, graphics processor 2908 couples to ring interconnect 2912 via I / O link 2913.

[0379] In at least one embodiment, I / O link 2913 represents at least one of a variety of I / O interconnects, including an on-package I / O interconnect that facilitates communication between various processor components and a high performance embedded memory module 2918, such as an eDRAM module. In at least one embodiment, each of processor cores 2902A-2902N and graphics processor 2908 use embedded memory module 2918 as a shared last level cache.

[0380] In at least one embodiment, the processor cores 2902A-2902N are homogenous cores that execute a common instruction set architecture. In at least one embodiment, the processor cores 2902A-2902N are heterogeneous in terms of instruction set architecture (ISA), where one or more of the processor cores 2902A-2902N execute a common instruction set, while one or more other of the processor cores 2902A-2902N execute a subset of the common instruction set, or a different instruction set. In at least one embodiment, the processor cores 2902A-2902N are heterogeneous in terms of micro-architecture, where one or more cores with relatively higher power consumption are combined with one or more cores with lower power consumption. In at least one embodiment, the processor 2900 can be implemented on one or more chips or as an SoC integrated circuit.

[0381] Inference and / or training logic 915 is used to perform inference and / or training operations associated with one or more embodiments. Details regarding the inference and / or training logic 915 are provided herein in conjunction with FIG. 9A and / or FIG. 9B. In at least one embodiment, some or all of the inference and / or training logic 915 may be incorporated into the graphics processor 2910. For example, in at least one embodiment, the training and / or inference techniques described herein may use one or more of the ALUs embodied in the 3D pipeline, graphics core 2902, shared function logic, or other logic of FIG. 29. Furthermore, in at least one embodiment, the inference and / or training operations described herein may be performed using logic other than that shown in FIG. 8A or FIG. 8B. In at least one embodiment, the weight parameters may be stored in on-chip or off-chip memory and / or registers (shown or not shown) that configure the ALUs of the processor 2900 to execute one or more machine learning algorithms, neural network architectures, use cases, or training techniques described herein.

[0382] In at least one embodiment, an application programming interface is adapted to receive an application programming interface call including a graph definition and a recursion attribute in association with the diagram, and to execute a recursive neural network based on the graph definition.

[0383] FIG. 30 is a block diagram of a graphics processor 3000, which may be a discrete graphics processing unit or a graphics processor integrated with multiple processing cores. In at least one embodiment, the graphics processor 3000 communicates with registers of the graphics processor 3000 via a memory-mapped I / O interface using commands placed in memory. In at least one embodiment, the graphics processor 3000 includes a memory interface 3014 for accessing memory. In at least one embodiment, the memory interface 3014 is an interface to local memory, one or more internal caches, one or more shared external caches, and / or system memory.

[0384] In at least one embodiment, the graphics processor 3000 also includes a display contr...

Claims

1. A machine-readable medium having stored thereon an application programming interface (API) for execution by one or more processors, comprising: at least, Receiving one or more API calls including a graph definition and a recursive attribute (802); running a recurrent neural network based at least in part on the graph definition (810); a machine-readable medium for implementation by said one or more processors.

2. 2. The machine-readable medium of claim 1, wherein an input to the recurrent neural network comprises a tensor, and access to the tensor is limited during an iteration of execution of the recurrent neural network to a slice of the tensor that corresponds to the iteration.

3. The machine-readable medium of claim 2 , wherein the slice of the tensor is advanced after the iteration.

4. 10. The machine-readable medium of claim 1 having stored thereon a further set of instructions that, when executed by the one or more processors, cause the one or more processors to at least optimize execution of the recurrent neural network over multiple iterations.

5. 5. The machine-readable medium of claim 4, wherein at least one of the inputs or outputs to the recurrent neural network includes a tensor, and the optimization of execution is based at least in part on a compiler assumption that access to the tensor is limited to a slice of the tensor during an iteration of the execution.

6. The machine-readable medium of claim 1 , wherein the one or more API calls include an API call for associating the graph definition with a recursive attribute.

7. The application programming interface, when implemented by one or more processors, provides at least determining that the recurrent neural network is a bidirectional recurrent neural network based at least in part on detecting a function that inverts inputs to the graph definition; optimizing the performance of the bidirectional recurrent neural network; The machine-readable medium of claim 1 , further comprising:

8. 2. The machine-readable medium of claim 1, wherein the application programming interface, when executed by one or more processors, causes a compiler to cause the one or more processors to optimize to eliminate chaining operations on outputs of iterations of the recurrent neural network.

9. One or more processors implementing an application programming interface (API), One or more arithmetic logic units (ALUs) that will be configured to at least receive one or more API calls including a graph definition and a recursive attribute, and execute a recursive neural network based at least in part on the graph definition. A processor comprising:

10. 10. The processor of claim 9, wherein the recurrent neural network is executed based at least in part on a tensor, and access to the tensor is limited during an iteration of execution of the recurrent neural network to a slice of the tensor corresponding to the iteration.

11. The processor of claim 10 , wherein the slice of the tensor is advanced after the iteration.

12. 10. The processor of claim 9, wherein the one or more arithmetic logic units (ALUs) are configured to at least optimize execution of the recurrent neural network over multiple iterations.

13. 13. The processor of claim 12, wherein at least one of the inputs or outputs to the recurrent neural network includes a tensor, and the optimization of execution is based at least in part on a compiler assumption that access to the tensor is limited to a slice of the tensor during an iteration of the execution.

14. 10. The processor of claim 9, wherein the effect of executing functions of the application programming interface for defining and executing the recurrent neural network is localized to the environment in which each of the functions is applicable.

15. 10. The processor of claim 9, wherein the graph definition is defined by invocation of one or more functions of an application programming interface, the one or more functions including a function for associating the graph definition with a recursive attribute.

16. The one or more arithmetic logic units (ALUs) include at least determining that the recurrent neural network is a bidirectional recurrent neural network based at least in part on detecting a function that inverts the graph definition; optimizing said implementation of said bidirectional recurrent neural network; 10. The processor of claim 9, configured to:

17. One or more processors implementing an application programming interface (API), the one or more processors being configured to at least receive one or more API calls including a graph definition and a recursion attribute, and execute a recurrent neural network based at least in part on the graph definition. A system comprising:

18. 20. The system of claim 17, wherein inputs to the recurrent neural network include tensors.

19. 20. The system of claim 17, wherein access to tensors comprising inputs to the recurrent neural network is limited during execution to a slice of the tensors corresponding to a current iteration.

20. 20. The system of claim 17, wherein the one or more processors are configured to at least optimize execution of the recurrent neural network over multiple iterations.

21. 21. The system of claim 20, wherein at least one of the inputs or outputs to the recurrent neural network includes a tensor, and the optimization of execution is based at least in part on a compiler assumption that access to the tensor is limited to a slice of the tensor during an iteration of execution.

22. 20. The system of claim 17, wherein a compiler optimizes to eliminate chaining operations on outputs of iterations of the recurrent neural network.

23. The one or more processors include at least determining that the recurrent neural network is a bidirectional recurrent neural network based at least in part on detecting a function that inverts the graph definition; optimizing the performance of the bidirectional recurrent neural network; The system of claim 17 , configured to:

24. One or more processors implementing an application programming interface (API), the one or more processors being configured to detect patterns in time series information based at least in part on one or more API calls including a graph definition and a recursive attribute, the patterns being detected by execution of a recurrent neural network based at least in part on the graph definition. A system comprising:

25. 25. The system of claim 24, wherein the recurrent neural network is a bidirectional neural network.

26. 26. The system of claim 25, wherein the bidirectional neural network is an incomplete bidirectional recurrent neural network.

27. 25. The system of claim 24, wherein input data to the recurrent neural network comprises tensors.

28. 28. The system of claim 27, wherein the compiler optimizes pattern detection using the recurrent neural network based at least in part on optimizing execution of the recurrent neural network based on an assumption enforced by a compiler that access to the tensor is limited to a fixed slice or slices of the tensor.

29. 25. The system of claim 24, wherein inputs to the recurrent neural network include a trip count associated with the recurrent neural network by an API call, the trip count representing a number of iterations to perform.

30. 25. The system of claim 24, wherein inputs to the recurrent neural network include a control tensor associated with the recurrent neural network by an API call and represented as a tensor whose value is calculated after every iteration.

31. 25. The system of claim 24, wherein the recurrent neural network is layered and the execution of the recurrent neural network is optimized based at least in part on loop fusion.

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