Semiconductor memory device

Abstract

To provide a semiconductor storage device capable of improving an electric characteristic.SOLUTION: A semiconductor storage device includes: a substrate; a first word line; a second word line; a first channel; a first memory film; a second channel; a second memory film; a first insulation layer; a first source line; and a first drain line. The second word line is apart from the first word line in a second direction being a thickness direction of the substrate. The first channel is in parallel to the first word line in a third direction. The second channel is in parallel to the second word line in a third direction. The first insulation layer is arranged between the first word line and the second word line in the second direction, and is further arranged between the first channel and the second channel in the second direction. The first source line and the first drain line extend in the second direction.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to a semiconductor memory device. [Background technology]

[0002] 2. Description of the Related Art A semiconductor memory device is known that has a stack in which insulating layers and word lines are alternately stacked in the thickness direction of a substrate, and a channel that penetrates this stack in the thickness direction of the substrate. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] U.S. Pat. No. 9,691,973 [Non-patent literature]

[0004] [Non-Patent Document 1] VLSI2018, PP177-178, A Novel 3D AND-type NVM Architecture Capable of High-density, Low-power In-Memory Sum-of-Product Computation for Artificial Intelligence Application, Hang-Ting Lue, Weichen Chen, Hung-Sheng Chang, Keh-Chung Wang, and Chih-Yuan Lu, Macronix International Co., Ltd. Summary of the Invention [Problem to be solved by the invention]

[0005] An object of the present invention is to provide a semiconductor memory device capable of improving electrical characteristics. [Means for solving the problem]

[0006] The semiconductor memory device of the embodiment includes a substrate, a first word line, a second word line, a first channel, a first memory film, a second channel, a second memory film, a first insulating layer, a first source line, a first drain line, and , a third word line, a fourth word line, a fifth channel, a fifth memory film, a sixth channel, a sixth memory film, and a second insulating layer. The first word line extends in a first direction along the surface of the substrate. The second word line extends in the first direction, away from the first word line, in a second direction that is a thickness direction of the substrate. The first channel extends in the first direction, parallel to the first word line in a third direction that intersects with the first and second directions. The first memory film is located between the first word line and the first channel in the third direction, and extends in the first direction. The second channel is located in the first direction, parallel to the second word line in the third direction. The second memory film is located between the second word line and the second channel in the third direction, and extends in the first direction. The first insulating layer is located between the first word line and the second word line in the second direction, and between the first channel and the second channel in the second direction. The first source line is located on the opposite side of the first word line to the first channel in the third direction, and extends in the second direction. The first drain line is spaced apart from the first source line in the first direction, is located on an opposite side of the first channel from the first word line in the third direction, and extends in the second direction. The third word line is located on the opposite side of the first word line with respect to the first source line in the third direction, and extends in the first direction. The fourth word line is located on the opposite side of the second word line with respect to the first source line in the third direction, and extends in the first direction. The fifth channel is located between the third word line and the first source line in the third direction, and extends in the first direction. The fifth memory film is located between the third word line and the fifth channel in the third direction, and extends in the first direction. The sixth channel is located between the fourth word line and the first source line in the third direction, and extends in the first direction. The sixth memory film is located between the fourth word line and the sixth channel in the third direction, and extends in the first direction. The second insulating layer is located between the third word line and the fourth word line in the second direction, and between the fifth channel and the sixth channel in the second direction. [Brief description of the drawings]

[0007] [Figure 1] 1 is a perspective cross-sectional view showing a semiconductor memory device according to a first embodiment. [Diagram 2] 2 is a cross-sectional view taken along line F2-F2 of the semiconductor memory device shown in FIG. 1; [Diagram 3] 3 is a cross-sectional view taken along line F3-F3 of the semiconductor memory device shown in FIG. [Figure 4A] FIG. 2 is a diagram showing an equivalent circuit of the semiconductor memory device according to the first embodiment. [Figure 4B] FIG. 4 is a diagram showing an equivalent circuit of a modified example of the semiconductor memory device of the first embodiment. [Figure 5A]1 is a perspective cross-sectional view illustrating a method for manufacturing the semiconductor memory device according to the first embodiment. [Figure 5B] 1 is a perspective cross-sectional view illustrating a method for manufacturing the semiconductor memory device according to the first embodiment. [Figure 5C] 1 is a perspective cross-sectional view illustrating a method for manufacturing the semiconductor memory device according to the first embodiment. [Figure 5D] 1 is a perspective cross-sectional view illustrating a method for manufacturing the semiconductor memory device according to the first embodiment. [Figure 5E] 1 is a perspective cross-sectional view illustrating a method for manufacturing the semiconductor memory device according to the first embodiment. [Figure 5F] 1 is a perspective cross-sectional view illustrating a method for manufacturing the semiconductor memory device according to the first embodiment. [Figure 5G] 1 is a perspective cross-sectional view illustrating a method for manufacturing the semiconductor memory device according to the first embodiment. [Figure 5H] 1 is a perspective cross-sectional view illustrating a method for manufacturing the semiconductor memory device according to the first embodiment. [Figure 5I] 1 is a perspective cross-sectional view illustrating a method for manufacturing the semiconductor memory device according to the first embodiment. [Figure 5J] 1 is a perspective cross-sectional view illustrating a method for manufacturing the semiconductor memory device according to the first embodiment. [Figure 6A] 3A to 3C are cross-sectional views illustrating the manufacturing method of the semiconductor memory device according to the first embodiment. [Figure 6B] 3A to 3C are cross-sectional views illustrating the manufacturing method of the semiconductor memory device according to the first embodiment. [Figure 6C] 3A to 3C are cross-sectional views illustrating the manufacturing method of the semiconductor memory device according to the first embodiment. [Figure 6D] 3A to 3C are cross-sectional views illustrating the manufacturing method of the semiconductor memory device according to the first embodiment. [Figure 7] FIG. 2 is a diagram showing an application example of the structure of the first embodiment. [Figure 8] FIG. 2 is a diagram for explaining an application example of the structure of the first embodiment. [Figure 9] FIG. 2 is a diagram for explaining an application example of the structure of the first embodiment. [Figure 10] FIG. 2 is a diagram for explaining an application example of the structure of the first embodiment. [Figure 11] FIG. 11 is a perspective cross-sectional view showing a semiconductor memory device according to a second embodiment. [Figure 12] FIG. 11 is a cross-sectional view showing a semiconductor memory device according to a third embodiment. [Figure 13] FIG. 13 is a cross-sectional view showing a semiconductor memory device according to a fourth embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0008] Hereinafter, the semiconductor memory device of the embodiment will be described with reference to the drawings. In the following description, the same reference numerals are used for configurations having the same or similar functions. Then, duplicated descriptions of those configurations may be omitted. "Parallel", "orthogonal", or "same" may also include "substantially parallel", "substantially orthogonal", or "substantially the same", respectively. "Connection" is not limited to mechanical connection, but may also include electrical connection. In other words, "connection" is not limited to a case where multiple elements are directly connected, but may also include a case where multiple elements are connected with another element interposed therebetween. "Annular" is not limited to a circular ring, but may include a rectangular ring or a triangular ring.

[0009] First, referring to FIG. 1, the +X direction, the -X direction, the +Y direction, the -Y direction, the +Z direction, and the -Z direction are defined. The +X direction, the -X direction, the +Y direction, and the -Y direction are directions along the surface 11a of the semiconductor substrate 11 described later. The +X direction is the direction in which the source line 62 and the drain line 63 of the upper structure 60 described later extend. The -X direction is the opposite direction to the +X direction. When the +X direction and the -X direction are not distinguished, they are simply referred to as the "X direction". The +Y direction and the -Y direction are directions that intersect (for example, are perpendicular to) the X direction. The +Y direction is the direction in which the word line WL described later extends. The -Y direction is the opposite direction to the +Y direction. When the +Y direction and the -Y direction are not distinguished, they are simply referred to as the "Y direction". The +Z direction and the -Z direction are directions that intersect (for example, are perpendicular to) the X direction and the Y direction, and are the thickness direction of the semiconductor substrate 11. The +Z direction is the direction from the semiconductor substrate 11 toward the stack 20 described later. The -Z direction is the opposite direction to the +Z direction. When there is no need to distinguish between the +Z direction and the -Z direction, they are simply referred to as the "Z direction." In this specification, the "+Z direction" may be referred to as "up" and the "-Z direction" as "down." However, these expressions are for convenience and do not define the direction of gravity. The Y direction is an example of the "first direction." The Z direction is an example of the "second direction." The X direction is an example of the "third direction."

[0010] (First embodiment) <1. Configuration of Semiconductor Memory Device> First, the configuration of the semiconductor memory device 1 of the first embodiment will be described. In the drawings described below, illustrations of insulating parts that are not related to the description may be omitted. Also, in some drawings, hatching is applied only to a part of the cross section in order to make the drawings easier to see.

[0011] 1 is a perspective cross-sectional view showing a semiconductor memory device 1. The semiconductor memory device 1 is, for example, a non-volatile semiconductor memory device and a NOR type semiconductor memory device. The semiconductor memory device 1 includes, for example, a lower structure 10, a stacked body 20, and an upper structure 60.

[0012] <1.1 Lower structure> The lower structure 10 includes, for example, a semiconductor substrate 11, a stopper layer 12, and a diffusion layer 13.

[0013] The semiconductor substrate 11 is a substrate that serves as a base of the semiconductor memory device 1. At least a portion of the semiconductor substrate 11 is plate-shaped along the X direction and the Y direction. The semiconductor substrate 11 has a surface 11a that faces the stacked body 20 described below. The semiconductor substrate 11 is formed of, for example, a semiconductor material containing silicon (Si). The semiconductor substrate 11 is an example of a "substrate".

[0014] The stopper layer 12 is provided on the semiconductor substrate 11. The stopper layer 12 is a layer extending along the X direction and the Y direction. The stopper layer 12 is a layer for suppressing deep digging of the trench MT (see FIG. 5C) in the manufacturing process of the semiconductor memory device 1 described later. The stopper layer 12 is formed of a semiconductor material such as polysilicon (Poly-Si).

[0015] The diffusion layer 13 is provided as a part of the upper surface of the stopper layer 12. The diffusion layer 13 is a layer along the X direction and the Y direction. The diffusion layer 13 is a layer for ensuring electrical withstand voltage between the source line SL and the drain line DL described later. The diffusion layer 13 contains impurities different from those of the source line SL and the drain line DL, and has a different conductivity type from those of the source line SL and the drain line DL. In this embodiment, the source line SL and the drain line DL contain impurities that become donors and have an n-type (e.g., n+ type) conductivity type. In contrast, the diffusion layer 13 contains impurities that become acceptors and has a p-type (e.g., p- type) conductivity type. The acceptor is, for example, boron (B), but is not limited thereto. The stopper layer 12 may be omitted, and the diffusion layer 13 may be provided as a part of the upper surface of the semiconductor substrate 11. In this case, the upper surface of the diffusion layer 13 becomes the surface 11a of the semiconductor substrate 11.

[0016] <1.2 Laminate> Next, the laminate 20 will be described. The laminate 20 is provided on the lower structure 10. The laminate 20 has a plurality of first structural parts 21 and a plurality of second structural parts 22. The plurality of first structural parts 21 and the plurality of second structural parts 22 are alternately arranged one by one in the X direction.

[0017] <1.2.1 First structure part> First, the first structural portion 21 will be described. The multiple first structural portions 21 are separated from each other in the X direction and extend parallel to each other in the Y direction. Hereinafter, the multiple first structural portions 21 at different positions in the X direction will be referred to as multiple columns S (first column S1, second column S2, third column S3, ...).

[0018] Each of the first structural portions 21 includes a plurality of functional layers 30 and a plurality of insulating layers 40. The functional layers 30 and the insulating layers 40 are alternately stacked one by one in the Z direction. Although six functional layers 30 and seven insulating layers 40 are shown in FIG. 1, in reality, even more functional layers 30 and insulating layers 40 are stacked.

[0019] Fig. 2 is a cross-sectional view of the semiconductor memory device 1 shown in Fig. 1 taken along line F2-F2. For convenience of explanation, Fig. 2 shows a cross section taken along a cutting line passing through a plurality of source lines SL, which will be described later. The functional layer 30 is layered along the X direction and the Y direction. The functional layer 30 includes, for example, a word line WL, a first side structure SB1 located on the -X direction side of the word line WL, and a second side structure SB2 located on the +X direction side of the word line WL.

[0020] The word line WL extends linearly in the Y direction. The word line WL is, for example, a wiring to which a voltage is applied when writing or reading a data value to a memory cell MC described later. In this embodiment, the word lines WL are separated from one another so that a voltage can be applied to each of them independently. The word line WL includes, for example, a main body portion 31a and a barrier metal film 31b. The main body portion 31a is provided inside the barrier metal film 31b to form a main portion of the word line WL. The main body portion 31a is formed of a conductive material such as tungsten (W) or polysilicon (Poly-Si) doped with impurities. The barrier metal film 31b is provided on the surface of the word line WL. The barrier metal film 31b is a film that suppresses the diffusion of a material contained in the main body portion 31a. The barrier metal film 31b is formed of, for example, titanium nitride (TiN).

[0021] Next, the first side structure SB1 will be described. The first side structure SB1 includes, for example, a block insulating film 32A, a memory film 33A, a tunnel insulating film 34A, and a channel 35A.

[0022] The block insulating film 32A is located on the −X direction side with respect to the word line WL (hereinafter referred to as the “specific word line WL”) included in the same functional layer 30. The block insulating film 32A is an insulating film for suppressing back tunneling. Back tunneling is a phenomenon in which charges return from the word line WL to the memory film 33A. The block insulating film 32A is provided, for example, along the side surface of the specific word line WL on the −X direction side, the upper surface of the insulating layer 40 below, and the lower surface of the insulating layer 40 above. The block insulating film 32A extends linearly in the Y direction along the side surface of the word line WL. The block insulating film 32A is formed, for example, of a laminated structure film in which a silicon oxide film, a metal oxide film, and a plurality of insulating films are laminated. An example of the metal oxide is aluminum oxide (Al2O3). The block insulating film 32A may include a high dielectric constant material (high-k material) such as silicon nitride (SiN) or hafnium oxide (HfO).

[0023] The memory film 33A is located on the −X direction side with respect to the specific word line WL. The memory film 33A is a functional film capable of storing information based on the state of the memory film 33A. The memory film 33A stores information based on, for example, a voltage applied to the specific word line WL. The memory film 33A is, for example, a charge trap film capable of storing charges in crystal defects. The charge trap film is formed of, for example, silicon nitride (Si3N4). The block insulating film 32A is provided, for example, along the side surface of the block insulating film 32A on the −X direction side, the upper surface of the lower part of the block insulating film 32A, and the lower surface of the upper part of the block insulating film 32A. The memory film 33A extends linearly in the Y direction along the side surface of the block insulating film 32A.

[0024] The tunnel insulating film 34A is located on the −X direction side with respect to the specific word line WL. The tunnel insulating film 34A is a potential barrier between the memory film 33A and the channel 35A. The tunnel insulating film 34A is provided, for example, along the side surface of the memory film 33A on the −X direction side, the upper surface of the lower part of the memory film 33A, and the lower surface of the upper part of the memory film 33A. The tunnel insulating film 34A extends linearly in the Y direction along the side surface of the memory film 33A. The tunnel insulating film 34A is formed of an insulating material including silicon oxide (SiO2) or silicon oxide (SiO2) and silicon nitride (SiN).

[0025] The channel 35A is located on the −X direction side with respect to the specific word line WL. The channel 35A is, for example, a wiring through which a current flows when writing or reading a data value to a memory cell MC described later. A current flows through the channel 35A between a pair of a source line SL and a drain line DL. The channel 35A is provided, for example, along the side surface of the tunnel insulating film 34A on the −X direction side, the upper surface of the lower part of the tunnel insulating film 34A, and the lower surface of the upper part of the tunnel insulating film 34A. The channel 35A extends linearly in the Y direction along the side surface of the tunnel insulating film 34A. The channel 35A is formed of, for example, a semiconductor material such as amorphous silicon (a-Si).

[0026] Next, the second side structure SB2 will be described. The second side structure SB2 includes, for example, a block insulating film 32B, a memory film 33B, a tunnel insulating film 34B, and a channel 35B. The details of the components of the second side structure SB2 are the same as those of the first side structure SB1 described above. That is, the details of the components of the second side structure SB2 can be obtained by replacing the "-X direction", "first side structure SB1", "block insulating film 32A", "memory film 33A", "tunnel insulating film 34A", and "channel 35A" in the above description of the first side structure SB1 with the "+X direction", "second side structure SB2", "block insulating film 32B", "memory film 33B", "tunnel insulating film 34B", and "channel 35B", respectively. In the following, when there is no distinction between the "memory film 33A" and the "memory film 33B", they will be referred to as the "memory film 33", and when there is no distinction between the "channel 35A" and the "channel 35B", they will be referred to as the "channel 35".

[0027] Next, the insulating layer 40 will be described. The insulating layer 40 is a layer along the X direction and the Y direction. The insulating layer 40 is made of an insulating material such as silicon oxide (SiO2). The insulating layer 40 is provided between the multiple functional layers 30 arranged in the Z direction, and electrically insulates the multiple functional layers 30 arranged in the Z direction from each other.

[0028] In this embodiment, the insulating layer 40 has a first portion 41, a second portion 42, and a third portion 43. The first portion 41 is located in the Z direction between the word line WL included in the functional layer 30 immediately below the insulating layer 40 and the word line WL included in the functional layer 30 immediately above the insulating layer 40. As a result, the first portion 41 electrically insulates the word line WL included in the functional layer 30 immediately below the insulating layer 40 from the word line WL included in the functional layer 30 immediately above the insulating layer 40.

[0029] The second portion 42 is located on the −X direction side with respect to the first portion 41. The second portion 42 is provided in the Z direction between the first side structure SB1 (i.e., the block insulating film 32A, the memory film 33A, the tunnel insulating film 34A, and the channel 35A) included in the functional layer 30 one layer below the insulating layer 40 and the first side structure SB1 (i.e., the block insulating film 32A, the memory film 33A, the tunnel insulating film 34A, and the channel 35A) included in the functional layer 30 one layer above the insulating layer 40. As a result, the second portion 42 electrically insulates the first side structure SB1 included in the functional layer 30 one layer below the insulating layer 40 from the first side structure SB1 included in the functional layer 30 one layer above the insulating layer 40.

[0030] The third portion 43 is located on the +X direction side with respect to the first portion 41. The third portion 43 is provided in the Z direction between the second side structure SB2 (i.e., the block insulating film 32B, the memory film 33B, the tunnel insulating film 34B, and the channel 35B) included in the functional layer 30 one layer below the insulating layer 40 and the second side structure SB2 (i.e., the block insulating film 32B, the memory film 33B, the tunnel insulating film 34B, and the channel 35B) included in the functional layer 30 one layer above the insulating layer 40. As a result, the third portion 43 electrically insulates the second side structure SB2 included in the functional layer 30 one layer below the insulating layer 40 from the second side structure SB2 included in the functional layer 30 one layer above the insulating layer 40.

[0031] <1.2.2 Second structure section> 1, the second structural portion 22 will be described. The second structural portions 22 are spaced apart from each other in the X direction and extend parallel to each other in the Y direction. Each of the second structural portions 22 includes a plurality of source lines SL, a plurality of drain lines DL, and a plurality of insulators 52.

[0032] The multiple source lines SL and multiple drain lines DL are alternately arranged with intervals in the Y direction. Each of the source lines SL and drain lines DL extends in the Z direction and penetrates the stack 20 along the Z direction. That is, each of the source lines SL and drain lines DL extends from above the uppermost functional layer 30 to the side of or below the lowermost functional layer 30 among the multiple functional layers 30 aligned in the Z direction.

[0033] Each of the source line SL and the drain line DL includes, for example, a main body portion 51a and a surface layer portion 51b. The main body portion 51a is provided inside the surface layer portion 51b to form the main portion of the source line SL or the drain line DL. The main body portion 51a is formed of, for example, a conductive material such as a metal material or polysilicon (Poly-Si) doped with impurities. In this embodiment, the main body portion 51a is formed of a metal material such as tungsten (W). The surface layer portion 51b is provided on the surface of the source line SL or the drain line DL, and is formed in a ring shape surrounding the main body portion 51a from the +X direction, the -X direction, the +Y direction, and the -Y direction. A part of the surface layer portion 51b covers the lower surface of the main body portion 51a and is located between the main body portion 51a and the diffusion layer 13. In this embodiment, the surface layer portion 51b contains impurities that serve as donors and has an n-type (for example, n+ type) conductivity type. The lower end portions of each of the source line SL and the drain line DL are in contact with the diffusion layer 13 of the lower structure 10. As a result, a PN junction 14 having a depletion layer and improving electrical breakdown voltage is formed between the semiconductor substrate 11 and each of the source line SL and the plurality of drain lines DL.

[0034] The multiple source lines SL and multiple drain lines DL included in one second structure 22 are arranged between two first structure parts 21 adjacent to each other in the X direction. Hereinafter, the multiple second structure parts 22 having different positions in the X direction will be referred to as multiple columns T (first column T1, second column T2, third column T3, ...).

[0035] The source lines SL and drain lines DL included in the first column T1 are located on the -X direction side with respect to the functional layers 30 included in the first column S1. The source lines SL and drain lines DL included in the first column T1 contact the channels 35A of the functional layers 30 included in the first column S1 from the -X direction side and are electrically connected to the channels 35A of the functional layers 30. As a result, the source lines SL and drain lines DL included in the first column T1 function as sources and drains for the channels 35A of the functional layers 30 included in the first column S1. That is, in the first column T1, one source line SL and one drain line DL adjacent to the source line SL can be electrically connected via the channel 35A. In this embodiment, the source lines SL and drain lines DL included in the first column T1 contact the insulating layers 40 included in the first column S1 from the -X direction side.

[0036] The source lines SL and drain lines DL included in the second column T2 are located between the functional layers 30 included in the first column S1 and the functional layers 30 included in the second column S2 in the X direction. The source lines SL and drain lines DL included in the second column T2 contact the channels 35B of the functional layers 30 included in the first column T1 from the +X direction side and are electrically connected to the channels 35B of the functional layers 30. As a result, the source lines SL and drain lines DL included in the second column T2 function as sources and drains for the channels 35B of the functional layers 30 included in the first column T1. That is, in the second column T2, one source line SL and one drain line DL adjacent to the source line SL can be electrically connected via the channel 35B. In this embodiment, the source lines SL and drain lines DL included in the second column T2 contact the insulating layers 40 included in the first column S1 from the +X direction side.

[0037] Furthermore, the source lines SL and drain lines DL included in the second column T2 contact the channels 35A of the functional layers 30 included in the second column S2 from the -X direction side and are electrically connected to the channels 35A of the functional layers 30. As a result, the source lines SL and drain lines DL included in the second column T2 function as sources and drains for the channels 35A of the functional layers 30 included in the second column S2. That is, in the second column T2, one source line SL and one drain line DL adjacent to the source line SL can be electrically connected via the channel 35A. The source lines SL and drain lines DL included in the second column T2 contact the insulating layers 40 included in the second column S2 from the -X direction side. The source lines SL and drain lines DL belonging to the third column T3 and subsequent columns T are similar to the source lines SL and drain lines DL included in the second column T2.

[0038] Next, the insulator 52 will be described. FIG. 3 is a cross-sectional view taken along line F3-F3 of a portion of the semiconductor memory device 1 shown in FIG. 1. The insulator 52 is provided between the source line SL and the drain line DL adjacent to each other in the Y direction. The width W2 of the insulator 52 in the X direction is the same as the width W1 of the source line SL or the drain line DL in the X direction. The insulator 52 extends in the Z direction over the entire length (total height) of the source line SL and the drain line DL. The insulator 52 is provided between the source line SL and the drain line DL adjacent to each other in the Y direction, and electrically insulates the source line SL and the drain line DL in the Y direction. For example, the insulator 52 is provided between a pair of the source line SL and the drain line DL electrically connected via the channel 35, and electrically insulates the source line SL and the drain line DL in the Y direction.

[0039] In this embodiment, the multiple source lines SL and multiple drain lines DL included in the even-numbered columns T (T2, T4, ...) are arranged shifted in the Y direction with respect to the multiple source lines SL and multiple drain lines DL included in the odd-numbered columns T (T1, T3, ...).

[0040] With the above-mentioned configuration, the semiconductor memory device 1 includes a plurality of memory cells MC. That is, in the first side structure SB1 and the second side structure SB2, a region located between a pair of a source line SL and a drain line DL that are electrically connected to each other functions as a memory cell MC. The memory cell MC is, for example, a MANOS (Metal-Al-Nitride-Oxide-Silicon) type memory cell. The plurality of memory cells MC are three-dimensionally arranged at intervals in the X-direction, the Y-direction, and the Z-direction.

[0041] <1.4 Upper structure> Next, returning to FIG. 1, the upper structure 60 will be described. The upper structure 60 includes, for example, a plurality of contacts 61, a plurality of source lines 62, and a plurality of drain lines 63. The plurality of contacts 61 are, for example, cylindrical or conical conductor parts. The plurality of contacts 61 are disposed above the stack 20 and extend in the Z direction. The plurality of contacts 61 are disposed corresponding to the plurality of source lines 62 and the plurality of drain lines 63, and are connected to the plurality of source lines 62 and the plurality of drain lines 63 in a one-to-one relationship.

[0042] The multiple source lines 62 are spaced apart from each other in the Y direction and extend in the X direction. The multiple source lines 62 include multiple source lines 62A (only one is shown in FIG. 1) and multiple source lines 62B (only one is shown in FIG. 1). The source line 62A is disposed above a contact 61 connected to multiple source lines SL included in odd-numbered columns T (T1, T3, ...), and is commonly connected to multiple source lines SL included in odd-numbered columns T via the contact 61. On the other hand, the source line 62B is disposed above a contact 61 connected to multiple source lines SL included in even-numbered columns T (T2, T4, ...), and is commonly connected to multiple source lines SL included in even-numbered columns T via the contact 61.

[0043] The drain lines 63 are spaced apart from each other in the Y direction and extend in the X direction. The drain lines 63 include a plurality of drain lines 63A (only one of which is shown in FIG. 1) and a plurality of drain lines 63B (only one of which is shown in FIG. 1). The drain line 63A is disposed above a contact 61 connected to the drain lines DL included in the odd-numbered columns T (T1, T3, ...), and is commonly connected to the drain lines DL included in the odd-numbered columns T via the contact 61. On the other hand, the second drain line 63B is disposed above a contact 61 connected to the drain lines DL included in the even-numbered columns T (T2, T4, ...), and is commonly connected to the drain lines DL included in the even-numbered columns T via the contact 61.

[0044] 4A is a diagram showing an equivalent circuit of the semiconductor memory device 1. As shown in FIG. 4A, a plurality of memory cells MC are three-dimensionally arranged at intervals in the X, Y, and Z directions. For example, one memory cell MC can be selected by a combination of a word line WL, a source line SL, and a drain line DL. In the semiconductor memory device 1, any memory cell MC can be randomly accessed.

[0045] FIG. 4B is a diagram showing an equivalent circuit of a modified example of the semiconductor memory device 1. In the modified example shown in FIG. 4B, among the word lines WL having the same position in the Z direction (i.e., the word lines WL aligned in the X direction), the word lines WL included in the odd-numbered columns S1, S3, S5, ... among the columns S are connected to each other via a connection part C1, and a voltage can be applied collectively. Also, among the word lines WL having the same position in the Z direction (i.e., the word lines WL aligned in the X direction), the word lines WL included in the even-numbered columns S2, S4, S6, ... among the columns S are electrically connected to each other via a connection part C2, and a voltage can be applied collectively. On the other hand, the source lines SL and / or the drain lines DL corresponding to the word lines WL connected to each other are separated one by one so that a voltage can be applied independently. According to such a configuration, it may be possible to simplify the wiring layout related to the word lines WL and to miniaturize the semiconductor memory device 1. Note that the word lines WL having the same position in the Z direction may be coupled every two lines instead of every two lines.

[0046] <2. Example of operation> Next, an example of the operation of the semiconductor memory device 1 will be described. In the semiconductor memory device 1, for example, a combination of a word line WL, a source line SL, and a drain line DL allows an arbitrary memory cell MC to be selected as a target for writing data values ​​or a target for reading data values. For example, in a write operation, the peripheral circuit of the semiconductor memory device 1 applies a voltage to the drain line DL (or source line SL) corresponding to the memory cell MC to be written, and applies a programming pulse as a write voltage to the word line WL corresponding to the memory cell MC to be written. The programming pulse is a pulse whose voltage gradually increases with each cycle. This causes a current to flow in the region between the source line SL and drain line DL corresponding to the memory cell MC to be written in the channel 35, and charges are accumulated in the memory cell MC to be written. This causes a data value to be stored in the memory cell MC.

[0047] On the other hand, in a read operation, the sense amplifier circuit of the semiconductor memory device 1 precharges the drain line DL corresponding to the memory cell MC to be read with the power supply potential Vcc. The peripheral circuit of the semiconductor memory device 1 sequentially applies a plurality of types of determination potentials (threshold determination voltages) to the word line WL corresponding to the memory cell MC to be read in order to determine the threshold voltage of the memory cell MC. The sense amplifier circuit determines the data value stored in the memory cell MC to be read by detecting which determination voltage is applied when the charge accumulated by the precharge flows out to the source line SL (or drain line DL).

[0048] <3. Manufacturing method of semiconductor memory device> Next, a description will be given of a method for manufacturing the semiconductor memory device 1. Figures 5A to 5J are perspective cross-sectional views for explaining the method for manufacturing the semiconductor memory device 1.

[0049] 5A, a diffusion layer 13 is formed on an upper surface of the stopper layer 12 (or the semiconductor substrate 11). The diffusion layer 13 is formed, for example, by doping an impurity into the upper surface of the stopper layer 12 (or the semiconductor substrate 11) and performing an annealing treatment.

[0050] Next, as shown in FIG. 5B, insulating layers 101 made of silicon oxide (SiO2) and insulating layers 102 made of silicon nitride (SiN) are alternately laminated on the diffusion layer 13. This forms the intermediate structure 100. The insulating layers 102 are sacrificial layers that will be replaced with a plurality of functional layers 30 in a later process. Then, a stopper layer 103 is provided as a mask on the intermediate structure 100. The stopper layer 103 is formed of, for example, amorphous silicon (aSi) or a metal material.

[0051] Next, as shown in FIG. 5C, a plurality of trenches MT are formed by etching using the stopper layer 103. Each trench MT is a groove dug in the Z direction and extending in the Y direction. As a result, the insulating layer 101 becomes a plurality of insulating layers 40 divided in the X direction, and the insulating layer 102 becomes a plurality of insulating layers 104 divided in the X direction. Next, an etching solution (for example, hot phosphoric acid (H3PO4)) is supplied to each trench MT, and both ends of the insulating layer 104 in the X direction are removed by etching. As a result, the side surface of the insulating layer 104 in the -X direction forms a first recess 105A recessed in the +X direction relative to the side surface of the insulating layer 40 in the -X direction. Similarly, the side surface of the insulating layer 104 in the +X direction forms a second recess 105B recessed in the -X direction relative to the side surface of the insulating layer 40 in the +X direction.

[0052] Next, as shown in FIG. 5D, the material that is the source of the block insulating film, the memory film, the tunnel insulating film, and the channel is supplied to the inner surface of the trench MT. Then, unnecessary parts are removed by etching. In this embodiment, after the inside of the first recess 105A and the second recess 105B are blocked with the channel material, a choline-based wet solution is used to etch back only the channel material, or the channel material, the tunnel insulating film material, and even the memory film material, thereby forming the channel 35 only inside the first recess 105A and the second recess 105B. As a result, the block insulating film 32A, the memory film 33A, the tunnel insulating film 34A, and the channel 35A are formed on the inner surface of the first recess 105A, and the block insulating film 32B, the memory film 33B, the tunnel insulating film 34B, and the channel 35B are formed on the inner surface of the second recess 105B. As a result, a plurality of first structural portions 21 are formed.

[0053] 5E, the trench MT is filled with an insulating material such as silicon oxide (SiO2) to form an insulator 111 inside the trench MT. The insulator 111 has a plate shape along the Y direction and the Z direction.

[0054] Next, as shown in FIG. 5F, holes H are formed by etching at positions where source lines SL and drain lines DL will be formed in a later process. The holes H are holes extending in the Z direction. Next, as shown in FIG. 5G, the source lines SL or drain lines DL are formed inside the holes H. For example, a surface layer portion 51b containing polysilicon (Poly-Si) doped with impurities is formed on the inner surface of the holes H. Next, a metal material is supplied inside the surface layer portion 51b to form a main body portion 51a. In this way, an intermediate structure 120 is obtained.

[0055] Next, as shown in FIG. 5H, a replacement step is performed. Specifically, first, a plurality of holes STH (see FIG. 6C) for the replacement step are formed in the intermediate structure 120. The holes STH penetrate the plurality of insulating layers 40 and the insulating layer 104 in the Z direction. Next, an etching solution (for example, hot phosphoric acid (H3PO4) is supplied to the holes STH, and the insulating layer 104 is removed by etching.

[0056] Next, as shown in FIG. 5I, the word line WL is formed in the space from which the insulating layer 104 has been removed. For example, first, a barrier metal film 31b is formed in the space from which the insulating layer 104 has been removed. Next, a metal material is supplied into the barrier metal film 31b to form the main body portion 31a. Next, as shown in FIG. 5J, the upper structure 60 is formed. Through these steps, the semiconductor memory device 1 is completed.

[0057] Next, a supplementary description will be given of some steps in the manufacturing method of the semiconductor memory device 1. Figures 6A to 6D are cross-sectional views for explaining the manufacturing method of the semiconductor memory device 1. Figures 6A to 6D typically show planar layouts of the semiconductor memory device 1 along the X and Y directions.

[0058] Fig. 6A is a process corresponding to Fig. 5C, in which a plurality of trenches MT are formed. In this embodiment, the intermediate structure 100 has a plurality of support parts 131 for supporting the stacked insulating layers 40 and the insulating layers 104 so as not to collapse. Fig. 6B is a process corresponding to Fig. 5E, in which an insulator 111 is formed inside the trench MT.

[0059] Fig. 6C is a process corresponding to Fig. 5H, in which a plurality of holes STH for the replacement process are formed in the intermediate structure 120. In this embodiment, the holes STH are provided at positions corresponding to the support portions 131. As a result, the support portions 131 are removed. Fig. 6D is a process corresponding to Fig. 5I, in which the word lines WL are formed.

[0060] <4. Advantages> As a comparative example, consider a structure having a stack in which a plurality of word lines and a plurality of insulating layers are alternately stacked on a substrate, a source line and a drain line extending in the thickness direction of the substrate within the stack, and a memory layer and a channel layer located between the source line and the drain line and adjacent to the plurality of word lines and the plurality of insulating layers. In such a structure, the electrical characteristics (e.g., data write characteristics or erase characteristics) of the semiconductor memory device may be degraded.

[0061] For example, in the above structure, since the channel layer is connected in the thickness direction of the substrate, a fringe electric field is also applied to the portion of the channel layer corresponding to the space between two adjacent word lines, and a fringe transistor portion is easily formed. As a result, when data is written at a low voltage, electrons are written to the transistor portion on the side of the word line in the memory layer, and the threshold voltage rises, but electrons are not easily written to the portion (the fringe transistor portion) corresponding to the space between two adjacent word lines, and the threshold voltage does not rise. As a result, when data is read, the transistor portion on the side of the word line, whose threshold voltage has risen, does not turn on, and the fringe transistor portion turns on, so it is determined that the data is not stored. Since such a read disturb phenomenon may occur, problems may arise with respect to the reliability of memory operation. A similar phenomenon may also occur when erasing data.

[0062] Furthermore, in the structure of the comparative example, the source line and drain line are formed by introducing n-type impurities into polysilicon integrated with the channel, so it is difficult to form the source line and drain line with a metal material. For example, if a metal material is embedded as the source line and drain line, the metal is formed including the channel, resulting in a structure in which the source line and drain line are shorted. For this reason, the source line and drain line are formed with polysilicon doped with impurities. As a result, the wiring resistance of the source line and drain line is high, and it is difficult to obtain a sufficient read speed due to RC delay.

[0063] On the other hand, as shown in FIGS. 2 and 3, in this embodiment, the semiconductor memory device 1 includes a first word line WL (WL1) extending in the Y direction, a second word line WL (WL2) separated from the first word line WL in the Z direction and extending in the Y direction, a first channel 35A aligned with the first word line WL in the X direction and extending in the Y direction, a first memory film 33A located between the first word line WL and the first channel 35A in the Z direction and extending in the Y direction, a second channel 35A aligned with the second word line WL in the X direction and extending in the Y direction, and a second memory film 33A located between the second word line WL and the second channel 35A in the X direction. The semiconductor memory device 1 includes a second memory film 33A located in the Y direction and extending in the Y direction, a first insulating layer 40 located between the first word line WL and the second word line WL in the Z direction and between the first channel 35A and the second channel 35A in the Z direction, a first source line SL (SL1) located on the opposite side of the first word line WL with respect to the first channel 35A in the X direction and extending in the Z direction, and a first drain line DL (DL1) separated from the first source line SL in the Y direction, located on the opposite side of the first word line WL with respect to the first channel 35A in the X direction and extending in the Z direction. With this configuration, the first channel 35A and the second channel 35A are separated in the Z direction, and a fringe transistor portion is unlikely to be formed. As a result, the semiconductor memory device 1 can improve electrical characteristics (for example, data write characteristics or erase characteristics).

[0064] Furthermore, in this embodiment, each of the source line SL and the drain line DL includes a metal material. With this configuration, the wiring resistance of the source line SL and the drain line DL can be reduced, and the influence of the RC delay can be suppressed. As a result, the read speed can be improved.

[0065] In this embodiment, the semiconductor memory device 1 further includes a first insulator 52 located between the first source line SL and the first drain line DL in the Y direction and extending in the X direction. The first source line SL1 and the first drain line DL1 can be electrically connected to each other via the first channel 35A. With this configuration, it is possible to increase the insulation between the first source line SL1 and the first drain line DL1, and to improve the selective write characteristics.

[0066] In this embodiment, the semiconductor memory device 1 further includes a third channel 35B extending in the Y direction and aligned with the first word line WL from the side opposite the channel 35A in the X direction, a third memory film 33B located between the first word line WL and the third channel 35B in the X direction and extending in the Y direction, a fourth channel 35B extending in the Y direction and aligned with the second word line WL from the side opposite the second channel 35A in the X direction, a fourth memory film 33B extending in the Y direction and aligned with the second word line WL from the side opposite the second channel 35A in the X direction, between the second word line WL and the fourth channel 35B in the X direction, a second source line SL (SL2) extending in the Z direction and aligned with the third channel 35B in the X direction, and a second drain line DL (DL2) extending in the Z direction, separated from the second source line SL in the Y direction, positioned on the side opposite the first word line WL1 with respect to the fourth channel 35B in the X direction. The first insulating layer 40 is located between the third channel 35B and the fourth channel 35B in the Z direction. With this configuration, the third channel 35B and the fourth channel 35B are separated in the Z direction, making it difficult for a fringe transistor portion to be formed. This allows the semiconductor memory device 1 to further improve its electrical characteristics (for example, data write characteristics or erase characteristics).

[0067] In this embodiment, the semiconductor memory device 1 includes a third word line WL (WL3) located on the opposite side of the first word line WL with respect to the first source line SL in the X direction and extending in the first direction, a fourth word line WL (WL4) located on the opposite side of the second word line WL with respect to the first source line SL in the X direction and extending in the Y direction, a fifth channel 35B located between the third word line WL and the first source line SL in the X direction and extending in the Y direction, and a fifth channel 35B between the third word line WL and the fifth channel 35B in the X direction. and extending in the first direction, a sixth channel 35B located between the fourth word line WL and the first source line SL in the X direction and extending in the Y direction, a sixth memory film 33B located between the fourth word line WL and the sixth channel 35B in the X direction and extending in the Y direction, and a second insulating layer 40 located between the third word line WL and the fourth word line WL in the Z direction and between the fifth channel 35B and the sixth channel 35B in the Z direction. With this configuration, the fifth channel 35B and the sixth channel 35B are separated in the Z direction, making it difficult for a fringe transistor portion to be formed. As a result, the semiconductor memory device 1 can further improve its electrical characteristics (for example, data write characteristics or erase characteristics).

[0068] <5. Other application examples> 7 is a diagram showing an application example of the structure of the first embodiment. The semiconductor memory device 1 described in the first embodiment can be used as a multiply-accumulate calculation element (MAC: Multiply-Accumulate calculation element). For example, the semiconductor memory device 1 can be used as a multiply-accumulate calculation element used for calculations in a trained model of machine learning such as deep learning.

[0069] In this application example, the multiple word lines WL included in the semiconductor memory device 1 are not coupled to each other, and different voltages can be applied to each of them independently. A gate voltage Vg (gate voltages Vg1, Vg2, ...) corresponding to weight data is applied to each of the multiple word lines WL. A voltage Vd (voltages Vd1, Vd2, ...) corresponding to input data is applied to each of the multiple source lines SL. A current Id (currents Id1, Id2, ...) corresponding to output data flows through each of the multiple drain lines DL. The magnitude of the current Id indicating the content of the output data is an addition result obtained by adding the multiplication results (products) in each memory cell MC for multiple memory cells MC included in the same column S, and further adding the addition results for multiple columns S (S1, S2, ...).

[0070] Fig. 8 is a diagram for explaining formula (1) described later. As shown in Fig. 8, in a transistor corresponding to a memory cell MC, the gate voltage applied to the gate (word line WL) is defined as Vg, the gate length as L, the gate width as W, the gate capacitance as Cox, the current flowing through the drain (drain line DL) as the drain current Id, the voltage of the drain current Id as the drain voltage Vd, the mobility as μ, and the threshold voltage as Vth. In this case, the magnitude of the drain current Id is calculated by the following formula (1).

[0071]

number

[0072] FIG. 9 is another diagram for explaining one application example. The solid line in FIG. 9 shows the relationship between the gate voltage Vg and the drain voltage Vd. The dashed line in FIG. 9 shows the magnitude of the drain current Id relative to the gate voltage Vg and the drain voltage Vd. The magnitude of the drain current Id is determined based on the product of the gate voltage Vg and the drain voltage Vd.

[0073] FIG. 10 is another diagram for explaining one application example. As shown in FIG. 10, the magnitude of the drain current Id is determined based on the relationship between the gate voltage Vg and the drain voltage Vd. The semiconductor memory device 1 as a product-sum operation element can sequentially add and output the drain currents Id related to a plurality of memory cells MC. This makes it possible to output the result of the product-sum operation.

[0074] Second embodiment Next, a second embodiment will be described. The second embodiment differs from the first embodiment in that an insulating layer 151 is provided between the source line SL and the drain line DL and the semiconductor substrate 11. The configuration other than that described below is the same as that of the first embodiment.

[0075] FIG. 11 is a perspective cross-sectional view showing a semiconductor memory device 1A of the second embodiment. The lower structure 10 of the semiconductor memory device 1A has an insulating layer 151 instead of the stopper layer 12 and the diffusion layer 13. The insulating layer 151 functions as an etching stopper layer and also functions as a layer for ensuring electrical withstand voltage between the source line SL and the drain line DL. The insulating layer 151 is formed of, for example, aluminum oxide (AlO), hafnium oxide (HfO), zirconia (ZrO), titanium oxide (TiO), oxygen-doped silicon carbide (SiCO), nitrogen-doped silicon carbide (SiCN), boron nitride (BN), high-temperature carbon, or the like. With such a configuration, the same effect as in the first embodiment can be expected.

[0076] Third embodiment Next, a third embodiment will be described. The third embodiment differs from the first embodiment in the layout of the source lines SL and the drain lines DL. The configuration other than that described below is the same as that of the first embodiment.

[0077] 12 is a cross-sectional view showing a semiconductor memory device 1B of the third embodiment. In the above-mentioned first embodiment, the source lines SL and drain lines DL included in the even-numbered columns T (T2, T4, ...) are arranged to be shifted in the Y direction with respect to the source lines SL and drain lines DL included in the odd-numbered columns T (T1, T3, ...). On the other hand, in the third embodiment, the source lines SL and drain lines DL included in the even-numbered columns T (T2, T4, ...) and the source lines SL and drain lines DL included in the odd-numbered columns T (T1, T3, ...) are arranged at the same positions in the Y direction. In other words, the source lines SL and drain lines DL included in the even-numbered columns T (T2, T4, ...) and the source lines SL and drain lines DL included in the odd-numbered columns T (T1, T3, ...) are aligned in the X direction. With this configuration, the electrical characteristics can be improved as in the first embodiment.

[0078] (Fourth embodiment) Next, a fourth embodiment will be described. The fourth embodiment differs from the third embodiment in that the memory cells MC arranged in the Y direction are separated from each other. The configuration other than that described below is the same as that of the third embodiment.

[0079] 13 is a cross-sectional view showing a semiconductor memory device 1C of a fourth embodiment. In this embodiment, a memory cell MC is provided between a pair of a source line SL and a drain line DL that are electrically connected to each other. A plurality of memory cells MC arranged in the Y direction are separated from each other. In this embodiment, a distance L1 in the Y direction between a pair of a source line SL and a drain line DL corresponding to the same memory cell MC is shorter than a distance L2 in the Y direction between a pair of a source line SL and a drain line DL that do not correspond to the same memory cell MC.

[0080] In this embodiment, the block insulating film 32A, the memory film 33A, the tunnel insulating film 34A, and the channel 35A are each separated between the memory cells MC arranged in the Y direction in the first side structure SB1. In this case, the block insulating film 32Aa, the memory film 33Aa, the tunnel insulating film 34Aa, and the channel 35Aa corresponding to each memory cell MC are formed. Similarly, the block insulating film 32B, the memory film 33B, the tunnel insulating film 34B, and the channel 35B are each separated between the memory cells MC arranged in the Y direction in the second side structure SB2. In this case, the block insulating film 32Ba, the memory film 33Ba, the tunnel insulating film 34Ba, and the channel 35Ba corresponding to each memory cell MC are formed.

[0081] In detail, the first column T1 includes a source line SL (first source line SL1), a drain line DL (first drain line DL1), another source line SL (third source line SL3), and another drain line DL (third drain line DL3) arranged in order in the Y direction. The third source line SL3 is located on the opposite side of the first drain line DL1 from the first source line SL1. The third drain line DL3 is located on the opposite side of the third source line SL3 from the first drain line DL1. A distance L1 in the Y direction between the first source line SL1 and the first drain DL1 is smaller than a distance L2 between the first drain DL1 and the third source line SL3. Similarly, a distance L1 in the Y direction between the third source line SL3 and the third drain DL3 is smaller than a distance L3 between the first drain DL1 and the third source line SL3.

[0082] The block insulating film 32Aa, memory film 33Aa, tunnel insulating film 34Aa, and channel 35Aa aligned with the first source line SL1 and the first drain line DL1 in the X direction are separated from the block insulating film 32Aa, memory film 33Aa, tunnel insulating film 34Aa, and channel 35Aa aligned with the third source line SL3 and the third drain line DL3 in the X direction in the Y direction. In this embodiment, the memory film 33Aa and channel 35Aa aligned with the first source line SL1 and the first drain line DL1 in the X direction are examples of the "first memory film" and the "first channel", respectively. The memory film 33Aa and channel 35Aa aligned with the third source line SL3 and the third drain line DL3 in the X direction are examples of the "seventh memory film" and the "seventh channel", respectively.

[0083] Similarly, the second column T2 includes a source line SL (second source line SL2), a drain line DL (second drain line DL2), another source line SL (fourth source line SL4), and another drain line DL (fourth drain line DL4) arranged in sequence in the Y direction. The fourth source line SL4 is located on the opposite side of the second source line SL2 with respect to the second drain line DL2. The fourth drain line DL4 is located on the opposite side of the second drain line DL2 with respect to the fourth source line SL4. A distance L1 in the Y direction between the second source line SL2 and the second drain DL2 is smaller than a distance L2 between the second drain DL2 and the fourth source line SL4. Similarly, a distance L1 in the Y direction between the fourth source line SL4 and the fourth drain DL4 is smaller than a distance L2 between the second drain DL2 and the fourth source line SL4.

[0084] The block insulating film 32Ba, the memory film 33Ba, the tunnel insulating film 34Ba, and the channel 35Ba aligned in the X direction with the second source line SL2 and the second drain line DL2, and the block insulating film 32Ba, the memory film 33Ba, the tunnel insulating film 34Ba, and the channel 35Ba aligned in the X direction with the fourth source line SL4 and the fourth drain line DL4, are each divided in the Y direction.

[0085] In this embodiment, each word line WL has a plurality of body portions WLa and a plurality of wide portions WLb. The body portions WLa are aligned in the X direction with the block insulating films 32Aa and 32Ba, the memory films 33Aa and 33Ba, the tunnel insulating films 34Aa and 34Ba, and the channels 35Aa and 35Ba. The body portions WLa aligned in the X direction with the first source line SL1 and the first drain line DL1 are an example of a "first portion." The body portions WLa aligned in the X direction with the third source line SL3 and the third drain line DL3 are an example of a "second portion."

[0086] The wide portions WLb are not aligned in the X direction with the block insulating films 32Aa, 32Ba, the memory films 33Aa, 33Ba, the tunnel insulating films 34Aa, 34Ba, and the channels 35Aa, 35Ba. The main body portions WLa and the wide portions WLb are alternately arranged in the Y direction.

[0087] A part of the wide portion WLb is provided between a plurality of memory cells MC adjacent in the Y direction in the first side structure SB1, and is located between a plurality of block insulating films 32Aa adjacent in the Y direction, between a plurality of memory films 33Aa adjacent in the Y direction, between a plurality of tunnel insulating films 34Aa adjacent in the Y direction, and between a plurality of channels 35Aa adjacent in the Y direction. The wide portion WLb located between the first and second portions of the word line WL described above is an example of a "third portion".

[0088] Similarly, another part of the wide portion WLb is provided between a plurality of memory cells MC adjacent in the Y direction in the second side structure SB2, and is located between a plurality of block insulating films 32Ba adjacent in the Y direction, between a plurality of memory films 33Ba adjacent in the Y direction, between a plurality of tunnel insulating films 34Ba adjacent in the Y direction, and between a plurality of channels 35Ba adjacent in the Y direction.

[0089] Next, a method for manufacturing the semiconductor memory device 1C of the fourth embodiment will be described. In the method for manufacturing the semiconductor memory device 1C, the steps shown in Fig. 5C and Fig. 5D of the first embodiment (i.e., the steps in which the recesses 105A and 105B are formed after processing the trenches MT, and the block insulating films 32A and 32B, the memory films 33A and 33B, the tunnel insulating films 34A and 34B, and the channels 35A and 35B are formed in the recesses 105A and 105B) are not performed, and after the step shown in Fig. 5F of the first embodiment (i.e., the step in which the holes H are formed), an etching solution (e.g., hot phosphoric acid (H3PO4)) is supplied to each hole H, and both ends of the insulating layer 104 in the X direction are partially removed by etching. As a result, the side surface of the insulating layer 104 in the -X direction is recessed in the +X direction with respect to the side surface of the insulating layer 40 in the -X direction, and a plurality of first recesses separated in the Y direction are formed. Similarly, the side surface of the insulating layer 104 in the +X direction is recessed in the -X direction with respect to the side surface of the insulating layer 40 in the +X direction, and forms a plurality of second recesses separated in the Y direction.

[0090] Next, materials that are the source of the block insulating film, memory film, tunnel insulating film, and channel are supplied to the inner surface of the hole H. Then, unnecessary parts are removed by etching. In this embodiment, after the insides of the first and second recesses are blocked with the channel material, a choline-based wet solution is used to etch back only the channel material, or the channel material, the tunnel insulating film material, and even the memory film material, thereby forming the channel 35 and the like only inside the first and second recesses. As a result, the block insulating film 32Aa, the memory film 33Aa, the tunnel insulating film 34Aa, and the channel 35Aa are formed on the inner surface of the first recess, and the block insulating film 32Ba, the memory film 33Ba, the tunnel insulating film 34Ba, and the channel 35Ba are formed on the inner surface of the second recess. As a result, a plurality of first structural portions 21 are formed.

[0091] Here, the intervals between the multiple sources SL and multiple drains DL arranged in the Y direction (the intervals between the multiple holes H) are unequal. The distance L1 between the source lines SL and the drain lines DL corresponding to the same memory cell MC is shorter than the distance L2 between the source lines SL and the drain lines DL corresponding to the multiple memory cells MC. For example, according to the above-mentioned configuration, a structure in which the channels 35 are separated is formed according to the amount of etching (recess amount) of the insulating layer 104, as shown in FIG.

[0092] According to such a configuration, it is possible to improve the electrical characteristics, as in the first embodiment. Furthermore, according to the configuration of this embodiment, it is possible to suppress disturbance compared to the first embodiment. This makes it possible to further improve the electrical characteristics. Note that the configuration of this embodiment may be realized in combination with a configuration in which the source lines SL and drain lines DL included in the even-numbered columns T (T2, T4, ...) are shifted in the Y direction with respect to the source lines SL and drain lines DL included in the odd-numbered columns T (T1, T3, ...) as in the first embodiment.

[0093] (Modification) In the first to fourth embodiments, the memory cell MC having a charge trap film as the memory film 33 has been described. However, the configuration of the memory cell MC is not limited to the above examples. For example, the memory cell MC may be a ferroelectric gate field effect transistor (FeFET) having a ferroelectric film as the memory film 33. The ferroelectric film stores data values ​​according to the direction of polarization, for example. The ferroelectric film is formed of, for example, hafnium oxide (HfO), zirconia (ZrO), hafnium-zirconia oxide (HfZrO), or the like.

[0094] Although several embodiments and modifications have been described above, the embodiments and modifications are not limited to the above examples.

[0095] According to at least one of the embodiments described above, the semiconductor memory device includes an insulating layer located between the first word line and the second word line in the Z direction and between the first channel and the second channel in the Z direction. With this configuration, it is possible to improve electrical characteristics.

[0096] Although some embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These embodiments can be implemented in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included in the scope of the invention and its equivalents described in the claims, as well as in the scope and spirit of the invention. [Explanation of symbols]

[0097] 1, 1A...semiconductor memory device, 11...semiconductor substrate (substrate), 20...laminated body, 33...memory film, 35...channel, 40...insulating layer, 51a...main body portion, 51b...surface layer portion, 52...insulator, WL...word line, SL...source line, DL...drain line.

Claims

1. A substrate; a first word line extending in a first direction along a surface of the substrate; a second word line extending in the first direction and spaced apart from the first word line in a second direction that is a thickness direction of the substrate; a first channel extending in the first direction and aligned with the first word line in a third direction intersecting the first direction and the second direction; a first memory film located between the first word line and the first channel in the third direction and extending in the first direction; a second channel aligned with the second word line in the third direction and extending in the first direction; a second memory film located between the second word line and the second channel in the third direction and extending in the first direction; a first insulating layer located between the first word line and the second word line in the second direction and between the first channel and the second channel in the second direction; a first source line located on an opposite side of the first word line with respect to the first channel in the third direction and extending in the second direction; a first drain line that is spaced apart from the first source line in the first direction, that is located on an opposite side of the first channel from the first word line in the third direction, and that extends in the second direction; a third word line located on an opposite side of the first word line with respect to the first source line in the third direction and extending in the first direction; a fourth word line located on an opposite side of the first source line from the second word line in the third direction and extending in the first direction; a fifth channel located between the third word line and the first source line in the third direction and extending in the first direction; a fifth memory film located between the third word line and the fifth channel in the third direction and extending in the first direction; a sixth channel located between the fourth word line and the first source line in the third direction and extending in the first direction; a sixth memory film located between the fourth word line and the sixth channel in the third direction and extending in the first direction; a second insulating layer located between the third word line and the fourth word line in the second direction and between the fifth channel and the sixth channel in the second direction; A semiconductor memory device comprising:

2. the first source line is located on an opposite side of the second channel from the second word line in the third direction; the first drain line is located on an opposite side of the second channel from the second word line in the third direction; 2. The semiconductor memory device according to claim 1.

3. a first insulator located between the first source line and the first drain line in the first direction and extending in the third direction; the first source line and the first drain line are electrically connectable to each other via the first channel.

3. The semiconductor memory device according to claim 1.

4. a third channel extending in the first direction, aligned with the first word line from a side opposite to the first channel in the third direction; a third memory film located between the first word line and the third channel in the third direction and extending in the first direction; a fourth channel extending in the first direction and aligned with the second word line from a side opposite to the second channel in the third direction; a fourth memory film located between the second word line and the fourth channel in the third direction and extending in the first direction; a second source line located on an opposite side of the third channel from the first word line in the third direction and extending in the second direction; a second drain line that is spaced apart from the second source line in the first direction, is located on an opposite side of the third channel from the first word line in the third direction, and extends in the second direction; Further equipped with the first insulating layer is located between the third channel and the fourth channel in the second direction; 4. The semiconductor memory device according to claim 1, wherein the first and second memory cells are connected to each other.

5. each of the first source line and the first drain line includes a metal material; 5. The semiconductor memory device according to claim 1, wherein the first and second memory cells are connected to each other.

6. each of the first source line and the first drain line has a surface portion having at least a portion that is annular, and a main body portion located inside the surface portion; the surface layer portion includes a semiconductor material doped with an impurity, The body portion includes a metal material.

6. The semiconductor memory device according to claim 1, wherein the first and second memory cells are connected to each other.

7. The first memory film includes a charge trap film or a ferroelectric film.

7. The semiconductor memory device according to claim 1, wherein the first and second memory cells are connected to each other.

8. a PN junction or an insulating layer provided between each of the first source line and the first drain line and the substrate in the second direction; 8. The semiconductor memory device according to claim 1, wherein the first and second memory cells are connected to each other.

9. a seventh channel spaced apart from the first channel in the first direction, aligned with the first word line in the third direction, and extending in the first direction; a seventh memory film spaced apart from the first memory film in the first direction, positioned between the first word line and the seventh channel in the third direction, and extending in the first direction; a third source line located on an opposite side of the seventh channel from the first word line in the third direction and extending in the second direction; a third drain line that is spaced apart from the third source line in the first direction, is located on an opposite side of the seventh channel from the first word line in the third direction, and extends in the second direction; Further equipped with 9. The semiconductor memory device according to claim 1, wherein the first and second memory cells are connected to each other.

10. the first word line has a first portion aligned with the first channel in the third direction, a second portion aligned with the seventh channel in the third direction, and a third portion having a width in the third direction larger than that of the first portion and including a portion located between the first channel and the seventh channel in the first direction; 10. The semiconductor memory device according to claim 9.

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