Multi-Terminal Phase-Change Memory Device

Abstract

A phase change memory device is provided that includes a phase change memory material inside an electrically insulating wall, a first heater terminal within the electrically insulating wall, and two read terminals within the electrically insulating wall.

Description

[Technical field]

[0001] The present invention relates generally to phase change memory (PCM) devices, and more particularly to phase change memory (PCM) devices with multiple terminals. [Background technology]

[0002] Phase change memory can use the difference in resistivity between the amorphous and crystalline phases to establish a state of the memory cell where the crystalline and amorphous states of a phase change memory material can have detectably different electrical resistivity values. The amorphous state of a phase change memory material can have a high resistivity. Summary of the Invention

[0003] According to an embodiment of the present invention, a phase change memory device is provided, the phase change memory device including a phase change memory material inside an electrically insulating wall, a first heater terminal within the electrically insulating wall, and two read terminals within the electrically insulating wall.

[0004] According to another embodiment of the present invention, there is provided a phase change memory device comprising a phase change memory material inside an electrically insulating wall, the phase change memory device further comprising two heater terminals within the electrically insulating wall, the heater terminals being on opposite sides of the phase change memory material, and two read terminals within the electrically insulating wall, the read terminals being on opposite sides of the two heater terminals.

[0005] According to yet another embodiment of the present invention, there is provided a method of forming a phase change memory device. The method includes forming a base plate layer on a substrate. The method further includes forming a first read terminal and a first heater terminal in the base plate layer. The method further includes forming a patterned phase change material having a first phase on the base plate layer and forming an encapsulation layer on the patterned phase change material. The method further includes forming a second read terminal in the encapsulation layer, where the second read terminal is in electrical contact with the patterned phase change material.

[0006] These and other features and advantages will become apparent from the following detailed description of illustrative embodiments, which is to be read in connection with the accompanying drawings.

[0007] The following description provides details of a preferred embodiment with reference to the following figures: [Brief description of the drawings]

[0008] [Figure 1] 1 is a cross-sectional side view illustrating a phase change memory device having a pair of write terminals and a separate pair of read terminals according to an embodiment of the present invention. [Diagram 2] 1 is a cross-sectional side view showing a phase change memory device during a writing process according to an embodiment of the present invention. [Diagram 3] 1 is a cross-sectional side view showing a phase change memory device during a read process according to an embodiment of the present invention. [Figure 4] FIG. 2 is a cross-sectional side view illustrating a fully configured phase change memory device according to an embodiment of the present invention. [Diagram 5] 1 is a cross-sectional side view of a partially reconfigured phase change memory device according to an embodiment of the present invention. [Figure 6] 1 is a cross-sectional side view illustrating a partially configured phase change memory device according to an embodiment of the present invention. [Figure 7]FIG. 2 is a cross-sectional side view illustrating a fully configured phase change memory device according to an embodiment of the present invention. [Figure 8] 1A-1C are cross-sectional side views of a phase-change memory device having a pair of write terminals and a different arrangement of read terminals illustrating a write process according to another embodiment of the present invention. [Figure 9] 1A-1C are cross-sectional side views of a phase-change memory device having a pair of write terminals and a different arrangement of read terminals illustrating a read process according to another embodiment of the present invention. [Figure 10] 1A-1C are cross-sectional side views of a phase-change memory device having a three-terminal arrangement illustrating a write process according to another embodiment of the present invention. [Figure 11] 1A-1C are cross-sectional side views of a phase-change memory device having a three-terminal arrangement illustrating a read process according to another embodiment of the present invention. [Figure 12] FIG. 2 is a cross-sectional side view showing a base plate layer according to another embodiment of the present invention. [Figure 13] FIG. 2 is a cross-sectional side view showing a heater terminal and a read terminal formed in a base plate layer according to another embodiment of the present invention. [Figure 14] 4 is a cross-sectional side view illustrating a phase change material layer formed on a base plate layer according to another embodiment of the present invention. [Figure 15] 4 is a cross-sectional side view showing a phase change material layer patterned on a base plate layer according to another embodiment of the present invention. [Figure 16] 4 is a cross-sectional side view illustrating an encasement layer formed over a patterned phase change material layer and a base plate layer according to another embodiment of the present invention. [Figure 17] FIG. 2 is a cross-sectional side view showing a second heater terminal and a second read terminal formed in an encasement layer according to another embodiment of the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0009] Embodiments of the present invention provide multi-terminal phase change memory (PCM) devices that have less resistance drift than two-terminal phase change memory devices. The use of separate read and write terminals to control phase change memory phase transformations can provide a more linear conductance to analog computing devices. Multi-terminal devices can avoid amorphous resistivity drift that can result from using heater terminals for read cycles.

[0010] An embodiment of the present invention provides a method of fabricating a multi-terminal phase change memory (PCM) device that avoids amorphous resistivity drift by forming separate heaters to control the write process that changes the phase of the phase change memory material. By forming four electrical terminals that use two terminals to read data stored in the phase change memory device and two separate terminals that change the volume of the amorphous phase change memory material, enhanced control over phase drift in the PCM device can be achieved.

[0011] Embodiments of the present invention provide a method of reading and writing to a multi-terminal phase change memory (PCM) device that avoids amorphous resistivity drift. Using two terminals to read data stored in a phase change memory device and two separate terminals to write to the device by changing the relative volumes of the amorphous and crystalline phase change memory materials provides enhanced control over phase drift in PCM devices. The read current path can bypass the amorphous volume of the phase change memory using a separate read terminal.

[0012] Embodiments of the present invention provide multi-terminal phase change memory (PCM) devices capable of storing multiple data bits through control of the relative volumes of amorphous and crystalline phase change memory materials in the electrical read path of the device.

[0013] Exemplary applications / uses to which the present invention may be applied include, but are not limited to, non-volatile memory devices, storage class memories, embedded cache memories, weight storage for analog computing applications, and application specific integrated circuits (ASICs).

[0014] Aspects of the invention are described in terms of given example architectures; however, it should be understood that other architectures, structures, substrate materials, and process features and steps can be varied within the scope of aspects of the invention.

[0015] Referring now to the drawings, where like numerals represent the same or similar elements, FIG. 1 shows a cross-sectional side view of a phase change memory device having a pair of write terminals and a separate pair of read terminals in accordance with an embodiment of the present invention.

[0016] In one or more embodiments, phase change memory device 100 can have a phase change material in a first phase 110 and a phase change material in a second phase 115, where the first phase and the second phase have different resistivities. An electrically insulating wall 120 can surround the phase change material to contain electrical current flow to the phase change material.

[0017] In one or more embodiments, the phase change memory material is Ge 2 Sb 2 Te 5 (GST), where the GST can have a crystalline phase and an amorphous phase, where the crystalline phase has a lower resistivity than the amorphous phase. The crystalline phase can be changed to the amorphous phase by heating the crystalline phase to a phase change temperature and rapidly reducing the temperature of the amorphous phase change material to quench the phase change material in the amorphous phase.

[0018] In various embodiments, the phase change memory device 100 can have two read terminals 130 formed in the electrically insulating wall 120, where each of the two read terminals 130 is electrically coupled to a volume of phase change material. In various embodiments, the phase change memory device 100 can have two heater terminals 140 formed in the electrically insulating wall 120, where each of the two heater terminals 140 is electrically coupled to a volume of phase change material. The two heater terminals 140 can be formed in opposing electrically insulating walls 120, where the two heater terminals 140 can be directly opposite each other through an intervening volume of phase change memory material. The two read terminals 130 can be located on opposite sides of the two or more heater terminals 140 such that a current flowing between the two read terminals 130 crosses between the two heater terminals 140. In various embodiments, the read terminals 130 can be located on opposite electrically insulating walls 120.

[0019] In various embodiments, the heater terminal 140 can have a width or diameter of less than 40 nanometers (nm), or in a range of about 5 nm to about 40 nm, or about 10 nm to about 30, or about 10 nm to about 20 nm, although other widths or diameters are contemplated.

[0020] In various embodiments, the read terminal 130 can have a width or diameter greater than 40 nanometers (nm), or in a range of about 40 nm to about 100 nm, or about 50 nm to about 90, or about 70 nm to about 80 nm, although other widths or diameters are contemplated. The read terminal 130 can have a larger width or diameter to reduce resistance during a read operation, while the heater terminal 140 can have a smaller width or diameter to concentrate heating to a smaller area of ​​the PCM.

[0021] In various embodiments, the heater terminal 140 may be composed of metal compounds including, but not limited to, metal nitrides, such as titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), and combinations thereof; metal silicides, such as titanium silicide (TiSi), cobalt silicide (CoSi), nickel silicide (NiSi), and combinations thereof; metal carbides, such as titanium carbide (TiC), tantalum carbide (TaC); high-resistivity metals, such as tungsten (W), cobalt (Co), platinum (Pt), palladium (Pd), or tantalum (Ta), and combinations thereof.

[0022] In one or more embodiments, the volume of the phase change material inside the electrically insulating wall 120 can be in a first phase 110 and a second phase 115. The second phase 115 can be an amorphous phase having a higher resistivity than a crystalline phase. The second phase 115 can be hemispherical in shape and overlap the edges of the heater terminals 140, where the diameter and shape of the second phase 115 region of the phase change material can be determined by heat transport from the heater terminals 140 to the phase change material. In various embodiments, the second phase 115 region of the phase change material can be hemispherical. By controlling the amount of amorphous volume, a continuum of resistance states can be programmed. In various embodiments, the dimensions of the volume of phase change material inside the electrically insulating wall 120 range from about 50 nm (length) x 50 nm (width) x 50 nm (height) to about 250 nm (length) x 250 nm (width) x 100 nm (height), (0.000123 um 3 ~about 0.00625um 3 ), or about 100nm (length) x 100nm (width) x 50nm (height) to about 150nm (length) x 150nm (width) x 100nm (height), (0.0005um 3 ~ approx. 0.00225um 3 ), although other lengths, widths, heights, and volumes are contemplated.

[0023] FIG. 2 is a cross-sectional side view showing a phase change memory device during a writing process according to an embodiment of the present invention.

[0024] In one or more embodiments, information can be written to the phase change memory device 100 by passing a current from a first heater terminal 140 in the electrically insulating wall 120, through a region of phase change material, to a second heater terminal 140 in the electrically insulating wall 120 away from the first heater terminal 140. The passage of a current through each of the heater terminals 140 can increase the temperature of the heater terminals 140 by resistive heating, while the high electrical conductivity of the first phase 110 of the phase change material can conduct a current without sufficient heating to cause a phase change. The current through the heater terminal 140 and the first phase 110 (e.g., crystalline phase) of the phase change material is a current pulse, I, in the range of about 50 microamperes (uA) to about 900 uA, or about 50 microamperes (uA) to about 900 uA, or about 70 uA to about 900 uA, or about 70 uA to about 800 uA, for about 40 nanoseconds (ns) to about 200 ns, or about 70 ns to about 150 ns. prog , where the current pulse is sufficient to cause resistive heating of the heater terminals 140, causing the first phase 110 (e.g., a crystalline phase) of the phase change material to melt and become amorphous.

[0025] In various embodiments, the heater terminals 140 can cause an increase in temperature of the first phase 110 (e.g., crystalline phase) surrounding the phase change material to a temperature in the range of about 600° C. to about 900° C., or about 650° C. to about 750° C., where the change in temperature is sufficient to cause a change in the phase change material from the first phase 110 (e.g., crystalline phase) to a second phase 115 (e.g., amorphous phase) in an adjacent region of the phase change material. In various embodiments, the region of phase change material converted to the second phase 115 (e.g., amorphous phase) can be a protrusion having a hemispherical shape adjacent each of the heater terminals 140.

[0026] In various embodiments, the crystalline phase of the phase change material can have a resistivity in the range of about 0.01 ohm-cm to about 6 ohm-cm, or in the range of about 0.1 ohm-cm to about 4 ohm-cm, or about 1 ohm-cm, although other resistivities are possible.

[0027] In various embodiments, the amorphous phase of the phase change material has a resistivity of about 1×10, although other resistivities are possible. 3 ohm-cm ~ approx. 1 x 10 6 ohm-cm range, or approximately 1×10 6 It may have a resistivity of greater than ohm-cm.

[0028] FIG. 3 is a cross-sectional side view showing a phase change memory device during a read process according to an embodiment of the present invention.

[0029] In one or more embodiments, the state of the phase change memory device 100 can be determined by measuring the electrical resistance between two read terminals 130 along an electrical path through the first phase 110 of the phase change material, where at least a portion of the electrical path is between regions of the second phase 115 of the phase change material. The read current can bypass the second phase 115 regions of the phase change material.

[0030] The second phase 115 region of the phase change material can be hemispherical with a radius ranging from about 40 nanometers (nm) to about 70 nm, or from about 50 nm to about 60 nm, where heating of the PCM is symmetric about the heater terminal 140. In various embodiments, the normalized conductance of the PCM device can be related to 1-2R / H, where R is the radius of the hemispherical second phase 115 region and H is the wall height of the phase change material volume.

[0031] In various embodiments, the phase change memory device can have more than one state, for example, two, three, four, or five states that can be determined. The ratio of the cross-sectional area of ​​the second phase 115 of the phase change material to the first phase 110 of the phase change material can determine the state of the phase change memory device 100. Because the state of the phase change material through the cross-sectional area can be non-uniform, the current density through the high conductance phase material and the low conductance phase material can be non-uniform.

[0032] In various embodiments, the state of a phase change memory device can be determined by measuring the resistance of the device via a read terminal.

[0033] FIG. 4 is a cross-sectional side view illustrating a fully configured phase change memory device according to an embodiment of the present invention.

[0034] In one or more embodiments, the phase change memory device 100 can be fully set by crystallizing the entire volume of the phase change material to the first phase 110 (e.g., the crystalline phase can be fully set by fully heating the phase change memory device 100 with a high current and a slow ramp down of the current to allow the phase change memory material to slowly cool and recrystallize to the crystalline state). Once fully set, the distance D1 between the heater terminals 140 occupied by the first phase 110 of the phase change material can be equal to the total height H of the phase change memory device 100. Thus, the resistance experienced by the read current is the resistance of the first phase 110 of the phase change material (e.g., the crystalline phase resistance).

[0035] In various embodiments, phase change memory device 100 can have a height ranging from about 40 nm to about 100 nm, although other heights are contemplated. In various embodiments, phase change memory device 100 can have a width ranging from about 40 nm to about 300 nm, although other widths are contemplated.

[0036] FIG. 5 is a cross-sectional side view illustrating a partially configured phase change memory device according to an embodiment of the present invention.

[0037] In one or more embodiments, the phase change memory device 100 can be partially configured by amorphizing a portion of the first phase 110 of the phase change material between the heater terminals 140 using a current pulse and quenching the first phase 110 to form a region of the second phase 115 adjacent the heater terminals 140. The size and shape of the second phase 115 region can be determined by the amount of current used to amorphize the first phase 110 of the phase change material and the duration of the current pulse. The distance D2 occupied by the first phase 110 of the phase change material can be 1-2R / H, which is less than the overall height H of the phase change memory device 100 by two times the radius of the second phase 115 region. Thus, the resistance experienced by the read current is the resistance of the first phase 110 of the phase change material (e.g., the crystalline phase resistance) over the cross-sectional distance D2.

[0038] FIG. 6 is a cross-sectional side view illustrating a partially configured phase change memory device according to an embodiment of the present invention.

[0039] In one or more embodiments, the phase change memory device 100 can be further partially configured by amorphizing a larger portion of the first phase 110 of the phase change material between the heater terminals 140 using a current pulse and quenching the first phase 110 to form a region of the second phase 115 adjacent the heater terminals 140. The size and shape of the second phase 115 region can be determined by the amount of current used to amorphize the first phase 110 of the phase change material and the duration of the current pulse. The distance D3 occupied by the first phase 110 of the phase change material can be less than the cross-sectional distance D2 of the phase change memory device 100 by the increased radius of the second phase 115 region, 1-2R / H. Thus, the resistance experienced by the read current is the resistance of the first phase 110 of the phase change material (e.g., the crystalline phase resistance) relative to the cross-sectional distance D3.

[0040] FIG. 7 is a cross-sectional side view illustrating a fully reconfigured phase change memory device according to an embodiment of the present invention.

[0041] In one or more embodiments, the phase change memory device 100 can be fully reconfigured by amorphizing a larger portion of the first phase 110 of the phase change material between the heater terminals 140 using a current pulse and quenching the first phase 110 to form a region of the second phase 115 adjacent the heater terminals 140. The size and shape of the second phase 115 region can be determined by the amount of current used to amorphize the first phase 110 of the phase change material and the duration of the current pulse. The distance D4 occupied by the first phase 110 of the phase change material can be less than the cross-sectional distance D3 of the phase change memory device 100 by the increased radius of the second phase 115 region, 1-2R / H. Thus, the resistance experienced by the read current is the resistance of the first phase 110 of the phase change material (e.g., the crystalline phase resistance) relative to the cross-sectional distance D4. In various embodiments, the second phase 115 regions do not extend the entire distance between the heater terminals 140, and the entire cross section of the phase change memory device 100 is not amorphized. By providing an electrical path through the crystalline phase of the PCM, resistance drift can be reduced or avoided.

[0042] Each of the different distances, D1, D2, D3, and D4, can identify a different state of the phase change memory device 100 based on the resistance between the read terminals 130, thereby storing a different data value.

[0043] FIG. 8 is a cross-sectional side view of a phase change memory device having a pair of write terminals and a different arrangement of read terminals illustrating a write process according to another embodiment of the present invention.

[0044] In another embodiment, the two read terminals 130 can both be positioned along the same electrically insulating wall 120 and separated by the two heater terminals 140 and any second phase 115 regions. The two read terminals 130 can be separated by a distance ranging from about 80 nm to about 300 nm, depending on the width of the device, where the distance is sufficient to allow for the formation of a second phase 115 region having a predetermined maximum radius. In various embodiments, the two read terminals 130 can be positioned within the same sidewall of the electrically insulating wall 120.

[0045] In various embodiments, the phase change memory device 100 can be written to using a current pulse between opposing heater terminals 140 .

[0046] FIG. 9 is a cross-sectional side view of a phase-change memory device having a pair of write terminals and a different arrangement of read terminals illustrating a read process according to another embodiment of the present invention.

[0047] In one or more embodiments, the state of the phase change memory device 100 can be determined by passing a read current between two read terminals 130 .

[0048] FIG. 10 is a cross-sectional side view of a phase change memory device having a three-terminal arrangement illustrating a write process according to another embodiment of the present invention.

[0049] In one or more embodiments, the phase change memory device 100 may have a single heater terminal 140 and two read terminals 130, where the read terminal 130 opposite the heater terminal 140 may be used to generate a current pulse for writing data to the phase change material. The second phase 115 region may be formed adjacent to the single heater terminal 140 and protruding toward one of the two read terminals 130, where the second phase 115 region may have a sloped dome shape with a height different from a radius. The distance D5 occupied by the first phase 110 of the phase change material may be the distance between the second phase 115 region and the opposite electrically insulating wall 120.

[0050] FIG. 11 is a cross-sectional side view of a phase change memory device having a three-terminal arrangement illustrating a read process according to another embodiment of the present invention.

[0051] In one or more embodiments, the state of the phase change memory device 100 can be determined by passing a read current between two read terminals 130 .

[0052] FIG. 12 is a cross-sectional side view showing a base plate layer according to another embodiment of the present invention.

[0053] In one or more embodiments, a base plate layer 122 can be formed on the substrate 101, where the base plate layer 122 can be formed by blanket deposition, such as chemical vapor deposition (CVD), plasma enhanced CVD (PECVD), physical vapor deposition (PVD), conformal deposition, such as atomic layer deposition (ALD), plasma enhanced ALD (PEALD), or combinations thereof. The substrate 101 can include a semiconductor material, such as silicon (Si) or silicon germanium (SiGe), and may have other devices formed thereon.

[0054] In various embodiments, the base plate layer 122 can be an insulating dielectric material, including, but not limited to, silicon oxide (SiO), silicon nitride (SiN), silicon oxynitride (SiON), silicon boron carbonitride (SiBCN), and combinations thereof.

[0055] In various embodiments, the base plate layer 122 can have a thickness ranging from about 10 nm to about 60 nm, or from about 20 nm to about 40 nm, although other thicknesses are contemplated.

[0056] FIG. 13 is a cross-sectional side view showing heater terminals and read terminals formed in a base plate layer according to another embodiment of the present invention.

[0057] In one or more embodiments, openings can be formed in the base plate layer 122 using lithography processes and etching (e.g., RIE). The openings can be configured and dimensioned to form the read terminals 130 and the heater terminals 140.

[0058] In one or more embodiments, a conductive material for the read terminal 130 can be deposited in an opening configured for the read terminal. A conductive material suitable for the heater terminal 140 can be deposited in an opening configured for the heater terminal.

[0059] FIG. 14 is a cross-sectional side view illustrating a phase change material layer formed on a base plate layer according to another embodiment of the present invention.

[0060] In one or more embodiments, a phase change material layer 111 can be formed on the base plate layer 122, where the phase change material layer 111 can be formed by blanket deposition. The phase change material layer 111 can cover and be in electrical and thermal contact with the heater terminal 140 and in electrical contact with the read terminal 130.

[0061] In various embodiments, phase change material layer 111 can have a thickness ranging from about 40 nm to about 100 nm, or from about 50 nm to about 100 nm, although other thicknesses are contemplated.

[0062] FIG. 15 is a cross-sectional side view showing a phase change material layer patterned on a base plate layer according to another embodiment of the present invention.

[0063] In one or more embodiments, phase change material layer 111 can be patterned using lithography techniques and etching to remove portions of phase change material layer 111 and expose sections of base plate layer 122.

[0064] In various embodiments, phase change material layer 111 can have a width ranging from about 40 nm to about 300 nm, or from about 50 nm to about 250 nm, although other widths are contemplated.

[0065] FIG. 16 is a cross-sectional side view illustrating an encasement layer formed over a patterned phase change material layer and a base plate layer according to another embodiment of the present invention.

[0066] In one or more embodiments, an encasement layer 124 can be formed over the patterned phase change material having the first phase 110 and the base plate layer 122. The encasement layer 124 can be formed by conformal deposition, blanket deposition, or a combination thereof. The encasement layer 124 can form an electrically insulating wall 120 that can surround the patterned phase change material layer 111 and cover exposed sections of the base plate layer 122 and surround the patterned phase change material.

[0067] In various embodiments, the encasement layer 124 can be an insulating dielectric material, including, but not limited to, silicon oxide (SiO), silicon nitride (SiN), silicon oxynitride (SiON), silicon boron carbonitride (SiBCN), and combinations thereof.

[0068] FIG. 17 is a cross-sectional side view showing a second heater terminal and a second read terminal formed in an encasement layer according to another embodiment of the present invention.

[0069] In one or more embodiments, the second heater terminal 140 and the second read terminal 130 can be formed in the encasement layer 124. The second heater terminal 140 and the second read terminal 130 can be formed by forming openings in the encasement layer 124 at predetermined locations using lithography and etching techniques. A conductive material for the read terminal 130 can be deposited in the openings configured for the read terminals. A conductive material suitable for the heater terminal 140 can be deposited in the openings configured for the heater terminals.

[0070] The present embodiment may also include a design for an integrated circuit chip, which may be created in a graphical computer programming language and stored on a computer storage medium (e.g., disk, tape, physical hard drive, or virtual hard drive in a storage access network, etc.). If the designer does not fabricate the chip, or the photolithography masks used in fabricating the chip, the designer may transmit the resulting design, directly or indirectly, to such an entity by physical means (e.g., by providing a copy of the storage medium storing the design) or electronically (e.g., via the Internet). The stored design is then converted to a suitable format (e.g., GDSII) for fabrication of a photolithography mask, which typically includes multiple copies of the chip design in question to be formed on a wafer. The photolithography mask is utilized to define areas of the wafer (or layers thereon), which are to be etched or otherwise processed.

[0071] The methods described herein can be used in the fabrication of integrated circuit chips. The resulting integrated circuit chips can be distributed by the fabricator in raw wafer form (i.e., as a single wafer having multiple unpackaged chips), as bare die, or in packaged form. In the latter case, the chips are mounted in a single-chip package (such as a plastic carrier with leads attached to a motherboard or other top carrier) or in a multi-chip package (such as a ceramic carrier with either surface interconnects or buried interconnects or both). In either case, the chips are then integrated with other chips, discrete circuit elements, or other signal processing devices, or a combination thereof, as part of either (a) an intermediate product such as a motherboard, or (b) a final product. The final product can be any product that includes the integrated circuit chip, from toys and other low-end applications to advanced computer products with displays, keyboards or other input devices, and a central processor.

[0072] It should also be understood that compounds of matter are described in terms of the elements listed, e.g., SiGe. These compounds may contain different ratios of elements within the compound, e.g., SiGe is Si x Ge 1-x where x is 1 or less, etc. Additionally, other elements can be included in the compounds and still function according to the present principles. Compounds with additional elements are referred to herein as alloys.

[0073] References herein to "one embodiment" or "an embodiment," as well as other variations thereof, mean that the particular features, structures, characteristics, etc. described in connection with that embodiment are included in at least one embodiment. Thus, appearances of the phrases "in one embodiment" or "in an embodiment," as well as any other variations appearing in various places throughout this specification, do not necessarily all refer to the same embodiment.

[0074] The use of any of the following terms " / ", "and / or" and "at least one" is intended to encompass, for example, in the case of "A / B", "A and / or B" and "at least one of A and B", the selection of only the first listed option (A), or the selection of only the second listed option (B), or the selection of both options (A and B). As a further example, in the case of "A, B, and / or C" and "at least one of A, B, and C", such language is intended to encompass the selection of only the first listed option (A), or the selection of only the second listed option (B), or the selection of only the third listed option (C), or the selection of only the first and second listed options (A and B), or the selection of only the first and third listed options (A and C), or the selection of only the second and third listed options (B and C), or the selection of all three options (A and B and C). This can be extended to any number of listed items, as would be apparent to one of ordinary skill in the art.

[0075] The terms used herein are for the purpose of describing particular embodiments only and are not intended to limit the exemplary embodiments. As used herein, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly dictates otherwise. It will be further understood that as used herein, the terms "comprises," "comprising," "includes," and / or "including" specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0076] Spatially relative terms such as "beneath," "below," "lower," "above," "upper," and the like, may be used herein for ease of description to describe the relationship of one element or feature to another element or feature as depicted in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, an element described as "below" or "below" the other element or feature will now be oriented "above" the other element or feature. Thus, the term "below" can encompass both an upward and downward orientation. The device can be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein can be interpreted accordingly. Additionally, it will be understood that when a layer is referred to as being "between" two layers, it may be the only layer between the two layers, or there may also be one or more intervening layers.

[0077] It will be understood that terms such as first, second, etc. may be used herein to describe various elements, but these elements should not be limited by these terms. These terms are used only to distinguish one element from another. Thus, a first element discussed below could also be named a second element without departing from the scope of the present concept.

[0078] Also, when an element, such as a layer, region, or substrate, is referred to as being "on" or "above" another element, it will be understood that it may be directly on the other element, or that intervening elements may be present. In contrast, when an element is referred to as being "directly on" or "directly above" another element, there are no intervening elements present. Also, when an element is referred to as being "connected" or "coupled" to another element, it will be understood that it is directly connected or coupled to the other element, or that intervening elements may be present. In contrast, when an element is referred to as being "directly connected" or "directly coupled" to another element, there are no intervening elements present.

[0079] While preferred embodiments of the device and methods of making the device have been described, which are intended to be illustrative and not limiting, it should be noted that modifications and variations may be made by those skilled in the art in light of the above teachings. It is therefore to be understood that changes may be made in the particular embodiments disclosed which are within the scope of the invention as outlined by the appended claims. Having described aspects of the invention above, it is what is claimed, and what protection by letters patent is desired, with the detail and particularity required by the patent laws.

Claims

1. 1. A phase change memory device comprising: a phase change memory material inside the electrically insulating wall; a first heater terminal in the electrically insulating wall on one opposing side of the phase change memory material; two read terminals in the electrically insulating wall, the two read terminals being disposed in the electrically insulating wall on the one and the other opposing sides of the phase change memory material, respectively; Equipped with one of the two read terminals in the electrically insulating wall on the other side of the phase change memory material that faces the other of the two read terminals is used as the other heater terminal corresponding to the first heater terminal; Phase change memory devices.

2. The phase change memory device of claim 1 , wherein at least a portion of the phase change memory material is in a crystalline phase.

3. The phase change memory device of claim 2 , wherein at least a portion of the phase change memory material is in an amorphous phase.

4. 4. The phase change memory device of claim 3, wherein the amorphous phase of the phase change memory material is a sloped dome shape adjacent the first heater terminal.

5. 4. The phase change memory device of claim 3, wherein the dimensions of the phase change memory material are in the range of 50 nm (length) x 50 nm (width) x 50 nm (height) to 250 nm (length) x 250 nm (width) x 100 nm (height).

6. 1. A method of forming a phase change memory device, comprising: forming a base plate layer on a substrate; forming a first read terminal and a first heater terminal in the base plate layer; forming a patterned phase change material having a first phase on the base plate layer; forming an encapsulation layer over the patterned phase change material; and forming only a second read terminal in the encapsulation layer, the second read terminal being used as the other heater terminal corresponding to the first heater terminal, the second read terminal being in electrical contact with the patterned phase change material; 16. A method for forming a phase change memory device comprising:

7. The phase change material is Ge. ２ Sb ２ Te ５ (GST).

8. The method of claim 7 , wherein at least a portion of the phase change material is in a crystalline phase.

9. The method of claim 8 , wherein the first heater terminal and the second read terminal are separated by a height of the phase change material in a range of 50 nm to 100 nm.

10. 10. The method of claim 9, wherein the first heater terminal is comprised of a material selected from the group consisting of titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), titanium silicide (TiSi), cobalt silicide (CoSi), nickel silicide (NiSi), titanium carbide (TiC), tantalum carbide (TaC), tungsten (W), cobalt (Co), platinum (Pt), palladium (Pd), or tantalum (Ta), and combinations thereof.

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