Packaging module and electronic device

Abstract

The present application provides a packaging module and an electronic device. The packaging module includes a substrate layer arranged in a stack and multiple chip layers stacked on the substrate layer. The substrate layer functions as a support structure supporting the multiple chip layers. The multiple chip layers include a top chip layer, which is the chip layer farthest from the substrate layer among the multiple chip layers. The top chip layer includes a first chip, whose connection surface faces the substrate layer and is conductively connected to chips on adjacent chip layers using first conductors. In the above technical solution, all chips are supported by a single substrate (substrate layer) to reduce the number of substrates used and further reduce the thickness of the packaging module. In addition, because the connection surface of the first chip faces the substrate layer, the first conductors connected to the first chip and other chips do not occupy additional space, thereby reducing the thickness of the packaging module and facilitating miniaturization of the packaging module.

Description

[Technical field]

[0001] The present application relates to the field of chip packaging technology, and in particular to packaging modules and electronic devices. [Background technology]

[0002] semiconductor device are widely used in electronic devices such as mobile phones and smart watches, and are used as the main electronic components of electronic devices. With the progress of thinning of electronic devices, the size of the packaging module has become the main factor limiting further thinning of electronic devices.

[0003] With the continuous development of the semiconductor industry, device The size of semiconductors is becoming smaller. device The density of electronic components inside the chip is becoming higher. In addition, to further reduce the space occupied, multiple semiconductor device are stacked and packaged to form a packaging module. However, for the system-level packaging module in an electronic device, the system-level packaging module needs to hold a relatively large number of chips, and a relatively large number of substrates are used when the chips are held, so the packaging module cannot further realize miniaturization, and the miniaturization requirements of existing electronic devices cannot be met. Summary of the Invention [Means for solving the problem]

[0004] The present application provides a packaging module and an electronic device to improve the size of the packaging module and facilitate the progress of miniaturization of the packaging module.

[0005] According to a first aspect, a packaging module is provided. The packaging module includes a substrate layer arranged in a stacked manner and a plurality of chip layers stacked on the substrate layer. The substrate layer functions as a support structure supporting the plurality of chip layers. In addition, the substrate layer is also provided with a circuit layer conductively connected to the chip layers, thereby realizing the function of the packaging module. The plurality of chip layers includes a top chip layer, which is the chip layer farthest from the substrate layer among the plurality of chip layers. The top chip layer includes a first chip, and a connection surface of the first chip faces the substrate layer, and the connection surface of the first chip is conductively connected to a chip of an adjacent chip layer by using a first conductor. In the above technical solution, all chips are supported by one substrate (substrate layer) to reduce the number of substrates used and further reduce the thickness of the packaging module. In addition, since the connection surface of the first chip faces the substrate layer, the first conductor connected to the first chip and another chip does not occupy additional space, thereby reducing the thickness of the packaging module and facilitating miniaturization of the packaging module.

[0006] In a particular possible implementation, a connection surface of a chip of the adjacent chip layer faces the substrate layer, and one end of the first conductor is connected to the connection surface of the first chip; First conductor The other end is connected to the connection surface of the chip on the adjacent chip layer, which makes it easier to arrange the first conductor.

[0007] In a particular possible implementation, the first conductor is located on the side of the first chip facing the substrate layer, which reduces the impact of the first conductor on the height of the packaging module.

[0008] In a particular possible implementation, the connection surface of the first chip is provided with a connection area exposed to the top surface of the chip of the adjacent chip layer, and one end of the first conductor is connected to the exposed connection area, thus facilitating placement of the first conductor.

[0009] In a particular possible implementation, the connection area of ​​the first chip is located in an edge area or a central area of ​​the connection surface of the first chip, thus facilitating the placement of the first conductor.

[0010] In one possible implementation, the conductors are bond wires to facilitate connections between chips on different layers.

[0011] In a particular possible implementation, the adjacent chip layer is closer to the substrate layer than the top chip layer, and the adjacent chip layer includes one or more chips. One or more connection surfaces of the one or more chips face the substrate layer or all face the substrate layer and are conductively connected to a circuit layer of the substrate layer. The connection surface of the first chip is connected to any of the one or more connection surfaces of the one or more chips by using one first conductor. Two chip layers are used to realize the functionality of the packaging module.

[0012] In a particular possible implementation, the adjacent chip layer includes multiple chips, the multiple chips include a second chip and a third chip. The connection surfaces of the second chip and the third chip both face the substrate layer, and the second chip and the third chip are separately conductively connected to the circuit layer of the substrate layer. The first chip is conductively connected to the second chip by using a first conductor, or the first chip is conductively connected to the second chip by using one first conductor, and the first chip is conductively connected to the third chip by using another first conductor. Two chip layers are used to realize the functionality of the packaging module.

[0013] In a particular possible implementation, the adjacent chip layer includes a plurality of chips, the plurality of chips including a fourth chip and a fifth chip. The connection surface of the fourth chip faces the substrate layer, and the connection surface of the first chip is conductively connected to the connection surface of the fourth chip by using a first conductor. The connection surface of the fifth chip faces away from the substrate layer. Facing the other side, the connection surface of the fifth chip is conductively connected to the circuit layer of the substrate layer by using a second conductor. Two chip layers are used to realize the function of the packaging module.

[0014] In a particular possible implementation, the substrate layer is provided with an avoidance groove for avoiding the first conductor. The thickness of the packaging module is further reduced.

[0015] In certain possible implementations, the multiple chip layers further include a bottom chip layer, the bottom chip layer being the chip layer closest to the substrate layer, and the adjacent chip layer being located between the bottom chip layer and the top chip layer.

[0016] The chips located in the adjacent chip layer include a sixth chip, the connection surface of the sixth chip faces the substrate layer. The chips located in the bottom chip layer include a seventh chip, the connection surface of the seventh chip faces the substrate layer and is conductively connected to the circuit layer of the substrate layer. The connection surface of the sixth chip is conductively connected to the connection surface of the first chip by using one first conductor and is conductively connected to the connection surface of the seventh chip by using another first conductor. Three chip layers are used to realize the functionality of the packaging module.

[0017] In a specific possible implementation, the packaging module further includes an embedded chip disposed on the substrate layer, and the embedded chip is conductively connected to the circuit layer of the substrate layer. The thickness of the packaging module is further reduced.

[0018] In certain possible implementations, the multiple chip layers further include a bottom chip layer, the bottom chip layer being the chip layer closest to the substrate layer, and the adjacent chip layer being located between the bottom chip layer and the top chip layer.

[0019] The chips located in the adjacent chip layer include an eighth chip, 8The connection surface of the chip of the eighth chip faces the substrate layer. The chips located in the bottom chip layer include a ninth chip, the connection surface of the ninth chip faces the substrate layer and is conductively connected to the circuit layer of the substrate layer. The connection surface of the first chip is conductively connected to the connection surface of the eighth chip by using a first conductor, and the connection surface of the ninth chip is conductively connected to the circuit layer of the substrate layer by using a third conductor. Three chip layers are used to realize the function of the packaging module.

[0020] In certain possible implementations, adjacent chip layers of the multiple chip layers are bonded together, which facilitates fixation between the chip layers.

[0021] In a particular possible implementation, the packaging module further includes a packaging layer for packaging the multiple chip layers, which improves the safety of the chips.

[0022] According to a second aspect, an electronic device is provided, the electronic device includes a housing and a packaging module according to any one of the above-mentioned implementations arranged in the housing. In the above-mentioned technical solution, all chips are supported by one substrate (substrate layer) to reduce the number of substrates used and further reduce the thickness of the packaging module. In addition, since the connection surface of the first chip faces the substrate layer, the first chip and the first conductor connected to another chip do not occupy additional space, thereby reducing the thickness of the packaging module and facilitating the miniaturization of the packaging module. [Brief description of the drawings]

[0023] [Figure 1] FIG. 1 is a schematic diagram of an application scenario of a packaging module in the prior art; [Diagram 2] FIG. 1 is a schematic diagram of a structure of a packaging module in the prior art; [Diagram 3] FIG. 2 is a schematic diagram of a structure of a packaging module according to an embodiment of the present application. [Figure 4a]4 is a manufacturing flow chart of a packaging module according to an embodiment of the present application. [Figure 4b] 4 is a manufacturing flow chart of a packaging module according to an embodiment of the present application. [Figure 4c] 4 is a manufacturing flow chart of a packaging module according to an embodiment of the present application. [Figure 4d] 4 is a manufacturing flow chart of a packaging module according to an embodiment of the present application. [Figure 4e] 4 is a manufacturing flow chart of a packaging module according to an embodiment of the present application. [Figure 4f] 4 is a manufacturing flow chart of a packaging module according to an embodiment of the present application. [Figure 4g] 4 is a manufacturing flow chart of a packaging module according to an embodiment of the present application. [Diagram 5] FIG. 2 is a schematic diagram of a structure of another packaging module according to an embodiment of the present application. [Figure 6] FIG. 2 is a schematic diagram of a structure of another packaging module according to an embodiment of the present application. [Figure 7] FIG. 2 is a schematic diagram of a structure of another packaging module according to an embodiment of the present application. [Figure 8] FIG. 2 is a schematic diagram of a structure of another packaging module according to an embodiment of the present application. [Figure 9] FIG. 2 is a schematic diagram of a structure of another packaging module according to an embodiment of the present application. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0024] The following further describes embodiments of the present application with reference to the accompanying drawings.

[0025] In order to facilitate understanding of the packaging module provided in the embodiments of the present application, an application scenario of the packaging module is first described.

[0026] The packaging module provided in the embodiment of the present application is applied to electronic devices such as mobile phones and smart watches. Ta Packaging Module Schematic diagram of the structure The electronic device includes a housing 100 and a main body disposed within the housing 100. board The packaging module 300 includes a main board Fixed above 200, main board 200 is conductively connected to

[0027] A conventional system-level packaging module is shown in FIG. Layer The semiconductor device includes a first substrate 1 and a second substrate 2, which are connected by using solder balls. The first substrate 1 holds a chip 6, which is connected to the first substrate 1 by using solder balls and is located between the first substrate 1 and the second substrate 2. The second substrate 2 holds stacked chips 3 and 4, and a packaging layer 5 that packages the chips 3 and 4. The chips 3 and 4 are arranged in a positive mount manner. Specifically, the connection surface of the chip 3 and the connection surface of the chip 4 are located on the top surface of the chip (the surface of the chip away from the second substrate 2). facing the directionThe connecting surface of the chip is located on the first substrate (the first substrate 1 and the second substrate 2). In this embodiment of the present application, the connecting surface of the chip refers to the surface on which the chip is provided with solder pads or windows used for conductive connection to another chip or circuit layer. When the chip 3 and the chip 4 are connected to the second substrate 2, the connecting surface of the chip 3 and the connecting surface of the chip 4 are separately connected to the second substrate 2 by using bonding wires 7. From FIG. 2, it can be seen that the packaging module in the prior art includes at least two substrates (the first substrate 1 and the second substrate 2), and the height of the bonding wires 7 needs to be ensured along the height direction of the packaging module. With the progress of miniaturization of electronic devices, the internal space of the electronic devices is also gradually reduced. As a result, the packaging module in the prior art is no longer applicable to miniaturized electronic devices, which is the main factor restricting further miniaturization of electronic devices. Therefore, an embodiment of the present application provides a packaging module for further miniaturizing the packaging module by improving the combination of chips in the packaging module. The following will describe in detail the packaging module provided in the embodiment of the present application with reference to certain accompanying drawings.

[0028] The packaging module provided in the embodiment of the present application is a system-level packaging module, which includes a CPU (Middle Central Processing Unit), SOC (S Stem-on-chip), DRAM (D Dynamic Random Access Memory), and NAND ( NAND Flash Memory ) may contain chips with different functions.

[0029] FIG. 3 illustrates a packaging module according to an embodiment of the present application. Schematic diagram of cross section3. The packaging module includes a substrate layer 10 and a plurality of chip layers, and the layer structure of the packaging module is named for ease of description. The plurality of chip layers of the packaging module include a top chip layer 30 and a bottom chip layer 20. The top chip layer 30 is the chip layer farthest from the substrate layer 10 among the plurality of chip layers, and the bottom chip layer 20 is the chip layer closest to the substrate layer 10 among the plurality of chip layers. In the structure shown in FIG. 3, the substrate layer 10, the bottom chip layer 20, and the top chip layer 30 are stacked in a vertical direction (the vertical direction may be referred to as the thickness direction of the packaging module, and the thickness direction of the packaging module is the same as the thickness direction of the substrate layer 10). The bottom chip layer 20 is an adjacent chip layer of the top chip layer 30. In addition, the bottom chip layer 20 is closer to the substrate layer 10 than the top chip layer 30.

[0030] The substrate layer 10 serves as a structure for holding the top chip layer 30 and the bottom chip layer 20. In addition, the substrate layer 10 is further used to realize conductive connections between external circuits and the chips of the top chip layer 30 and the bottom chip layer 20. For example, a circuit layer may be separately disposed on the surface of the substrate layer 10 and inside the substrate layer 10, and the circuit layer on the surface of the substrate layer 10 and the circuit layer inside the substrate layer 10 may be electrically connected by using vias.

[0031] In an optional solution, an embedded chip is disposed in the substrate layer 10, and the embedded chip is electrically connected to a circuit layer on the surface of the substrate layer 10 or embedded in the substrate layer 10 by using a via or a first conductor a. FIG. 3 shows two embedded chips, a first embedded chip 11 and a second embedded chip 12. The first embedded chip 11 and the second embedded chip 12 are conductively connected to the circuit layer of the substrate layer 10 by using a via. Although two embedded chips are shown in FIG. 3, it should be understood that the number of embedded chips is not particularly limited in the packaging module provided in this embodiment of the present application, and the number of embedded chips may be one, three, etc.

[0032] In an optional solution, the substrate layer 10 may be a printed circuit board or another type of circuit board.

[0033] The bottom chip layer 20 is a layer structure formed by chips arranged on the same layer. For example, the chips of the bottom chip layer 20 include one or more chips. The one or more chips are chips used to connect to the first chip 31 of the top chip layer. As shown in FIG. 3, for example, the bottom chip layer 20 includes a second chip 21 and a third chip 22. When the chips of the bottom chip layer 20 are arranged, one or more connection surfaces of the one or more chips face the substrate layer 10 or all face the substrate layer 10 and are conductively connected to the circuit layer of the substrate layer 10. For example, the connection surface of the second chip 21 faces the substrate layer 10 and is conductively connected to the circuit layer of the substrate layer 10 by using solder balls. The connection surface of the third chip 22 faces the substrate layer 10, and the connection surface of the third chip 22 is conductively connected to the circuit layer of the substrate layer 10. During assembly, the connection surface of the second chip 21 is conductively connected to the circuit layer of the substrate layer 10 by using solder balls, and the connection surface of the third chip 22 is conductively connected to the circuit layer of the substrate layer 10 by using solder balls. The second chip 21 and the third chip 22 may be electrically connected to an embedded chip (the first embedded chip or the second embedded chip) by using the circuit layer of the substrate layer 10.

[0034] It should be understood that the packaging module provided in this embodiment of the present application does not limit the number of chips in the bottom chip layer 20, and different numbers of chips may be arranged as required. For example, the number of chips in the bottom chip layer 20 can be one, two, or 3 One be.

[0035] The top chip layer 30 is a layer structure formed by chips arranged on the same layer. The top chip layer 30 includes a first chip 31. In FIG. 3, for example, the top chip layer 30 includes OneThe first chip 31 includes the second chip 21 and the third chip 22. Layer The connection surface of the first chip 31 faces the substrate layer 10, and the connection surface of the first chip 31 is conductively connected to the connection surface of the second chip 21 by using a first conductor a. Specifically, one end of the first conductor a is connected to the connection surface of the first chip 31, The first conductor a The other end is connected to the connection surface of a chip (second chip 21) in the adjacent chip layer. For example, the first conductor a may be a bonding wire or another type of conductive wire.

[0036] 3, when placed, the first conductor a is placed on the side of the first chip 31 facing the substrate layer 10, and the highest point of the first conductor a is located on the top surface of the first chip 31 (away from the substrate layer 10). facing the direction surface).

[0037] When the first chip 31 is connected to the second chip 21, the connection surface of the first chip 31 is separated from the connection surface of the second chip 21 by using an adhesive. facing the direction The upper surface and the third chip 22 are separated from the connecting surface. facing the direction The first chip 31 is bonded separately to the upper surface and the lower surface of the second chip 21. The connection surface of the first chip 31 is provided with a connection region 311 exposed to the second chip 21 and the third chip 22. One end of the first conductor a is connected to the connection region 311. As shown in FIG. 3, for example, the connection region 311 is located in an edge region of the connection surface of the first chip 31. This makes it easy to arrange the first conductor a.

[0038] The packaging module provided in this embodiment of the present application further includes a packaging layer 40. The packaging layer 40 includes the bottom chip layer 20, the top chip layer 30, the first conductors a between the bottom chip layer 20 and the top chip layer 30, and the solder balls used to connect the bottom chip layer 20 to the substrate layer 10. Wrap it up , to protect components such as chips within a packaging module.

[0039] To facilitate understanding of the packaging module provided in this embodiment of the present application, the following describes the fabrication steps of the packaging module in detail.

[0040] Step 1: The first chip 31 is attached to the holding plate 400 .

[0041] Referring to FIG. 4a, the carrier plate 400 may be made of a material such as metal, glass, or silicon. Use The holding plate 400 is covered with a layer of film adhesive material, which is used to fix the first chip 31. The film adhesive material may be a photosensitive material or a heat-sensitive material. After being irradiated by ultraviolet light or placed under a certain heating condition, the adhesive force of the material is greatly reduced, which facilitates the later interface separation operation. When the first chip 31 is fixed to the holding plate 400, the connection surface of the first chip 31 can be separated from the holding plate 400 and can be easily separated from the holding plate 400. Facing the other side The thickness of the first chip 31 may be in the range of 25 μm to 400 μm. For example, the thickness of the first chip 31 may be 25 μm, 50 μm, 80 μm, or 400μ m It's fine.

[0042] Step 2: Attach the third chip 22 and the second chip 21 to the first chip 31.

[0043] Referring to FIG. 4b, an adhesive material is provided at the bottom of the third chip 22 and the bottom of the second chip 21 to bond the third chip 22 and the second chip 21 onto the first chip 31. , solid The surface of the third chip 22 and the surface of the second chip 21 are each provided with a solder pad structure (not shown) that is connected to a circuit layer of the substrate layer. When the third chip 22 and the second chip 21 are fixed to the first chip 31, the solder pads (structures on the connection surface) of the third chip 22 and the solder pads of the second chip 21 are separated from the first chip 31. Facing the other sideSecond chip 21, third chip 22, and first chip 31 form a stacked chip.

[0044] The bonding material used for bonding between the third chip 22 and the second chip 21 and the first chip 31 may be cured at a specific temperature or in an ultraviolet environment. The thickness of the first chip 31 is the same as that of the second chip 21. Set to For example, the thickness range of each of the third chip 22 and the second chip 21 is 25 μm to 400 μm. For example, the thickness of the second chip 21 and the thickness of the third chip 22 are 25 μm, 50 μm, 80 μm, or 400μ m be.

[0045] Step 3: Connect the first chip 31 and the second chip 21 by using bonding wires.

[0046] Referring to FIG. 4c, a wire bonding process is used to make bond wire connections to the connection surfaces of the first chip 31 and the solder pads of the second chip 21. Gu and refers to the use of heat, pressure, and ultrasonic energy to firmly weld a metal lead wire to a board solder pad using a fine bonding wire. The bonding wire may be gold, copper, or alloy bonding wire, and the diameter of the bonding wire may be 18 μm to 30 μm. For example, the diameter of the bonding wire may be 18 μm, 25 μm, or 30μ m be.

[0047] Step 4: Remove the stacked chips from the holding plate 400 and place the stacked chips upside down.

[0048] 4d, the adhesive force of the film adhesive material on the holding plate 400 is greatly reduced by ultraviolet light or heating, and then the second chip 21 and the upper surface of the second chip 21 are sucked by a vacuum rubber suction nozzle. The vacuum rubber suction nozzle is lifted by a lifting device to separate the first chip 31 from the holding plate 400, and the stacked chip structure is temporarily held. stand 500 is placed upside down.

[0049] Step 5: A substrate layer 10 is fabricated, and metal bumps 13 are implanted onto the surface of the substrate layer 10 .

[0050] Referring to FIG. 4e, the substrate layer 10 is To Forming Technology or Panel Level Package J-Tech The substrate layer 10 is embedded with a first embedded chip 11 and a second embedded chip 12, which are implemented with a rewiring structure on the surface of the substrate layer 10 by using a circuit layer and vias to fan out the connection ends of the first embedded chip 11 and the second embedded chip 12, respectively. The circuit layer on the surface of the substrate layer 10 includes a solder pad structure, and metal bumps 13 are provided on the main board or driven into a solder pad structure for connection to another circuit structure. The circuit layer on the surface of the substrate layer 10 may be made of a copper material, the material of the solder pad structure may be copper, and the material of the bump on the solder pad may be copper or tin.

[0051] When the metal bumps 13 are fabricated on the substrate layer 10, the metal bumps 13 are driven into the solder pad structures by printing or electroplating. The height of the metal bumps 13 may be 20 μm to 70 μm. For example, the height of the metal bumps 13 may be 20 μm, 40 μm, or 70μ m be.

[0052] Step 6: Metal bump UseThe laminated chip structure is bonded to the substrate layer 10 by this.

[0053] 4f, the stacked chip structure and the substrate layer 10 are placed together so that the metal bumps are aligned with the pads corresponding to the third chip 22 and the pads corresponding to the second chip 21. The metal bumps are metallurgically bonded to the pads on the third chip 22 and the pads on the second chip 21 by a reflow soldering process or a heat press-in process. In the above-mentioned fabrication process, the reflow soldering process and the heat press-in process increase the temperature to melt the solder and melt-bond the solder with the material of the metal bump.

[0054] Step 7: The entire packaging structure is plastically packaged and the solder balls are hammered into the substrate layer 10.

[0055] Referring to FIG. 4g, the entire chip structure may be packaged by using a molding tool and a thermosetting material, which is cured by heating to form a packaging layer 40. Finally, the solder balls are attached to the substrate layer 10. Bottom surface and the solder balls may be driven in by solder printing and reflow soldering.

[0056] From the above description, in the packaging module provided in this embodiment of the present application, the first chip 31 is inverted (the connection surface of the first chip 31 faces the substrate layer 10), so that the first conductor a for connecting the first chip 31 to the second chip 21 is Height value of is the thickness of the second chip 21 In range To can be It can be seen that no additional height is required. Thus, the packaging module can be thinner. can be .

[0057] In order to facilitate understanding of the thinning effect of the packaging module provided in this embodiment of the present application, the packaging module provided in this embodiment of the present application is compared with a packaging module in the prior art shown in FIG.

[0058] In this embodiment of the present application, the chips shown in FIG. 2 are arranged in a positive mount manner, and the connection surfaces of the chips (chip 3 and chip 4) are separated from the substrate layer. Facing the other side Therefore, when the chip is connected to the second substrate, the bonding wire needs to be drawn out from the top of the chip 4. When the bonding wire is routed, the required bending radian needs to be ensured, and the thickness from the packaging layer 5 to the top chip (chip 4) needs to reach at least 100 μm to cover the bonding wire. However, in the packaging module provided in this embodiment of the present application, since the connection surface of the first chip faces the substrate layer, the bonding wire is arranged toward the substrate layer. Although the bending radian needs to be ensured when the bonding wire is connected to the chip of the bottom chip layer, the space occupied by the bending of the bonding wire overlaps with the space of the solder ball used to weld the bottom chip layer and the substrate layer, so no additional space is required. From FIG. 3 of the present application, it can be seen that the highest point of the bonding wire along the chip stacking direction (the point connected to the connection surface of the first chip) is lower than the top surface of the first chip, effectively reducing the restriction on the thickness from the packaging layer to the top surface of the first chip. Therefore, the packaging module is thinner and Can be , the size of the packaging module is minimized.

[0059] In addition, since the system-level packaging module in the prior art includes two substrates (the first substrate 1 and the second substrate 2), the packaging thickness of the packaging module increases. however,In this embodiment of the present application, some chips (first embedded chip 11 and second embedded chip 12) are disposed in an embedded manner, and other chips (first chip 31, second chip 21, and third chip 22) are directly bonded to the substrate layer 10. This saves the thickness of one substrate component compared to the system-level packaging module shown in FIG. 2, and reduces the overall thickness of the packaging module. In addition, by using the direct bonding method between the chip and the substrate layer, more I / O can be provided compared to the conventional system-level packaging module. (Enter Input / output (I / O) connections are realized to increase the connection bandwidth or reduce power consumption between chips in a system-level packaging module Can be do.

[0060] From the above description, compared with the packaging module in the prior art, the packaging module disclosed in this embodiment of the present application has a significantly reduced packaging occupation height. Can be For example, in the prior art, Sachi Top of The occupied height of the packaging layer in the stacked packaging module is about 1.2 mm, and the processor of the smart watch of The occupied height of the packaging layer in the stacked packaging module is about 0.8 mm. However, the thickness of the packaging layer in the packaging module provided in this embodiment of the present application is only about 0.5 mm. In addition, compared with the solution in the prior art in which the packaging module uses two substrates, in the packaging module provided in this embodiment of the present application, the number of I / O interconnections of the chip inside the packaging module is increased when the chip is directly connected to the substrate layer. can be For example, in the prior art, the I / O between the CPU and the upper layer DRAM packaging in the stacked packaging module connection The number of I / O connections between the embedded chips and the upper chips of the substrate layer provided in this embodiment of the present application is about 200, and the number of I / O connections between the embedded chips and the upper chips of the substrate layer provided in this embodiment of the present application is more than 500. connectionThis significantly increases the number of connections, further increasing the connection bandwidth or reducing power consumption.

[0061] Figure 5 shows a modified structure based on the packaging module shown in Figure 3. The second chip 21 and the third chip 22 are located on the bottom chip layer 20, and the first chip 31 is located on the top chip layer 30. For the connection manner between the second chip 21 and the third chip 22 and the substrate layer 10, please refer to the related description of Figure 3. The details will not be described again here.

[0062] The substrate layer 10 may be provided with an avoidance groove 14 for avoiding the bonding wire, and the avoidance groove 14 is located on the surface of the substrate layer 10 facing the second chip. The arrangement position, width, and depth of the avoidance groove 14 may be matched based on the position and size of the bending structure of the bonding wire a connected to the first chip 31 and the second chip 21. This is not particularly limited in this embodiment of the present application.

[0063] In addition, the number of the avoidance grooves 14 is also not particularly limited in this embodiment of the present application, and the number may match the number of the bonding wires a, or the number of the avoidance grooves 14 is less than the number of the bonding wires a. During configuration, one avoidance groove 14 may accommodate the bending structure of one bonding wire a, or one avoidance groove 14 accommodates the bending structures of multiple bonding wires a. During a specific arrangement, the position of the avoidance groove 14 and the number of the avoidance grooves 14 may be flexibly configured based on the metal wiring of the circuit layer on the surface of the substrate layer 10, so as to prevent the arranged avoidance groove 14 from affecting the metal wiring of the circuit layer.

[0064] From FIG. 5, when the avoidance groove 14 is arranged, the size of the packaging module is further reduced. Can be Therefore, the solder balls connecting the second chip 21 and the third chip 22 to the substrate layer 10 are of a smaller size to further reduce the height of the packaging module. can haveIn addition, since the avoidance groove 14 is arranged, the bonding wire has more space for bending, which ensures the reliability of the bonding wire after bending.

[0065] Figure 6 shows another modified structure based on the packaging module shown in Figure 3. The second chip 21 and the third chip 22 are located on the bottom chip layer 20, and the first chip 31 is located on the top chip layer 30. For the connection manner between the second chip 21 and the third chip 22 and the substrate layer 10, please refer to the related description of Figure 3. The details will not be described again here.

[0066] In the packaging structure shown in FIG. 6, the second chip 21 and the third chip 22 of the packaging module are separately connected to the central region of the first chip 31. As can be seen from FIG. 6, the connection region 311 of the first chip 31 is located in the central region of the connection surface of the first chip 31, the second chip 21 and the third chip 22 are spaced apart, and a space for exposing the connection region 311 is spaced apart between the second chip 21 and the third chip 22. When the first chip 31 is connected to the second chip 21 and the third chip 22, the first chip 31 is conductively connected to the second chip 21 by using one first conductor, and the first chip 31 is conductively connected to the third chip 22 by using another first conductor.

[0067] The first conductor uses a bonding wire. For example, the bonding wire b and the bonding wire c are located in the gap between the second chip 21 and the third chip 22. When the packaging structure shown in FIG. 6 is used, a space for accommodating the bonding wire b and the bonding wire c is formed between the second chip 21 and the third chip 22 by utilizing the difference between the size of the first chip 31, the size of the second chip 21, and the size of the third chip 22. Therefore, the bonding wire b and the bonding wire c do not affect the size of the packaging module in the horizontal direction (direction B shown in FIG. 6). This further reduces the size of the packaging module and facilitates miniaturization of the packaging module.

[0068] In addition, the packaging module shown in Fig. 6 may also use the avoidance groove shown in Fig. 5. Specifically, in order to further reduce the height of the packaging module, a bonding wire b and bonding wire c An avoidance groove may also be provided that matches the above.

[0069] Fig. 7 shows a packaging module obtained by a modification based on the packaging module shown in Fig. 3. For some reference numbers in Fig. 7, please refer to the same reference numbers in Fig. 3. The fourth chip 23 and the fifth chip 24 are located on the bottom chip layer 20, and the first chip 31 is located on the top chip layer 30.

[0070] In the packaging module shown in FIG. 7, the lead-out surface of some chips in the bottom chip layer 20 faces the substrate layer 10. As shown in FIG. 7, the lead-out surface of the fourth chip 23 faces the substrate layer 10. For the connection manner between the fourth chip 23 and the substrate layer 10, please refer to the related description of the second chip 21 and the substrate layer 10 in FIG. 3. The details will not be described again here. When the fifth chip 24 is arranged, the fifth chip 24 is bonded to the substrate layer 10, and the connection surface of the fifth chip 24 is separated from the substrate layer 10. Facing the other side The connection surface of the fifth chip 24 is conductively connected to the circuit layer of the substrate layer 10 by using a second conductor. For example, the second conductor may be a bonding wire d.

[0071] When the first chip 31 and the fifth chip 24 are arranged, the fifth chip 24 and the first chip 31 are arranged alternately, so that the connection surface of the fifth chip 24 is exposed to the outside of the first chip 31, and the bonding wire d is connected to a portion of the connection surface of the fifth chip 24 exposed to the outside of the first chip 31.

[0072] In an optional solution, the height of the bonding wire d is lower than the height of the surface of the first chip 31 facing away from the substrate layer 10 to prevent the placed bonding wire d from affecting the height of the packaging module.

[0073] 8 shows another modified structure based on the packaging module shown in FIG. 3. Some reference numbers in FIG. 8 should refer to the same reference numbers in FIG. 3. The multiple chip layers include a top chip layer 30, a middle chip layer 50, and a bottom chip layer 20. The bottom chip layer 20 is the chip layer closest to the substrate layer. The middle chip layer 50 is the chip layer located between the bottom chip layer 20 and the top chip layer 30, and the middle chip layer 50 is the chip layer located between the top chip layer 20 and the top chip layer 30. 30The top chip layer 30 includes a first chip 31, the middle chip layer includes a sixth chip 51. The connection surface of the sixth chip 51 faces the substrate layer 10, and the bottom chip layer 20 includes a seventh chip 25 and a tenth chip 26. The connection surfaces of the seventh chip 25 and the tenth chip 26 face the substrate layer 10 and are conductively connected to the circuit layer of the substrate layer 10.

[0074] Regarding the connection method between the seventh chip 25 and the tenth chip 26 in the bottom chip layer 20 and the substrate layer 10, please refer to the connection method between the second chip 21 and the third chip 22 and the substrate layer 10 shown in Fig. 3. The details will not be described again here.

[0075] The connection surface of the sixth chip 51 is conductively connected to the connection surface of the first chip 31 and the connection surface of the seventh chip 25 separately by using a first conductor. As shown in FIG. 8, the first conductor is a bonding wire e and a bonding wire f. The first chip 31 and the sixth chip 51 are connected to each other by a bonding wire e. Wire The sixth chip 51 and the seventh chip 25 are connected by using a bonding wire. Wire The first chip 31 and the second chip 32 are connected by using the same. 2 Chip 2 1 Please refer to the method in which the and are connected by using a bonding wire a in Figure 3. The details will not be described again here.

[0076] Figure 9 shows another modified structure based on the packaging module shown in Figure 3. It will be understood that in the structure shown in Figure 9, the embedded chip of the substrate layer 10 shown in Figure 3 is disposed on the surface of the substrate layer.

[0077] In FIG. 9, the multiple chip layers include a top chip layer 30, a middle chip layer 50, and a bottom chip layer 20. The bottom chip layer 20 is the chip layer closest to the substrate layer. The middle chip layer 50 is the chip layer located between the bottom chip layer 20 and the top chip layer 30, and the middle chip layer 50 is the chip layer adjacent to the top chip layer 20. The bottom chip layer 20 includes a ninth chip 27 and an eleventh chip 28, the middle chip layer 50 includes an eighth chip 52 and a twelfth chip 53, and the top chip layer 30 includes a first chip 31.

[0078] Regarding the connection method between the ninth chip 27 and the eleventh chip 28 in the bottom chip layer 20 and the substrate layer 10, please refer to the connection method between the second chip 21 and the third chip 22 and the substrate layer 10 shown in Fig. 3. The details will not be described again here.

[0079] The connection side of the ninth chip 27 and the connection side of the eleventh chip 28 both face the substrate layer 10. The ninth chip 27 and the eleventh chip 28 are conductively connected to the circuit layer of the substrate layer 10 by using solder pads. In addition, the ninth chip 27 and the eleventh chip 28 are spaced apart to provide wiring space for conductive connections between another chip and the circuit layer of the substrate layer 10.

[0080] The eighth chip 52 and the ninth chip 27 of the intermediate chip layer 50 are bonded by an adhesive. The eighth chip 52 and the ninth chip 27 are arranged alternately, so that the eighth chip 52 is partially exposed to the outside of the ninth chip 27. The connection surface of the eighth chip 52 faces the substrate layer 10, and the part of the connection surface of the eighth chip 52 exposed to the outside of the ninth chip 27 is a conductive Pillarh is used to conductively connect the twelfth chip 53 to the circuit layer of the substrate layer 10. The twelfth chip 53 is bonded to the ninth chip 27 and the eleventh chip 28 by an adhesive. The twelfth chip 53 and the eleventh chip 28 are arranged alternately, so that the twelfth chip 53 is partially exposed to the outside of the eleventh chip 28. The connection surface of the twelfth chip 53 faces the substrate layer 10, and the parts of the connection surfaces of the twelfth chip 53 exposed to the outside of the ninth chip 27 and the eleventh chip 28 are conductively connected to the circuit layer of the substrate layer 10 by an adhesive. Pillar (third conductor) is used to conductively connect to the circuit layer of the substrate layer 10. As shown in FIG. 9, the twelfth chip 53 is Pillar j and conductivity Pillar i are separately used to conductively connect to the circuit layer of the substrate layer 10. It should be understood that the conductive connection scheme between the twelfth chip 53 and the circuit layer of the substrate layer 10 shown in FIG. 9 is merely a specific example scheme. In actual manufacturing, the wiring design may be implemented based on the specific location of the chip.

[0081] Top chip layer 30 includes a first chip 31 that is separately bonded to an eighth chip 52 and a twelfth chip 53 by adhesive. In addition, Since the first chip 31 and the eighth chip 52 are arranged alternately, the first chip 31 is partially exposed to the outside of the eighth chip 52. The connection surface of the first chip 31 faces the substrate layer 10, and a part of the connection surface of the first chip 31 exposed to the outside of the eighth chip 52 is conductively connected to the connection surface of the eighth chip 52 by using a bonding wire g (first conductor).

[0082] Although the above examples show that different chip layers include one or two chips, it should be understood that in this embodiment of the present application, the number of chips in each chip layer is not particularly limited, and different numbers of chips may be selected based on actual situations.

[0083] From the structure of the packaging module shown in Fig. 9, it can be seen that in the packaging module provided in this embodiment of the present application, the chip on the top layer is inverted, so that the conductor for the conductive connection between the chip on the top layer and the chip on another layer does not occupy the space of the packaging module. The size of the packaging module is reduced. In addition, although the packaging module shown in Fig. 9 does not use embedded chips, the packaging module shown in Fig. 9 reduces the number of substrates used compared with the packaging module shown in Fig. 2. This also reduces the size of the packaging module.

[0084] An embodiment of the present application further provides an electronic device, such as a mobile phone or a smart watch. The structure of the electronic device shown in FIG. 1 is used as an example. The electronic device includes a housing 100 and a main body disposed in the housing 100. board The packaging module 300 includes a main board Fixed above 200, main board The packaging module 300 is conductively connected to the packaging module 200 in the previous example. Use In this case, all the chips are supported by one substrate (substrate layer) to reduce the number of substrates used and further reduce the thickness of the packaging module. In addition, since the connection surface of the first chip faces the substrate layer, the first chip and the first conductor connected to another chip do not occupy additional space, thereby reducing the thickness of the packaging module and facilitating miniaturization of the packaging module.

[0085] Obviously, those skilled in the art will appreciate that Example Various modifications and variations can be made to the present application without departing from the scope of the present invention. The present application is intended to cover such modifications and variations of the present application as long as they fall within the scope of protection defined by the following claims and their equivalent technologies. [Explanation of symbols]

[0086] 1 First Substrate 2 Second Board 3. Chip 4 Chips 5 Packaging Layer 6 Chips 7 Bonding Wire 10 Substrate Layer 11 The first embedded chip 12 Second embedded chip 13 Metal bump 14 Avoidance Groove 20 Bottom Chip Layer 21 The second chip 22 The third chip 23 The Fourth Chip 24 The Fifth Chip 25 The Seventh Chip 26 The 10th Chip 27 The 9th Chip 28 The 11th Chip 30 Top Chip Layer 31 The First Chip 40 Packaging Layer 50 Middle chip layer 51 The Sixth Chip 52 The 8th Chip 53 The 12th Chip 100 Housing 200 Main Plate 300 Packaging Module 311 Connection Area 400 Retaining Plate 500 Temporary Retaining Plate

Claims

1. A packaging module including a substrate layer and a plurality of chip layers stacked on the substrate layer, the plurality of chip layers including a top chip layer, the top chip layer being the chip layer furthest from the substrate layer; the top chip layer includes a first chip, a connection side of the first chip facing the substrate layer, the connection side of the first chip conductively connected to a chip of an adjacent chip layer by using a first conductor; A packaging module, wherein the substrate layer is provided with an avoidance groove for avoiding the first conductor.

2. The packaging module described in claim 1, wherein a connection surface of the chip of the adjacent chip layer faces the substrate layer, one end of the first conductor is connected to the connection surface of the first chip, and the other end of the first conductor is connected to the connection surface of the chip of the adjacent chip layer.

3. 3. The packaging module of claim 1, wherein the first conductor is located on a side of the first chip that faces the substrate layer.

4. A packaging module described in any one of claims 1 to 3, wherein the connection surface of the first chip has a connection area exposed to an upper surface of the chip of the adjacent chip layer, and one end of the first conductor is connected to the exposed connection area.

5. 5. A packaging module as claimed in any one of claims 1 to 4, wherein the adjacent chip layer includes one or more chips, one or more connection surfaces of the one or more chips facing the substrate layer or all facing the substrate layer and conductively connected to a circuit layer of the substrate layer, and the connection surface of the first chip is connected to any of the one or more connection surfaces of the one or more chips by using one first conductor.

6. the adjacent chip layer includes a plurality of chips, the plurality of chips including a second chip and a third chip, a connection surface of the second chip and a connection surface of the third chip both facing the substrate layer, the second chip and the third chip being separately conductively connected to the circuit layer of the substrate layer; the first chip is conductively connected to the second chip by using the first conductor; or 6. The packaging module of claim 5, wherein the first chip is conductively connected to the second chip by using one first conductor, and the first chip is conductively connected to the third chip by using another first conductor.

7. the adjacent chip layer includes a plurality of chips, the plurality of chips including a fourth chip and a fifth chip, a connection surface of the fourth chip facing the substrate layer, the connection surface of the first chip being conductively connected to the connection surface of the fourth chip by using the first conductor; 6. The packaging module of claim 5, wherein a connection surface of the fifth chip faces away from the substrate layer, and the connection surface of the fifth chip is conductively connected to the circuit layer of the substrate layer by using a second conductor.

8. the plurality of chip layers further includes a bottom chip layer, the bottom chip layer being the chip layer closest to the substrate layer, and the adjacent chip layer being located between the bottom chip layer and the top chip layer; the chips located in the adjacent chip layer include a sixth chip, a connection surface of the sixth chip facing the substrate layer, the chips located in the bottom chip layer include a seventh chip, a connection surface of the seventh chip facing the substrate layer and conductively connected to a circuit layer of the substrate layer; 5. A packaging module according to claim 1, wherein the connection surface of the sixth chip is conductively connected to the connection surface of the first chip by using one first conductor and is conductively connected to the connection surface of the seventh chip by using another first conductor.

9. The packaging module of claim 5 , further comprising an embedded chip disposed on the substrate layer, the embedded chip being conductively connected to the circuit layer of the substrate layer.

10. the plurality of chip layers further includes a bottom chip layer, the bottom chip layer being the chip layer closest to the substrate layer, and the adjacent chip layer being located between the bottom chip layer and the top chip layer; the chips located in the adjacent chip layer include an eighth chip, a connection surface of the eighth chip facing the substrate layer, the chips located in the bottom chip layer include a ninth chip, a connection surface of the ninth chip facing the substrate layer and conductively connected to a circuit layer of the substrate layer; the connection surface of the first chip is conductively connected to the connection surface of the eighth chip by using the first conductor; 5. The packaging module of claim 1, wherein the connection surface of the ninth chip is conductively connected to the circuit layer of the substrate layer by using a third conductor.

11. The packaging module of claim 1 , wherein adjacent chip layers in the plurality of chip layers are bonded together.

12. An electronic device comprising a housing and a packaging module according to any one of claims 1 to 11 disposed within the housing.

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