Semiconductor device and inspection method

Abstract

To provide an inspection method by which deterioration in a wire connection state can be detected with high accuracy in a state where a semiconductor device is mounted on a circuit board, and a semiconductor device suitable for the inspection method.SOLUTION: A semiconductor device A1 comprises: a semiconductor element 6 including an element principal surface 6a, an element rear surface 6b, an electrode 61 and an electrode 62 disposed on the element principal surface 6a; a lead 1 on which the semiconductor element 6 is mounted; a lead 2 conducted to the electrode 61; a lead 3 conducted to the electrode 62; a plurality of wires 71 bonded to the electrode 61 and the lead 2; and a sealing resin 8 covering the semiconductor element 6. The sealing resin 8 includes a resin principal surface 81 directed to the same side as the element principal surface 6a, and a resin side face 83 communicating with the resin principal surface 81. The lead 2 includes an exposure part (top face 27) exposed from the sealing resin 8. The lead 3 includes an exposure part (terminal end face 34) exposed from the sealing resin 8. The exposure part of the lead 2 includes a portion which is positioned closer to the resin principal surface 81 than the exposure part of the lead 3.SELECTED DRAWING: Figure 3

Description

[Technical field]

[0001] The present disclosure relates to a semiconductor device and an inspection method. [Background technology]

[0002] Various configurations have been proposed for semiconductor devices equipped with semiconductor elements. One example of a semiconductor device is a semiconductor device in which a semiconductor element mounted on a die pad is connected to leads by wires, and these are covered with a sealing resin. In recent years, there has been a demand for semiconductor devices to be smaller and have larger capacities. To achieve this, the semiconductor device needs to operate at higher temperatures, and therefore the wire bonding portion needs to be more reliable than ever before. If deterioration of the wire bonding state can be detected in an actual use state in which the semiconductor device is mounted on a circuit board, it is possible to prevent system failures caused by the semiconductor device by repairing or replacing the semiconductor device.

[0003] Patent Document 1 discloses an inspection method for determining the bonding state of wires in a semiconductor device based on a resistance value. Even when the semiconductor device is in actual use, deterioration of the bonding state of the wires can be detected by monitoring the voltage change in the steady state. However, in this case, a change in resistance caused by a temperature change due to self-heating of the semiconductor device is unavoidable. Since it is difficult to separate the change in resistance caused by the temperature change, the accuracy of detecting the deterioration of the bonding state decreases. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Application Publication No. 5-41435 Summary of the Invention [Problem to be solved by the invention]

[0005] The present disclosure has been devised in light of the above-mentioned circumstances, and has an object to provide an inspection method capable of detecting deterioration of a wire bonding state with high accuracy when a semiconductor device is mounted on a circuit board, and a semiconductor device suitable for said inspection method. [Means for solving the problem]

[0006] The semiconductor device inspection method provided by the present disclosure is an inspection method for inspecting a bonding state of a plurality of first connection parts bonded to a source terminal of a semiconductor device having a gate terminal, a source terminal, and a sense source terminal while the semiconductor device is mounted on a circuit board, and includes a signal input step of inputting a pulse signal to the gate terminal, a voltage detection step of detecting a sense voltage which is the voltage of the sense source terminal with respect to the source terminal, and a comparison step of comparing the sense voltage when the pulse signal is turned off with a threshold voltage.

[0007] The semiconductor device provided by the present disclosure comprises a semiconductor element having an element principal surface and an element back surface facing opposite each other in a thickness direction, and a first electrode and a second electrode arranged on the element principal surface, a first lead on which the semiconductor element is mounted, a second lead arranged at a distance from the first lead and conductive to the first electrode, a third lead arranged at a distance from the first lead and the second lead and conductive to the second electrode, a plurality of first connection portions joined to the first electrode and the second lead, and a sealing resin covering the semiconductor element, the sealing resin having a resin principal surface facing the same side as the element principal surface, a resin back surface facing the same side as the element back surface, and a resin side surface connected to the resin principal surface and the resin back surface, the second lead having a second lead exposed portion exposed from the sealing resin, and the third lead having a third lead exposed portion exposed from the sealing resin, the second lead exposed portion including a portion located on the resin principal surface side than the third lead exposed portion. Effect of the Invention

[0008] The method for inspecting a semiconductor device according to the present disclosure can detect deterioration of a wire bond with high accuracy when the semiconductor device is mounted on a circuit board. Furthermore, the semiconductor device according to the present disclosure is suitable for the inspection method.

[0009] Other features and advantages of the present disclosure will become more apparent from the following detailed description taken in conjunction with the accompanying drawings. [Brief description of the drawings]

[0010] [Figure 1] 1 is a perspective view showing a semiconductor device according to a first embodiment of the present disclosure. [Diagram 2] 2 is a perspective view of the semiconductor device shown in FIG. 1 with the bottom side facing up. [Diagram 3] FIG. 2 is a plan view of the semiconductor device shown in FIG. [Figure 4] 2 is a bottom view of the semiconductor device shown in FIG. 1. [Diagram 5] FIG. 4 is a cross-sectional view taken along line VV in FIG. [Figure 6] FIG. 4 is a cross-sectional view taken along line VI-VI in FIG. [Figure 7] FIG. 4 is a cross-sectional view taken along line VII-VII in FIG. [Figure 8] 2 is a perspective view for explaining a method of inspecting the semiconductor device shown in FIG. 1 mounted on a circuit board. [Figure 9] 2 is a circuit diagram showing the semiconductor device shown in FIG. [Figure 10] 4 is a time chart showing a change in a sense voltage at the time of turn-off. [Figure 11] FIG. 4 is a perspective view showing a semiconductor device according to a second embodiment of the present disclosure. [Figure 12] 12 is a cross-sectional view of the semiconductor device shown in FIG. [Figure 13] 12 is a perspective view for explaining a method of inspecting the semiconductor device shown in FIG. 11 mounted on a circuit board. FIG. [Figure 14] FIG. 11 is a perspective view showing a semiconductor device according to a third embodiment of the present disclosure. [Figure 15]15 is a cross-sectional view of the semiconductor device shown in FIG. 14. [Figure 16] FIG. 11 is a plan view showing a semiconductor device according to a fourth embodiment of the present disclosure. [Figure 17] FIG. 13 is a plan view showing a semiconductor device according to a fifth embodiment of the present disclosure. [Figure 18] FIG. 13 is a plan view showing a semiconductor device according to a sixth embodiment of the present disclosure. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0011] Hereinafter, preferred embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0012] In this disclosure, "a certain object A is formed on a certain object B" and "a certain object A is formed on a certain object B" include "a certain object A is formed directly on a certain object B" and "a certain object A is formed on a certain object B with another object interposed between the certain object A and the certain object B" unless otherwise specified. Similarly, "a certain object A is disposed on a certain object B" and "a certain object A is disposed on a certain object B" include "a certain object A is disposed directly on a certain object B" and "a certain object A is disposed on a certain object B with another object interposed between the certain object A and the certain object B" unless otherwise specified. Similarly, "a certain object A is located on a certain object B" includes "a certain object A is located on a certain object B in contact with a certain object B" and "a certain object A is located on a certain object B with another object interposed between the certain object A and the certain object B". In addition, unless otherwise specified, "an object A overlaps with an object B when viewed in a certain direction" includes "an object A overlaps with the entirety of an object B" and "an object A overlaps with a part of an object B."

[0013] [First embodiment] A semiconductor device A1 according to a first embodiment of the present disclosure will be described with reference to Figures 1 to 7. The semiconductor device A1 includes leads 1 to 4, a semiconductor element 6, wires 71 to 73, and a sealing resin 8.

[0014] FIG. 1 is a perspective view showing the semiconductor device A1. FIG. 2 is a perspective view showing the semiconductor device A1 with the bottom side facing up. FIG. 3 is a plan view showing the semiconductor device A1. In FIG. 3, for ease of understanding, the outer shape of the sealing resin 8 is shown by an imaginary line (two-dot chain line) through the sealing resin 8. FIG. 4 is a bottom view showing the semiconductor device A1. FIG. 5 is a cross-sectional view taken along line VV in FIG. 3. FIG. 6 is a cross-sectional view taken along line VI-VI in FIG. 3. FIG. 7 is a cross-sectional view taken along line VII-VII in FIG. 3.

[0015] The semiconductor device A1 shown in these figures is a device that is surface-mounted on the circuit board of various devices. The use and function of the semiconductor device A1 are not limited. The package format of the semiconductor device A1 is DFN (Dual Flatpack No-leaded). The package format of the semiconductor device A1 is not limited to DFN. The shape of the semiconductor device A1 when viewed in the thickness direction is rectangular. For convenience of explanation, the thickness direction (direction when viewed in a plane) of the semiconductor device A1 is the z direction, the direction along one side of the semiconductor device A1 perpendicular to the z direction (left-right direction in FIG. 3) is the x direction, and the direction perpendicular to the z direction and the x direction (up-down direction in FIG. 3) is the y direction. In addition, one side of the z direction (lower side in FIG. 5 and FIG. 6) is the z1 side, and the other side (upper side in FIG. 5 and FIG. 6) is the z2 side. One side of the x direction (left side in FIG. 3 and FIG. 4) is the x1 side, and the other side (right side in FIG. 3 and FIG. 4) is the x2 side. One side in the y direction (the lower side in FIG. 3) is the y1 side, and the other side (the upper side in FIG. 3) is the y2 side. The z direction corresponds to the "thickness direction" in this disclosure. Each dimension of the semiconductor device A1 is not particularly limited, and in this embodiment, for example, the x direction dimension is about 8 mm, the y direction dimension is about 8 mm, and the z direction dimension is about 1 mm.

[0016] The leads 1 to 4 are electrically connected to the semiconductor element 6. The leads 1 to 4 are formed, for example, by subjecting a metal plate to etching or punching. The leads 1 to 4 are made of metal, and preferably made of either Cu or Ni, or an alloy thereof or a 42 alloy. In this embodiment, the case where the leads 1 to 4 are made of Cu will be described as an example. The thickness of the leads 1 to 4 is not particularly limited, and is, for example, 0.08 to 0.3 mm, and is about 0.2 mm in this embodiment.

[0017] As shown in Fig. 3, lead 1 is disposed at an end portion on the y2 side in the y direction of the semiconductor device A1, and spreads over the entire x direction. Leads 2 to 4 are disposed at an end portion on the y1 side in the y direction of the semiconductor device A1, spaced apart from lead 1, and arranged in the x direction, spaced apart from each other. Lead 2 is disposed at a corner portion on the y1 side of the x direction x1 of the semiconductor device A1 (the lower left corner in Fig. 3). Lead 3 is disposed at a corner portion on the y1 side of the y direction x2 of the semiconductor device A1 (the lower right corner in Fig. 3). Lead 4 is disposed between lead 2 and lead 3.

[0018] The lead 1 supports a semiconductor element 6 and has a main surface 11 , a back surface 12 , a back surface recess 13 , a plurality of terminal back surfaces 18 , a plurality of terminal end surfaces 14 , and a plurality of connecting end surfaces 15 .

[0019] The main surface 11 and the back surface 12 face opposite to each other in the z direction. The main surface 11 faces the z direction z2 side. The main surface 11 is a surface on which the semiconductor element 6 is mounted. In this embodiment, the shape of the main surface 11 is a shape having a portion protruding from a rectangle long in the x direction to the y direction y2 side and both sides in the x direction. There are four protruding portions on the y direction y2 side, which are arranged at equal intervals in the x direction, and each of them reaches the edge of the semiconductor device A1 on the y direction y2 side. There are two protruding portions on the x direction x1 side, which are arranged in the y direction, and each of them reaches the edge of the semiconductor device A1 on the x direction x1 side. There are two protruding portions on the x direction x2 side, which are arranged in the y direction, and each of them reaches the edge of the semiconductor device A1 on the x direction x2 side. The back surface 12 faces the z direction z1 side. The back surface 12 is exposed from the sealing resin 8 and becomes a back surface terminal. In this embodiment, the shape of the back surface 12 is a rectangle long in the x direction.

[0020] The back surface side recess 13 is a portion of the lead 1 recessed from the back surface 12 toward the main surface 11, and is disposed so as to surround the back surface 12. The thickness (dimension in the z direction) of the portion of the lead 1 where the back surface side recess 13 is located is approximately half the thickness of the portion where the back surface 12 is located. The back surface side recess 13 is formed, for example, by a half etching process. As shown in FIG. 4, the back surface side recess 13 is not exposed from the sealing resin 8, but is covered by the sealing resin 8. This prevents the lead 1 from peeling off from the sealing resin 8 to the z1 side in the z direction.

[0021] The multiple terminal back surfaces 18 are disposed on the y2 side of the back surface 12 in the y direction. The multiple terminal back surfaces 18 face the z1 side and are exposed from the sealing resin 8. The multiple terminal back surfaces 18 are at the same position as the back surface 12 in the z direction and are separated from the back surface 12 by the sealing resin 8. Like the back surface 12, the multiple terminal back surfaces 18 are portions that remain unetched when the back surface side recess 13 is formed by the half etching process. In this embodiment, there are four terminal back surfaces 18, which are arranged at equal intervals in the x direction and all reach the edge of the semiconductor device A1 on the y2 side in the y direction.

[0022] The multiple terminal end faces 14 are perpendicular to the main surface 11 and the back surface 12 and face in the y direction y2. Each terminal end face 14 is connected to one of the protruding parts of the main surface 11 on the y direction y2 side and one of the terminal back surfaces 18, and is exposed from the sealing resin 8. The terminal end faces 14 are formed by dicing in a cutting process in the manufacturing process. In this embodiment, there are four terminal end faces 14, each separated by the sealing resin 8 and arranged at equal intervals in the x direction. Each terminal end face 14 and the terminal back surface 18 connected thereto become terminals exposed from the sealing resin 8 (see FIGS. 4 and 6).

[0023] The multiple connection end faces 15 are perpendicular to the main surface 11 and the back surface 12 and face the x direction. Each connection end face 15 is connected to the main surface 11 and the back surface recess 13 and is exposed from the sealing resin 8. The connection end faces 15 are formed by dicing in a cutting step in the manufacturing process. In this embodiment, the multiple connection end faces 15 include two connection end faces 15 facing the x direction x1 side and two connection end faces 15 facing the x direction x2 side. The two connection end faces 15 facing the x direction x1 side are separated by the sealing resin 8 and lined up in the y direction. The two connection end faces 15 facing the x direction x2 side are separated by the sealing resin 8 and lined up in the y direction.

[0024] The shape of the lead 1 is not limited to the above. For example, the terminal end surface 14 and the terminal back surface 18 may be omitted, or the terminal back surface 18 may be connected to the back surface 12. Furthermore, the back surface recess 13 may be omitted.

[0025] The lead 2 has a main surface 21 , a back surface 22 , a back surface recess 23 , a plurality of terminal end surfaces 24 , and a connecting end surface 25 .

[0026] The main surface 21 and the back surface 22 face opposite to each other in the z direction. The main surface 21 faces the z2 side in the z direction. The main surface 21 is a surface to which the wire 71 is bonded. In this embodiment, the shape of the main surface 21 is a shape having a portion protruding from an elongated rectangle in the x direction to the y1 side in the y direction. There are two protruding portions, which are lined up in the x direction, and both reach the edge of the semiconductor device A1 on the y1 side in the y direction. The back surface 22 faces the z1 side in the z direction. The back surface 22 is exposed from the sealing resin 8 and becomes a back surface terminal. In this embodiment, the shape of the back surface 22 is a U-shape that is open on the y1 side in the y direction. Both ends of the U-shape reach the edge of the semiconductor device A1 on the y1 side in the y direction.

[0027] The rear surface side recess 23 is a portion of the lead 2 recessed from the rear surface 22 toward the main surface 21, and is disposed around the rear surface 22. The thickness (dimension in the z direction) of the portion of the lead 2 where the rear surface side recess 23 is located is approximately half the thickness of the portion where the rear surface 22 is located. The rear surface side recess 23 is formed, for example, by half etching. As shown in FIG. 4, the rear surface side recess 23 is not exposed from the sealing resin 8, but is covered by the sealing resin 8. This prevents the lead 2 from peeling off from the sealing resin 8 to the z1 side in the z direction.

[0028] The multiple terminal end faces 24 are perpendicular to the main surface 21 and the back surface 22 and face in the y direction y1. Each terminal end face 24 is connected to one of the protruding parts of the main surface 21 and one of the two ends of the U-shape of the back surface 22, and is exposed from the sealing resin 8. The terminal end faces 24 are formed by dicing in a cutting process in the manufacturing process. In this embodiment, there are two terminal end faces 24, which are spaced apart by the sealing resin 8 and lined up in the x direction. Each terminal end face 24 and the back surface 22 connected thereto form a terminal exposed from the sealing resin 8 (see FIGS. 2, 4, and 6).

[0029] The connecting end surface 25 is a surface that is perpendicular to the main surface 21 and the back surface 22 and faces the x-direction x1 side. The connecting end surface 25 is connected to the main surface 21 and the back surface side recess 23, and is exposed from the sealing resin 8. The connecting end surface 25 is formed by dicing in a cutting process in the manufacturing process.

[0030] Further, the lead 2 has a protrusion 26. The protrusion 26 is a portion protruding from the main surface 21 toward the z2 side in the z direction. When viewed in the z direction, the protrusion 26 is located closer to the y1 side of the main surface 21 in the y direction and closer to the x1 side in the x direction. In this embodiment, the protrusion 26 is disposed on the y2 side in the y direction than the terminal end surface 24. The protrusion 26 reaches the edge of the semiconductor device A1 on the z2 side in the z direction and is exposed from the sealing resin 8. The protrusion 26 has a top surface 27. The top surface 27 is a surface facing the z2 side in the z direction and is exposed from the sealing resin 8. In this embodiment, the protrusion 26 has a rectangular prism shape, and the top surface 27 has a rectangular shape. In this embodiment, the protrusion 26 is a prism-shaped pillar made of the same material as the other parts of the lead 2, fixed to a predetermined position on the main surface 21 of the lead 2. The position, material, shape, and forming method of the protrusion 26 are not limited. For example, protrusion 26 may be formed by performing an etching process, bending process, or the like, or by plating when forming leads 1 to 4 from a metal plate. Protrusion 26 may have a cylindrical shape, for example. In this case, top surface 27 has a circular shape. Protrusion 26 may be disposed at any position as long as it does not interfere with bonding of wire 71.

[0031] The shape of the lead 2 is not limited to the above. For example, the rear surface recess 23 may be omitted.

[0032] The lead 3 has a main surface 31, a back surface 32, a back surface recess 33, a terminal end surface 34, and a connecting end surface 35.

[0033] The main surface 31 and the back surface 32 face opposite to each other in the z direction. The main surface 31 faces the z2 side in the z direction. The main surface 31 is a surface to which the wire 73 is bonded. In this embodiment, the shape of the main surface 31 is a shape having a portion protruding from an elongated rectangle long in the x direction to the y1 side in the y direction. The protruding portion reaches the edge of the semiconductor device A1 on the y1 side in the y direction. The back surface 32 faces the z1 side in the z direction. The back surface 32 is exposed from the sealing resin 8 and becomes a back surface terminal. In this embodiment, the shape of the back surface 32 is rectangular. The back surface 32 reaches the edge of the semiconductor device A1 on the y1 side in the y direction.

[0034] The back surface side recess 33 is a portion of the lead 3 recessed from the back surface 32 toward the main surface 31, and is disposed around the back surface 32. The thickness (dimension in the z direction) of the portion of the lead 3 where the back surface side recess 33 is located is approximately half the thickness of the portion where the back surface 32 is located. The back surface side recess 33 is formed, for example, by half etching. As shown in FIG. 4, the back surface side recess 33 is not exposed from the sealing resin 8, but is covered by the sealing resin 8. This prevents the lead 3 from peeling off from the sealing resin 8 to the z1 side in the z direction.

[0035] The terminal end surface 34 is a surface that is perpendicular to the main surface 31 and the back surface 32 and faces the y-direction y1 side. The terminal end surface 34 is connected to the protruding portion of the main surface 31 and the back surface 22, and is exposed from the sealing resin 8. The terminal end surface 34 is formed by dicing in a cutting step in the manufacturing process. The terminal end surface 34 and the back surface 32 become terminals exposed from the sealing resin 8 (see FIGS. 2 and 4).

[0036] The connecting end surface 35 is a surface that is perpendicular to the main surface 31 and the back surface 32 and faces the x-direction x2 side. The connecting end surface 35 is connected to the main surface 31 and the back surface side recess 33, and is exposed from the sealing resin 8. The connecting end surface 35 is formed by dicing in a cutting process in the manufacturing process.

[0037] The shape of the lead 3 is not limited to the above. For example, the rear surface side recess 33 does not have to be provided.

[0038] The lead 4 has a main surface 41 , a back surface 42 , a back surface recess 43 , and a terminal end surface 44 .

[0039] The main surface 41 and the back surface 42 face opposite to each other in the z direction. The main surface 41 faces the z2 side in the z direction. The main surface 41 is a surface to which the wire 72 is bonded. In this embodiment, the shape of the main surface 41 is a rectangular shape having a portion protruding toward the y1 side in the y direction. The protruding portion reaches the edge of the semiconductor device A1 on the y1 side in the y direction. The back surface 42 faces the z1 side in the z direction. The back surface 42 is exposed from the sealing resin 8 and becomes a back surface terminal. In this embodiment, the shape of the back surface 42 is rectangular. The back surface 42 reaches the edge of the semiconductor device A1 on the y1 side in the y direction.

[0040] The rear surface side recess 43 is a portion of the lead 4 recessed from the rear surface 42 toward the main surface 41, and is disposed around the rear surface 42. The thickness (dimension in the z direction) of the portion of the lead 4 where the rear surface side recess 43 is located is approximately half the thickness of the portion where the rear surface 42 is located. The rear surface side recess 43 is formed, for example, by a half etching process. As shown in FIG. 4, the rear surface side recess 43 is not exposed from the sealing resin 8, but is covered by the sealing resin 8. This prevents the lead 4 from peeling off from the sealing resin 8 to the z1 side in the z direction.

[0041] The terminal end surface 44 is a surface that is perpendicular to the main surface 41 and the back surface 42 and faces the y-direction y1 side. The terminal end surface 44 is connected to the protruding portion of the main surface 41 and the back surface 42, and is exposed from the sealing resin 8. The terminal end surface 44 is formed by dicing in a cutting step in the manufacturing process. The terminal end surface 44 and the back surface 42 become terminals exposed from the sealing resin 8 (see FIGS. 2 and 4).

[0042] Further, the lead 4 has a protruding portion 46. The protruding portion 46 is a portion protruding from the main surface 41 toward the z2 side in the z direction. When viewed in the z direction, the protruding portion 46 is located closer to the y1 side of the main surface 41 in the y direction. In this embodiment, the protruding portion 46 is disposed on the y2 side in the y direction than the terminal end surface 44. The protruding portion 46 reaches the edge of the semiconductor device A1 on the z2 side in the z direction and is exposed from the sealing resin 8. The protruding portion 46 has a top surface 47. The top surface 47 is a surface facing the z2 side in the z direction and is exposed from the sealing resin 8. In this embodiment, the protruding portion 46 has a rectangular prism shape, and the top surface 47 has a rectangular shape. In this embodiment, the protruding portion 46 is a prism-shaped pillar made of the same material as the other parts of the lead 4, fixed to a predetermined position on the main surface 41 of the lead 4. The position, material, shape, and forming method of the protruding portion 46 are not limited. For example, the protrusion 46 may be formed by performing an etching process, a bending process, or the like, or by plating when the leads 1 to 4 are formed from a metal plate. The shape of the protrusion 46 may be, for example, a cylindrical shape. In this case, the shape of the top surface 47 is circular. The position of the protrusion 46 may be any position as long as it does not interfere with the bonding of the wire 72.

[0043] The shape of the lead 4 is not limited to the above. For example, the rear surface recess 43 does not have to be provided.

[0044] The semiconductor element 6 is an element that exerts the electrical function of the semiconductor device A1. The type of the semiconductor element 6 is not particularly limited. In this embodiment, the semiconductor element 6 is a metal-oxide-semiconductor field-effect transistor (MOSFET). The semiconductor element 6 may be another transistor such as an insulated gate bipolar transistor (IGBT) or a high electron mobility transistor (HEMT). The semiconductor element 6 includes an element body 60, an electrode 61, an electrode 62, and an electrode 63.

[0045] The element body 60 is a rectangular plate-like shape when viewed in the z direction. The element body 60 is made of a semiconductor material, and in this embodiment, is made of Si (silicon). The material of the element body 60 is not limited, and may be other materials such as SiC (silicon carbide) and GaN (gallium nitride). The element body 60 has an element main surface 6a and an element back surface 6b. The element main surface 6a and the element back surface 6b face opposite each other in the z direction. The element main surface 6a faces the z2 side in the z direction. The element back surface 6b faces the z1 side in the z direction. The electrode 61 and the electrode 62 are disposed on the element main surface 6a. The electrode 63 is disposed on the element back surface 6b. In this embodiment, the electrode 61 is a source electrode, the electrode 62 is a gate electrode, and the electrode 63 is a drain electrode.

[0046] As shown in FIG. 5 and FIG. 6, the semiconductor element 6 is mounted at approximately the center of the main surface 11 of the lead 1 via a bonding material 79. In this embodiment, the bonding material 79 is a conductive bonding material, for example, solder. The bonding material 79 may be a conductive bonding material such as silver paste or a sintered silver bonding material. The semiconductor element 6 has a back surface 6b bonded to the main surface 11 of the lead 1 by the bonding material 79. The electrode 63 of the semiconductor element 6 is conductively connected to the lead 1 via the bonding material 79. As a result, the lead 1 is conductively connected to the electrode 63 (drain electrode) of the semiconductor element 6 and functions as a drain terminal.

[0047] The electrode 62 of the semiconductor element 6 is conductively connected to the lead 3 via the wire 73 as shown in FIG. 3. As a result, the lead 3 is conductively connected to the electrode 62 (gate electrode) of the semiconductor element 6 and functions as a gate terminal. Also, the electrode 61 of the semiconductor element 6 is conductively connected to the lead 2 via the wire 71 as shown in FIG. 3. As a result, the lead 2 is conductively connected to the electrode 61 (source electrode) of the semiconductor element 6 and functions as a source terminal. Furthermore, the electrode 61 of the semiconductor element 6 is also conductively connected to the lead 4 via the wire 72 as shown in FIG. 3. As a result, the lead 4 is conductively connected to the electrode 61 (source electrode) of the semiconductor element 6 and functions as a sense source terminal. The sense source terminal is a terminal for detecting the potential of the electrode 61 (source electrode).

[0048] The wires 71 to 73 connect the semiconductor element 6 and the leads 2 to 4 and conduct them. The wires 71 to 73 are made of metal such as Cu, Au, Ag, and Al. The material of the wires 71 to 73 is not limited. As shown in FIG. 3, each of the wires 71 is bonded to the electrode 61 of the semiconductor element 6 and the main surface 21 of the lead 2. In this embodiment, the electrode 61 is connected to the lead 1 by six wires 71. The number of wires 71 is not limited. The wire 72 is bonded to the electrode 61 of the semiconductor element 6 and the main surface 41 of the lead 4. In this embodiment, the electrode 61 is connected to the lead 4 by one wire 72. The number of wires 72 is not limited. The wire 73 is bonded to the electrode 62 of the semiconductor element 6 and the main surface 31 of the lead 3. In this embodiment, the electrode 62 is connected to the lead 3 by one wire 73. The number of wires 73 is not limited.

[0049] The sealing resin 8 covers a part of each of the leads 1 to 4, the semiconductor element 6, the bonding material 79, and the wires 71 to 73. The sealing resin 8 is made of, for example, a black epoxy resin. Note that the material of the sealing resin 8 is not limited.

[0050] The sealing resin 8 has a resin main surface 81, a resin back surface 82, and four resin side surfaces 83. The resin main surface 81 and the resin back surface 82 face opposite each other in the z direction. The resin main surface 81 faces the z-direction z2 side, and the resin back surface 82 faces the z-direction z1 side.

[0051] Each of the four resin side surfaces 83 is perpendicular to the resin main surface 81 and the resin back surface 82, connects the resin main surface 81 and the resin back surface 82, and faces outward in the x direction or y direction. Each of the resin side surfaces 83 is formed by dicing in a cutting step in the manufacturing process. The four resin side surfaces 83 include a resin side surface 831, a resin side surface 832, a resin side surface 833, and a resin side surface 834. The resin side surface 831 and the resin side surface 832 face opposite each other in the x direction. The resin side surface 831 is a surface disposed on the x1 side in the x direction and faces the x1 side in the x direction, and the resin side surface 832 is a surface disposed on the x2 side in the x direction and faces the x2 side in the x direction. The resin side surface 833 and the resin side surface 834 face opposite each other in the y direction. The resin side surface 833 is a surface that is disposed on the y1 side in the y direction and faces the y1 side in the y direction, and the resin side surface 834 is a surface that is disposed on the y2 side in the y direction and faces the y2 side in the y direction.

[0052] As shown in FIG. 2 and FIG. 4, the rear surface 12 of the lead 1 and the rear surfaces 18 of the terminals, the rear surface 22 of the lead 2, the rear surface 32 of the lead 3, and the rear surface 42 of the lead 4 are exposed from the resin rear surface 82 of the sealing resin 8 and are flush with the resin rear surface 82. In this embodiment, as shown in FIG. 1 and FIG. 6, the top surface 27 of the lead 2 and the top surface 47 of the lead 4 are exposed from the resin main surface 81 of the sealing resin 8 and are flush with the resin main surface 81. The top surface 27 and the top surface 47 only need to be exposed from the resin main surface 81 of the sealing resin 8, and do not need to be flush with the resin main surface 81. For example, the protruding portion 46 of the lead 1 and the protruding portion 46 of the lead 4 may protrude from the resin main surface 81, and the top surface 27 and the top surface 47 may be located on the z-direction z2 side of the resin main surface 81. Furthermore, the top surface 27 and the top surface 47 may be located on the z-direction z1 side of the resin main surface 81 and exposed from a recess disposed on the resin main surface 81.

[0053] Furthermore, the two connecting end faces 15 of lead 1 facing the x1 side in the x-direction and the connecting end face 25 of lead 2 are exposed from a resin side face 831 and are flush with each other. The two connecting end faces 15 of lead 1 facing the x2 side in the x-direction and the connecting end face 35 of lead 3 are exposed from a resin side face 832 and are flush with each other. The multiple terminal end faces 24 of lead 2, the terminal end face 34 of lead 3, and the terminal end face 44 of lead 4 are exposed from a resin side face 833 and are flush with each other. The multiple terminal end faces 14 of lead 1 are exposed from a resin side face 834 and are flush with each other.

[0054] The portion of the lead 2 exposed from the sealing resin 8 corresponds to the "second lead exposed portion" of the present disclosure, and includes the back surface 22, the multiple terminal end faces 24, the connecting end face 25, and the top surface 27. The portion of the lead 3 exposed from the sealing resin 8 corresponds to the "third lead exposed portion" of the present disclosure, and includes the back surface 32, the terminal end face 34, and the connecting end face 35. The portion of the lead 4 exposed from the sealing resin 8 corresponds to the "fourth lead exposed portion" of the present disclosure, and includes the back surface 42, the terminal end face 44, and the top surface 47. The top surface 27 of the lead 2 and the top surface 47 of the lead 4 are located on the z-direction z2 side of the portion of the lead 3 exposed from the sealing resin 8 (the back surface 32, the terminal end face 34, and the connecting end face 35).

[0055] Next, an inspection method according to this embodiment will be described below with reference to Fig. 8 to Fig. 10. The inspection method is a method for inspecting the bonding state of a plurality of wires 71 of the semiconductor device A1 in a state in which the semiconductor device A1 is mounted on a circuit board.

[0056] Fig. 8 is a perspective view for explaining a method for inspecting the semiconductor device A1 mounted on a circuit board, Fig. 9 is a circuit diagram showing the semiconductor device A1, and Fig. 10 is a time chart showing a change in the sense voltage at the time of turn-off.

[0057] As shown in FIG. 8, the semiconductor device A1 is mounted on a circuit board 91. Each terminal of the semiconductor device A1 is joined by solder to a wiring 92 formed on the circuit board 91. A solder fillet 93 is formed between each terminal end face 24 of the lead 2, the terminal end face 34 of the lead 3, and the terminal end face 44 of the lead 4 and each wiring 92. Each solder fillet 93 covers most of each terminal end face 24, the terminal end face 34, and the terminal end face 44. The semiconductor device A1 is also connected to each electronic component mounted on the circuit board 91 through each wiring 92. As shown in FIG. 9, the lead 3 (gate terminal) is connected to an output terminal of a gate driver 99, and a control signal (pulse signal) can be input from the gate driver 99. The lead 1 (drain terminal) is conductively connected to a power source, and a power source voltage is applied to the lead 1 (source terminal). The lead 2 (source terminal) is grounded. In FIG. 9, a plurality of wires 71 are shown as inductors.

[0058] In the inspection method according to this embodiment, two probes 95 are used to detect a sense voltage Vss (see FIG. 9), which is the voltage of lead 4 (sense source terminal) relative to lead 2 (source terminal). As shown in FIG. 8, each of terminal end faces 24 and 44 is covered with a solder fillet 93, so it is difficult to directly contact each probe 95. In this embodiment, one of the two probes 95 is brought into contact with top face 27 of lead 2, and the other is brought into contact with top face 47 of lead 4. This allows the sense voltage Vss to be detected with high accuracy.

[0059] In the inspection method of this embodiment, a control signal (pulse signal) is input from the gate driver 99 to the lead 3 (signal input process), the sense voltage Vss is detected (voltage detection process), and the bonding state of the multiple wires 71 is determined based on the peak voltage of the sense voltage Vss when the control signal (pulse signal) is turned off.

[0060] FIG. 10(a) shows the time change of the voltage Vds of lead 1 relative to lead 2 (see FIG. 9) and the current Id flowing through leads 1 and 2. FIG. 10(b) shows the time change of the sense voltage Vss. When the control signal (pulse signal) is turned off, the voltage Vds increases and the current Id decreases. At this time, the decrease in current Id generates a back electromotive force between lead 2 and electrode 61 to which multiple wires 71 acting as inductors are connected. This causes a negative peak to appear in the sense voltage Vss, as shown in FIG. 10(b).

[0061] When any of the wires 71 connected to the electrodes 61 and the leads 2 of the semiconductor element 6 becomes open due to deterioration, the inductance of the wires 71 as a whole becomes large. Even if the wires 71 do not become open, if the connection state of the wires 71 deteriorates, the inductance becomes large compared to the normal state. Therefore, the back electromotive force generated at the time of turn-off becomes large, and the peak of the sense voltage Vss becomes large. In FIG. 10(b), the waveform Vss1 shows the waveform of the sense voltage Vss when all six wires 71 are connected normally. The waveform Vss2 shows the waveform of the sense voltage Vss when one wire 71 is in an open state and only five wires 71 are connected normally. The waveform Vss3 shows the waveform of the sense voltage Vss when two wires 71 are in an open state and only four wires 71 are connected normally. In the inspection method according to the present embodiment, as shown in FIG. 10(b), a voltage that the sense voltage Vss does not exceed when all six wires 71 are connected normally is set as the threshold voltage V0. Then, if the sense voltage Vss at the time of turning off the control signal (pulse signal) exceeds the threshold voltage V0 (becomes equal to or less than the threshold voltage V0), it is determined that the bonded state of the wire 71 has deteriorated (comparison step). On the other hand, if the sense voltage Vss does not exceed the threshold voltage V0 (does not become equal to or less than the threshold voltage V0), it is determined that the bonded state of the wire 71 is normal. Note that the comparison step may be performed by comparing at one turn-off, or may be performed by comparing at several turn-offs. For example, it may be determined that the wire 71 has deteriorated if the sense voltage Vss exceeds the threshold voltage V0 even once in a comparison at five turn-offs, and may be determined to be normal if the sense voltage Vss does not exceed the threshold voltage V0 in any of the five comparisons.

[0062] The inspection method according to the present embodiment may be performed using a detection device including a start-up unit for starting the gate driver 99, a detection unit for detecting the sense voltage Vss, and a comparison unit for comparing the detected sense voltage Vss with a threshold voltage V0. The inspection method according to the present embodiment may be performed manually by an operator. The waveform of the sense voltage Vss detected in the voltage detection process may be displayed on an oscilloscope or the like, and it may be visually determined whether or not the displayed waveform exceeds the threshold voltage V0. In the present embodiment, a case has been described in which a control signal is input from the gate driver 99 mounted on the circuit board 91 to the semiconductor device A1, but the present embodiment is not limited to this, and a pulse signal may be input to the semiconductor device A1 from outside the circuit board 91.

[0063] Next, the effects of the semiconductor device A1 and the inspection method will be described.

[0064] In the inspection method according to the present embodiment, a control signal (pulse signal) is input from the gate driver 99 to the lead 3, the sense voltage Vss is detected, and the bonding state of the multiple wires 71 is judged according to the peak voltage of the sense voltage Vss when the control signal (pulse signal) is turned off. According to this inspection method, since the judgment can be made based on the change in the sense voltage Vss when the control signal is turned off, there is no need to pass a large current for a long time, as in the case of judging based on the voltage change in a steady state. Therefore, the deterioration of the bonding state of the wires can be detected with high accuracy without being affected by the temperature change due to the self-heating of the semiconductor device A1.

[0065] The semiconductor device A1 according to this embodiment has a top surface 27 of lead 2 and a top surface 47 of lead 4 that are exposed from the resin main surface 81. Therefore, when the semiconductor device A1 is mounted on the circuit board 91, even if each terminal end surface 24 of lead 2 and each terminal end surface 44 of lead 4 are covered with a solder fillet 93, each probe 95 can be brought into contact with the top surface 27 and the top surface 47. This allows the sense voltage Vss to be detected with high accuracy without being affected by the solder fillet 93.

[0066] In this embodiment, the protrusion 26 (46) is disposed on the y2 side of the terminal end face 24 (44) in the y direction, and therefore the side surface on the y1 side is covered with the sealing resin 8 and is not exposed from the resin side surface 833. In other words, in the cutting process in the manufacturing process of the semiconductor device A1, the protrusion 26 (46) is not in a position to be diced. Therefore, dicing is easy.

[0067] In this embodiment, the case of inspecting the semiconductor device A1 has been described, but the present invention is not limited to this. The inspection method according to this embodiment can also be used for conventional semiconductor devices other than the semiconductor device A1, in which the top surface 27 and the top surface 47 are not exposed. When inspecting a conventional semiconductor device mounted on a circuit board 91, the sense voltage Vss may be detected by contacting each probe 95 with the wiring 92 that is conductive to the lead 2 (or the lead 4) or the solder fillet 93 formed on the lead 2 (or the lead 4). However, in this case, the sense voltage Vss is detected in a state in which the inductance components of the wiring 92 and the solder fillet 93 are also included, so that the detection accuracy is reduced compared to the case in which each probe 95 is directly contacted with the lead 2 (top surface 27) and the lead 4 (top surface 47). Even in this case, the deterioration of the bonding state of the wires can be detected without being affected by temperature changes due to self-heating of the semiconductor device.

[0068] In addition, in the present embodiment, the semiconductor element 6 and the leads 2 to 4 are connected to each other by the wires 71 to 73, but this is not limiting. The semiconductor element 6 and the leads 2 to 4 may be connected to each other by other conductive connecting parts such as metal plates (clips).

[0069] 11 to 18 show other embodiments of the present disclosure. In these figures, elements that are the same as or similar to those in the above embodiment are given the same reference numerals as in the above embodiment, and duplicated explanations will be omitted.

[0070] Second Embodiment A semiconductor device A2 according to a second embodiment of the present disclosure will be described with reference to Figs. 11 to 13. Fig. 11 is a perspective view showing the semiconductor device A2 and corresponds to Fig. 1. Fig. 12 is a cross-sectional view showing the semiconductor device A2 and corresponds to Fig. 6. Fig. 13 is a perspective view for explaining a method of inspecting the semiconductor device A2 mounted on a circuit board 91 and corresponds to Fig. 8. The semiconductor device A2 according to this embodiment differs from the semiconductor device A1 according to the first embodiment in the shapes of the leads 2 and 4.

[0071] The lead 2 according to this embodiment is different from the lead 2 according to the first embodiment in the position of the protrusion 26 and the dimension in the z direction. In this embodiment, as shown in FIG. 12, the protrusion 26 is disposed closer to the y1 side in the y direction and reaches the edge of the main surface 21 on the y1 side in the y direction. The surface on the y1 side of the protrusion 26 is exposed from the resin side surface 833, is flush with the resin side surface 833, and is a part of the terminal end surface 24 on the x1 side. In this embodiment, in order to distinguish between the two terminal end surfaces 24, the terminal end surface 24 on the x1 side is referred to as the terminal end surface 24a, and the terminal end surface 24 on the x2 side is referred to as the terminal end surface 24b. The protrusion 26 according to this embodiment is formed by fixing a pillar so as to straddle a portion of the metal plate (lead frame) that will become the lead 2 and a portion that will be removed by dicing, and dicing in a cutting process in the manufacturing process. 12, in this embodiment, the dimension of the protrusion 26 in the z direction is smaller than that of the protrusion 26 according to the first embodiment, and the surface of the protrusion 26 facing the z direction z2 side is not exposed from the resin main surface 81. In other words, the protrusion 26 does not have a top surface 27.

[0072] The lead 4 according to this embodiment is different from the lead 4 according to the first embodiment in the position of the protrusion 46 and the dimension in the z direction. In this embodiment, the protrusion 46 is disposed closer to the y direction y1 side and reaches the edge of the main surface 41 on the y direction y1 side. The surface on the y1 side of the protrusion 46 is exposed from the resin side surface 833, is flush with the resin side surface 833, and is a part of the terminal end surface 44. The protrusion 46 according to this embodiment is formed by fixing a pillar so as to straddle a portion of the metal plate (lead frame) that becomes the lead 4 and a portion that is removed by dicing, and dicing in a cutting process in the manufacturing process. In this embodiment, the dimension in the z direction of the protrusion 46 is smaller than that of the protrusion 46 according to the first embodiment, and the surface of the protrusion 46 facing the z direction z2 side is not exposed from the resin main surface 81. In other words, the protrusion 46 does not have a top surface 47.

[0073] As shown in FIG. 11, the distance in the z direction between the terminal end face 24a of the lead 2 and the terminal end face 44 of the lead 4 and the resin main surface 81 is smaller than the distance in the z direction between the terminal end face 34 of the lead 3 and the resin main surface 81. In this embodiment, the dimension T1 in the z direction of the terminal end face 24a of the lead 2 and the terminal end face 44 of the lead 4 is at least twice the dimension T2 in the z direction of the terminal end face 24b of the lead 2 and the terminal end face 34 of the lead 3. In addition, in this embodiment, the dimension T1 is at least half the dimension T3 in the z direction of the resin side surface 833. Note that the dimension T1 is not limited, and may be large enough to leave an exposed portion for contacting the probe 95 even when the solder fillet 93 is formed on the terminal end face 24a and the terminal end face 44. Terminal end face 24a of lead 2 and terminal end face 44 of lead 4 include portions located on the z-direction z2 side of portions of lead 3 exposed from sealing resin 8 (rear surface 32, terminal end face 34, and connecting end face 35). Terminal end face 24a corresponds to the "second lead end face" of the present disclosure. Terminal end face 44 corresponds to the "fourth lead end face" of the present disclosure. Terminal end face 34 corresponds to the "third lead end face" of the present disclosure.

[0074] As shown in FIG. 13, the semiconductor device A2 is mounted on a circuit board 91. Each terminal of the semiconductor device A2 is joined by solder to a wiring 92 formed on the circuit board 91. A solder fillet 93 is formed between the terminal end faces 24a and 24b of the lead 2, the terminal end face 34 of the lead 3, and the terminal end face 44 of the lead 4 and each wiring 92. The terminal end faces 24b and 34 are mostly covered by the solder fillets 93. On the other hand, the terminal end faces 24a and 44 are partially covered by the solder fillets 93, but have portions exposed from the solder fillets 93. In the inspection method according to this embodiment, each probe 95 is brought into contact with the portion exposed from the solder fillets 93 to detect the sense voltage Vss.

[0075] In the present embodiment, the inspection method can also determine the deterioration of the wire bonding state by the change in the sense voltage Vss when the control signal is turned off, and therefore there is no need to pass a large current for a long time, as in the case of determining the deterioration by the voltage change in the steady state. Therefore, the deterioration of the wire bonding state can be detected with high accuracy without being affected by the temperature change due to the self-heating of the semiconductor device A2.

[0076] Furthermore, in the semiconductor device A2 according to this embodiment, the terminal end surface 24a of the lead 2 and the terminal end surface 44 of the lead 4 extend toward the z-direction z2 side, and have portions exposed from the solder fillet 93. Therefore, even when the semiconductor device A2 is mounted on the circuit board 91, the probes 95 can be brought into contact with the portions of the terminal end surface 24a and the terminal end surface 44 exposed from the solder fillet 93. This allows the sense voltage Vss to be detected with high accuracy without being affected by the solder fillet 93.

[0077] Third Embodiment A semiconductor device A3 according to a third embodiment of the present disclosure will be described with reference to Fig. 14 and Fig. 15. Fig. 14 is a perspective view showing the semiconductor device A3 and corresponds to Fig. 1. Fig. 15 is a cross-sectional view showing the semiconductor device A3 and corresponds to Fig. 6. The semiconductor device A3 according to this embodiment differs from the semiconductor device A1 according to the first embodiment in the shapes of the leads 2 and 4.

[0078] The lead 2 according to this embodiment is different from the lead 2 according to the first embodiment in the position of the protrusion 26. In this embodiment, as shown in FIG. 15, the protrusion 26 is disposed closer to the y1 side in the y direction and reaches the edge of the main surface 21 on the y1 side in the y direction. The surface of the protrusion 26 on the y1 side is exposed from the resin side surface 833, is flush with the resin side surface 833, and is a part of the terminal end surface 24 on the x1 side. In this embodiment, in order to distinguish between the two terminal end surfaces 24, the terminal end surface 24 on the x1 side is referred to as the terminal end surface 24a, and the terminal end surface 24 on the x2 side is referred to as the terminal end surface 24b. The protrusion 26 according to this embodiment is formed by fixing a pillar so as to straddle a portion of the metal plate (lead frame) that will become the lead 2 and a portion that will be removed by dicing, and dicing in a cutting process in the manufacturing process.

[0079] The lead 4 according to this embodiment differs from the lead 4 according to the first embodiment in the position of the protrusion 46. In this embodiment, the protrusion 46 is disposed closer to the y1 side in the y direction, and reaches the edge of the main surface 41 on the y1 side in the y direction. The surface on the y1 side of the protrusion 46 is exposed from the resin side surface 833, is flush with the resin side surface 833, and forms part of the terminal end surface 44. The protrusion 46 according to this embodiment is formed by fixing a pillar so as to straddle a portion of the metal plate (lead frame) that will become the lead 4 and a portion that will be removed by dicing, and dicing in a cutting step in the manufacturing process.

[0080] In the inspection method according to the present embodiment, each probe 95 may be brought into contact with top surface 27 and top surface 47, or may be brought into contact with the portions of terminal end surface 24a and terminal end surface 44 exposed from solder fillet 93.

[0081] In the present embodiment, the inspection method can also determine the deterioration of the wire bonding state by the change in the sense voltage Vss when the control signal is turned off, and therefore there is no need to pass a large current for a long time, as in the case of determining the deterioration by the voltage change in the steady state. Therefore, the deterioration of the wire bonding state can be detected with high accuracy without being affected by the temperature change due to the self-heating of the semiconductor device A3.

[0082] Furthermore, in the semiconductor device A3 according to this embodiment, the terminal end faces 24a and 44 extend toward the z-direction z2 side, and have portions exposed from the solder fillet 93. The semiconductor device A3 also has top faces 27 and 47 exposed from the resin main surface 81. Therefore, even when the semiconductor device A2 is mounted on the circuit board 91, the probes 95 can be brought into contact with the portions of the terminal end faces 24a and 44 exposed from the solder fillet 93, or the top faces 27 and 47. This allows the sense voltage Vss to be detected with high accuracy without being affected by the solder fillet 93.

[0083] [Fourth embodiment] A semiconductor device A4 according to a fourth embodiment of the present disclosure will be described with reference to Fig. 16. Fig. 16 is a plan view showing the semiconductor device A4, and corresponds to Fig. 3. In Fig. 16, for ease of understanding, the outer shape of the sealing resin 8 is shown by an imaginary line (two-dot chain line) through the sealing resin 8. The semiconductor device A4 according to this embodiment differs from the semiconductor device A1 according to the first embodiment in that the lead 2 is divided into two members.

[0084] The semiconductor device A4 according to this embodiment includes leads 2a and 2b instead of the lead 2. The leads 2a and 2b are obtained by dividing the lead 2 into two members in the x direction, with the lead 2a being disposed on the x1 side in the x direction and the lead 2b being disposed on the x2 side in the x direction. The leads 2a and 2b each include a main surface 21, a back surface 22, a back surface recess 23, and a terminal end surface 24. The lead 2a further includes a connecting end surface 25. In addition, the leads 2a and 2b each include a protrusion 26. Each protrusion 26 is similar to the protrusion 26 according to the first embodiment and includes a top surface 27.

[0085] In this embodiment, the wires 71 that are joined to the lead 2a are referred to as wires 71a, and the wires that are joined to the lead 2b are referred to as wires 71b, among the plurality of wires 71. In this embodiment, there are three wires 71a and three wires 71b.

[0086] Hereinafter, the inspection method for determining the bonding state of the plurality of wires 71 according to the peak voltage of the sense voltage Vss at the time of turning off the control signal (pulse signal) described in the first embodiment is referred to as the "first inspection method". In this embodiment, the first inspection method is performed by bringing each probe 95 into contact with the top surface 27 of the lead 2a and the top surface 47 of the lead 4, thereby inspecting the bonding state of the plurality of wires 71a. Also, in this embodiment, the first inspection method is performed by bringing each probe 95 into contact with the top surface 27 of the lead 2b and the top surface 47 of the lead 4, thereby inspecting the bonding state of the plurality of wires 71b. Furthermore, in this embodiment, the second inspection method can be performed by bringing each probe 95 into contact with the top surface 27 of the lead 2a and the top surface 27 of the lead 2b. In the second inspection method, a voltage is applied between the two probes 95, and a flowing current is detected, thereby detecting the resistance value of the current path consisting of the lead 2a, the plurality of wires 71a, the electrode 61, the plurality of wires 71b, and the lead 2b. When any of the wires 71a and the wires 71b deteriorates, the resistance value of the corresponding current path increases. This makes it possible to detect deterioration of the bonding state of the wires 71a and the wires 71b while the semiconductor device A4 is mounted on the circuit board 91.

[0087] In this embodiment, lead 2a or lead 2b can be considered to correspond to the "second lead" of the present disclosure. Also, one of lead 2a and lead 2b can be considered to correspond to the "second lead" of the present disclosure, and the other can be considered to correspond to the "fourth lead" of the present disclosure.

[0088] In the present embodiment, in the first inspection method, since the deterioration can be judged by the change in the sense voltage Vss when the control signal is turned off, there is no need to pass a large current for a long time, as in the case of judging by the voltage change in the steady state. Therefore, the deterioration of the wire bonding state can be detected with high accuracy without being affected by the temperature change due to the self-heating of the semiconductor device A4. Furthermore, in the second inspection method, the current passed for the inspection can be small, and there is no need to pass a large current for a long time, as in the case of judging by the voltage change in the steady state. Therefore, the deterioration of the wire bonding state can be detected with high accuracy without being affected by the temperature change due to the self-heating of the semiconductor device A4.

[0089] Moreover, the semiconductor device A4 according to this embodiment includes the top surface 27 of the lead 2a, the top surface 27 of the lead 2b, and the top surface 47 of the lead 4, which are exposed from the resin main surface 81. Therefore, even if the terminal end surface 24 of the lead 2a, the terminal end surface 24 of the lead 2b, and the terminal end surface 44 of the lead 4 are covered with the solder fillet 93 when the semiconductor device A4 is mounted on the circuit board 91, each probe 95 can be brought into contact with each top surface 27 and top surface 47. As a result, in the first inspection method, the sense voltage Vss can be accurately detected without being affected by the solder fillet 93. Also, in the second inspection method, the resistance value of the current path can be accurately detected without being affected by the solder fillet 93. Also, in this embodiment, the protrusion 26 (46) is disposed on the y2 side of the terminal end surface 24 (44) in the y direction, so that in the cutting process in the manufacturing process of the semiconductor device A6, the protrusion 26 (46) is not in a position to be diced. Therefore, dicing is easy.

[0090] Fifth embodiment A semiconductor device A5 according to a fifth embodiment of the present disclosure will be described with reference to Fig. 17. Fig. 17 is a plan view showing the semiconductor device A5, and corresponds to Fig. 3. In Fig. 17, for ease of understanding, the outer shape of the sealing resin 8 is shown by an imaginary line (two-dot chain line) through the sealing resin 8. The semiconductor device A5 according to this embodiment differs from the semiconductor device A1 according to the first embodiment in that the type of semiconductor element 6 is different and that the semiconductor device A5 further includes leads 5.

[0091] The lead 1 according to this embodiment does not have a terminal end surface 14 or a terminal back surface 18, and is disposed on the semiconductor device A5 from the center in the y direction toward the y1 side. The semiconductor device A5 according to this embodiment further includes a lead 5. The lead 5 is disposed at an end of the semiconductor device A5 on the y2 side in the y direction, away from the lead 1. The lead 5 extends over the entire semiconductor device A5 in the x direction. The lead 5 includes a main surface 51, a back surface 52, a back surface recess 53, multiple terminal end surfaces 54, and multiple connecting end surfaces 55.

[0092] The main surface 51 and the back surface 52 face opposite to each other in the z direction. The main surface 51 faces the z2 side in the z direction. The main surface 51 is a surface to which the wire 74 is bonded. The wire 74 is the same as the wires 71 to 73. In this embodiment, the main surface 51 has a shape having a portion protruding from a rectangular shape long in the x direction to the y2 side in the y direction. There are four protruding portions, which are lined up in the x direction, and each of them reaches the edge of the semiconductor device A5 on the y2 side in the y direction. The back surface 52 faces the z1 side in the z direction. The back surface 52 is exposed from the sealing resin 8 to become a back surface terminal. In this embodiment, the back surface 52 has a shape having a portion protruding from a rectangular shape long in the x direction to the y2 side in the y direction. There are four protruding portions, which are lined up in the x direction, and each of them reaches the edge of the semiconductor device A5 on the y2 side in the y direction.

[0093] The back surface side recess 53 is a portion of the lead 5 recessed from the back surface 52 toward the main surface 51, and is disposed around the back surface 52. The thickness (dimension in the z direction) of the portion of the lead 5 where the back surface side recess 53 is located is approximately half the thickness of the portion where the back surface 52 is located. The back surface side recess 53 is formed, for example, by a half etching process. The back surface side recess 53 is not exposed from the sealing resin 8, but is covered by the sealing resin 8. This prevents the lead 5 from peeling off from the sealing resin 8 to the z1 side in the z direction.

[0094] The multiple terminal end faces 54 are perpendicular to the main surface 51 and the back surface 52 and face the y-direction y2 side. Each terminal end face 54 is connected to one of the protruding parts of the main surface 51 and one of the protruding parts of the back surface 52, and is exposed from the sealing resin 8. The terminal end faces 54 are formed by dicing in a cutting process in the manufacturing process. In this embodiment, there are four terminal end faces 54, each separated by the sealing resin 8 and arranged at equal intervals in the x-direction. Each terminal end face 54 and the back surface 52 connected thereto form a terminal exposed from the sealing resin 8.

[0095] The multiple connecting end faces 55 are perpendicular to the main surface 51 and the back surface 52 and face the x direction. Each connecting end face 55 is connected to the main surface 51 and the back surface side recess 53, and is exposed from the sealing resin 8. In this embodiment, the connecting end faces 55 are arranged one each on the x1 side and the x2 side in the x direction. The connecting end faces 55 are formed by dicing in a cutting process in the manufacturing process. The shape of the lead 5 is not limited to the above. For example, the back surface side recess 53 may not be present.

[0096] The semiconductor element 6 according to the present embodiment is a semiconductor element using a nitride semiconductor, and is a HEMT using gallium nitride (GaN). The element body 60 is formed by laminating a buffer layer, a GaN layer constituting an electron transit layer, an AlGaN layer constituting an electron supply layer, a p-type GaN layer, and a protective film made of, for example, a SiN film, on a substrate of, for example, Si. A two-dimensional electron gas (2DEG: 2 Dimensional Electron Gas) generated at a position close to the interface between the GaN layer and the AlGaN layer is used as a current path. In the semiconductor element 6 according to the present embodiment, an electrode 61, an electrode 62, and an electrode 63 are disposed on the element main surface 6a. In the present embodiment, the electrodes 61, 62, and 63 are each disposed in a plurality of separate parts. The layout of the electrodes 61, 62, and 63 is not limited. In the present embodiment, the electrode 61 is a source electrode, the electrode 62 is a gate electrode, and the electrode 63 is a drain electrode.

[0097] The electrode 62 is conductively connected to the lead 3 via the wire 73. As a result, the lead 3 is conductively connected to the electrode 62 (gate electrode) and functions as a gate terminal. In addition, the electrode 61 of the semiconductor element 6 is conductively connected to the lead 2 via the wire 71. As a result, the lead 2 is conductively connected to the electrode 61 (source electrode) of the semiconductor element 6 and functions as a source terminal. In addition, the electrode 61 of the semiconductor element 6 is also conductively connected to the lead 4 via the wire 72. As a result, the lead 4 is conductively connected to the electrode 61 (source electrode) of the semiconductor element 6 and functions as a sense source terminal. In addition, the electrode 63 is conductively connected to the lead 5 via the wire 74. As a result, the lead 5 is conductively connected to the electrode 63 (drain electrode) and functions as a drain terminal.

[0098] In the first inspection method of the present embodiment, since the change in the sense voltage Vss when the control signal is turned off can be used to make the determination, there is no need to pass a large current for a long time, as in the case of determining the change in voltage in a steady state. Therefore, the deterioration of the wire bonding state can be detected with high accuracy without being affected by temperature changes due to self-heating of the semiconductor device A5.

[0099] Also in this embodiment, the semiconductor device A5 has the top surface 27 and the top surface 47 exposed from the resin main surface 81. Therefore, even if the terminal end surface 24 of the lead 2 and the terminal end surface 44 of the lead 4 are covered with the solder fillet 93 when the semiconductor device A5 is mounted on the circuit board 91, the probes 95 can be brought into contact with the top surface 27 and the top surface 47. This allows the sense voltage Vss to be detected with high accuracy without being affected by the solder fillet 93. Also, in this embodiment, the protrusion 26 (46) is disposed on the y2 side of the terminal end surface 24 (44) in the y direction, so that the protrusion 26 (46) is not at a position to be diced in the cutting process in the manufacturing process of the semiconductor device A5. Therefore, dicing is easy.

[0100] Sixth Embodiment A semiconductor device A6 according to a sixth embodiment of the present disclosure will be described with reference to Fig. 18. Fig. 18 is a plan view showing the semiconductor device A6, and corresponds to Fig. 3. In Fig. 18, for ease of understanding, the outer shape of the sealing resin 8 is shown by an imaginary line (two-dot chain line) through the sealing resin 8. The semiconductor device A6 according to this embodiment differs from the semiconductor device A5 according to the fifth embodiment in that the lead 5 is divided into four members.

[0101] The semiconductor device A6 according to this embodiment includes leads 5a, 5b, 5c, and 5d instead of the lead 5. The leads 5a, 5b, 5c, and 5d are obtained by dividing the lead 5 into four members in the x direction, and are arranged in this order from the x1 side to the x2 side in the x direction. The leads 5a, 5b, 5c, and 5d each include a main surface 51, a back surface 52, a back surface recess 53, and a terminal end surface 54. The leads 5a and 5d further include a connecting end surface 55. The leads 5a, 5b, 5c, and 5d each include a protrusion 56.

[0102] The protrusion 56 is a portion protruding from the main surface 51 toward the z2 side in the z direction. When viewed in the z direction, the protrusion 56 is located closer to the y2 side of the main surface 51 in the y direction. In this embodiment, the protrusion 56 is disposed on the y1 side in the y direction than the terminal end surface 54. The protrusion 56 reaches the edge of the semiconductor device A6 on the z2 side in the z direction and is exposed from the sealing resin 8. The protrusion 56 has a top surface 57. The top surface 57 is a surface facing the z2 side in the z direction and is exposed from the sealing resin 8. In this embodiment, the protrusion 56 has a rectangular prism shape, and the top surface 57 has a rectangular shape. The position, material, shape, and formation method of each protrusion 56 are not limited. The position of each protrusion 56 may be any position that does not interfere with the bonding of the wire 74.

[0103] In this embodiment, of the multiple wires 74, the wire 74a is connected to the lead 5a, the wire 74b is connected to the lead 5b, the wire 74c is connected to the lead 5c, and the wire 74d is connected to the lead 5d. In this embodiment, there are two of each of the wires 74a to 74d.

[0104] In this embodiment, the deterioration of the bonding state of the wires 74a to 74d can be detected by the second inspection method. By bringing each probe 95 into contact with the top surface 57 of the lead 5a and the top surface 57 of the lead 5b and performing the second inspection method, the deterioration of the bonding state of the wires 74a and the wires 74b can be detected. Similarly, by bringing each probe 95 into contact with the top surface 57 of the lead 5c and the top surface 57 of the lead 5d and performing the second inspection method, the deterioration of the bonding state of the wires 74c and the wires 74d can be detected.

[0105] In this embodiment, any one of the leads 5a, 5b, 5c, and 5d can be considered to correspond to the "second lead" of the present disclosure, and any one of the others can be considered to correspond to the "fourth lead" of the present disclosure. In this case, the electrode 63 corresponds to the "first electrode" of the present disclosure.

[0106] In the first inspection method of the present embodiment, since the deterioration can be judged by the change in the sense voltage Vss when the control signal is turned off, there is no need to pass a large current for a long time, as in the case of judging by the voltage change in the steady state. Therefore, the deterioration of the bonded state of the wire can be detected with high accuracy without being affected by the temperature change due to the self-heating of the semiconductor device A6. Moreover, in the second inspection method, the current passed for the inspection may be small, and there is no need to pass a large current for a long time, as in the case of judging by the voltage change in the steady state. Therefore, the deterioration of the bonded state of the wire can be detected with high accuracy without being affected by the temperature change due to the self-heating of the semiconductor device A6.

[0107] The semiconductor device A6 according to the present embodiment also includes the top surface 27 of the lead 2, the top surface 47 of the lead 4, the top surface 57 of the lead 5a, the top surface 57 of the lead 5b, the top surface 57 of the lead 5c, and the top surface 57 of the lead 5d, which are exposed from the resin main surface 81. Therefore, even if the terminal end surface 24 of the lead 2 and the terminal end surface 44 of the lead 4 are covered with the solder fillet 93 when the semiconductor device A6 is mounted on the circuit board 91, the probes 95 can be brought into contact with the top surface 27 and the top surface 47. This allows the sense voltage Vss to be detected accurately without being affected by the solder fillet 93 in the first inspection method. Even if the terminal end surface 54 of the lead 5a, the terminal end surface 54 of the lead 5b, the terminal end surface 54 of the lead 5c, and the terminal end surface 54 of the lead 5d are covered with the solder fillet 93, the probes 95 can be brought into contact with any of the top surfaces 57. As a result, in the second inspection method, the resistance value of the current path can be detected with high accuracy without being affected by the solder fillet 93. Also, in this embodiment, the protrusion 26 (46) is located on the y2 side of the terminal end face 24 (44) in the y direction, so that the protrusion 26 (46) is not in a position to be diced in the cutting step in the manufacturing process of the semiconductor device A6. Also, since each protrusion 56 is located on the y1 side of each terminal end face 54 in the y direction, each protrusion 56 is not in a position to be diced in the cutting step in the manufacturing process of the semiconductor device A6. Therefore, dicing is easy.

[0108] The semiconductor device and inspection method according to the present disclosure are not limited to the above-described embodiment. The specific configuration of each part of the semiconductor device according to the present disclosure and the specific processing of each step of the inspection method according to the present disclosure can be freely designed in various ways.

[0109] [Appendix 1] a semiconductor element having a main surface and a back surface facing opposite each other in a thickness direction, and a first electrode and a second electrode disposed on the main surface; a first lead on which the semiconductor element is mounted; a second lead disposed apart from the first lead and electrically connected to the first electrode; a third lead disposed apart from the first lead and the second lead and connected to the second electrode; a plurality of first connection portions joined to the first electrode and the second lead; a sealing resin for covering the semiconductor element; Equipped with the sealing resin includes a resin main surface facing the same side as the element main surface, a resin back surface facing the same side as the element back surface, and a resin side surface connected to the resin main surface and the resin back surface; the second lead includes a second lead exposed portion exposed from the sealing resin; the third lead includes a third lead exposed portion exposed from the sealing resin; the second lead exposed portion includes a portion located closer to the resin main surface than the third lead exposed portion; Semiconductor device. [Appendix 2] a fourth lead arranged apart from the first to third leads and connected to the first electrode; the fourth lead includes a fourth lead exposed portion exposed from the sealing resin, the fourth lead exposed portion includes a portion located closer to the resin main surface than the third lead exposed portion; The semiconductor device according to claim 1. [Appendix 3] the second lead exposed portion includes a second lead top surface exposed from the resin main surface, the fourth lead exposed portion includes a fourth lead top surface exposed from the resin main surface; The semiconductor device according to claim 2. [Appendix 4] the second lead exposed portion includes a second lead end surface exposed from the resin side surface, the third lead exposed portion includes a third lead end surface exposed from the resin side surface, the fourth lead exposed portion includes a fourth lead end surface exposed from the resin side surface, a distance in the thickness direction between the second lead end face and the resin main surface and between the fourth lead end face and the resin main surface is smaller than a distance in the thickness direction between the third lead end face and the resin main surface; 4. The semiconductor device according to claim 2 or 3. [Appendix 5] a dimension in the thickness direction of the second lead end face and the fourth lead end face is at least twice as large as a dimension in the thickness direction of the third lead end face; The semiconductor device according to claim 4. [Appendix 6] a dimension in the thickness direction of the second lead end face and the fourth lead end face is equal to or greater than half a dimension in the thickness direction of the resin side face; The semiconductor device according to claim 4. [Appendix 7] the second lead exposed portion includes a second lead back surface exposed from the resin back surface, the third lead exposed portion includes a third lead back surface exposed from the resin back surface, the fourth lead exposed portion includes a fourth lead back surface exposed from the resin back surface, 7. The semiconductor device according to claim 2, [Appendix 8] further comprising a plurality of second connection portions joined to the first electrode and the fourth lead; 8. The semiconductor device according to claim 2, [Appendix 9] the plurality of first connection portions and the plurality of second connection portions are wires; 9. The semiconductor device according to claim 8. [Appendix 10] the semiconductor element is a transistor, The second electrode is a gate electrode. 10. The semiconductor device according to claim 2. [Appendix 11] The semiconductor element further includes an electron transport layer made of a nitride semiconductor. The semiconductor device according to claim 10. [Appendix 12] The first electrode is a source electrode. 12. The semiconductor device according to claim 10 or 11. [Appendix 13] The first electrode is a drain electrode. 12. The semiconductor device according to claim 10 or 11. [Appendix 14] 13. A method for inspecting a bonding state of the plurality of first connection portions of the semiconductor device according to claim 2 in a state where the semiconductor device is mounted on a circuit board, comprising: a signal input step of inputting a pulse signal to the third lead; a voltage detection step of detecting a sense voltage, the sense voltage being the voltage of the fourth lead relative to the second lead; a comparing step of comparing the sense voltage at the time when the pulse signal is turned off with a threshold voltage; An inspection method comprising: [Appendix 15] In the voltage detection step, two probes for detecting the sense voltage are brought into contact with the second lead exposed portion or the fourth lead exposed portion, respectively. The inspection method according to claim 14. [Appendix 16] 1. A method for inspecting a bonding state of a plurality of first connection parts bonded to a source terminal of a semiconductor device having a gate terminal, a source terminal, and a sense source terminal, in a state where the semiconductor device is mounted on a circuit board, comprising: a signal input step of inputting a pulse signal to the gate terminal; a voltage detection step of detecting a sense voltage, the sense voltage being a voltage of the sense source terminal relative to the source terminal; a comparing step of comparing the sense voltage at the time when the pulse signal is turned off with a threshold voltage; An inspection method comprising: [Appendix 17] In the comparison step, when the sense voltage becomes equal to or lower than the threshold voltage, it is determined that the junction state is deteriorated. 17. The inspection method according to any one of claims 14 to 16. [Explanation of symbols]

[0110] A1 to A6: Semiconductor device 1: Lead 11: Main surface 12: Back side 13: Reverse side recess 14:Terminal end face 15: Connection end face 18: Terminal back side 2, 2a, 2b: Lead 21: Main surface 22: Back side 23: Reverse side recess 24, 24a, 24b: Terminal end face 25: Connection end face 26:Protrusion 27:Top surface 3: Lead 31: Main surface 32: Back side 33: Reverse side recess 34:Terminal end face 35: Connection end face 4: Lead 41: Main surface 42: Back side 43: Reverse side recess 44:Terminal end face 46: Protrusion 47:Top surface 5, 5a, 5b, 5c, 5d: Lead 51: Main surface 52: Back side 53: Reverse side recess 54:Terminal end face 55: Connection end face 56:Protrusion 57:Top surface 6: Semiconductor elements 60: Element body 6a: Element main surface 6b: Back side of element 61,62,63: ​​Electrode 71, 71a, 71b, 72, 73, 74, 74a, 74b, 74c, 74d: Wire 79: Bonding material 8: Sealing resin 81: Resin main surface 82: Resin back 83,831,832,833,834: Resin side 91: Circuit board 92: Wiring 93: Solder fillet 95: Probe 99: Gate driver

Claims

1. a semiconductor element having a main surface and a back surface facing opposite each other in a thickness direction, and a first electrode and a second electrode disposed on the main surface; a first lead on which the semiconductor element is mounted; a second lead disposed apart from the first lead and electrically connected to the first electrode; a third lead disposed apart from the first lead and the second lead and electrically connected to the second electrode; a fourth lead disposed apart from the first to third leads and electrically connected to the first electrode; a plurality of first connection portions joined to the first electrode and the second lead; A sealing resin that covers the semiconductor element; Equipped with the sealing resin includes a resin main surface facing the same side as the element main surface, a resin back surface facing the same side as the element back surface, and a resin side surface connected to the resin main surface and the resin back surface; the second lead includes a second lead exposed portion exposed from the sealing resin; the third lead includes a third lead exposed portion exposed from the sealing resin, the fourth lead includes a fourth lead exposed portion exposed from the sealing resin, the second lead exposed portion includes a portion located closer to the resin main surface than the third lead exposed portion, the fourth lead exposed portion includes a portion located closer to the resin main surface than the third lead exposed portion; Semiconductor device.

2. the second lead exposed portion includes a second lead top surface exposed from the resin main surface, the fourth lead exposed portion includes a fourth lead top surface exposed from the resin main surface; The semiconductor device according to claim 1 .

3. the second lead exposed portion includes a second lead end surface exposed from the resin side surface, the third lead exposed portion includes a third lead end surface exposed from the resin side surface, the fourth lead exposed portion includes a fourth lead end surface exposed from the resin side surface, a distance in the thickness direction between the second lead end face and the resin main surface and between the fourth lead end face and the resin main surface is smaller than a distance in the thickness direction between the third lead end face and the resin main surface; 3. The semiconductor device according to claim 1 or 2.

4. a dimension in the thickness direction of the second lead end face and the fourth lead end face is equal to or greater than twice a dimension in the thickness direction of the third lead end face; The semiconductor device according to claim 3 .

5. a dimension in the thickness direction of the second lead end surface and the fourth lead end surface is equal to or greater than half a dimension in the thickness direction of the resin side surface; The semiconductor device according to claim 3 .

6. the second lead exposed portion includes a second lead back surface exposed from the resin back surface, the third lead exposed portion includes a third lead back surface exposed from the resin back surface, the fourth lead exposed portion includes a fourth lead back surface exposed from the resin back surface, 6. The semiconductor device according to claim 1.

7. 7. The semiconductor device according to claim 1, further comprising a plurality of second connection portions joined to said first electrode and said fourth lead.

8. the first connection portions and the second connection portions are wires; The semiconductor device according to claim 7.

9. the semiconductor element is a transistor, The second electrode is a gate electrode.

9. The semiconductor device according to claim 1.

10. The semiconductor element further includes an electron transport layer made of a nitride semiconductor. The semiconductor device according to claim 9.

11. The first electrode is a source electrode. The semiconductor device according to claim 9 or 10.

12. The first electrode is a drain electrode. The semiconductor device according to claim 9 or 10.

13. 12. A method for inspecting a bonding state of the plurality of first connection portions of the semiconductor device according to claim 1 in a state where the semiconductor device is mounted on a circuit board, comprising: a signal input step of inputting a pulse signal to the third lead; a voltage detection step of detecting a sense voltage, the sense voltage being the voltage of the fourth lead relative to the second lead; a comparing step of comparing the sense voltage at the time when the pulse signal is turned off with a threshold voltage; An inspection method comprising:

14. In the voltage detection step, two probes for detecting the sense voltage are brought into contact with the second lead exposed portion or the fourth lead exposed portion, respectively. The inspection method according to claim 13.

15. 1. A method for inspecting a bonding state of a plurality of first connection portions bonded to a source terminal of a semiconductor device having a gate terminal, a source terminal, and a sense source terminal, in a state in which the semiconductor device is mounted on a circuit board, the method comprising: a signal input step of inputting a pulse signal to the gate terminal; a voltage detection step of detecting a sense voltage, the sense voltage being a voltage of the sense source terminal relative to the source terminal; a comparing step of comparing the sense voltage at the time when the pulse signal is turned off with a threshold voltage; An inspection method comprising:

16. In the comparison step, when the sense voltage becomes equal to or lower than the threshold voltage, it is determined that the junction state is deteriorated.

16. The inspection method according to claim 13.

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