Semiconductor Structure

Abstract

An embodiment of the present invention provides a semiconductor structure, the semiconductor structure including a substrate and an active pillar located on the substrate, the active pillar extending along a first direction, the first direction being parallel to a substrate plane, the active pillar including a body region extending along the first direction and a peripheral region surrounding the body region, the peripheral region including a channel region, a doping ion type of the channel region and a doping ion type of the body region being the same, and a doping concentration of the channel region being greater than a doping concentration of the body region.

Description

[Technical field]

[0001] (CROSS-REFERENCE TO RELATED APPLICATIONS) This application claims priority to a Chinese patent application filed with the China Patent Office on May 30, 2022, bearing application number 202210599310.4 and entitled "Semiconductor Structure," the entire contents of which are incorporated herein by reference.

[0002] The present invention relates to the field of semiconductor technology, and more particularly to semiconductor structures. [Background technology]

[0003] Semiconductor structures such as three-dimensional dynamic random access memory (3D DRAM) typically include multiple transistors stacked on top of each other on a substrate.

[0004] However, because the transistors are floating above the substrate, charges are easily accumulated in the channel region of the transistor, resulting in the floating body effect, warping effect, parasitic bipolar transistor effect, threshold voltage shift, etc., which affect the performance of the semiconductor structure. Summary of the Invention [Means for solving the problem]

[0005] An embodiment of the present invention provides a semiconductor structure, the semiconductor structure comprising: The semiconductor device includes a substrate and an active pillar located on an upper portion of the substrate, the active pillar extending along a first direction, the first direction being parallel to a substrate plane, the active pillar including a body region extending along the first direction and a peripheral region surrounding the body region, the peripheral region including a channel region, a doping ion type of the channel region and a doping ion type of the body region being the same, and a doping concentration of the channel region being greater than a doping concentration of the body region.

[0006] In some embodiments, the body region includes an inner layer extending along a first direction and an outer layer surrounding the inner layer, the doping concentration of the inner layer being greater than the doping concentration of the outer layer.

[0007] In some embodiments, the doping concentration of the body region gradually decreases from the center to the periphery along a radial direction of the active pillar.

[0008] In some embodiments, the peripheral region further includes a first doping region and a second doping region, the first doping region, the channel region, and the second doping region being sequentially arranged along a first direction, and the body region further includes an extension region not surrounded by the peripheral region, the extension region being adjacent to the first doping region.

[0009] In some embodiments, the semiconductor structure further includes a conductive structure extending along a second direction and electrically connected to the extension region, the second direction intersecting the first direction and parallel to the substrate plane.

[0010] In some embodiments, the semiconductor structure further includes a conductive structure extending along a third direction and electrically connected to the extension region, the third direction being perpendicular to the substrate plane.

[0011] In some embodiments, the number of the active pillars is multiple, and the active pillars are arranged into a plurality of active pillar rows and a plurality of active pillar columns, the active pillar rows extending along a second direction, the second direction intersecting the first direction and parallel to the substrate plane, and the active pillar columns extending along a third direction, the third direction being perpendicular to the substrate plane.

[0012] In some embodiments, the semiconductor structure further includes a conductive structure located on the substrate, the conductive structure being plate-shaped, and the conductive structure being electrically connected to extension regions of a plurality of the active pillar rows.

[0013] In some embodiments, the conductive structure is connected to ground.

[0014] In some embodiments, the semiconductor structure further includes: a plurality of word lines, each of the word lines extending along a third direction, the plurality of word lines arranged along a second direction, each of the word lines corresponding to one of the active pillar columns, each of the word lines covering a plurality of the channel regions in the corresponding active pillar column; and a plurality of bit lines, each of the bit lines extending along the second direction, the plurality of bit lines arranged along a third direction, each of the bit lines corresponding to one of the active pillar rows, each of the bit lines electrically connected to a plurality of the first doping regions in the corresponding active pillar row.

[0015] In some embodiments, the semiconductor structure further includes a plurality of word lines, each of the word lines extending along a second direction, the plurality of word lines arranged along a third direction, each of the word lines corresponding to one of the active pillar rows, each of the word lines covering a plurality of channel regions in the corresponding active pillar row, and a plurality of bit lines, each of the bit lines extending along the third direction, the plurality of bit lines arranged along the second direction, each of the bit lines electrically connected to a plurality of first doping regions in the corresponding active pillar row.

[0016] In some embodiments, the word lines surround the corresponding channel regions.

[0017] In some embodiments, the word lines cover one sidewall of the corresponding channel region.

[0018] In some embodiments, the word lines include a first sublayer and a second sublayer opposite to each other, the first sublayer and the second sublayer respectively covering two opposing sidewalls of the corresponding channel region.

[0019] In some embodiments, the bit lines surround the corresponding first doped regions.

[0020] In some embodiments, the bit line includes a plurality of sub-portions, the sub-portions being stacked in alternating fashion with the first doping regions in one of the active pillar columns along a third direction. Effect of the Invention

[0021] The semiconductor structure provided by the embodiment of the present invention includes a substrate and an active pillar located on the substrate, the active pillar extends along a first direction, the first direction is parallel to a substrate plane, the active pillar includes a body region extending along the first direction and a peripheral region surrounding the body region, the peripheral region includes a channel region, the doping ion type of the channel region and the doping ion type of the body region are the same, and the doping concentration of the channel region is greater than the doping concentration of the body region. The active pillar provided by the embodiment of the present invention includes a body region and a peripheral region surrounding the body region, the doping concentration of the body region is less than the doping concentration of the channel region, thus reducing charge accumulation in the body region and reducing the floating body effect, and further, when there is excess charge in the channel region, the charge is discharged via the body region, i.e., the body region provides a path for discharging excess charge, thereby reducing or eliminating the floating body effect and improving the performance of the semiconductor structure.

[0022] The details of one or more embodiments of the invention are set forth in the drawings and description which follow. Other features and advantages of the invention will become more apparent from the description, drawings, and claims.

[0023] In order to more clearly describe the technical solutions of the embodiments of the present invention, the following briefly introduces the drawings used in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention, and those skilled in the art can also obtain other related drawings based on these drawings without creative work. [Brief description of the drawings]

[0024] [Figure 1] 1 is a perspective view of a semiconductor structure according to an embodiment of the present invention. [Figure 2a] FIG. 2 is a perspective view of an active pillar according to an embodiment of the present invention. [Figure 2b] FIG. 2b is a schematic diagram of a cross-sectional structure taken along line AA' in FIG. 2a. [Figure 2c] FIG. 2b is a schematic diagram of a cross-sectional structure taken along line BB' in FIG. 2a. [Diagram 3] FIG. 2 illustrates another example of a perspective view of a semiconductor structure according to an embodiment of the present invention. [Figure 4] FIG. 2 illustrates another example of a perspective view of a semiconductor structure according to an embodiment of the present invention. [Diagram 5] FIG. 2 illustrates another example of a perspective view of a semiconductor structure according to an embodiment of the present invention. [Figure 6] FIG. 2 illustrates another example of a perspective view of a semiconductor structure according to an embodiment of the present invention. [Figure 7] FIG. 2 illustrates another example of a perspective view of a semiconductor structure according to an embodiment of the present invention. [Figure 8] FIG. 2 illustrates another example of a perspective view of a semiconductor structure according to an embodiment of the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0025] In the following, exemplary embodiments disclosed by the present invention will be described in more detail with reference to the drawings. Although exemplary embodiments of the present invention are shown in the drawings, it should be understood that the present invention can be implemented in various forms and should not be limited to the specific embodiments described herein. Rather, these embodiments are provided so that the present invention may be more fully understood and the scope of the present invention may be fully conveyed to those skilled in the art.

[0026] In the following description, many specific details are given to provide a more complete understanding of the present invention. However, it is clear to those skilled in the art that the present invention can be implemented without one or more of these details. In another example, in order to avoid confusion with the present invention, some technical features well known in the art are not described, that is, this specification does not describe all the features of the actual embodiment, and does not describe well-known functions and structures in detail.

[0027] In the drawings, sizes of layers, regions, elements, as well as their relative sizes may be exaggerated for clarity. Like reference numbers refer to like elements throughout.

[0028] When an element or layer is referred to as being "on...", "adjacent to...", "connected" or "coupled" to another element or layer, it is understood that it may be directly on, directly adjacent to, directly connected or coupled to the other element or layer, or that there may be intervening elements or layers. Conversely, when a reference is made to being "directly on...", "directly adjacent to...", "directly connected to" or "directly coupled" to another element or layer, there are no intervening elements or layers. Terms such as first, second, third, etc. may be used to describe various elements, components, regions, layers and / or sections, but it is understood that these elements, components, regions, layers and / or sections are not limited by these terms. These terms are used only to distinguish one element, component, region, layer, or section from another element, component, region, layer, or section. Thus, a first element, component, region, layer, or section discussed below could be referred to as a second element, component, region, layer, or section without departing from the teachings of the present invention. However, the description of a second element, component, region, layer or section does not imply that the first element, component, region, layer or section is necessarily present in the invention.

[0029] Spatial relationship terms such as "under...", "lower of...", "lower", "below...", "above...", "over" and the like may be used herein to describe the relationship of one illustrated element or feature to another element or feature for convenience of description. It should be understood that the spatial relationship terms are intended to encompass different orientations of the device in use and operation in addition to the orientation depicted. For example, the device in the drawings may be turned over, and then an orientation of an element or feature described as "under" or "below" or "below" other elements or features would be "above" the other elements or features. Thus, the exemplary terms "under..." and "under..." can encompass both an orientation of above and below. The device may be otherwise oriented (rotated 90 degrees or other orientations) and the spatial descriptions used herein interpreted accordingly.

[0030] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the present invention. As used herein, the singular forms "a", "one" and "the" are intended to include the plural forms unless the context clearly indicates otherwise. Additionally, the terms "comprising" and / or "comprising" as used herein determine the presence of the stated features, integers, steps, operations, elements and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components and / or groups. As used herein, the term "and / or" includes any and all combinations of the associated listed items.

[0031] A semiconductor structure such as a three-dimensional dynamic random access memory (3D DRAM), particularly a 3D DRAM including a multilayer horizontal cell (MHC), typically includes a plurality of transistors stacked on top of each other on a substrate, the plurality of transistors including a channel region located in a middle region and source / drain doping regions located at both ends, the doping ion type of the channel region and the doping ion type of the source / drain doping regions being different.

[0032] However, since the transistor is floating on the substrate, charges are easily accumulated in the channel region of the transistor, and the charges accumulated in the channel region cannot be released due to the different doping ion type between the channel region and the source / drain doping region, which causes the floating body effect, and further causes the warping effect, parasitic bipolar transistor effect, threshold voltage shift, etc., which affect the performance of the semiconductor structure.

[0033] Based on this, the following technical solutions are proposed in the embodiments of the present invention. The specific embodiments of the present invention will be described in detail below with reference to the drawings. When describing the embodiments of the present invention in detail, for convenience of description, the schematic diagrams are not partially enlarged according to a general scale, and the schematic diagrams are merely examples and do not limit the protection scope of the present invention.

[0034] Fig. 1 is a perspective view of a semiconductor structure according to an embodiment of the present invention, Fig. 2a is a perspective view of an active pillar according to an embodiment of the present invention, Fig. 2b is a schematic view of a cross-sectional structure taken along line A-A' in Fig. 2a, Fig. 2c is a schematic view of a cross-sectional structure taken along line B-B' in Fig. 2a, and Figs. 3 to 8 are diagrams showing another example of a perspective view of a semiconductor structure according to an embodiment of the present invention. Hereinafter, the semiconductor structure provided by the embodiment of the present invention will be further described with reference to Figs. 1 to 8.

[0035] As shown in FIG. 1, the semiconductor structure includes a substrate 10 and an active pillar 11 located on the upper part of the substrate 10, the active pillar 11 extending along a first direction, the first direction being parallel to a plane of the substrate 10; as shown in FIGS. 2a-2b, the active pillar 11 includes a body region 12 extending along a first direction and a peripheral region 13 surrounding the body region 12, the peripheral region 13 includes a channel region 132, the doping ion type of the channel region 132 and the doping ion type of the body region 12 are the same, and the doping concentration of the channel region 132 is greater than the doping concentration of the body region 12.

[0036] In actual operation, the semiconductor structure provided by the embodiments of the present invention may be, but is not limited to, a three-dimensional dynamic random access memory (3D DRAM), and the semiconductor device may also be any semiconductor device with floating transistors. The substrate may be a semiconductor substrate and may include at least one elemental semiconductor material (such as a silicon (Si) substrate, a germanium (Ge) substrate, etc.), at least one III-V compound semiconductor material, at least one II-VI compound semiconductor material, at least one organic semiconductor material, or other semiconductor materials known in the art. In one particular embodiment, the substrate is a silicon substrate, which may be doped or undoped.

[0037] The active pillar provided by the embodiment of the present invention includes a body region and a peripheral region surrounding the body region, and the doping concentration of the body region is less than the doping concentration of the channel region, so that the accumulation of charges in the body region can be reduced and the floating body effect can be mitigated; further, when there is excess charge in the channel region, the charge can be discharged via the body region, i.e., the body region provides a path for discharging the excess charge, thereby reducing or eliminating the floating body effect and improving the performance of the semiconductor structure.

[0038] Here, if the ratio of the doping concentration of the channel region 132 to the doping concentration of the body region 12 is too low, the charge accumulation in the body region 12 is still large, and the effect of mitigating the floating body effect is not obvious. If the ratio of the doping concentration of the channel region 132 to the doping concentration of the body region 12 is too high, the effect of releasing excess charge from the body region 12 becomes insufficient. Therefore, in some embodiments, the ratio of the doping concentration of the channel region 132 to the doping concentration of the body region 12 is 10:1 or more, specifically, for example, 13:1, 15:1, 19:1, 22:1, etc. Furthermore, in some other embodiments, the ratio of the doping concentration of the channel region 132 to the doping concentration of the body region 12 is 25:1 or less.

[0039] As shown in FIG. 2c, in one embodiment, the body region 12 includes an inner layer 12a extending along a first direction and an outer layer 12b surrounding the inner layer 12a, and the doping concentration of the inner layer 12a is greater than the doping concentration of the outer layer 12b. In this way, on the one hand, the outer layer 12b has a lower doping concentration, so that the amount of charge accumulated in the channel region 132 can be reduced, thereby reducing the floating body effect, and on the other hand, the inner layer 12a has a higher doping concentration, so that the discharge effect of the charge accumulated in the channel region 132 can be effectively improved. In one particular embodiment, the ratio of the doping concentration of the inner layer 12a to the doping concentration of the outer layer 12b is in the range of 5 to 10, specifically, for example, 6, 8, 9, etc. In some embodiments, the ratio of the radial extension length of the inner layer 12a to the radial extension length of the body region 12 is less than 0.5, thus ensuring that the outer layer 12b, which has a low doping concentration, has a sufficient thickness to timely release the charge accumulated in the channel region 132.

[0040] In another embodiment, the doping concentration of the body region 12 gradually decreases from the center to the periphery along the radial direction of the active pillar 11. In practical operation, the gradually decreasing manner is preferably an exponentially gradually decreasing manner. In this way, on the one hand, the lower concentration part in the body region can reduce the amount of charge accumulated in the body region 12, thereby reducing the floating body effect, and on the other hand, the region with a larger doping concentration in the body region 12 can effectively improve the release effect of the charge accumulated in the channel region 132.

[0041] In some other embodiments, the body region 12 includes a first layer and a second layer that are stacked alternately in a radial direction of the active pillar 11, and the doping concentrations of the first layer and the second layer are different (not shown). It should be understood that the body region 12 includes at least two first layers and two second layers, and the doping concentrations of the first layer and the second layer are both smaller than the doping concentration of the channel region 132. In some specific embodiments, the ratio of the doping concentration of the first layer to the doping concentration of the second layer is in the range of 2 to 5, for example, 2.5, 3, 4.5, etc. In this way, by arranging the high doping concentration layer and the low doping concentration layer alternately, the amount of charge stored in the body region 12 can be reduced, thereby better reducing the floating body effect.

[0042] In one embodiment, as shown in Figures 1 and 2a to 2c, the peripheral region 13 further includes a first doping region 131 and a second doping region 133, the first doping region 131, the channel region 132, and the second doping region 133 are sequentially arranged along a first direction, and the body region 12 further includes an extension region 121 that is not surrounded by the peripheral region 13, and the extension region 121 is adjacent to the first doping region 131.

[0043] In some embodiments, the materials of the body region 12 and the peripheral region 13 are the same, and the materials of the body region 12 and the peripheral region 13 may be one or more selected from silicon, indium oxide, tin oxide, indium zinc oxide, tin zinc oxide, aluminum zinc oxide, indium gallium oxide, indium gallium zinc oxide, indium aluminum zinc oxide, indium tin zinc oxide, tin gallium zinc oxide compounds, aluminum gallium zinc oxide, tin aluminum zinc oxide, and may be silicon, for example. In other embodiments, the materials of the body region 12 and the peripheral region 13 are different. For example, the material of the body region 12 may be one or more selected from silicon or germanium, and the material of the peripheral region 13 may be one or more selected from indium oxide, tin oxide, indium zinc oxide, tin zinc oxide, aluminum zinc oxide, indium gallium oxide, indium aluminum zinc oxide, indium tin zinc oxide, tin gallium zinc oxide, aluminum gallium zinc oxide, and tin aluminum zinc oxide. Furthermore, the material of the extension region 121 and the portion of the body region 12 surrounded by the peripheral region 13 may be the same or different. In some particular embodiments, the doping concentration of the extension region 121 is different from the doping concentration of the body region 12, e.g., the average doping concentration of the extension region 121 is greater than the average doping concentration of the body region 12, thus improving the efficiency of discharging charges stored in the body region 12.

[0044] In one embodiment, as shown in Figures 2a and 2b, the radial size of the extension region 121 is smaller than the radial size of the active pillar 11, in other words, the projection of the extension region 121 along the first direction is within the projection of the active pillar 11 along the first direction, and the extension region 121 does not contact the first doping region 131.

[0045] In an actual manufacturing process, the above active pillar 11 can be formed in the following manner: first, expose the initial active pillar 11 to a gas-phase doping environment so as to dope the active pillar 11 entirely with a first type of doping ion; then, form a first mask layer surrounding the active pillar 11; etch the first mask layer to expose one end of the active pillar; etch the end to form an extension region whose radial size is smaller than that of the active pillar 11; then, remove the first mask layer to form a second mask layer surrounding the active pillar 11; etch the second mask layer to expose an area on the active pillar 11 where a channel region will be formed; A channel region 132 having a higher doping concentration is formed on the active pillar 11 by exposing the region where the channel region is to be formed to a gas phase doping environment and controlling the doping parameters, and then the second mask layer is removed to form a third mask layer surrounding the active pillar 11, and the third mask layer is etched to expose the region where the first doping region 131 and the second doping region 133 are to be formed to be exposed to the gas phase doping environment, and the first doping region 131 and the second doping region 133 having a second doping type are formed by controlling the doping parameters. The first type of doping ions may be P-type doping ions and the second type of doping ions may be N-type doping ions, or the first type of doping ions may be N-type doping ions and the second type of doping ions may be P-type doping ions. The body region having different doping concentration regions mentioned above may be formed by multiple doping processes, which will not be described again in detail here.

[0046] However, without being limited thereto, in another embodiment, the extension region 121 and the active pillar 11 have the same radial size, in other words, the extension region 121 along the first direction overlaps with the projection of the active pillar 11 along the first direction. Furthermore, one end of the extension region 121 close to the first doping region 131 can also contact the first doping region 131. By setting the extension region 121 and the active pillar 11 to have the same radial size, compared with a technical solution in which the radial size of the extension region 121 is smaller, it is permitted not to etch the extension region 121 when manufacturing the active pillar 11, which simplifies the process and reduces the cost.

[0047] In some embodiments, the number of active pillars 11 may be one. In some other embodiments, as shown in FIG. 1, the number of active pillars 11 is multiple and arranged in an array. Specifically, as shown in FIG. 1, the number of active pillars 11 is multiple, and the multiple active pillars 11 are arranged in multiple active pillar rows M and multiple active pillar columns N, the active pillar rows M extending along a second direction, the second direction intersecting with the first direction and parallel to the plane of the substrate 10, and the active pillar columns N extending along a third direction, the third direction being perpendicular to the plane of the substrate 10. In some embodiments, the first direction and the second direction are perpendicular. However, this is not limited thereto, and the first direction may also intersect the second direction obliquely.

[0048] 1, in some embodiments, the semiconductor structure further includes the conductive structure 17 extending along a third direction and electrically connected to the extension region 121, the third direction being perpendicular to the plane of the substrate 10. Here, the conductive structure 17 may be, for example, a linear structure. In some embodiments, there may be a plurality of conductive structures 17 parallel to each other, the plurality of conductive structures 17 arranged along the second direction, each conductive structure 17 extending to the substrate 10 along a third direction perpendicular to the plane of the substrate 10, each of the conductive structures 17 corresponding to one active pillar row N, and each conductive structure 17 electrically connected to the extension region 121 of the plurality of active pillars 11 in the corresponding one active pillar row N.

[0049] 3, in another embodiment, the conductive structure 17 extends along the second direction and is electrically connected to the extension region 121, the second direction intersecting the first direction and parallel to the plane of the substrate 10. Here, the conductive structure 17 may be, for example, a linear structure. In some embodiments, the conductive structure 17 may be multiple, the multiple conductive structures 17 are arranged along a third direction, each of the conductive structures 17 corresponds to one active pillar row M, and each conductive structure 17 is electrically connected to the extension region 121 of the multiple active pillars 11 in the corresponding one of the active pillar rows M.

[0050] 4, in some other embodiments, the conductive structure 17 is plate-shaped, and the conductive structure 17 is electrically connected to extension regions 121 of the multiple active pillar rows M. Specifically, the conductive structure 17 extends to the substrate 10 along the third direction, and is electrically connected to the extension regions 121 of each of the active pillars 11 in each of the active pillar rows M.

[0051] Here, the conductive structure 17 can be grounded, and thus, if there is excess charge in the channel region 132, the charge can be discharged into the body region 12 and discharged via the conductive structure 17, which is grounded, thereby further reducing or eliminating the floating body effect.

[0052] The plate-shaped conductive structure 17 can perform global discharge for all active pillars 11, and has a simple structure and high discharge efficiency. Compared with the plate-shaped conductive structure 17, the linear conductive structure 17 can perform floating body charge discharge for one row of active pillars 11 or one column of active pillars 11, so that discharge can be selectively performed for some rows or columns that require floating body charge discharge according to the actual operating conditions of each active pillar 11, thereby reducing the floating body effect and minimizing the additional impact of discharge on the operation of the device.

[0053] In actual operation, the material of the conductive structure 17 includes at least one conductive material such as polysilicon, for example, the material of the conductive structure 17 includes one or more of polysilicon, tungsten (W), copper (Cu), titanium (Ti), tantalum (Ta), titanium nitride (TiN), tantalum nitride (TaN), metal silicide, metal alloy, etc. The conductive structure 17 can be formed using a process such as chemical vapor deposition (CVD), plasma enhanced CVD (PECVD), physical vapor deposition (PVD), atomic layer deposition (ALD), plating, chemical plating, sputtering, etc.

[0054] As shown in FIG. 5 , in one embodiment, the semiconductor structure further includes a plurality of word lines 14, each of which extends along a third direction and the plurality of word lines 14 are arranged along the second direction, each of the word lines 14 corresponding to one of the active pillar rows N, each of the word lines 14 covering a plurality of the channel regions 132 in the corresponding active pillar row N, and a plurality of bit lines 16, each of which extends along the second direction and the plurality of bit lines 16 are arranged along a third direction, and each of the bit lines 16 is electrically connected to a plurality of first doping regions 131 in the corresponding active pillar row M.

[0055] However, without being limited thereto, the word lines 14 can also extend along the second direction, and the bit lines 16 can also extend along the third direction. Specifically, the semiconductor structure further includes a plurality of word lines 14, each of which extends along the second direction, the plurality of word lines 14 arranged along the third direction, each of which corresponds to one of the active pillar rows M, each of which covers a plurality of channel regions 132 in the corresponding active pillar row M, and a plurality of bit lines 16, each of which extends in the third direction, the plurality of bit lines 16 arranged along the second direction, and each of which is electrically connected to a plurality of first doping regions 131 in the corresponding active pillar row N.

[0056] As shown in Fig. 1 or Fig. 5, in one embodiment, the word line 14 surrounds the corresponding channel region 132, and the word line 14 extends along the second direction or the third direction; or as shown in Fig. 6, in some other embodiments, the word line 14 covers one sidewall of the corresponding channel region 132, and the word line 14 extends in the second direction or the third direction; or as shown in Fig. 7, in some other embodiments, the word line 14 includes a first sublayer 141 and a second sublayer 142 arranged opposite to each other, and the first sublayer 141 and the second sublayer 142 cover two opposite sidewalls of the corresponding channel region 132, respectively, and the first sublayer 141 and the second sublayer 142 extend along the second direction or the third direction. It can be understood that the first sublayer 141 and the second sublayer 142 are electrically connected to each other.

[0057] As shown in FIG. 5 or 6, in some embodiments, the bit line 16 surrounds the corresponding first doping region 131, and the bit line 16 extends along the second direction or the third direction. In some other embodiments, the bit line 16 can also cover one sidewall of the corresponding first doping region 131. However, as shown in FIG. 8, but without being limited thereto, in some other embodiments, the bit line 16 includes a plurality of sub-portions 161, and the plurality of sub-portions 161 are stacked alternately with the first doping region 131 in one of the active pillar columns N along the third direction, or the plurality of sub-portions 161 can also be arranged alternately with the first doping region 131 in one of the active pillar rows M along the second direction.

[0058] The material of the wordlines 14 and the bitlines 16 may include one or more of tungsten (W), copper (Cu), titanium (Ti), tantalum (Ta), titanium nitride (TiN), tantalum nitride (TaN), metal silicides, metal alloys, etc. The wordlines 14 and the bitlines 16 may be formed using processes such as chemical vapor deposition (CVD), plasma enhanced CVD (PECVD), physical vapor deposition (PVD), atomic layer deposition (ALD), plating, chemical plating, sputtering, etc.

[0059] In one embodiment, the semiconductor structure further includes a gate dielectric layer 15, the gate dielectric layer 15 being sandwiched between the word line 14 and the channel region 132. The material of the gate dielectric layer 15 can be a high-k material such as tantalum oxide, hafnium oxide, zirconium oxide, niobium oxide, titanium oxide, barium oxide, strontium oxide, yttrium oxide, lanthanum oxide, praseodymium oxide, or barium strontium titanate. The gate dielectric layer 15 can be formed using a process such as chemical vapor deposition (CVD), plasma-enhanced CVD (PECVD), physical vapor deposition (PVD), atomic layer deposition (ALD), etc. However, without being limited thereto, the material of the active pillar 11 can be silicon, the material of the gate dielectric layer 15 can be silicon oxide, and the gate dielectric layer 15 can be formed by a thermal oxidation process.

[0060] In some embodiments, the semiconductor material further includes a plurality of capacitor structures 18 for information storage, and the capacitor structures 18 are electrically connected to the second doped regions 133 of the active pillars 11. Specifically, the capacitor structures 18 extend along the first direction, and the capacitor structures 18 are arranged in an array along the second direction and the third direction, respectively.

[0061] In one embodiment, the capacitor structure includes a bottom electrode electrically connected to the second doping region, a dielectric layer covering the bottom electrode, and a common top electrode covering the dielectric layer and located between a plurality of the capacitor structures. In some embodiments, the bottom electrode is columnar and extends along the first direction. In other embodiments, but not limited to, the bottom electrode is a cylindrical structure, and an opening of the cylindrical structure faces the first direction.

[0062] Thus, the active pillar 11 provided by the embodiment of the present invention includes a body region 12 and a peripheral region 13 surrounding the body region 12, and the doping concentration of the body region 12 is lower than that of the channel region 132, so that the doping concentration of the body region 12 can be set to a lower doping concentration than that of the channel region 132 to reduce charge accumulation in the body region 12 and mitigate the floating body effect. Furthermore, if there is excess charge in the channel region 132, the charge can be discharged via the body region, i.e., the body region provides a path for discharging the excess charge. Furthermore, the conductive structure 17 provided by the embodiment of the present invention is grounded, and if there is excess charge in the channel region 132, the charge can be discharged to the body region 12 and discharged via the conductive structure 17 which is grounded, thereby reducing or eliminating the floating body effect.

[0063] The above are only preferred embodiments of the present invention, and are not intended to limit the scope of protection of the present invention. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principle of the present invention should all be included within the scope of protection of the present invention. [Industrial Applicability]

[0064] The active pillar provided by the embodiment of the present invention includes a body region and a peripheral region surrounding the body region, and the doping concentration of the body region is less than the doping concentration of the channel region, so that the accumulation of charges in the body region can be reduced and the floating body effect can be mitigated; further, when there is excess charge in the channel region, the charge can be discharged via the body region, i.e., the body region provides a path for discharging the excess charge, thereby reducing or eliminating the floating body effect and improving the performance of the semiconductor structure.

Claims

1. 1. A semiconductor structure comprising: a substrate and an active pillar disposed on the substrate, the active pillar extending along a first direction, the first direction being parallel to a substrate plane; the active pillar includes a body region extending along the first direction and a peripheral region surrounding the body region, the body region including an extension region not surrounded by the peripheral region, the peripheral region including a channel region, a doping ion type of the channel region and a doping ion type of the body region are the same, and a doping concentration of the channel region is greater than a doping concentration of the body region; The semiconductor structure further includes a conductive structure electrically connected to the extension region and grounded.

2. The body region includes an inner layer extending along the first direction and an outer layer surrounding the inner layer, and a doping concentration of the inner layer is greater than a doping concentration of the outer layer. The semiconductor structure of claim 1 .

3. the doping concentration of the body region gradually decreases from the center to the periphery along the radial direction of the active pillar; The semiconductor structure of claim 2 .

4. the peripheral region further includes a first doping region and a second doping region, the first doping region, the channel region, and the second doping region are sequentially arranged along the first direction, and the extension region is adjacent to the first doping region; The semiconductor structure of claim 1 .

5. the conductive structures extend along a second direction, the second direction intersecting the first direction and parallel to the substrate plane; The semiconductor structure of claim 4.

6. the conductive structures extend along a third direction, the third direction being perpendicular to a plane of the substrate; The semiconductor structure of claim 4.

7. the number of the active pillars is more than one, the active pillars are arranged into a plurality of active pillar rows and a plurality of active pillar columns, the active pillar rows extend along a second direction, the second direction intersects with the first direction and is parallel to the substrate plane, the active pillar columns extend along a third direction, the third direction is a direction perpendicular to the substrate plane; The semiconductor structure of claim 1 .

8. The conductive structure is plate-shaped, and the conductive structure is electrically connected to extension regions of a plurality of the active pillar rows.

8. The semiconductor structure of claim 7.

9. The semiconductor structure further comprises: a plurality of word lines, each of the word lines extending along the third direction, the plurality of word lines arranged along the second direction, each of the word lines corresponding to one of the active pillar columns, and each of the word lines covering a plurality of the channel regions in the corresponding active pillar column; a plurality of bit lines, each of the bit lines extending along the second direction, the plurality of bit lines arranged along the third direction, each of the bit lines corresponding to one of the active pillar rows, each of the bit lines electrically connected to a plurality of first doping regions in the corresponding active pillar row; 8. The semiconductor structure of claim 7.

10. The semiconductor structure further comprises: a plurality of word lines, each of the word lines extending along the second direction, the plurality of word lines arranged along the third direction, each of the word lines corresponding to one of the active pillar rows, and each of the word lines covering a plurality of the channel regions in the corresponding active pillar row; a plurality of bit lines, each of the bit lines extending along the third direction, the plurality of bit lines arranged along the second direction, each of the bit lines electrically connected to a plurality of first doping regions in a corresponding one of the active pillar columns; 8. The semiconductor structure of claim 7.

11. The word lines surround the corresponding channel regions.

11. A semiconductor structure according to claim 9 or 10.

12. the word lines include a first sublayer and a second sublayer opposed to each other, the first sublayer and the second sublayer covering two opposed sidewalls of the corresponding channel region, respectively; 11. A semiconductor structure according to claim 9 or 10.

13. The bit lines surround the corresponding first doping regions.

11. A semiconductor structure according to claim 9 or 10.

14. the bit line includes a plurality of sub-portions, the plurality of sub-portions being stacked alternately with the first doping region in one of the active pillar columns along the third direction; 11. The semiconductor structure of claim 10.

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