Low power, high bandwidth, low latency data bus

Abstract

To provide a system and method enabling multi-drop high speed bi-directional communications using a terminated transmission line.SOLUTION: An audio system 100 includes: a host device coupled to a differential multi-drop bus for digital communication using a communication protocol with multiple timeslots; and a connection device 130 coupled to the multi-drop bus and transmitting / receiving digital communications with the host device 110 in accordance with the communication protocol. The multi-drop bus is a differential data bus which is terminated at different voltage levels on two lines and facilitates a low power operation and reduced electromagnetic interference. Power consumption may be reduced by using a signaling rate that is greater than a required signaling rate and leaving the multi-drop bus idle for a portion of every cycle.SELECTED DRAWING: Figure 1A

Description

[Technical field]

[0001] This application is a continuation of U.S. Provisional Patent Application No. 62 / 678,999, filed May 31, 2018. 3 and U.S. Provisional Patent Application No. 62 / 721,412, filed August 22, 2018. No. 6,313,635, filed on Dec. 13, 2003, and claims priority from and the benefit of which, each of which is hereby incorporated by reference. The entire contents of which are incorporated herein by reference.

[0002] This application is a continuation of U.S. patent application Ser. No. 16 / 125,617, filed Sep. 7, 2018. This application is a continuation-in-part of US Pat. No. 6,399,433, filed on Oct. 13, 2003, which is hereby incorporated by reference in its entirety. Be absorbed.

[0003] This application relates generally to data communications, and more specifically to, for example, The present invention relates to a system and method for communication of digital data. [Background technology]

[0004] Various interfaces for transmitting and receiving digital data between electronic devices are included in this technology. However, the existing interfaces are not compatible with many modern systems. However, it does not meet all the requirements of the system. It must be reliable, have good signal quality, and be low cost. It provides high bandwidth communication for a variety of connected devices while meeting the demands of low power devices. It is often desirable to enable signal transmission. For example, dynamic noise cancellation Active Noise Cancellation (ANC) headsets can require complex and expensive equipment. High bandwidth communication between the set and the host device reduces noise on the host device. Cancellation may be desirable for certain applications such as signal processing. There is.

[0005] In some approaches, high-bandwidth communications are transmitted over a digital communications link that terminates at the receiver. These approaches provide satisfactory signal integrity for certain configurations. In some cases, the receiver may provide high reliability but at the same time, low power consumption is required. Fixed power consumption at the termination may be undesirable. Many are not optimized for low latency data transfer because data communication is digital. This is because it may take an entire sample period to transfer over the digital communications link. Some systems often support connections to multiple devices or require a specific length Additional features such as supporting a physical link that meets the requirements (e.g., 1 to 2 meters) Additional requirements include communication between connected devices, supporting different device types, and ,Flexibility to adapt, and data is transported in a serialized format. Supporting various data transfer implementations, including bulk data transfer, in the system This can happen.

[0006] In view of the above, the present technology provides an improved digital data communication system and method. There is a continuing demand for Summary of the Invention

[0007] The present disclosure relates to a method for improving digital data communication between physically connected devices. In various embodiments, the present invention provides a system and method for addressing the need in data The bus system and method are for communicating digital audio data according to a first communication protocol. The device controller is connected to a first interface for The controller is a master bus that controls the multi-drop bus according to the second communication protocol. The first slave device is connected to the multidrop bus. and transmits digital audio data to the device controller according to a second communication protocol. Each transmission line is configured to transmit and receive signals. The signaling is terminated by another device attached to the other end. Reflections due to impedance mismatches caused by the inclusion of switching nodes in multi-drop devices The second communication protocol is controlled so as to be compatible with various speeds and to enable high-speed signal transmission. Although it supports multiple audio data rates using a fixed frame format, good.

[0008] In some embodiments, a first slave device and a second slave device connected to a bus. A time-series signal is a time-series signal that is timed so that the transmitted message is sent as a series of forward or backward propagating waves. This allows for multi-drop high speed bidirectional operation using terminated transmission lines. In one embodiment, differential signaling is used for communication, and common mode To reduce interference, one line is terminated to a logic high and one line is terminated to a logic low. In one embodiment, differential signaling is used to reduce EMI and data is transmitted When no signal is being transmitted and the bus is free, the bus goes high or low depending on the termination level. The termination of each transmission line is handled by setting the output driver to the same value. This allows for reduced power consumption by the transmission endpoints.

[0009] In some embodiments, intermediate nodes on a transmission line cause short interruptions in the propagating wave. and the stubs and / or transmission line disruptions are longer than the shortest wavelength used for signal transmission. The requirement is that the length of the transmission line must be extremely short (e.g., less than 1 / 50 of the shortest wavelength). Provided that the output termination level is equal to the final output state level (quiescent level), The power consumption is increased by a signal transmission rate higher than the minimum required signal transmission rate for each clock cycle. This is reduced by keeping the bus idle for part of each frame or each cycle, which reduces the The power required for signal transmission is reduced by capacitive or inductive drop regulation. This may be achieved by a regulator, thereby minimizing power loss in the regulator. By reducing the transmission voltage on the bus, power consumption can be further limited, Dynamic signaling ensures that the system is robust against external noise and EMI while still providing low voltage signals. It may be used to enable signal transmission.

[0010] In some embodiments, the delay between components charges the bus to a known value; To ensure that the bus is floating and not terminated during the measurement, Disables the drivers at the beginning and end to prevent devices from changing levels on the bus. The delay is measured by waiting for the next 100ms and measuring the transition delay. The drivers at each end of the transmission line are By allowing the driver to change the current bus state, the components connected to the bus can The current bus state is set by the controller. In a given time window that allows counting of devices, one or more The device controller may also change the transmission line to an opposite value. A first clock signal for synchronizing communication according to one communication protocol and a second clock signal for synchronizing communication according to a second communication protocol The second clock signal is used to synchronize communications by the The clock signal may further include a phase-locked loop (PLL) or a delay-locked loop (DLC) that provides a good.

[0011] In various embodiments, the second communication protocol uses a fixed frame structure while allowing different In some embodiments, the data ports or each of the The data following the phase signal is modulated by a high frequency carrier or a pseudorandom number generator, thereby To reduce current modulation in the audio bandwidth for the reduction of interference in audio systems. The device controller, the first slave device and the second slave device In some embodiments, the device may include a microphone or other audio listening device. To achieve this, the termination at the end of the transmission line is temporarily disabled during transmitter activation. can be.

[0012] In various embodiments, a method includes communicating with a first interface according to a first communication protocol. and transmitting digital audio data through the device according to a second communication protocol. Controlling a multi-drop bus using a controller and connecting to the multi-drop bus and communicating with the first slave device according to a second communication protocol. It allows the transmission and reception of digital voice data using a controller and allows arbitrary signal termination. and setting the transmitters at each end of the transmission line to a known state in order to In some embodiments, the second communication protocol uses a fixed frame format. Multiple audio data rates may be supported.

[0013] The method further comprises using a phase locked or delay locked loop to synchronize the first communication protocol. a first clock signal for synchronizing communication according to the second communication protocol; and a third clock signal used for processing audio data. In some embodiments, the second communication protocol may include a fixed It uses a frame structure to support different communication bandwidths. Dithering may be added to the PLL or DLL to reduce radiated EMI. Data transmitted over the network is encoded using a 10-bit ... The signal may be scrambled into a single bit and descrambled upon reception.

[0014] The scope of the invention is defined by the claims, the disclosure of which is hereby incorporated by reference. A more complete understanding of the embodiments of the invention may be obtained by reference to one or more of the following embodiments, which are incorporated herein by reference in their entirety. Additional advantages will be realized and afforded to those skilled in the art upon consideration of the detailed description of the embodiments. In the following, reference is made to the attached sheets of drawings which will first be briefly described. [Brief description of the drawings]

[0015] [Figure 1A] FIG. 1A is an exemplary bus interface system according to one or more embodiments.

[0016] [Figure 1B] FIG. 1B illustrates an exemplary headset according to one or more embodiments. [Figure 1C] FIG. 1C illustrates an exemplary headset according to one or more embodiments.

[0017] [Figure 2A] FIG. 2A is an exemplary bus interface system according to one or more embodiments.

[0018] [Figure 2B] FIG. 2B illustrates an exemplary headset according to one or more embodiments.

[0019] [Diagram 3] FIG. 3 illustrates an example timing sequence in accordance with one or more embodiments.

[0020] [Figure 4] FIG. 4 illustrates an exemplary phase-locked loop (PLL) with time gating in accordance with one or more embodiments.

[0021] [Figure 5A] FIG. 5A illustrates an example clock solution according to one or more embodiments. [Figure 5B] FIG. 5B illustrates an exemplary clock solution according to one or more embodiments.

[0022] [Figure 6A] FIG. 6A illustrates an example clock solution according to one or more embodiments. [Figure 6B] FIG. 6B illustrates an example clock solution according to one or more embodiments.

[0023] [Figure 7] FIG. 7 illustrates an example clock solution according to one or more embodiments.

[0024] [Figure 8A] FIG. 8A illustrates an example clock solution according to one or more embodiments. [Figure 8B]FIG. 8B illustrates an example clock solution according to one or more embodiments.

[0025] [Figure 9A] FIG. 9A illustrates an example frame structure according to one or more embodiments. [Figure 9B] FIG. 9B illustrates an example frame structure according to one or more embodiments. [Figure 9C] FIG. 9C illustrates an example frame structure according to one or more embodiments. [Figure 9D] FIG. 9D illustrates an example frame structure according to one or more embodiments. [Figure 9E] FIG. 9E illustrates an example frame structure according to one or more embodiments. [Figure 9F] FIG. 9F illustrates an exemplary frame structure according to one or more embodiments.

[0026] [Figure 10A] FIG. 10A illustrates a method for delay measurement of connected devices according to one or more embodiments.

[0027] [Figure 10B] FIG. 10B illustrates a method for counting connected devices according to one or more embodiments.

[0028] [Figure 11A] FIG. 11A illustrates an exemplary bidirectional communication arrangement according to one or more embodiments.

[0029] [Figure 11B] FIG. 11B illustrates an example of differential signaling, synchronization, and digital data communication in accordance with one or more embodiments.

[0030] [Figure 11C] FIG. 11C illustrates an example of a differential signaling system according to one or more embodiments.

[0031] [Figure 11D] FIG. 11D illustrates another example of a differential signaling system in accordance with one or more embodiments.

[0032] [Figure 12] FIG. 12 illustrates an example PLL locking sequence in accordance with one or more embodiments.

[0033] [Figure 13] FIG. 13 is an example PLL sync enable circuit according to one or more embodiments.

[0034] [Figure 14] FIG. 14 illustrates example synchronization signaling in accordance with one or more embodiments.

[0035] [Figure 15] FIG. 15 illustrates an exemplary operation of a digital data communications system in accordance with one or more embodiments.

[0036] [Figure 16A] FIG. 16A illustrates an exemplary frame structure that may be used in one or more embodiments. [Figure 16B] FIG. 16B illustrates an exemplary frame structure that may be used in one or more embodiments. [Figure 16C] FIG. 16C illustrates an exemplary frame structure that may be used in one or more embodiments.

[0037] [Figure 17] FIG. 17 illustrates an example frame according to one or more embodiments.

[0038] [Figure 18A] FIG. 18A illustrates an example frame structure for read and write operations involving bulk transfers in accordance with one or more embodiments. [Figure 18B]FIG. 18B illustrates an example frame structure for read and write operations involving bulk transfers in accordance with one or more embodiments. [Figure 18C] FIG. 18C illustrates an example frame structure for read and write operations involving bulk transfers in accordance with one or more embodiments.

[0039] [Figure 19] FIG. 19 illustrates an exemplary frame synchronization algorithm in accordance with one or more embodiments.

[0040] The included figures are for illustrative purposes and provide context sensitive audio processing. The disclosed methods and systems are merely provided as examples of possible systems and methods for These drawings are intended to serve as a guide to the present disclosure in no way departing from the spirit and scope of the present disclosure. Any modifications in form and details are not intended to be construed as limiting the scope of the invention to those disclosed by those skilled in the art. It is not something to do. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0041] The present disclosure addresses the need in the art for improved digital data communication between electronic devices. In various embodiments, a master device connected via a physical data link Low power, high bandwidth, multi-drop and / or low power between a single device and one or more slave devices A system and method for providing latency communication is disclosed. Combined bandwidth and long link length, low and more controlled latency, point-to-point connections Plus support for multi-drop topologies and easy inter-device synchronization It offers many advantages over previous systems and methods.

[0042] In various embodiments, a bit may be transmitted early and then the remainder of the clock cycle or Through the process of leaving the bus quiesced for the remainder of the frame duration, the terminated device Differential data buses terminated with opposite polarity provide low power operation. The present disclosure also provides a method for manufacturing a cable having an unterminated end, which facilitates operation and low electromagnetic interference (EMI). This facilitates low power consumption in configurations where high frequency clocks or timing elements are , used to ensure that data is available for reception in one or more time units; This allows for high signal-to-noise ratio (SNR) and high resolution without modifying the physical system. For example, multiple time slots allow for the selection of bandwidth and signal interferometry. may be used to define symbols to allow compromise between stomach.

[0043] The present disclosure further provides a multi-band 1000 MHz ... For a drop-drop differential long line bus, use the end transmitter as the actual termination, and reverse termination The algorithm for synchronizing connected devices is The aim is to find a time slot that does not change according to the expected pattern and to ensure a safe synchronization. This involves systematically eliminating all invalid positions in order to The implementation of this system makes it possible to guarantee safe synchronization even with arbitrary random data. The search will be terminated first when only a single synchronization candidate remains, and thus Therefore, any random data will not cause false synchronization. Also, it is independent of bus traffic. To facilitate transfers between memory modules, an algorithm for bulk data transfers has been developed. In some embodiments, EMI reduction is achieved by de-rating the system clock. This is achieved by adding interference to the voice band, which is then filtered out by the data symbols before transmission. By scrambling it and then descrambling the value after it is received (to get the original value) These and other features and advantages of the present disclosure may be understood by reference to the following disclosure: will be understood.

[0044] Various embodiments are disclosed herein. In one embodiment, a system includes: A multi-threaded digital communication protocol having a time slot for a master device coupled to the multi-drop bus; a first digital communication device configured to receive and transmit digital communications with a master device according to a protocol; At least one of the time slots is dynamically bandwidth and and / or communication settings for the first slave device to optimize signal integrity A multi-drop bus is a bus that uses different voltage levels on the two signal lines. A differential data bus terminated in a 10-pin casing, facilitating low-power operation and low electromagnetic interference. In one aspect, the multi-drop bus is a multi-slave bus using edge transmitters. A multi-drop differential long line length bus is configured to receive multiple devices. and a multi-drop bus that operates at a signal transmission rate higher than the signal transmission rate of the multi-drop bus that is being By pausing for part of the cycle, power consumption is reduced.

[0045] In one embodiment, the system is further configured to detect changes that do not follow a fixed expected pattern. Including identifying time slots and eliminating invalid positions for secure synchronization , configured to synchronize two or more connected devices. To facilitate bulk data transfer independent of the digital communications traffic on the drop bus. In another embodiment, a first slave device and a second slave device connected to the bus are The probe device is designed so that the transmitted message is sent as a series of forward and backward propagating waves. This allows for multi-drop high speed operation using terminated transmission lines. Intermediate nodes on a multi-drop bus create short interruptions in the propagating waves. The system is connected to a multi-drop bus so that any disruption to the transmission line caused by an intermediate node The physical length of the optical fiber is shorter than the shortest wavelength used for signal transmission.

[0046] In some embodiments, the delay between devices is determined by charging the bus to a known value and The drivers at the beginning and end of the bus are left floating and unterminated during the measurement. By enabling the bus and waiting for a device to change level on the bus and measuring the transition delay. The PLL or DLL is between the master device and the first slave device. The system timing is used to obtain a lock on the master device and / or the 1 The frequency is derived from a fractional PLL in the slave device and is generated by a pseudorandom number generator. The output of the PLL is dithered by adding it to a fractional adder, which reduces EMI. In one embodiment, a pseudorandom number generator scrambles the output of one or more data ports. This reduces EMI by whitening the output spectrum. The PLL and / or DLL can be configured to lock the PLL to random bus traffic. It is enabled during the initial lock of the PLL to avoid There may be a time gate that only allows it through.

[0047] In various embodiments, a method uses a communication protocol comprising a plurality of time slots. providing a master device coupled to a multi-drop bus for digital communications over a network; and coupling a first slave device to the multi-drop bus and communicating the first slave device in accordance with the communication protocol. The slave device is configured to send and receive digital communications with the master device using the and dynamically adjusting bandwidth and / or signal intensity using at least one of the time slots. and defining communication settings of the first slave device to optimize reliability. The method further comprises: forming the multi-drop data bus into a reverse polarity terminated differential data bus. This may include operating the device as a single unit, facilitating low power operation and low electromagnetic interference. and / or identify time slots that do not change according to an expected fixed pattern; Safely sync two or more connected devices, including erasing invalid positions In some embodiments of the method, a first slave device and a second slave device connected to the bus may be The two slave devices communicate with each other in a way that the transmitted message is transmitted as a series of forward and backward propagating waves. This allows for multi-dropout using terminated transmission lines. This enables high-speed two-way communication.

[0048] Referring to FIG. 1A, an exemplary audio system 100 is shown in accordance with one or more embodiments of the present disclosure. The system 100 includes a host device 110 and at least one connected device 13. The host device 110 transmits audio data to the connected device 130. or any electronic device configured to receive from the connection device 130, e.g. , smartphones, tablet computers, laptop computers, automotive Audio interfaces, audio conferencing systems, audio playback systems or other electronic devices. The connected device 130 may transmit, receive, and / or process audio data. The device may include one or more electronic devices configured to The device may include a headset, loudspeaker, or audio processing system. Although discussed with reference to voice communications, the systems and methods described herein are not intended to be limiting of the scope of the present disclosure. It will be appreciated that other electronic devices and data types may be implemented in accordance with the present invention.

[0049] In the illustrated embodiment, the host device 110 includes an application processor 112, an audio codec 114, and an interface component 116. The application processor 112 controls the host device 110 and the connected device 13. 0. The audio codec 114 controls digital audio data communication between the host device and the The audio input processing and / or audio output processing are performed according to the request of the interface 110. The component 116 is connected to the host device 11 via a cable 120 and a compatible connector. 0 and the connecting device 130. The interface component 116 has ports that accept connectors and corresponding and an interface controller for implementing the communication protocol. In the embodiments described herein, a Universal Serial Bus (USB) connector and However, other cables, connectors and protocols may be used. It will be appreciated that may be used in accordance with the embodiments described herein.

[0050] In one or more embodiments, the application processor 112 may be, for example, a SoundWire standard Multi-wire with clock and data lines as specified by the USB standard or USB A bus protocol is used to facilitate communication between the host device 110 and the connected device 130. The application processor 112 may be connected to a SoundWire or other digital interface. A master-slave voice codec is used to communicate with the voice interface. The audio codec 114 may communicate with the two interface processors. The application processor 112 and the voice processor 112 communicate with each other while converting voice data between protocols. The audio data is transmitted to and from the interface component 116. A source component 116 and a cable 120 configured to handle data transmission. The device controller 140 is , and further via the interface bus of the connection device 130, the audio component 14 2 and a master component 144 for communication with one or more slave devices, such as an audio component 144. It acts as a star device and allows users to interact with it via a user interface component 146. The device also supports facilitating other device functions such as processing user input. So, the bus lines are the power bus (VBUS) and the differential pair D+, D- for data transmission. , ground, and device ID. Other bus line configurations may be used in accordance with the teachings of this disclosure. Those skilled in the art will appreciate that various devices and Communications between the components may be performed using the digital data communications systems and methods disclosed herein. This can be facilitated according to the methods and methods.

[0051] 1B, the example connection device 130 of FIG. 1A is A USB connector 152 for connecting to the interface component 116 and a connector The device controllers housed in the controller 152 and the user interfaces (such as buttons) The interface 157 and the device controller 152 are connected to the audio component 160 and 70 and a wired data bus 158 connecting the USB headset 150. In one embodiment, the headset 150 may include dynamic noise cancellation (AN C) A headset. See FIG. 1C for use in an ANC headset. Exemplary embodiments of audio components 160, 170 are shown. The component 160 / 170 is a slave device on the data bus 158 of the headset 150. Each of the audio components 160 / 170 is implemented as a slave. Receives audio data from the component and drives one or more speakers 186 to provide audio to the user. an audio output circuit 182 for playing audio data for the 4, digitizes the received data, and transmits it to the data bus 158 To provide digitized audio data to the slave for transmission to the master via and a voice input circuit 180 for receiving the voice.

[0052] Another embodiment of a connection device is shown in FIG. connector 216, cable 220, device controller 240, and user interface The connector 216 includes a base 246 and audio components 242, 244. A host device (such as, for example, interface component 116 of FIG. 1A) The cable 220 is adapted to be coupled to an interface component. The connector 216 is connected to a host device and a communication protocol used to communicate with the host device. A device controller that provides an interface between the device 230 and the bus protocol The device controller 240 is coupled to an audio component 242 and an audio A master of a communication bus that couples one or more slave devices, such as component 244 The user interface 246 is coupled to the device controller 240. Provides user control (such as volume control or muting an earphone set) .

[0053] 2B, the example connection device 230 of FIG. 2A is a USB connector 252 for connecting to the interface component 116; B cable 254, a device controller 256, and a user interface (such as a button). The interface 257 and the audio components 260 and 270 are connected to a device controller 256 and a wired data bus 258 that connects to a USB headset 250 (e.g., It can be implemented as a USB earphone.

[0054] The disclosed systems and methods support long wired links, low power implementations and high bandwidth communications. In various embodiments, a low duty cycle is used for the signal, which The fixed power consumption associated with more terminated links is reduced. In this case, the low duty cycle is based on a symbol-by-symbol basis (e.g., short symbols). and / or by sending a data packet and then immediately short-circuiting the bus. One advantage of these approaches is that the data packets Low latency links are supported by allowing the bus to be paused after a quick transmission. and the low latency link consumes little or no power. In the above embodiment, each receiving device has an internal phase-locked loop (PLL) or DLL (delay-locked loop) to generate a high-speed internal clock based on a periodically sent synchronization symbol By adding a low duty cycle to the symbol, higher data rates are supported. One advantage of using cycles is that they allow low power consumption for medium transmission rates. This is because the fixed power consumption of the terminated links is low duty cycle. In other words, the noise caused by the use of terminated transmission lines is reduced by the Therefore, a link capable of high baud rates is required to obtain low power consumption for low to medium speed signal transmission. Because of the power consumption of the various embodiments disclosed herein, The cost scales linearly with the bandwidth used (the receiver power used to receive data). The power consumption from the LL will be constant, but it can be a small percentage of the total power budget. Thus, the data link implementations disclosed herein are suitable for medium to low bandwidth applications. Low power consumption is possible when using a 1000W ... In both cases, the PLL clock frequency or the DLL The delay may be fixed or may vary to suit system requirements.

[0055] The present disclosure further provides an improved method for eliminating intermediate noise that would otherwise degrade signal integrity in conventional systems. A control that ensures a high quality signal is obtained even if there is an impedance mismatch in the Multi-drop bus configurations are supported by providing control at intermediate nodes. In many conventional systems, this avoids terminating the ends of the transmission lines and instead Instead, this problem is solved by controlling the slew rate of the signal, but this The maximum slew rate constraint that can be avoided slows down the system. The various systems and methods disclosed in are not subject to such limitations.

[0056] The embodiments disclosed herein provide robust signal integrity with minimal degradation. In some embodiments, the transmitter provides a strong and reliable data link. To further reduce power consumption, the parallel termination resistor may be disabled during transmission. In some embodiments, the transmitters at each end of the bus transmission line are not transmitting. Termination may be achieved by setting the output level to a fixed value when the Set the system to a fixed quiescent value and match the series output impedance to the bus impedance ( That is, the output transmitter at each end is used as a termination when not transmitting. , low power consumption will be realized (e.g., the internal clock will be turned off when there is no data to transmit). (e.g., no power consumption other than the generation) In conventional systems, the impedance of the transmission line Changes in the frequency band can cause reflections in the transmitted signal. The system is capable of inserting multiple components into intermediate nodes on a transmission line without significantly distorting the transmitted signal. The design is limited by the notion that the components cannot be easily installed. .

[0057] However, in this disclosure, the wavelengths are measured over relatively short distances compared to the shortest wavelengths of interest. If no impedance change occurs, there will be very little signal disturbance and it will be practical. It is recognized that practical systems can be implemented. For example, an experiment using a 50 Ω transmission line The system used had multiple intermediate nodes, each of which was a small stub (1-2cm long), which reduces the slew rate to 4.7ns to 4.8ns (or an increase of about 100 ps), resulting in a decrease in amplitude of about 6% for each node. Thus, even a slight increase in slew rate and a small decrease in amplitude can The changes were minimal, a good eye diagram was obtained, and robust data transmission was achieved. Therefore, in conventional theory, the impedance along the transmission line must be This led to a system requirement that prohibits changes in the length of these disturbances, but As long as it is much shorter than the wavelength of the high-speed signal, it will not be detrimental to a practically functioning system. These reflections can be controlled to have a small intensity.

[0058] The experimental system had a stub length of 2 cm, which is 0.1 n in air. This is equal to a transit time shorter than s, which is much shorter than the rise time (5ns). In this case The ratio between the rise time and delay due to the stub is greater than 50, which is the optimal ratio for the system. If the delay is 5ns (150cm unshielded), If the 100mV / s ... The cable would have appeared to have an open end. When dimensioned as disclosed herein, one or more systems of the present disclosure may , allowing the transmission of very high speed signals with proper termination at the end of the transmission line while at the same time providing multiple This allows components to be placed on the same transmission line, still allowing high speed transmission. The problem of obtaining a multi-drop bus system that allows forward or reverse wave By timing the sequence of signal transmissions so that the backward wave is controlled , which refers to an active transmitter located at an intermediate node on the transmission line and disturbing the propagating wave. This makes it possible to avoid problems that may occur.

[0059] An example of a timing sequence according to one or more embodiments will now be described with reference to FIG. Figure 3 shows the propagation of information between a master device and three slave devices. Higher bandwidth is achieved by optimizing the timing relative to the direction of data transfer. In various embodiments, all data packages can be obtained as they are absorbed. When the master M1 reaches the end of the transmission line, It is provided with multiple slave devices (S1, S2, S3) on the same transmission line. The slave devices are labeled with numbers 1, 2, 3, etc., and each thread A slave device is further away from the master device.

[0060] When sending a forward propagating wave from Master M1, Master M1 sends a message first. (Time A). Then, just after the forward wave passes the slave device S1 ( At time C), slave device S1 follows, and the message from slave device S1 When the end of the message is complete (time E), slave device S2 transmits its forward propagating wave message. Slave device S3 receives a message from slave device S2 that is complete. When all forward propagating wave messages are completed, the transmission line is absorbed by the termination at the other end of the transmission line, the last device in the line (for example, time F The slave device S3 in the master node M1 starts transmitting a backward propagating wave toward the master node M1. Following this backward propagating wave, the message from the last device just passed, and then the transmission The penultimate device on the line (e.g., slave device S2 at time G) The backward propagation wave from the master is transmitted. All backward propagation wave messages are completed. Once absorbed by the termination in the -device, the master M1 again, as described above, It will begin transmitting messages using forward propagating waves.

[0061] In some embodiments, two devices may be coupled together if the devices are inversely connected to the transmission line. It is located at the end of the pair and the effect of the waves it transmits is the measured waves (forward and backward propagating waves) It is okay to send messages simultaneously, provided that they are subtracted from the In embodiments, this may even be done for devices located at the midpoint of the transmission line. However, in some embodiments, the devices located at the midpoints are generally should not transmit and receive at the same time, because this would cause reflections of forward or backward propagating waves. Because it can cause.

[0062] In various embodiments, a voice device such as an audio headset may be used The communication bus for this is differential impedance matched to allow high bandwidth and low power consumption. It has a multi-drop bus with signaling that provides high-speed control and voice-bandwidth It has a width of 10 meters and supports links up to 10 meters. In some embodiments, the total bus link length is 2 meters or less. The link length is the distance between the two terminal points Z END is the length of the signal line between the A device controller 140 may transmit a user interface component 1 Cable 120 length up to 46 (Length A), User Interface Component 1 The length of the signal line from 46 to the intermediate node (length B1 and length B2), and The length of the signal line from the link to the termination point (length C1, length C2). The total length from the terminal end point is 0 to 200 cm, including the following ranges: length A, 0 to 80 cm; length B, 0-60 cm; and length C, 0-60 cm. In one embodiment, the stub B2 and C2 are kept as short as possible to minimize the impact on signal integrity. It should be.

[0063] Referring to FIG. 2A, in one embodiment, the length of the USB cable is 0-200 cm; The link length between each end point and the device controller 240 is 0 to 100c. In the illustrated embodiment, the headset is connected to the terminal end and the farthest speaker or The link between the microphones is less than 200 cm, although other distances can be used.

[0064] In various embodiments, the link operates at a standard clock rate, e.g., 12.288M. Hz and 19.200MHz, which allows standard telecommunications and audio In one embodiment, in the 12.288 MHz operating mode, By increasing the turnaround delay when switching the direction of signal propagation, A coupling distance of 10m is supported.

[0065] In various embodiments, the lock-in range of the PLL is narrow and constant between each synchronization symbol. Additionally, in various embodiments, multiple clocks may be used to maintain a It is desirable to maintain 48kHz compatibility with the system. This disclosure provides a simple and robust initial synchronization between a slave device and a master device. Further, various embodiments use a constant frame size. The use of multiple frame sizes ensures compatibility with multiple clock systems. In contrast to SoundWire and similar protocols, which allow Synchronization between multiple sources, such as multiple audio ports with different sampling frequencies To maintain this, one or more beacon bits are signaled in the frame.

[0066] Exemplary modes of operation according to one or more embodiments of the present disclosure are illustrated in the table below. R: [Table 1]

[0067] The systems and methods disclosed herein are energy efficient in design and frame. Resolved some issues with sync symbols interfering with column size and moved the sync column to It includes efficient bandwidth usage by mixing multiple clocks, has a simple clocking scheme, and is a single clock. 12.2 Supports 88, 19.200, and 12.000 MHz systems, with wideband P LL tracking is not required (i.e., the PLL only supports a relatively narrow lock-in range). Variable data format to support multiple clock systems A constant frame size is available for all inputs, and the eye diagram is optimized during data reception. Tracking, including accurate measurement of slave delay with fine stepping of sample interval for optimization In various embodiments, for example, while maintaining a constant frame length, Multi-drop buses can support multiple clocks such as telecommunications, USB, and audio operating modes. In some cases, a lower synchronization frequency such as 768 kHz may be used for the system. may be used for longer bus diameters.

[0068] The time slot after the master completes a synchronization symbol (typically a 0 to 1 transition). This time slot can be used for signaling commands or can be left undriven. This allows multiple devices to change the current level (wired-OR) By not allowing the current levels to be driven (as in the configuration), multiple devices To allow both slaves to respond to the same time slot, the sync symbol is With careful timing it may be merged into the signalling of the command.

[0069] Clock Support As previously discussed, one problem encountered with conventional bus topologies is that the desired fundamental frequency Support for different clock frequencies, including any multipliers or dividers required to obtain the desired number. As an example, 48 kHz is 19.200 MHz divided by 400 (4 x 5×5) or divide 12.288MHz by 256 (4×4×4×4) In various embodiments disclosed herein, The commands sent do not interrupt the voice flow. In one or more embodiments, the commands In some embodiments, the data is issued at the same cadence (or a sub-multiple thereof). PL to incorporate the clock into the data lines, thereby saving lines and power consumption L or DLL clock synchronization constraints. By using differential signaling, electromagnetic interference ( It is possible to constrain the EMI.

[0070] In one embodiment, overhead bits are added to the communication frame to provide room for synchronization and commands. The system includes: The frame structure is optimized for bandwidth utilization given the constraints of long bus diameters. The structure of the present embodiment is deterministic and simple to decode, e.g. For example, a precise clock frequency can be set, such as a constant number of clock pulses between each synchronization frame. No complex analog circuitry is required for determination.

[0071] Existing systems like SoundWire, for example, only have 8 Includes various predefined frame formats, such as 1000 column sizes and 19 possible row values. One challenge is that each one has a different multiplier (19200 / 48=4 00 and 12288 / 48=256), 12.2 without the need for special analog systems By designing a system that supports both 88MHz and 19.200MHz operation In various embodiments disclosed herein, 12.288 MHz, 19.200 MHz A single frame capable of supporting both 12.000 Hz and even 12.000 MHz systems. The size of the system may be used.

[0072] The PLL and clocking solutions disclosed herein overcome the various problems associated with conventional systems. When you have an unterminated transmission line, there are reflections that affect signal integrity. One solution is to slow down the data transmission. However, many systems require high speed transmission and therefore need to eliminate unwanted reflections. Terminated signal lines are preferred to ensure that the Faster clock speeds and lower duty cycles for data (as pause spaces at the end of the line) By using a time cycle, the fixed power consumption per transmitted bit is reduced, This allows for reduced power consumption for medium speed links.

[0073] When there are only two devices, there is no cross traffic, so the same Furthermore, since these two devices are located at the ends of the transmission line, Such a system may not require termination at each end since the two signals will not overlap. When using multiple devices, if a slave device loses lock with the master device, One solution is to restart the bus, but this may cause the system to be silent for a period of time. This is undesirable in many implementations, as it would result in a loss of voice. By resolving clock synchronization, devices that have lost synchronization can be Addresses slave device issues.

[0074] Referring to FIG. 4, here, the device controller 140 of FIG. 1A may include 2A and the device controller 240 of FIG. , slave devices 142, 144 in FIG. 1A and 242, 244 in FIG. 2A. The LL300 supports a primary sync signal and time-multiplexed signals from multiple slave devices. This allows the circuit to maintain lock even if a

[0075] The PLL (or DLL) 300 generates a phase and frequency matching the phase and frequency of an input reference clock. During operation, the reference clock signal is fed to a time gate to generate an output clock signal having a frequency of 100 kHz. A feedback signal from the divider 310 is fed to the phase detector 304 via the output 302. The phase detector 304 detects the phase of the input reference clock signal and the feedback signal. and the frequency is compared to output a control signal, and the feedback signal is the phase of the reference clock signal. and a feedback signal having a phase and frequency synchronized with the The phase detector 304 adjusts the rising edge of the reference clock signal and the feedback signal. The output of the phase detector 304 is fed to the voltage controlled oscillator (VCO). The signal is fed to a loop filter 306 to adjust the voltage and frequency of a VCO 308 . The signal output from the VCO 308 passes through a divider 310 to generate a feedback signal. The output clock signal is provided to the various system components described herein. In the illustrated embodiment, the divider divides the 144-bit frame size in multiples. However, other integer values ​​(e.g., M=16, M=42, M=48, or M = 80) can be chosen. Using M = 4 directly results in 4 time slots, Using both phases of the clock to capture the signal results in eight time slots. Using M=8 gives us 8 time slots directly, and using both phases gives us 16. time slots, which provides a simple solution for high resolution.

[0076] In various embodiments, the time gate 302 is always enabled during initial startup, After that, it is only enabled while receiving a reference sync pulse from the master device. Multiple slave devices can also transmit signals on the bus, and at any one time they are the master This allows the circuit to lock onto the master even if the circuit is out of sync with the master. Therefore, if the PLL / DLL loses lock with the master sync, the device will continue to drive the output drivers. Disabling it will avoid bus collisions and re-enable the wide-area search for sync pulses. In some embodiments, time gating (e.g., by using a sufficiently narrow time window) can be used. By using it as a phase detector, it is possible to eliminate the phase detector altogether. This is because This can be used to reduce jitter (time gates can be used to divide the output from the VCO through In some embodiments, the phase detector may be It is sensitive to both temperature and phase differences, ensuring that the correct state is obtained initially and safely. The detector may be of the phase-frequency type (type III-IV phase detector) as shown in FIG.

[0077] Provided herein are exemplary clock division solutions for use with embodiments of the present disclosure. In one embodiment, as shown in FIG. 5A and FIG. 5B, The solution consists of an audio clock 402 that is used for audio input and output processing, and a host device. A USB clock 404 used for USB communication between the device and a connected device, Three data bus and DSP clocks 406 for use in a low latency data bus This is an implementation of a frequency-locked loop (FLL) 400 that generates a synchronous clock signal. The synchronization pulses present in the protocol may be used as a timing reference.

[0078] In the illustrated embodiment, a synchronous detector 410 is coupled to the input of the FLL 400. The synchronous detector 410 detects whether the clock signal is in line with the system clock to allow proper bus communication. Determines whether the sync symbol is synchronized with the sync clock (see USB Clock). If it arrives outside of the sync detector 410, the sync detector 410 notifies the FLL 400 that the clock cycle is This will correct the clock cycle to synchronize with the Star Clock. FLL40 0 includes a digital filter and predictor 412 and a delta-sigma D A digital-to-analog converter (DAC) 410 such as AC and a voltage-controlled oscillator (VC O) 417, a frequency divider 424, a frequency counter 418, and the result is compared with the reference frequency 408. The embodiment may be implemented with a subtractor block 414 for comparison. The reference frequency integer value is 48384 (see reference number 408). , divider 420, divider 422, and fractional divider 426 are used to provide the desired frequency to the FLL 400. It can be used to generate a fractional frequency. It can be used to divide a clock signal by a fractional value. An embodiment of a fractional divider 430 that may be used is illustrated in FIG. is implemented using a phase adder 432 and a frequency divider 434. Here, a certain phase value is added to the phase sum for each clock cycle, and when the current phase sum exceeds a certain maximum phase value, When the other phase value is added, the current sum is subtracted and the output is activated. A two's complement adder is used. If the phase is 2, N This may be taken in stages, and the automatic operation that occurs in two's complement arithmetic may be taken in stages. Due to wraparound, no subtraction is necessary. In some embodiments, the delta-sigma The converter performs accumulation instead of a phase adder, which eliminates the spurious response caused by fractional division. This can be achieved by eliminating the output clock signal by spreading the output spectrum. It can also be used to reduce EMI.

[0079] Exemplary clock solutions for various embodiments of the present disclosure are shown in the table below. As used herein, the term "ear link" means a Reference is made to the audio bus system and method disclosed herein. [Table 2]

[0080] An exemplary embodiment of the second clock solution is illustrated in FIGS. 6A and 6B. The second clock solution is the audio clock used for audio input and output processing. 502 and the USB clock used for USB communication between the host device and the connected device. 504, and a data bus and DSP clock for use in the low latency data bus of the present disclosure. The embodiment of the frequency locked loop (FLL) 500 generates three synchronized clock signals for the clock 506. FLL 500 is the same as that of FIGS. 5A and 5B except as described herein. A synchronous detector 510 and a filter and predictor 520 may be implemented similarly to the corresponding components. 512, a delta-sigma DAC 516, a VCO 517, a divider 524, and a frequency converter 526. The FLL 400 includes a divider 520, a divider block 518, and a subtractor block 514. a frequency divider 522 and a PLL that outputs a frequency 125 / 128 times the audio clock frequency 540 to generate the desired divided frequency. An embodiment of PLL 540 is shown in FIG. 5, and includes a 1 / 128 reference input from the output of divider 520, a phase detector 544, and a loop The frequency converter 540 includes a loop filter 546, a VCO 548, and a 1 / 125 frequency divider 550.

[0081] An exemplary embodiment of the third clock solution is illustrated in FIG. The clock solution includes an audio clock 602 that is used for audio input and output processing, and a A USB clock 604 used for USB communication between the host device and the connected device; The data bus and DSP clock 606 used in the low latency data bus of the present disclosure FL is an implementation of a frequency locked loop (FLL) 600 that generates two synchronous clock signals. The L600 has the same components as those of FIGS. 5A, 5B, and 6 except as described herein. The synchronous detector 610, the filter and predictor 612, and the delay component 614 may be implemented similarly to the delay component 614. A 1 / 2-bit DAC 616, a VCO 617, a divider 624, and a frequency counter 618. and a subtractor block 614. The FLL 600 includes a divider 620 and a 22 and the PLL630 that outputs a frequency 21 times the audio clock frequency is used to obtain the desired division. Generates an oscillating frequency.

[0082] An exemplary embodiment of a fourth clock solution is illustrated in FIGS. 8A and 8B. The fourth clock solution is the 12.288 clock used for audio input and output processing. MHz audio clock signal 702 and USB communication between the host device and the connected device The 12 MHz USB clock signal 704 used for the low latency data bus of the present disclosure. The three synchronous signals of the 258.058 MHz data bus and the DSP clock signal 706 An implementation of a frequency locked loop (FLL) 700 that generates a clock signal. are implemented similarly to the corresponding components in Figures 5 through 7, except as described here. A synchronous detector 710, a filter and predictor 712, and a delta-sigma DAC 714 may be implemented. 16, VCO 717, divider 724, frequency counter 718, and subtractor block 7 The FLL 700 includes a fractional divider 720, a divider 722, and an audio clock. A fractional divider 730 is used to output a frequency at 21 times the clock signal 702 to obtain the desired divided frequency. It can be used to generate the data bus and DSP clock signals 706. An embodiment of the fractional divider 720 is shown in FIG. The fractional divider 720 is implemented using a fractional divider 732 and a fractional divider 734. In the fractional divider 720, a phase value is is added to the phase sum for each clock cycle, and if the current phase sum exceeds a certain maximum phase value, When the phase is equal to the sum of the two, the other phase value is subtracted from the phase sum to activate the output. The divider 736 not only divides the clock by a fractional value, but also adds a dither value to the intermediate phase value. This dithers the phase adder to reduce the jitter of the clock. However, controlling the amount of dither added reduces EMI on the system clock. Typically, this action reduces radiated EMI by 15-20%. The dither generator 736 generates a digital pseudorandom number generator or It can be implemented using other digital circuits that generate pseudorandom numbers. If the pseudorandom number generator is different from zero, If the average value is added to the phase summation sequence, this means that when the phase summation is updated This should be taken into consideration when

[0083] Frame structure According to various embodiments of the present disclosure, a single frame is generated across multiple supported frequencies. A frame structure may be used. Examples are given here for use with the disclosed embodiments. An exemplary frame structure will now be described.

[0084] With reference to the embodiment of FIG. 9A, the frame structure defines a fixed size frame of 42 bits. In one embodiment, the synchronization pattern repeats once per frame. The number of command bits per message is 32 bits, and the message synchronization bit is , repeated once every 48 kHz. Each frame may consist of one or more subframes, e.g. 4 subframes. Each subframe may have the same structure and may be synchronized with respect to An exemplary organization of the command bits is shown below, where SC MD is the start of a command, S48 is a 48kHz beacon, and RES is a hold. field, OP2-OP0 is a 3-bit opcode, and DEV3-0 are 4 DAT is the data to be transferred as part of the command. , PAR is a parity bit for security, and ACK is an acknowledgement bit. do. [Table 3]

[0085] Bit S is every 48 kHz time tick, or every 64th frame, or 256 subframe (for 9.600 MHz systems, 24 kHz time ticks or 5 For 12 subframes, it is equal to 1 at the beginning of the first subframe. The bits are used to find the start of a frame and to synchronize multiple audio sources to 48 kHz (e.g. , the start of the first frame should be a sample event, etc.) .

[0086] Further details of the data organization are shown in FIG. 9A. A 0 to 1 transition indicates the master It is used by the PLL of the slave device to synchronize its internal timing to the Then 16-bit audio is sent from the master device to the slave device. The data may then be transferred to the master device and then handed over to the slave device. During a bar (including a read, R command), one or more taps (to change signal direction) A time slot delay follows. Then the 16-bit audio is transferred from the slave device to the master device. The packet may then be forwarded to the device followed by a delay of one or more time slots.

[0087] The 9.600MHz, 12.000MHz, and 16.000MHz system embodiments are 9B and 9C. These formats are used to support telecommunication clocks. This will enable the ports and limit the bandwidth used between the master and slave. The bandwidth used by the master or slave varies from about 1 / 3 to 2 / 3. These formats correspond to a clock frequency of 19.200 MHz. 10 or slightly more bits per line for more efficient transfer in This frequency, or 38.40MHz (=2×19.20MHz), has the advantage that z) is often used in telecommunications applications such as mobile phones and handheld devices. Used.

[0088] 9D and 9E, additional frame structures are described. For example, there are the same number of bits in each frame between each sync pulse. The number of bits can be changed, for example, by changing the amount of bandwidth used for the command. The frame structure may also vary in the number of rows and columns while still maintaining the same number of bits. For example, both Figures 9D and 9E have the same number of bits per frame. A larger number of bits per frame that can be decomposed into various divisors (e.g., 80 or 144 bits) resulting in higher jitter in the receive eye opening due to the higher bandwidth However, it is possible to change the frame organization without changing the PLL multiplication factor. .

[0089] An exemplary message field organization is illustrated below. [Table 4]

[0090] Many commands are conventional (do nothing, read and write registers) Although it may be possible to achieve this, the DELAY command determines the optimal timing between devices connected to the transmission line. It will be appreciated that this can be used to find delays for timing purposes. The master first charges the line to a value and then holds this value in the bus holder. Or, use a floating bus and then release the main driver and then This can be achieved by allowing any connected device to toggle this value. The device closest to the master is the first to affect the toggling of the bus lines. This would be done using a counter that is clocked at high speed to detect timing events. or multiple delay circuits can be used to measure with high reliability. The bus will not be terminated so as not to affect the slave transmit timing. This can be done internally in the master (to optimize the slave-slave communication parameters) This can also be done internally in the slave device (to optimize timing).

[0091] 9F illustrates an exemplary protocol symbol in accordance with various embodiments. Another set of typical commands is further illustrated in the table below. [Table 5]

[0092] Here, an embodiment of the "register read operation" will be described. To do so, the following sequence may be performed: (i) an address write operation (ii) Perform a register read operation (using the data filter). (The field will contain the read value.) If you need to read a range of registers, If so, this can be done without updating the address register between each read operation. This is possible because the address counter can be incremented by 1 with each read operation. It has become a Noh play.

[0093] Here, an embodiment of the "register write operation" will be described. To do this, the following sequence may be performed: (i) using an address write operation; (ii) Perform a register write operation (data field (The command will contain the read value.) If a range of registers is to be written, If so, this can be done without updating the address register between each write operation. This is possible because the address counter can be incremented by 1 with each write operation. It has become a Noh play.

[0094] Here, an embodiment of "address register write operation" will be described. The access is controlled by the address register. Before performing any register operation, the address The value of the register is defined. This is caused by an address register write operation. The address register points to the currently active register in the destination slave device. Subsequent accesses (read or write operations) increment the address register. This allows faster access to multiple registers. In various embodiments, only a single register is required to control both read and write operations. No read or write operation will ever invert the value of this address register. An increment occurs when the value of the address register is read or written. In a write operation, the current value of the address register is , they cannot be read back using the commands shown in the table.

[0095] Here, an embodiment of the "beacon" command is described. This command is a 48 kHz This may be sent by the master with a repeating period of 100 ms. Used by the slave to synchronize audio timing to the start of a frame so that This can sometimes happen.

[0096] Here, an embodiment of the "device loop delay" command is described. The slave is detected by measuring the transitions that are initiated by the slave device and propagated to the master. Measure the turnaround delay from the device to the master. In this embodiment, two paths are used. A mechanism for measuring delay is provided. Here, an implementation of a method 800 for measuring delay is provided. The form will be described with reference to FIG. 10A. First, the master sends a command to the device. This indicates that delay measurement is to begin (step 802). Next, termination is disabled on both ends. (step 804), and the transmission line is charged with a known symbol (step 806). The known device responds by discharging the transmission line in step 808. The delay from the charge event to the discharge event is determined in step 810. In step 812, if the system has end termination, , termination is enabled at both ends of the transmission line.

[0097] In one implementation, the master issues a device loop delay command and then The master then writes the device ID in the data field. If the device ID is the same as the data field, the internal flag (" If the device ID is If the bus is not identical to the master, an internal flag will be reset. The bus is set to a known state (i.e., the bus is initialized to a known logical value, 0). The star maintains this condition with a weak bus holder or by using a floating bus. The bus is driven to a known state and then its transmitter is disabled, and the load at both ends is For example, the master may use A 0-1 signal may be used to force the bus into a "1" state.

[0098] The slave device then uses a strong internal driver inside the slave device to In one embodiment, the slave device can drive the states of Outputs the sequence -ZZZZ-00-ZZZZ-, where Z is the disabled driver and 0 drives a low signal. The two zeros ensure that a zero is read correctly under all delay conditions. When the master's receiver receives a transition signal from one or more slaves, ,The master will know the delay from the timing.,The timing of this event is Finding two-way delays to adjacent devices and controlling transmit or receive timing delays The delay value is , may be measured based on an internal oversampled clock inside the master device. , may be measured based on the use of delay lines or delayed samples inside the master device. In cases where a significant amount of noise or clock jitter is present on the bus, a good delay reading is required. This process may need to be repeated multiple times to obtain the desired result. A few time slots are obtained with high resolution, e.g., 2 ns, and then multiple, e.g., 64 may include a return reading that is averaged over a number of readings. If the delay can occur anywhere between 0 and 36ns, then it is possible to determine the delay accurately in all cases. To determine the maximum number of active devices, each is based on multiple measurements returned from the slave device. A total of 19 values ​​will be needed to obtain a good average in each case. It may be necessary to perform multiple (e.g., 64) reads to ensure By starting the search from an intermediate delay position, the search time can be significantly reduced. Furthermore, the final returned value gives an indication of whether the delay was too long or too short, so that It is possible to reduce search time by changing the search direction depending on what value is returned later. In this limiting case, the slave returns exactly at the transition. Approximately 50% of the 0s and 1s will be measured. In addition to this, to get the best sampling points, To do this, an additional 1 / 2 data slot would be required.

[0099] In other implementations, the master writes back the values ​​it reads from the slave and then The device itself may adjust its internal delays, which optimizes slave to master communication. It can be used to optimize, i.e., reduce the bandwidth required for regulation. A slave device writes the value it reads from another slave device, and the other slave It may also allow the device to adjust its own internal transmission timing.

[0100] The charge remaining on the bus is determined by the master setting the bus to a known value, which causes the When you have no prior information, you will be absorbed by the Master. If multiple slaves exist, they will share their device IDs (16-bit The slaves closest to the master can be killed one at a time using a constant In other words, the delay of the device connected to the bus will correspond to the delay value obtained. During counting of connected devices, the first device connected to the transmission line (typically the master ) and the last device connected to the bus (typically a slave device) During the process, the driver is disabled and the state is maintained by the inherent charge inside the transmission line. This will enable a floating bus that

[0101] In various embodiments, the device ID includes the number DEV and a data field value equal to or greater than the device ID. Only the device with the highest address currently connected to the bus will activate its output. Discover devices with different device IDs (typically 3 bits) to remove this device from the search and Then, continue searching for the next highest device address, and so on. In other words, the MSB of the Device ID is read first, and the lower An arbitration procedure is first used to ensure that all slaves with the same device ID leave. This procedure will continue until only one device responds. :This procedure is I 2 C Similar to multi-master and SoundWire address arbitration.

[0102] In one embodiment, a delay command is used to ensure that the measurement is not disturbed. When the frame is In some embodiments, the slave devices may be configured to support certain geometric configurations. This component is programmed to use a specific delay to Eliminates the need to find the physical delay before acquisition and stores the delay value in non-volatile memory or internal circuitry. It may not be necessary to include other means for carrying.

[0103] Refer to Figure 10B. A method 850 for counting non-retained connected devices is illustrated. Step 85 In step 2, the master sends a command to start counting. Termination at both ends is disabled at 854, and the master then, at step 856, Proceed to charge the transmission line with a known symbol. If a bit from the device number If the bit is high, the unknown device on the bus responds by discharging the transmission line. After a known delay, the device number for this location is populated with low bits (step 858). All devices that have the same port will be stopped (step 860). If it is still there (step 862), the next device bit is checked and the status Device arbitration continues at step 864. If only a single device remains, If so, the device is assigned an address in step 866. If the master But you know in advance the long IDs (e.g. 16 bits) of all connected devices. Then the master can simply call them one by one and perform address arbitration immediately after startup. It is possible to reassign each device a new short ID (3 bits) without the need to run can.

[0104] Here, an embodiment of the "Set Device Address" command will be described. After this command, the slave device is assigned a device address value of 0. When executed, the destination device will get a new address (0 to 7). Address 7 (111) is included for broadcast purposes. Only devices that have _update_ready set will be updated.

[0105] double action A dual action embodiment will now be described with reference to FIG. Thus, bus 900 can operate in simplex or duplex modes of operation. may be configured to simultaneously transmit and receive signals depending on the design of the output drivers. This arrangement is suitable for use with a bus length of 25, as may be used in home audio systems. It may be used to allow for distances beyond a metre.

[0106] In this embodiment, the transient response of the forward and backward propagating waves is calculated using the two drivers simultaneously. This is used to evaluate what happens when the voltage at any point is forward and backward. Therefore, the impedance of the output driver and the transmission line are By taking impedance into account, it is rather simple to measure the point at any node. and subtract the contributions from the two drivers.

[0107] For simplicity, we first consider only two drivers 902 and 904 located at each end of the transmission line. To properly terminate the link, drivers 902 and 904 must Let us also assume that we use a series termination with a value equal to the impedance Z0 of the transmission line. This is , meaning that both the forward and backward propagating waves will be at half the initial driver voltage. The voltage at any point can be found from the sum of the forward and backward propagating waves, so The correct received voltage can be found by subtracting half the driver voltage from the measured voltage. In the differential case, this is simply done by adding half the inverted transmit voltage to the receive voltage, e.g. For example, this can be achieved by using capacitors to exchange and add half the differential transmit voltage. This approach allows for bidirectional transmission during transmitter direction turnarounds in many configurations. No delay is required, and the lack of turnaround delays allows for continuous operation and data storage. Much longer links (e.g. 25 meters) are possible without having to put pauses in the ream This structure allows extremely high-speed full-duplex operation (0.1 to 5 Gbps). The configuration is such that operation is limited to one node at each end of the line, and at least one node is periodically synchronized. As long as the timing pulse is sent out, no timing adjustments are required.

[0108] Multiple Slaves Various embodiments of multiple slaves are described here. Dual operation is a single master This is relatively easy when there is only one slave device and The situation becomes more complicated when there are relay nodes in both directions. This means that the relay node will also reflect the waves from the other nodes. Therefore, traditional duplex operation is However, it is possible to time the signals appropriately. By taking advantage of this gap, throughput can be increased. The signal will first go from the master to the slave device. The forward wave from the master must reach these devices before they can start transmitting. Therefore, any handover delays may need to be An example timing diagram that addresses this situation without requiring {M, S1, S2, S3, S4, S5} and then reverse this pattern when changing direction. S5, S4, S3, S2, S1, M}, where M stands for master and S 1 is the slave device closest to the master, and S5 is the slave device furthest from the master. In other words, the devices connected to the bus advance or It transmits a backward wave, thus naturally avoiding the problem of reflections from midpoints on the transmission line. The timing delays of devices connected to the bus should be verified before attempting this technique. , will naturally be identified and corrected.

[0109] Ensuring that differential signaling techniques are used for all communications reduces emissions The received EMI will be significantly reduced. 9 is an example of differential signaling 920 where a periodic signal is followed by data, then a pause again. The quiet period has a differential nature to avoid common mode noise. This avoids fixed power consumption during downtime and thus allows for conservative bandwidth usage. To allow for very low power consumption for the bandwidth requirements, the termination on one signal line is , meaning that one should end at a high level and the other at a low level.

[0110] FIG. 11C shows the lowest possible EMI and lowest possible power consumption in sleep mode. FIG. 9 is an example of a differential signaling system 930 that terminates to high and low signaling voltages for FIG. 11D shows that transmitters 942, 944, 946 and 948 at each end Used as a series termination for the bus, thus eliminating the need for a terminating load at the end nodes. A similar example of a differential signaling system 940 is shown, which reduces power consumption and simplifies implementation. The bus drivers on each end go into a quiesced state when they are not sending data, and by default This provides a default termination voltage, thereby reducing power consumption in hibernate states. In this configuration, one of the two transmission lines uses a power line instead of a ground for shielding, Some embodiments also use a shielded coaxial cable. Instead of, for example, the DATA You may use four twisted wires: +, DATA-, ground and power. The ground and power wires are In another embodiment, a single shield is used to provide both power and differential data. The capacitors are located on the three cables inside the shield.

[0111] In some applications, audio induced by random signal transmissions occurring on the bus may be It is important to minimize noise. This is because the signaling levels of the various sources on the bus Vary the signal level, for example by using pseudorandom number generation at the transmitter and receiver of a data port. This randomizes the bus traffic, thereby reducing the signal quality in the voice band. In some cases, randomization may be performed by reducing the spectral content of the audio signal. The spectral content of the data signal is multiplied by the high frequency components, for example, to convert each row into a The specs are then multiplied by a random or predefined value to make them even lower. In some cases, randomization may be done by simply moving the lines to the This may be done by multiplying with a carrier outside the width. The port may also include an error tester (e.g., an 8-bit pseudorandom number generator for verification and testing). This port tester is also used for scrambling and descrambling voice data. Multiplication in the digital domain can be performed by XOR or XNOR gates. For example, a nearly identical pseudorandom number generator can be used to recover the original sequence of data. For an example of a pseudorandom number generator and a receiver / tester, see, for example, SoundWir See the e standard. Similar techniques have been used in the past, for example in wireless modems, to transmit data It has been used to reduce or remove DC components from a stream. The use of a rule does not even avoid situations involving the transmission of multiple symbols of the same value, This can lead to loss of synchronization, but it reduces the low frequency content of the output spectrum, e.g. It is used to avoid interference in the voice band.

[0112] In some cases, the randomization may involve, for example, randomizing the outputs from the various transmitters. This not only reduces any disturbances to the audio, but also reduces the noise transmission of the modulator. Noise shaping of the noise output spectrum by intentionally controlling the This can be implemented using a delta-sigma modulator using a known pattern, such as

[0113] Cable Specifications Here we describe exemplary cable specifications according to various embodiments. For the dock set, use a shielded cable, e.g., thin AWG30 or AWG34 wire. To meet user requirements such as tight configurations, thinner cables may be used. For long links or large headsets and headphones, thicker cables are used. It may be possible, which also reduces the attenuation a bit. Only 4 wires instead of 8 One example is a dual-mode cable similar to CAT5 requirements (wire type AWG24), except that For example, a standard 100BASE-TX cable can be used. The attenuation of a 15 meter link is 66db / 100m x 15m = 9.9dB or 3.1 Thus, when designing a system, the transmit voltage and maximum receiver hysteresis should be considered. Differences between the different standards should be taken into account.

[0114] Intermediate Nodes Exemplary embodiments of intermediate nodes are described herein. In various embodiments, The node has a series output impedance of Z0 to match the transmission line, From the perspective of the intermediate node, the impedance will be 1 / 2Z0 (because The board essentially sees two transmission lines, each with impedance Z0. It is often desirable for all nodes to have the same capabilities. In one embodiment, (i) each node has an output voltage of U0, and (ii) each end node has an output impedance of Z0. The impedance of the intermediate node is If a node is active during the time that a propagating wave arrives at that node, it will produce a reflected wave. This situation allows the timing of the signal to be correct, i.e., to match the previously transmitted information. This can be avoided by each node first transmitting a signal after the signal wave with the information has passed. The propagating wave will eventually be absorbed at the end of the transmission line. In this case, exemplary transmission line impedances and signal voltages are Z0=75Ω, U0= It may include 250 mV.

[0115] In addition, an intermediate node on a transmission line may face two line inputs, and if If these output impedances are the same as the nodes at the far ends of the transmission lines, The output signal voltage will be lower. This is due to the lower output impedance for the intermediate node. By using a resistor, increasing the output drive voltage of the intermediate node, or by using a receiver on the transmission line, This can be corrected by adjusting the threshold voltage of the

[0116] Startup sequence An exemplary start-up sequence is now described. In various embodiments, Nulling is a differential two-level signaling. However, possible slave failures A unique pattern for start-up or resynchronization after a power down condition. To achieve this, the master may be instructed to send out a third, or higher, different voltage level. This level is not used for data transmission and may be configured to It should only be used for synchronization or for the Wake-up state (wake-up from low-power standby). This will not affect the radiated EMI because this higher This is because the level is only used during the initial synchronization (e.g., the first 1 ms). In an embodiment, the start-up sequence is a 12-bit sequence with a voltage level twice the normal signal transmission level. In various embodiments, the PLL generates a The synchronization edge used will continue to be Therefore, the start-up sequence would not be transmitted during normal operation. During startup or resynchronization, the master uses a clock frequency of approximately 12.288 MHz. (using ) 62.5% of the original bandwidth is left, and in 9.60MHz operating mode, This leaves 40% of the normal bandwidth. A simple implementation would be to add a DC offset for a certain number of typ. time slot, for example, 12 timeslots, and the receiver is differential, so the additional The additional offset does not affect the data, but can be used to detect the power-up state. In a simpler implementation, for the initial and start-up conditions only, a voltage such as 1.0V can be used. The logic voltage is used for wake-up detection, which allows the differential receiver to be driven low. There may be no need to power up.

[0117] Exemplary differential signaling voltages are illustrated in the table below. [Table 6]

[0118] In various embodiments, to ensure a secure startup mechanism for the slave devices, When the slave devices need to get back in sync again, a higher voltage level appears on the bus lines. This higher voltage is used for normal data traffic and reset states. It will be used to distinguish between low power we This may be used for power-on circuits (e.g., a wake-up word) for powering up the device. This higher bus voltage triggers the wake-up circuitry to reduce power consumption. , which is turned on for a longer period than normal data symbols to avoid random noise on the bus. To obtain reasonable robustness, good noise immunity, and low power consumption, the wake-up It is suggested that a pop event will consist of a series of 12-bit slots. This means that At the highest bit clock of 134.400MHz, this equates to a minimum on-time of approximately 89ns. .

[0119] Referring to FIG. 12, in step 1002, the system is powered on and the lock flag The driver is disabled (step 1004), and the phase detector is disabled (step 1 006). In step 1008, a broad search is enabled to discover devices. If a special sequence is detected for a device in step 1010, Then, in step 1012, a sync pulse is detected. If the sequence is not found, this step is repeated until it is found. In step 1014, if the PLL is locked, the wide range search is disabled. The synchronization is then completed (step 1016) and the driver is enabled (step 1018). The sequence (steps 1012 to 1018) begins when the time gate is opened (step 1020 ), and so on. If the PLL is not locked (step 1014) and the narrow band If it is enabled (step 1022), the driver is disabled in step 1024. Then, control passes to step 1008 to repeat the wide range search at high power.

[0120] The operation of the special start-up circuit 1100 will now be described with reference to FIG. There will be no start-up sequence in between and the output from this circuit will be zero. The output of this circuit is used until the PLL is locked. Filters the input and, if the bus is above a certain high threshold for a certain amount of time, Enables the PLL to detect the transition from high to low when the bus level is low. The circuit drains any accumulated charge and again resumes an uninterrupted sequence of high values. Start looking for a spot. [Table 7] The length of this string of logic 1's depends on the clock frequency and the length of the high sync pulse. This is because the analog circuitry checks the start of synchronization in an error condition. It may also be used in.

[0121] The output from the phase detector will be 50ns (at most 120ns) or more than one logic 1. This means that in the illustrated embodiment, at most four Allows voice transfer even during failures over consecutive time slots. The first four columns are reserved for voice transmission, while every fifth column is reserved for transmitting a logic 0. After the 0 to 1 transition, the position The output of the phase detector is again disabled. After obtaining the lock, it searches for a synchronization transition in a narrow window determined by the current lock position. Ignore all bus traffic. Lock-on detector [Table 8]

[0122] Here, an exemplary signal transmission solution is described. First signal transmission sequence solution In the application, Three-level signaling is used: similar to CAT5 signaling, 100 / ... To do this, {-1, 0, +1} is signaled by {low, zero, high}. Logical 0: Same level as before. (After the four zeros, a value from the reverse sequence may follow, i.e. to ensure safe start detection. (Then go backwards after some zeros to ensure accuracy.) Logical 1: Adjacent values ​​in a sequence of 3 values, e.g., multiple 1s in the sequence {zero, The sync and data are then signaled as {high, zero, low, zero, high, low, etc.}. To distinguish between these, the synchronization value must be a sequence that differs from those allowed by the legal data values. For example, you might use {high, low, high, low} or {zero, high, zero, high} In other words, ternary encoding reduces EMI by reducing the harmonics generated. To reduce the signal loss while still allowing the receiver to distinguish between sync and data. do.

[0123] The second signal transmission sequence solution uses two-level signaling. In an embodiment, a device other than the master may not use more than four time slots in a row. If multiple devices are When sending data back and forth, a gap is provided between each set of four bits, and zeros are inserted. If analog delay circuits could be made with even tighter tolerances than those mentioned above, This means that the synchronization symbol, which is different from any valid data value, can be transmitted sequentially. This is an example where bandwidth is traded off to allow for special encoding of the file. Other encoding methods, such as 8 / 10B encoding, separate the sync and data. can be used to distinguish

[0124] In the third signal transmission sequence solution, the DC offset is While a DC offset is added to the signal, the slave will not use it. May be modulated with a common mode signal by the master to indicate the start of a frame This will increase EMI somewhat, but this is for a short period during the initial synchronization. This change in DC offset will be reliably detected by the slaves. This allows the current signaling pattern on the bus and any slave devices to be Synchronization can always be achieved regardless of any previously encountered conditions within the device. 4(3) illustrates an example of this solution.

[0125] fast transition An embodiment of the operation of the present disclosure will be described with reference to FIG. 15. This solution is It allows the synchronization rate to be changed even while still running. In one embodiment, 250mV signaling may be used in both slow and fast modes, with gating The synchronous edge of the received signal in the determined time window is used to sample the audio. In slow mode, there is no additional power consumption on the bus if a timeslot is not driven. There is no cost and only a small additional power consumption from the internal PLL running at high speed. Therefore, a higher frequency is selected for the low-speed mode, which is used as the low-power mode. In slow mode, the device can check synchronization relatively easily (e.g. , 2 out of 12 slots are used for synchronization). In one embodiment, all devices In other embodiments, the device goes into a sleep mode and, in particular, It may wait for another VDD wake-up signal. This delay may occur before the device is functional. (e.g., 1 ms).

[0126] In one or more embodiments, the transition to high speed is initiated by a slow sync (e.g., 76 8 kHz). An extra sync symbol is inserted for high speed mode and the time stamp is The slot is shortened but the original 768 kHz transition is maintained. The symbol is Assumes it is read in the center. The additional sync symbols are invisible to slow mode devices. Each transmitter must re-clock the original timeslot to insert the shorter symbols. The NI 8110 has an internal clock that runs at least twice as fast as the NI 8110. , there are more time slots. In various embodiments, the slow device Read out in high speed mode. This solution maintains audio operation and It allows both high-speed and low-speed devices to be connected to the bus simultaneously while increasing bandwidth and synchronization repetition rate. It basically allows you to insert a sub-period into the existing timing. These subperiods are then used to add bandwidth to existing transport protocols. This approach is used for backward compatibility with existing interfaces like SoundWire. It can be used to support higher bandwidths that the original interface may not be able to provide. This may make it possible to

[0127] Frame Synchronization and Bulk Transfers Those skilled in the art will recognize many advantages of the systems and methods disclosed herein. In various embodiments, multiple upstream connection interface devices (threads) may be used. A bus may be fitted with a number of different devices at various points, depending in part on the exact timing. Due to different packet transfer policies, they may communicate with each other at full speed. Signal transmission involves timing control and distinguishing between forward and backward waves propagating through a transmission line. This allows for tight stacking with a gentle slew rate that reduces EMI. This allows for high bandwidth even at low power consumption. This is FCC Class A and B devices, Part 15 This is useful for certification and compliance with EMI standards such as

[0128] The system described herein is intended to facilitate low-power data communication over two wires. This interface can be used to communicate with one master and one or more slave devices. Supports multi-drop operation with 100 Mbps latency, faster than traditional time-multiplexed low latency systems Allows point-to-point communication between slaves at full speed over long distances Low electromagnetic interference (EMI) is achieved through differential low voltage operation and controlled slew rate. Each slave device has a PLL or DLL, and the system is a terminated, master It supports multi-drop and multi-device system configurations.

[0129] The present system and method is a simple framework that offers many advantages over conventional approaches. In various embodiments, the slave and Initial synchronization between master devices is simple and robust, using a constant frame size. In order to ensure compatibility with multiple clock systems, conventional systems use a variable Frame size has been used, but in this disclosure a different approach is taken. The disclosure provides an overhaul of the disclosed techniques to provide a flexible and effective solution. It uses the additional degrees of freedom provided by sampled clock systems. In some embodiments, the actual clock frequency is determined by the beacon signal that constitutes part of the frame. may be inferred from

[0130] In some embodiments, a line of data is read regardless of the clock frequency and mode of operation. The data has 80 time slots. The individual fields are in the same sequence. However, the interpretation of these time slots may depend on the configuration selected. The default data format is set for the longest bus diameter (lowest speed). With reference to FIG. 16A, the different fields of data for each line are illustrated. By changing the interpretation of the time slots, various compromises can be made between baud rate and bus diameter. The sync pattern repeats once per line of data (e.g. (For example, the sync rate is 3.072MHz as shown in the figure.) Each line is This transition is initiated by the internal delta-sigma transition to 0 so that a bit can be received. Example for the master converter and for locking the PLL / DLL on the bus. FIG. 16A illustrates the synchronization pattern and simplified line description. The 0 to 1 transition event is sampled for the delta-sigma converter. One advantage of using the CLKIN as a triggering event is that it reduces the jitter from the master clock. This includes only the clock and does not include the additional jitter associated with clock recovery in slave devices. Therefore, this solution is suitable for slave devices due to the low current consumption requirement of PLL / DLL. Even if high jitter exists inside the clock recovery unit of the device, the audio sampling Therefore, jitter can be reduced.

[0131] Each line consists of a sync field (the frame begins with a logic 1 and ends with a logic 0) and a coherent Command field (C is a command from the master) and forward (typically It also provides a field for transporting audio (from master to slave) and the possibility to change the signaling direction. A two-way delay "turnaround" (T1) to allow for a response from the slave device Answer field "R" (used only when reading from a slave device) and A field for transporting audio from one device to another (typically from slave to master) and a synchronization pattern. The line also has a possible empty field that completes the beginning of the line. Command (master to slave), framing (beacon) field (F) and , may contain data fields D0 to D4. Each of these fields The number of slots allocated to the line may vary depending on the application. The total number of time slots is a fixed number, for example 80. The number of columns in a line can be changed. To change the sync rate, use the technique in Figure 15 (e.g., changing the sync rate from 768 to 3072 kHz). Figure 16 shows the default configuration at startup, where ,The index shown below is the number of time slots at the start of each field. .

[0132] The transport of data will occur on the transmission line. Data packets from multiple devices To avoid collisions between the master and the other, we distinguish between forward and backward waves. The reverse or inverse wave is directed from the slave device to the master. This is the data sent and propagates towards the master. During the turnaround period In this case, the device does not transfer any information and the driver (apart from the possibility of dynamic termination) is disabled.

[0133] Audio data flows in both directions on the link, from the master device to the slave device. It can propagate forward from the slave device to the master device and backward from the slave device to the master device. If a slave device is located farther away from the master than the slave device itself, If you want to transfer data to another slave device that is also connected to the same bus, you can do so as shown in Figure 16B. As shown, in the forward direction, i.e., in the fields labeled D0 to D7, In various embodiments, the system transmits control data (register reads, Isochronous voice (PDM and PCM), heterochronous voice (PCM), and Bulk transfer operations may also be supported.

[0134] The table below provides a guide to suiting various bandwidth requirements for signal integrity determination. The following lists registers that allow fine-tuning of the interface of some embodiments. will cause the interface to start with default values ​​after a reset is applied. In this embodiment, the TX delay is coded to ensure compatibility with multi-drop configurations. The RX delay is stored as a signed two's complement value. Due to delays in the PLL / DLL, a negative offset may exist. If register F If the value of is the same as the value of register G, no block data will be transferred. If If the value of register J is the same as the value of register K, no block data will be transferred. In this embodiment, all register values ​​are counted in half clock increments, and the TX and Except for the RX Delay register, all register values ​​are positive (single byte).

[0135] Refer to the table below to determine the TX delay to ensure compatibility with multi-drop configurations. The RX delay is stored as a signed two's complement value. The RX delay is stored as a signed two's complement value. The offset is stored in register F, and there may be a negative offset due to delays in the PLL. If the value is the same as the value in register G, no block data will be transferred. If the value of register J is the same as the value of register K, no block data will be transferred. All register values ​​are counted in half clock increments, except for the TX and RX delay registers. In this case, all register values ​​are positive (single byte). [Table 9]

[0136] A summary of the frames is shown in Figure 17. The boxes in the first and last columns are The synchronous clock is driven at a rate of 3.072MHz by the following two lines of specific boxes (e.g., OP,ID,##,C,FA,SA) is the command field driven by the master. The box labeled M represents the audio data from the master to the slave. The box labeled S contains the voice data or response from the slave to the master. The boxes labeled 1 in the second column indicate turnaround delays or logic 1s. The box labeled T may contain a master to slave turnaround time. In the illustrated embodiment, one string is a multi-drop, multi-write application. Most rows are dedicated to a single device. However, with careful timing control as described herein, sharing is also possible. .

[0137] To conserve bandwidth, register read and write operations are first It updates the internal address register of the device and then initiates the actual read or write operation. In this way, the read and write operations can be repeated. When doing so, it would be unnecessary to transfer the address with every command.

[0138] The command requires at least two errors to cause an unexpected behavior. Although the code is encoded with redundancy as shown here, there are usually many more blocks before this situation even occurs. An error is required. The operation was designed with conservative operation in mind - possible malfunctions Rather than trying to take action and proceed, any single error will result in no action being taken. The command is built on the following symbols {A,B,C,D}. The symbols are , which is defined as follows: A={D2,D1,D0}={1,0,0} B={D2,D1,D0}={0,1,0} C={D2,D1,D0}={0,0,1} D={D2,D1,D0}={1,1,1} These commands have a Hamming distance between them, i.e., one correct sequence. Two errors are required to map the symbol to another valid symbol. The value is considered a fault or an illegal symbol. F1={D2,D1,D0}={0,1,1} F2={D2,D1,D0}={1,0,1} F3={D2,D1,D0}={1,1,0} F4={D2,D1,D0}={0,0,0}

[0139] If any invalid symbol is encountered in a command, the command The request address may be ignored and the intended receiver shall return the request address at the end of this frame. Any ongoing blocking actions can be responded to with a Request Attention. should also be interrupted and only non-blocking operations will continue.

[0140] The command is defined by the opcode field, which can be 3 or 6. Configurable in bits. Only 24-bit reads from memory are possible with the shortened opcode. In other words, the specific opcode for "24-bit read" If a frame is encountered, the frame is read even before all six opcode bits are read. It should be immediately recognized as an extension frame.

[0141] Block operations are suitable for transferring large amounts of data to and from registers. These transfers are identified by dedicating special fields in the line to these types of transfers. has been protected from interfering with any voice transmission. Thus, voice transmission is This is done by the lowest hardware layer. This is to ensure that simple programming errors do not crash the bus. Reducing the time slots allocated to blocking operations to zero This means that no block is generated even if a frame contains multiple errors. This will ensure that the action is not taken.

[0142] In one embodiment, all block operations start with symbol A, followed by the second symbol, followed by one of these values: (i) “A” (stop blocking) - this block The block is the penultimate block in the sequence of block operations, and the next frame is the This is the last block containing frame data, i.e. the block transfer stops one frame late. (ii) “B” (Define the starting address for consecutive write operations) - Define The data is stored in memory starting from the specified starting address, and each of the next data words Then, the contents of the adjacent memory cell are stored, and the third frame from the current frame uses block transfer. (iii) “C” (contiguous) Define the starting address for subsequent read operations - Reads data starting from the defined starting address. The data is stored in memory, and each subsequent data word stores the contents of the adjacent memory cell. ,The third frame from the current frame uses block transfer, i.e., the block transfer is 2 frames. It will probably start with a frame delay.

[0143] In another embodiment, instead of using a "stop block operation", copy during bulk transfers. The number of elements to be scanned will be defined first along with the starting address. After the operation is initiated, the destination device itself performs all operations and waits for the end of the bulk transfer. Instead, an IRQ ("Request Attention") is generated to inform the master that the transfer is The master then checks if the bulk transfer was successful and checks if the CRC value is correct. It is now possible to access the state of the slave device to check This is also fine.

[0144] A single read and write operation first defines the starting address of the register operation, then After this, any subsequent operations can perform I / O operations using the address values ​​defined before it. The address definition for the subsequent register operations is done by sending the symbol D, followed by the symbol B.

[0145] Read and write operations with an address increment are performed by first incrementing the register. Defines a starting address, after which any subsequent operations use the address value defined before. It works by performing I / O operations using the After the operation is completed, any subsequent read or write operations inside the device will The subsequent register with the address increment will be The definition of the address for a master operation is to send the symbol D followed by the symbol C. It is defined as:

[0146] A single write operation is performed by sending symbol D followed by symbol A. The addresses used may need to be defined before using this action.

[0147] When performing a single read operation, the timing details of the bus are complex and may require multiple reads. The read operation will block all the bits of the second symbol. The behavior is completely defined by the first symbol, while the second symbol is ignored. (In this case, the master will not drive the bus.) Furthermore, the read operation It should start immediately after the symbol (the first three lines of the frame) has been read and interpreted. The ejection action is defined by the symbol C.

[0148] If the device ID number is 7, it performs a status read operation and connects to the bus. All connected devices (except the master) will return their status. The three bits returned from the INTEGER_TIME_HEADER are as follows (MSB returned first, LSB returned last): (will be): [Table 10]

[0149] If the device ID number is 7, it performs a status read operation and connects to the bus. All connected devices (except the master) will return their status. The three bits returned from the INTEGER_TIME_HEADER are as follows (MSB returned first, LSB returned last): will be done).

[0150] Devices 0-6 store the associated device status data in the corresponding AG field. (connected to bus, IRQ level) to respond. Since the previous value on the bus was 1, Therefore, all changes must be signaled using negative logic (zero active events). Only the last 21 bits of the possible 24 bits are used in this operation. A device may use dynamic address allocation to obtain this 3-bit address. , or a fixed device address (eg, programmed by pins) may be used. If dynamic address allocation is used, the device will initially be assigned address 0 If the master sets the ID to 0 during a read, indicates that the 24-bit CRC value should be read from the last bulk transfer port accessed. This will represent the first omission if the device state is being read. The opcode is "C", meaning that a second opcode is not being sent.

[0151] To return status from all devices connected to the bus, set the acknowledge and interest flags. A number of status flags are provided, including the confirmation flag, which indicates that the transaction was successful. and (e.g., a read or write verified by a 3-bit CRC value). Bus collisions that can occur when multiple devices try to drive the bus with different values. To avoid collisions, this is defined as an active logic low signal. If a device requires a read, it should drive this time slot low. Otherwise, the device should not drive any value in this time slot. Since this is a shared bit, all devices can respond to this time slot. An attention flag (e.g., AT) can be noticed by any device connected to the bus. Multiple devices may attempt to drive the bus with different values. To avoid possible bus collisions with When a device requests attention, it uses this time slot. should be driven low otherwise the device will No values ​​should be driven. To prevent a single error from causing a block transfer operation, the block transfer The number of command bits per row will be fully defined in the frame before By changing, for example, to upload a DSP program, to the register or Large amounts of data can be transferred very quickly from a register. Block transfers are done by This will only occur if a register that defines the start of a block transfer is assigned to it. If the block transfer register is If the register is equal to or greater than the following turnaround register, the block transfer command Even if a block has been issued, the block data will not be transferred. The lock data ensures that the audio data cannot be accidentally overwritten. An exemplary command table for encoding the commands is provided below: [Table 11]

[0152] 18A, 18B and 18C, a block transfer operation will now be described in further detail. As shown in frame 1802, the 32-bit address is assigned to the chair (not incremented on subsequent actions). Therefore, the device ID and initial value in column 2 are the values ​​sent after the command is As shown in frame 1804, As shown, a 32-bit address is assigned to the slave device (which is then As shown in frame 1806, the previously assigned You get a 24-bit read using the address (if ID=address 7, As shown in frame 1808, all connected Read status of the device that was specified (if ID=address 7, The first 3 bits of the 24-bit returned data are unused, the last Frame 1810 may be overwritten by the last Read status from a bulk transfer operation, e.g., from the last used bulk transfer port The 24-bit read CRC value is shown (if ID=address 0, the read (This is an exception to the SET command.) Frame 1812 is a previously assigned address. The slave device writes 32 bits using this until line 6. This is a possible write command. This means that it will be necessary to buffer the register data on lines 4, 5, and 6 in order to is doing.

[0153] Frame 1814 of FIG. 18B illustrates the start of a 32-bit block write transfer operation. Data is written two frames later (i.e., not in this frame, but in the next frame). The frame layer will start automatically until the third frame starts. Frame 1816 illustrates the transfer of write bulk data (continuously). Frame 1818 indicates the start of a 32-bit block bulk read transfer operation. The register data reading will not start until the third frame. Until the third frame begins, the frame layout is the same as the previous frame. (i.e., the bulk transfer has not yet started). D0 to D23 are assigned to devices 0 to 7. Each device has at most three bulk transfer ports. A value of 0 indicates that the port will be active for 2 frames. are assigned 3 bits (e.g. device 1 is assigned bits D3-D5, (Each corresponds to an internal bulk transfer port.) Frame 1820 is a read 1 illustrates the transfer of bulk data (continuous).

[0154] Frame Synchronization Algorithm The master will wait a period of time until the slave has achieved synchronization (PLL / DLL lock). Slave devices may connect to the bus at any supported speed. It allows the slave to read messages before starting communication. Embodiments are provided for checking whether message synchronization is obtained. In this mode, a single frame message is used. A beacon indicates the start of a frame. It can be used for synchronization and for

[0155] Referring now to FIG. 19, an embodiment of a frame synchronization algorithm 1900 will now be described. In step 1902, the process waits for the PLL or DLL to lock with the master. In step 1904, the shift register (SHIFT1) is set to 0xFFFF.FFF In step 1906, the first value is read from the first line and set to the second line. This process uses 32 lines to initialize the search register. In some embodiments, each line repeats at 3.072 MHz. This may provide sampling points for PDM and high quality audio. The frame is repeated over 32 lines, giving a frame repetition frequency of 96 kHz. In some embodiments, a beacon indicating the end of the frame is included in each second frame (48 kHz repetition rate).

[0156] The following steps are then repeated for 64 frames: A value is read from shift register 2. The value is the opposite of the new read value. If not, the first shift register This bit in the data is reset in step 1902. Otherwise, the processor The process proceeds to step 1912 to update the second shift register, SHIFT2. Step 1908 shifts both registers and completes 32 lines in a row. The process is then repeated for 64 frames. Check for alternating patterns. Therefore, frame synchronization can be achieved after 64 frames. In other words, the actual synchronization Instead of checking the position, the algorithm iterates through all the possible positions until only one valid position is left. This method works even if random data occurs in the command sequence. This ensures that the slave device is always locked. If the 32-bit register If after 64 frames, the frame still contains multiple set bits, The method is repeated until all invalid positions are eliminated.

[0157] In the illustrated embodiment, the only bit in the first shift register that is a 1 is the frame sync. In some embodiments, if the first shift register has a value of 1, If there are more than two bits, an error occurs and the algorithm should be restarted. This does not happen under normal circumstances (for random data, the probability of this happening is , 2 -64 <10 -20 It is expected that

[0158] In one implementation, all fields are oversampled using the master clock. One line of data is divided into 80 time slots, and multiple time slots are It is used to define the data on the network. All fields use the master clock. In this embodiment, the clock may be oversampled at the default clock frequency The frequency is set to 245.76 MHz, but other frequencies can be used. The initial PLL synchronization frequency is set to 3.072MHz for the master device and the , as described herein, other frequencies may also be used.

[0159] The interpretation of these time slots is that the individual fields will be in the same order, but At startup, the default data format will be The speed is set to match the diameter (slowest speed). are shown, showing the different fields in each line of data. By changing the interpretation of the time slot, various compromises between baud rate and bus diameter can be selected. The sync pattern repeats once per line of data. The periodic pattern is a transition from 0 to 1.

[0160] In the illustrated embodiment, one line is a sync field (0-1), a turnaround During the T1 period (when neither the master nor any slave device is allowed to change direction), This time slot is also a period of inactivity for forward commands (master The command field (CMD or response) contains the frame control information and the framing information F. R) and a field for transporting audio forward (typically from master to slave). field B1 for transporting bulk register data from the master to the slave; , a turnaround period T2 to allow a change in signal propagation direction, and then backwards (typically The MIDI field contains two fields for transporting audio (from slave to master) and for transporting audio (from slave to master). Field B2 to transport bulk data to the data recorder and field B3 to hold the data until the start of the next line. It contains an empty field for data alignment.

[0161] When the master issues a command to the command field, it must have a good timing margin. To ensure this, the master will also drive adjacent T1 fields with the same value. However, when the master is expecting a response from the slave device, the master The T1 and CMD fields will not be driven by any device. It is not driven by the device and is assigned to the data turnaround. If the device issues a response to the command field, it will only include the “CMD” field. The adjacent T1 field is not driven and is used for signal turnaround. The actual distance from the slave device to the master device may be unknown. Therefore, when a command is issued, the slave device sends an The actual delay will be measured by optimizing the timing, e.g. This may be used to optimize the signal eye diagram.

[0162] The number of time slots allocated to each of these fields depends on the application. Although it can vary, in the illustrated embodiment, the total number of time slots per line is 80. The startup default setting indicates the number of time slots at the start of each field. At power up, no time slots are allocated for bulk transfers.

[0163] T N The time slots marked are for turnaround delays. No actual data values ​​are defined within these time slots. The extension T1-T2 allows the data direction to be changed (i.e., from forward wave to backward wave and vice versa). The number of bits transmitted by the master and slave devices is It is subject to change and should be programmed before any transmission begins. In the example given above, the master sends 6 bits on each line to the slave, The slave transmits 4 bits on each line to the master. This example uses the default settings. The bandwidth allocated to the master and slave is programmed according to other settings. The synchronization pattern remains fixed regardless of the data organization. The number of time slots allocated per data bit for round-around etc. is programmed. By programming, the 100-MHz 10Gb / s ... This programmable nature allows for a significant increase in bandwidth. The controller determines how much bandwidth is available in each direction for synchronization, commands, and data. This trades off bandwidth for high signal integrity. It also allows programming of the slew rate and output transmit voltage. Optimize signal integrity while enabling your system to pass EMI requirements. It can be optimized.

[0164] When the master issues a command in the command field, the master To ensure a tight timing margin, adjacent T1 and T2 fields are driven with the same value. However, if the master is expecting a response from the slave device, When a slave device is in a slave mode, the master will not drive the T1, CMD, and T2 fields. When the slave device issues a response in the command field, the slave device writes “CMD "Only the T1 and T2 fields are driven, and the adjacent T1 and T2 fields are not driven, It will be used for synchronization from the slave device to the master device. The actual distance may be unknown. Therefore, when a command is issued, the slave device The actual delay from the timing This may be used to optimize the signal quality, for example, by optimizing the receiver eye diagram. While the values ​​used for data integrity are centered on each data unit, The master samples 1 / 2 data unit before normal sampling for latency optimization, i.e. , it will sample the slave delay on the edge between the two data values.

[0165] By using both edges of the clock, two times oversampling can be achieved. When a master issues a command in the command field, it The slave device will drive the “T” field that corresponds to the command field with the same value. When issuing a response in this mode, the slave device drives only the “R” field. The adjacent "T" field is not driven and is used for signal turnaround. If the bus diameter is short and the bus frequency is low, Leakage currents may change the bus value before a delay measurement can be performed. In this case, A bus holder is provided in the system to ensure that it has no effect on the delay measurement. The output impedance of such a bus holder is typically 1 to 2 It would be in the kΩ range.

[0166] A slave device, once it is locked, will report the device state by reporting the device status. The slave PLL circuit should acquire lock with the master within 1 ms. and a "PLL lock" signal for use by other control circuitry. In addition, the PLL should be able to output the logic signal (the "message sync" signal). The "message sync" signal is high. Once the slave PLL determines that it is in lock, it starts the narrow band In narrow bandwidth mode, the time gate is set to This would allow the output from the phase detector to be positive only in a narrow time window. If any of these signals are not active (high), the PLL performs wideband phase detection. out and slave devices should be prevented from writing to the bus. (Once this is done, other devices cannot be overwritten.)

[0167] Voice data travels in both directions over the link, i.e. from the master device to the slave device. It can be propagated forward from the slave device to the master device and backward from the slave device to the master device. A slave device sends data to another slave device that is located farther away from the master than the master device itself. When a slave device wants to forward audio, it will forward the The data is transmitted in the specified field.

[0168] Port Programming In various embodiments, data transfer is handled by port programming. To allow data to be transferred from any sending port to any receiving port, the data is stored in a module. Using this approach, stereo channels may be treated as and multi-channel systems require more bandwidth than situations where channels are treated as a group. This would result in a long programming sequence. However, this approach , is simpler and gives more flexibility for arbitrary data transfer.

[0169] Every register associated with a port will have a banked (shadow) register. The selection of main and shadow registers is accomplished by writing to the bank select register. Catastrophic changes to bus behavior due to changes in bank register values ​​caused by one or more errors. To prevent accidental changes, this register was specially protected. To change the value, you must enter a specific 8-bit value in a specific register to select bank number 1. A value needs to be written and there is a long space between these two words to select bank number 0. You need to write different 8-bit values ​​that have a small Hamming distance from one scenario to another. Change between two or more play modes without encountering glitches or distortions when changing scenarios A bank register is used to seamlessly perform the above steps. To avoid this, the group delay should be adjusted when changing filter configurations by using appropriate buffering. You may need to pay attention.

[0170] Allows any data to be freely transferred from any sending port to any receiving port To achieve this, both the transmitting and receiving ports can freely program the position of the data within the frame. For example, a row variable allows selection of the first row of data to be written. The line increment can be used to select the spacing between adjacent active lines. The column variable can be used to select the first column to be written, and the "last column" variable can be used to select the last column to which data is being written or read. The length of data (e.g., data word length) from a given data port can also be programmed. In some embodiments, a data value may extend over one or more frames, The synchronization of the beams may be programmed. This typically involves This is achieved by using beacon bits for

[0171] Bulk transfers require the start row, row increment, start column and stop column levels to be specified before the bulk transfer is enabled. A register may need to be defined. The bulk control bits indicate the bulk transfer command. Can be used to enable and disable bulk transfers only on ports that support bulk transfers. Use this bit, otherwise the value is ignored. Bulk transfers are performed by the port. It stores a 24-bit CRC check value of all bits transferred during the last bulk operation performed. Each device may have additional registers that hold the data. A bulk transfer port can only have one send port, and normally cannot have more than two bulk transfer ports. The bulk control registers are the starting registers (for example, 32-bit addresses) and , an end register (e.g., a 32-bit address) and a length register (e.g., 32 bits). A register, a flag indicating single or continuous transfer, and a read / write direction flag. Note that the port must be initially enabled to respond to a bulk transfer start command. The ports that are enabled during port forwarding must be written by the master. During the start of a bulk transfer operation, the 24-bit word is given Written by the master. Each device internally sets these bits (if any) 1. Assign the NIC to the bulk transfer port (if one is implemented).

[0172] power consumption For simple systems with modest bandwidth requirements, avoiding link termination can be This can significantly reduce power consumption. Instead, the transmitter reduces line impedance. To avoid any reflections from the transmitter side, ,The output impedance of the transmitter is relatively stable even during changes in output level. This is to ensure that there is no time zone where the output impedance suddenly becomes very high. This can be achieved by having multiple drivers that are activated sequentially, but only one at a time. Also, if there are only two devices located at each end of the transmission line, the reflection problem disappears. This eliminates the need for a series-terminated transmitter at either end of the link, allowing high speed and low power to be achieved. It is possible to achieve this.

[0173] By avoiding parallel termination, power consumption is reduced by (250mV signaling, 50pF 2 x 1 by capacitive charging only (based on load and 40Mbit signal transmission) 25μW = 250μW. In practical use, the receiver PLL (e.g., 25 0μW power consumption and the need to add some extra bandwidth for control overhead However, a power budget below 1 mW is unrealistic.

[0174] In various embodiments, the master should be able to wake up the slave. The slave should be able to wake up the master. To ensure low power consumption of the TI and all other circuits, the simplest zero power wave The backup (<1µA) mode uses a higher signal voltage (approximately 1V). In some implementations it would be possible to maintain the same signal voltage in all modes, but this would be more complicated. The master and receiver circuits must be turned on at all times (100 μA). It will write to the bus and tell it to start the next frame with a bus stall. For a chip-drop bus, this means that the nodes at the ends of the frame will not terminate. In the next frame, the master will need to enable the weak driver. A resistor (approximately 5kΩ) will be used to drive D+ to VDD. As long as D+ is at VDD, this means This indicates that the low power state is still active. The slave is A driver (approximately 600 Ω) is used to pull the D+ line to signal a wake-up event. This ensures a transition of at least 7ns (15pF or greater load). (If the standard 32.768kHz low-power wake-up clock is used by the master, To ensure that the master has registered the event (even if the master is not running), use this line must be pulled low for at least 50µs. At most 100 After μs, the slave disables the pull-down event and the master waits until the event is registered. After the bus has restarted, the bus will begin activating for at least 100 us.

[0175] PLL synchronization When the system is powered on, the slave device establishes synchronization with the master device. This can be achieved as follows: (i) The master must establish a (ii) The master transmits a fixed synchronization pattern (a transition from 0 to 1) in the All frames except for the time slots allocated for command responses and turnarounds. (iii) The PLL / DLL of the slave device is locked to the master. When this occurs, it is the “Slave Lock Status” bit (see EarLink Commands section). (iv) The master device then responds by activating the grams are possible.

[0176] In one embodiment, one line can hold 80 timers regardless of clock frequency and power mode. The sync pattern repeats once per line. The sync pattern is a 0 to 1 transition. Only the first 0 to 1 transition of a line / period is used by the slave device's PLL / DLL. Immediately following the sync time slot, this means that initially, one line contains a single 0 to This means that there can only be one transition to 1, and therefore the synchronization event of the PLL is uniquely defined. As long as the rising clock edge is used for synchronization, the slave's P The LL / DLL circuit should be able to acquire lock with the master within 1 ms. It is possible to output an internal "PLL / DLL lock" signal that may be used for other control circuits. In addition, the PLL / DLL should be synchronized with the logic signal ( "Message Sync" signal is high, If a slave PLL / DLL determines that it is locked, it switches to low bandwidth mode. In low bandwidth mode, the time gate synchronizes the output from the phase detector with the It will only tolerate narrow time windows around the edges. If these signals When either of these is not active (high), the PLL / DLL operates in wideband phase detection. (i.e., disable the phase / delay detector window gating logic and prevent bus collisions) (disable the slave output transmitter to avoid The slave should read the device state and thus detect when the slave has acquired the lock. In addition, this message is used to optimize delay timing for slave devices. This may take some time and should be completed before port forwarding can begin.

[0177] After synchronization is obtained, a window around the transition (e.g., + / - 3 time slots, i.e. , half of the 6-timeslot synchronous time slot) is free for the PLL / DLL The reason for the narrow time window used in the PLL is that The output from the phase detector must not be perturbed by any data communication on the bus. In this way, the PLL can be started with a wide, i.e., wide, reception bandwidth in the time domain. ,Then the input to the PLL synthesis unit needs to be time gated. The width of the window depends on the width of the time slot. A time slot is a time slot for a sequence of It is determined by one clock period of the PLL. For an internal clock frequency of 100 Hz x 96, it takes 6 ms to transmit one sync bit. In a system using 32-bit slots, this translates to approximately + / - 10.2ns. is (10 -12 (For bit error rate of For a given input, jitter up to about 727psRMS would be acceptable.

[0178] Where applicable, the various embodiments provided in this disclosure may be implemented in hardware, software, or other configurations. The present invention may be implemented using hardware, software, or a combination of hardware and software. Also, where applicable, the various hardware components presented herein and / or software components may be incorporated into the software without departing from the scope of this disclosure. may be combined into composite components comprising software, hardware and / or both. Where applicable, the various hardware components and and / or software components may be incorporated into the software without departing from the scope of this disclosure. The present invention may be separated into subcomponents comprising software, hardware and / or both. Where applicable, software components shall be and vice versa.

[0179] The foregoing disclosure is not intended to limit the disclosure to the precise form or particular area of ​​use disclosed. It is not intended to be limiting. Accordingly, various alternative embodiments and / or modifications to the present disclosure are contemplated herein. Nothing herein, whether expressly stated or implied, is available upon disclosure. Given the above embodiments of the present disclosure, it is contemplated that one skilled in the art may deviate from the scope of the present disclosure. It will be recognized that changes may be made in form and detail without departing from the spirit and scope of the present disclosure. It is limited only by the claims.

Claims

1. 1. A system comprising: a device controller coupled to a first interface for digital audio data communication according to a first communication protocol, the device controller including a master bus controller for controlling a multi-drop bus according to a second communication protocol; a first slave device coupled to the multi-drop bus and configured to receive digital audio data communications with the device controller according to the second communications protocol; each transmission line of the multi-drop bus is terminated with the first slave device attached at one end of the transmission line and the device controller attached at the other end of the transmission line; A system in which the power required for signaling on said multi-drop bus is obtained by a capacitive or inductive drop regulator, thereby minimizing power loss in said regulator.

2. A system comprising: a device controller coupled to a first interface for digital audio data communication according to a first communication protocol, the device controller including a master bus controller for controlling a multi-drop bus according to a second communication protocol; a first slave device coupled to the multi-drop bus and configured to receive digital audio data communications with the device controller according to the second communications protocol; each transmission line of the multi-drop bus is terminated with the first slave device attached at one end of the transmission line and the device controller attached at the other end of the transmission line; delays between components are measured by charging the multi-drop bus to a known value, disabling drivers at the beginning and end of the transmission lines to ensure that the multi-drop bus is floating and unterminated during measurement, waiting for the device controller to change levels on the multi-drop bus, and measuring a transition delay; the drivers on both ends of the transmission line are disabled while counting components connected to the multi-drop bus by allowing multiple drivers to change a current bus state; The current bus state is set by a controller; A system in which one or more devices can change the transmission line to an opposite value during a predetermined time window that allows for counting of the devices.

3. A system comprising: a device controller coupled to a first interface for digital audio data communication according to a first communication protocol, the device controller including a master bus controller for controlling a multi-drop bus according to a second communication protocol; a first slave device coupled to the multi-drop bus and configured to receive digital audio data communications with the device controller according to the second communications protocol; each transmission line of the multi-drop bus is terminated with the first slave device attached at one end of the transmission line and the device controller attached at the other end of the transmission line; A system in which each data port or data following each synchronization signal is modulated with a high frequency carrier to reduce voice band current modulation to reduce interference in voice systems.

4. A system comprising: a device controller coupled to a first interface for digital audio data communication according to a first communication protocol, the device controller including a master bus controller for controlling a multi-drop bus according to a second communication protocol; a first slave device coupled to the multi-drop bus and configured to receive digital audio data communications with the device controller according to the second communications protocol; each transmission line of the multi-drop bus is terminated with the first slave device attached at one end of the transmission line and the device controller attached at the other end of the transmission line; a phase locked loop (PLL) or a delay locked loop (DLL) providing timing information based on timing information provided by another device on the bus; A system that uses time gates to synchronize the PLL or DLL to another device based on time windows located around clock transitions, thereby ignoring data traffic and preventing the data traffic from interfering with acquiring and maintaining timing lock.

5. The system of any one of claims 1 to 4, wherein the second communications protocol supports multiple audio data rates using a fixed frame format.

6. 6. The system of claim 1, wherein the first slave device and a second slave device connected to the multi-drop bus are time-aligned such that a transmitted message is transmitted as a series of forward or backward propagating waves to enable multi-drop high speed bidirectional communication using the terminated transmission lines.

7. the second communication protocol uses differential signaling to reduce electromagnetic interference; A system as claimed in any preceding claim, wherein the first line is terminated to a logic high and the second line is terminated to a logic low to reduce common mode interference.

8. Differential signaling is used to reduce electromagnetic interference; The system of any one of claims 1 to 7, wherein the termination of each transmission line is handled by setting an output driver to either a high level or a low level according to the termination level when no data is being transferred and the multi-drop bus is idle, thereby reducing power consumption by the transmission endpoints.

9. 9. The system of claim 1, further comprising: a signaling rate greater than the minimum required signaling rate for a portion of each cycle, said signaling rate being greater than the minimum required signaling rate for a portion of each cycle, thereby reducing power consumption by idling said multi-drop bus, thereby reducing power dissipation at terminations.

10. 10. The system of claim 1, wherein the device controller further includes a phase locked loop that provides a first clock signal for synchronizing communications according to the first communication protocol, a second clock signal for synchronizing communications according to the second communication protocol, and a third clock signal used for voice data processing.

11. The system of any one of claims 1 to 10, wherein the second communication protocol supports a different communication bandwidth.

12. The system of any one of claims 1 to 11, wherein the second communication protocol supports different communication bandwidths using a fixed frame structure.

13. The system of any one of claims 1 to 12, wherein terminations at both ends of the transmission line are temporarily disabled during power-up of a device transmitter to reduce power consumption.

14. 1. A method comprising: a device controller transmitting and receiving digital audio data via a first interface according to a first communication protocol; the device controller controls a multi-drop bus including a plurality of transmission lines according to a second communication protocol; a first slave device coupled to the multi-drop bus receiving the digital audio data using the device controller according to the second communication protocol, the transmission line terminating at the device controller and the first slave device; using a phase locked loop or a delay locked loop to generate a first clock signal for synchronizing communications according to the first communications protocol, a second clock signal for synchronizing communications according to the second communications protocol, and a third clock signal used for audio data processing; The method, wherein the phase locked loop or the delay locked loop includes an input time gate that is used to synchronize on-clock transitions and ignore data traffic.

15. 15. The method of claim 14, wherein the second communications protocol supports multiple audio data rates using a fixed frame format.

16. The method of claim 14 or 15, wherein the device controller, the first slave device, and the second slave device include audio headsets.

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