CMOS circuits

Abstract

To provide a CMOS circuit having high resistance to a single event.SOLUTION: A CMOS circuit formed on a substrate of a first conductivity type comprises: a first logical operation circuit comprising a combination of a first transistor of the first conductivity type having a first well of a second conductivity type differing from the first conductivity type and a second transistor of the second conductivity type having a second well of the first conductivity type; and a transmission circuit that is connected to an output terminal of the first logical operation circuit and comprises any one or both of a third transistor of the first conductivity type and a fourth transistor of the second conductivity type. The third transistor and the fourth transistor have a gate terminal to which a well of a transistor of a different conductivity type of the first transistor and the second transistor or an output terminal of a second logical operation circuit comprising a combination of a fifth transistor of the first conductivity type having the first well and a sixth transistor of the second conductivity type having the second well and comprising an input terminal fixed to a predetermined electric potential is connected.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to CMOS circuits. [Background technology]

[0002] Conventionally, semiconductor integrated circuits such as CMOS (Complementary Metal Oxide Semiconductor) type LSI (Large Scale Integration), ASIC (Application Specific Integrated Circuit), FPGA (Field-Programmable Gate Array), GPU (Graphics Processing Unit), etc., have been used in various devices and equipment. In a CMOS type semiconductor integrated circuit, a function that performs a required operation is realized by forming a circuit by connecting a plurality of circuit elements such as transistors formed on a semiconductor substrate (e.g., a silicon substrate).

[0003] For example, CMOS type semiconductor integrated circuits used in outer space, such as artificial satellites orbiting the earth, are used in an environment where radiation such as high-energy charged particles is incident. It is also known that CMOS type semiconductor integrated circuits used on the ground are also affected by radiation such as neutrons. It is known that radiation incident on a CMOS type semiconductor integrated circuit can cause circuit elements formed on a semiconductor substrate to malfunction. More specifically, it is known that when a high-energy charged particle is incident on a CMOS type semiconductor integrated circuit, for example, a fluctuation in potential (so-called Single Event Transient: SET) or storage of erroneous data due to the propagation of a signal affected by the fluctuation in potential (so-called Single Event Upset: SEU) occurs.

[0004] Conventionally, various technologies have been disclosed for taking measures against single events such as single event transients and single event upsets (see Patent Document 1 and Non-Patent Document 1). For example, Patent Document 1 discloses that a circuit element is configured with a dual structure (vertical stacking structure) to prevent a malfunction caused by a single event generated by a high-energy charged particle from propagating to a downstream stage. For example, Non-Patent Document 1 discloses a technology relating to the design (structure) of an embedded circuit element that has increased resistance (robustness) against single event errors (soft errors). [Prior art documents] [Patent documents]

[0005] [Patent Document 1] JP 2004-048170 A [Non-patent literature]

[0006] [Non-Patent Document 1] S. Mitra, N. Seifert, M. Zhang, Q. Shi, KSKim, “Robust system design with built-in soft-error resilience”, IEEE Computer Society, vol.38, no.2, pp.43-52, Feb.2005, doi:10.1109 / MC.2005.70. Summary of the Invention [Problem to be solved by the invention]

[0007] However, the technology disclosed in Patent Document 1 is effective only when circuit elements are formed on a semiconductor substrate with an SOI (Silicon on Insulator) structure. A semiconductor substrate with an SOI structure has an insulating layer provided inside the substrate, and is therefore more expensive than, for example, a single crystal silicon substrate (so-called a bulk substrate). Furthermore, in recent years, the manufacturing process of a CMOS type semiconductor integrated circuit has become finer. For this reason, it is no longer possible to expect a countermeasure effect against a single event from a circuit element to which a conventional technology is applied, as the manufacturing process becomes finer. This is because, in the conventional technology, a countermeasure against a single event is taken by providing a spatial distance between each component constituting the circuit element, but when the manufacturing process becomes finer, the circuit elements formed on the semiconductor substrate become smaller, and it becomes impossible to ensure a necessary distance between each component, and the countermeasure effect against a single event by the conventional technology is nullified.

[0008] The present invention has been made based on the above-mentioned problem recognition, and has an object to provide a CMOS circuit that is highly resistant to single events. [Means for solving the problem]

[0009] In order to achieve the above object, a CMOS circuit according to one embodiment of the present invention is a CMOS circuit including a first logic operation circuit formed on a substrate of a first conductivity type, and a transmission circuit that transmits a signal of an output terminal of the first logic operation circuit, in which the first logic operation circuit includes a combination of a first transistor of the first conductivity type having a first well of a second conductivity type different from the first conductivity type, and a second transistor of the second conductivity type having a second well of the first conductivity type, and the transmission circuit is connected to the output terminal of the first logic operation circuit and includes either or both of a third transistor of the first conductivity type and a fourth transistor of the second conductivity type, and gate terminals of the third transistor and the fourth transistor include wells of transistors of different conductivity types from the first transistor and the second transistor, or a combination of a fifth transistor of the first conductivity type having the first well and a sixth transistor of the second conductivity type having the second well, and an output terminal of a second logic operation circuit having an input terminal fixed to a predetermined potential is connected to the CMOS circuit. Effect of the Invention

[0010] According to one aspect of the present invention, it is possible to increase the tolerance to single events in a CMOS circuit. [Brief description of the drawings]

[0011] [Figure 1] 1 is a diagram showing an example of the configuration of a CMOS circuit according to a first embodiment; [Diagram 2] 4 is a timing chart showing an example of a normal operation of the CMOS circuit according to the first embodiment. [Diagram 3] 2 is a diagram illustrating an example of a state in which high-energy charged particles are incident on the CMOS circuit according to the first embodiment. FIG. [Figure 4] 4 is a timing chart showing an example of an operation when a single event occurs due to a high-energy charged particle incident on the CMOS circuit according to the first embodiment. [Diagram 5]10 is a timing chart showing another example of the operation when a single event occurs due to a high-energy charged particle incident on the CMOS circuit according to the first embodiment. [Figure 6] FIG. 4 is a diagram showing another example of the configuration of the CMOS circuit according to the first embodiment. [Figure 7] FIG. 4 is a diagram showing another example of the configuration of the CMOS circuit according to the first embodiment. [Figure 8] FIG. 4 is a diagram showing another example of the configuration of the CMOS circuit according to the first embodiment. [Figure 9] FIG. 11 is a diagram showing an example of the configuration of a CMOS circuit according to a second embodiment. [Figure 10] FIG. 11 is a diagram showing another example of the configuration of the CMOS circuit according to the second embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0012] Hereinafter, with reference to the drawings, an embodiment of a CMOS (Complementary Metal Oxide Semiconductor) circuit of the present invention will be described. The CMOS circuit of the embodiment is a single logic operation circuit that performs a logic operation, such as a logical negation circuit (NOT circuit or inverter circuit), a logical sum circuit (OR circuit), a logical product circuit (AND circuit), a negative logical sum circuit (NOR circuit), a negative logical product circuit (NAND circuit), an exclusive logical sum circuit (EXOR circuit), or an exclusive logical sum circuit (EXNOR circuit). The CMOS circuit of the embodiment can be configured to hold data (signal level), such as a latch circuit or a flip-flop circuit, by combining a plurality of single logic operation circuits. Furthermore, the CMOS circuit of the embodiment can be configured to store (memorize) data (signal level), such as an SRAM (Static Random Access Memory), by combining a plurality of single logic operation circuits, flip-flop circuits, transmission gate circuits, etc.

[0013] First Embodiment In the following description, for ease of explanation, a logical negation circuit (hereinafter referred to as an "inverter circuit"), which is a logical operation circuit with the simplest configuration, will be described as an example of the CMOS circuit of the first embodiment.

[0014] [Inverter circuit configuration] Fig. 1 is a diagram showing an example of the configuration of a CMOS circuit (inverter circuit) according to the first embodiment. The inverter circuit 1 includes a P-channel MOS transistor P1, an N-channel MOS transistor N1, a P-channel MOS transistor P2, and an N-channel MOS transistor N2. The inverter circuit 1 shown in Fig. 1 is an example in which each transistor is formed on a P-type single crystal semiconductor substrate (bulk substrate).

[0015] The P-channel MOS transistor P1 has a gate terminal connected to the input terminal IN of the inverter circuit 1, a source terminal connected to the power supply VDD, and a drain terminal connected to the drain terminal of the N-channel MOS transistor N1. The N-channel MOS transistor N1 has a gate terminal connected to the input terminal IN of the inverter circuit 1, a source terminal connected to the ground GND, and a drain terminal connected to the drain terminal of the P-channel MOS transistor P1. The P-channel MOS transistor P2 has a gate terminal connected to the P-well Pw of the N-channel MOS transistor N1 (the body of the N-channel MOS transistor N1 in FIG. 1), a source terminal connected to the drain terminals of the P-channel MOS transistor P1 and the N-channel MOS transistor N1, and a drain terminal connected to the output terminal OUT of the inverter circuit 1. The N-channel MOS transistor N2 has a gate terminal connected to the N-well Nw of the P-channel MOS transistor P1 (the body of the P-channel MOS transistor P1 in FIG. 1), a source terminal connected to the drain terminals of the P-channel MOS transistor P1 and the N-channel MOS transistor N1, and a drain terminal connected to the output terminal OUT of the inverter circuit 1. The gate terminals of the P-channel MOS transistor P2 and the N-channel MOS transistor N2 may be connected to the corresponding wells by, for example, well contacts.

[0016] In the inverter circuit 1, the configuration of the P-channel MOS transistor P1 and the N-channel MOS transistor N1 is the configuration of a basic logical NOT circuit (inverter circuit) in a general logical operation circuit. In the following description, the inverter circuit of the basic configuration using the P-channel MOS transistor P1 and the N-channel MOS transistor N1 is called a "NOT circuit" to distinguish it from the inverter circuit 1 of the first embodiment. In the inverter circuit 1, the configuration of the P-channel MOS transistor P2 and the N-channel MOS transistor N2 is the configuration of a basic transmission gate circuit in a general semiconductor circuit. In other words, the inverter circuit 1 is configured to include a NOT circuit and a transmission gate circuit of a basic configuration, and the node of the output terminal of the NOT circuit (hereinafter referred to as "internal node Io") is connected to the input terminal of the transmission gate circuit.

[0017] The P-type single crystal semiconductor substrate is an example of a "first conductive type substrate" in the claims. The P-channel MOS transistor P1 is an example of a "first transistor" in the claims, and the N-channel MOS transistor N1 is an example of a "second transistor" in the claims. The N-well Nw is an example of a "first well" in the claims, and the P-well Pw is an example of a "second well" in the claims. The P-type and P-channel are examples of a "first conductive type" in the claims, and the N-type and N-channel are examples of a "second conductive type" in the claims. The NOT circuit is an example of a "first logic operation circuit" in the claims. The P-channel MOS transistor P2 is an example of a "third transistor" in the claims, and the N-channel MOS transistor N2 is an example of a "fourth transistor" in the claims. The transmission gate circuit is an example of a "transmission circuit" in the claims.

[0018] [Operation of inverter circuit] The operation timing of the inverter circuit 1 will be described below. First, normal operation of the inverter circuit 1 will be described. FIG. 2 is a timing chart showing an example of normal operation of the CMOS circuit (inverter circuit 1) according to the first embodiment. FIG. 2 is a timing chart showing a normal state in which high-energy charged particles of radiation are not incident on the inverter circuit 1. In the following description, the "High" level of each signal in the inverter circuit 1 is the level of the power supply VDD (hereinafter referred to as the "VDD level"), and the "Low" level is the level of the ground GND (hereinafter referred to as the "GND level").

[0019] FIG. 2 shows the timing at which the signals at the input terminal IN, the internal node Io, the output terminal OUT, the N-well Nw, and the P-well Pw change and their signal levels when an input signal is input to the input terminal IN of the inverter circuit 1 with the signal level changing between the VDD level and the GND level at a predetermined time interval.

[0020] In normal operation of the inverter circuit 1, an input signal input to the input terminal IN is inverted at a timing delayed by a predetermined delay time in the NOT circuit and output to the internal node Io. In the inverter circuit 1, the N-well Nw is at the VDD level, and the P-well Pw is at the GND level. Therefore, the P-channel MOS transistor P2 and the N-channel MOS transistor N2 provided in the transmission gate circuit are always in the ON state. Therefore, a signal output to the internal node Io by the NOT circuit in normal operation of the inverter circuit 1 (hereinafter referred to as the "internal signal") is transmitted at a timing delayed by a predetermined delay time in the transmission gate circuit, and output to the output terminal OUT.

[0021] Thus, in normal operation of the inverter circuit 1, the internal signal output by the NOT circuit is transmitted by the transmission gate circuit and output as an output signal to the output terminal OUT. In other words, in normal operation of the inverter circuit 1, like a general logical NOT circuit, the input signal input to the input terminal IN of the inverter circuit 1 is inverted and output to the output terminal OUT.

[0022] Next, the operation when high-energy charged particles of radiation are incident on the inverter circuit 1 will be described. FIG. 3 is a diagram showing a schematic example of a state in which high-energy charged particles are incident on the CMOS circuit (inverter circuit 1) according to the first embodiment. FIG. 3 shows a case in which a high-energy charged particle E of radiation R is incident on a NOT circuit constituting the inverter circuit 1. Due to the incident charged particle E, a single event transient corresponding to the charge of the incident charged particle E also occurs in the inverter circuit 1. It is known that the incident charged particle E has a greater effect on transistors in an off state than on transistors in an on state.

[0023] 4 and 5 are timing charts showing an example of the operation when a single event occurs due to a high-energy charged particle incident on the CMOS circuit (inverter circuit 1) according to the first embodiment. Fig. 4 is a timing chart showing the case where a charged particle E is incident when a GND level signal is input to the input terminal IN of the inverter circuit 1, and Fig. 5 is a timing chart showing the case where a charged particle E is incident when a VDD level signal is input to the input terminal IN of the inverter circuit 1.

[0024] First, the timing chart shown in Figure 4 will be explained. When a charged particle E is incident on the NOT circuit at timing t1 when a GND level signal is being input to the input terminal IN of the inverter circuit 1, the potential of the N-channel MOS transistor N1, which is in the OFF state and which constitutes the NOT circuit, fluctuates transiently according to the charge of the incident charged particle E. This causes an instantaneous pulse of the GND level to appear at the internal node Io, which is the output signal of the NOT circuit. This is a single event transient.

[0025] The right side of FIG. 4 shows the period during which the single event transient occurred in an enlarged manner, and shows the detailed timing and the signal level. With the occurrence of the single event transient, for example, the potential level of the N-well Nw drops, and the potential level of the P-well Pw rises. The right side of FIG. 4 shows an example in which the potential level of the N-well Nw drops to the GND level, and the potential level of the P-well Pw rises to a level between the VDD level and the GND level. The difference in the amount of fluctuation in the potential level in each well shown on the right side of FIG. 4 is an example based on the assumption that the potential level of the N-well Nw fluctuates more than that of the P-well Pw because the semiconductor substrate forming the CMOS circuit is a P-type single crystal semiconductor substrate, and the amount of fluctuation in the potential level in each well is considered to change depending on, for example, the charge of the charged particle E.

[0026] Then, the N-channel MOS transistor N2 constituting the transmission gate circuit is turned off due to the drop in the potential level of the N-well Nw, and the P-channel MOS transistor P2 constituting the transmission gate circuit is turned off due to the rise in the potential level of the P-well Pw. That is, the transmission gate circuit is turned off. On the right side of FIG. 4, the transmission gate circuit is in the off state from timing t1 to timing t2. As a result, the transmission gate circuit does not transmit (output) the internal signal including the single event transient outputted to the internal node Io by the NOT circuit as it is to the output terminal OUT. In other words, the transmission gate circuit excludes the transmission (output) of the single event transient included in the internal signal outputted to the internal node Io by the NOT circuit to the output terminal OUT. Alternatively, the transmission gate circuit reduces the single event transient included in the internal signal outputted to the internal node Io by the NOT circuit and transmits (outputs) it to the output terminal OUT. On the right side of FIG. 4, an example is shown in which the single event transient included in the internal signal of the internal node Io is reduced and transmitted (output) to the output terminal OUT.

[0027] Next, the timing chart shown in Fig. 5 will be described. When a charged particle E is incident on the NOT circuit at timing t3 when a VDD level signal is input to the input terminal IN of the inverter circuit 1, the potential of the P-channel MOS transistor P1, which is in the OFF state and which constitutes the NOT circuit, fluctuates according to the charge of the incident charged particle E. As a result, a momentary VDD level pulse appears at the internal node Io, which is the output signal of the NOT circuit.

[0028] On the right side of FIG. 5, the period during which the single event transient occurs is enlarged to show more detailed timing and its signal level. When the single event transient occurs, the transmission gate circuit is turned off, as in the case where a charged particle E is incident on the NOT circuit when a GND level signal is input to the input terminal IN of the inverter circuit 1 shown in FIG. 4. On the right side of FIG. 5, the transmission gate circuit is in the off state from timing t3 to timing t4. As a result, the transmission gate circuit does not transmit (output) the internal signal including the single event transient output by the NOT circuit to the internal node Io as it is to the output terminal OUT. On the right side of FIG. 5, an example is shown in which the single event transient included in the internal signal of the internal node Io is reduced and transmitted (output) to the output terminal OUT.

[0029] In this way, in the inverter circuit 1, the internal signal of the internal node Io, including the single event transient generated in the NOT circuit by the incident charged particle E, is prevented from being output to the output terminal OUT by the transmission gate circuit being turned off. In other words, in the inverter circuit 1, the single event transient output to the output terminal OUT is eliminated or reduced by the transmission gate circuit turned off by the incident charged particle E. As a result, the inverter circuit 1 does not propagate the single event transient generated inside the inverter circuit 1 to, for example, another CMOS circuit connected in the rear stage of the inverter circuit 1. As a result, in a CMOS type semiconductor integrated circuit including the inverter circuit 1, it is possible to prevent a single event upset in which erroneous data is stored due to the propagation of a signal including the generated single event transient. In other words, it is possible to increase the resistance to a single event generated by the incident charged particle E to the CMOS circuit.

[0030] [Other CMOS circuit configurations] In the above description, the inverter circuit 1 has been described as an example of the CMOS circuit of the first embodiment. However, the CMOS circuit of the first embodiment may have another configuration different from the inverter circuit 1. Hereinafter, an example of the configuration of a CMOS circuit other than the inverter circuit 1 in the CMOS circuit of the first embodiment will be described. FIGS. 6 to 8 are diagrams showing another example of the configuration of the CMOS circuit according to the first embodiment.

[0031] 6 is an example of a two-input NAND circuit. The NAND circuit 2 includes a P-channel MOS transistor P1A, a P-channel MOS transistor P1B, an N-channel MOS transistor N1A, an N-channel MOS transistor N1B, a P-channel MOS transistor P2, and an N-channel MOS transistor N2. The NAND circuit 2 shown in FIG. 6 is an example in which each transistor is formed on a P-type single crystal semiconductor substrate.

[0032] In the NAND circuit 2, the configuration of the P-channel MOS transistor P1A, the P-channel MOS transistor P1B, the N-channel MOS transistor N1A, and the N-channel MOS transistor N1B is the configuration of a basic NAND circuit (NAND circuit) in a general logic operation circuit. In the NAND circuit 2, the configuration of the P-channel MOS transistor P2 and the N-channel MOS transistor N2 is the same as the transmission gate circuit in the inverter circuit 1. That is, the NAND circuit 2 includes a NAND circuit and a transmission gate circuit of a basic configuration, and an internal node Io of the output terminal of the NAND circuit is connected to the input terminal of the transmission gate circuit. In the NAND circuit 2, a P-well Pw common to the N-channel MOS transistor N1A and the N-channel MOS transistor N1B is connected to the gate terminal of the P-channel MOS transistor P2, and an N-well Nw common to the P-channel MOS transistor P1A and the P-channel MOS transistor P1B is connected to the gate terminal of the N-channel MOS transistor N2. The connection between the gate terminal of the P-channel MOS transistor P2 and the P-well Pw common to the N-channel MOS transistor N1A and the N-channel MOS transistor N1B, and the connection between the gate terminal of the N-channel MOS transistor N2 and the N-well Nw common to the P-channel MOS transistor P1A and the P-channel MOS transistor P1B may be made by, for example, a well contact.

[0033] The P-channel MOS transistor P1A and the P-channel MOS transistor P1B are an example of a "first transistor" in the claims, and the N-channel MOS transistor N1A and the N-channel MOS transistor N1B are an example of a "second transistor" in the claims. A basic NAND circuit is an example of a "first logic operation circuit" in the claims.

[0034] In the NAND circuit 2, in normal operation, like a general NAND circuit, an output signal corresponding to the input signals input to the input terminals INA and INB of the NAND circuit 2 is output to the output terminal OUT. Like the inverter circuit 1, the NAND circuit 2 also eliminates or reduces the transmission (output) of an internal signal including a single event transient generated in any of the transistors in the off state in response to the incident high-energy charged particle E to the output terminal OUT by a transmission gate circuit that is turned off by the incident charged particle E.

[0035] 7 is an example of a two-input NOR circuit. The NOR circuit 3 includes a P-channel MOS transistor P1A, a P-channel MOS transistor P1B, an N-channel MOS transistor N1A, an N-channel MOS transistor N1B, a P-channel MOS transistor P2, and an N-channel MOS transistor N2. The NOR circuit 3 shown in FIG. 7 is an example in which each transistor is formed on a P-type single crystal semiconductor substrate.

[0036] In the NOR circuit 3, the configuration of the P-channel MOS transistor P1A, the P-channel MOS transistor P1B, the N-channel MOS transistor N1A, and the N-channel MOS transistor N1B is the configuration of a basic NOR circuit (NOR circuit) in a general logical operation circuit. In the NOR circuit 3, the configuration of the P-channel MOS transistor P2 and the N-channel MOS transistor N2 is the same as the transmission gate circuit in the inverter circuit 1. That is, the NOR circuit 3 includes a NOR circuit and a transmission gate circuit of a basic configuration, and an internal node Io of the output terminal of the NOR circuit is connected to an input terminal of the transmission gate circuit. In the NOR circuit 3, a P-well Pw common to the N-channel MOS transistors N1A and N1B is connected to the gate terminal of the P-channel MOS transistor P2, and an N-well Nw common to the P-channel MOS transistors P1A and P1B is connected to the gate terminal of the N-channel MOS transistor N2.

[0037] A basic NOR circuit is an example of the "first logic operation circuit" in the claims.

[0038] In the NOR circuit 3, in normal operation, like a general NOR circuit, an output signal corresponding to the input signals input to the input terminals INA and INB of the NOR circuit 3 is output to the output terminal OUT. Like the inverter circuit 1, the NOR circuit 3 also eliminates or reduces the transmission (output) of an internal signal including a single event transient generated in any of the transistors in the off state in response to the incident high-energy charged particle E to the output terminal OUT by a transmission gate circuit that is turned off by the incident charged particle E.

[0039] FIG. 8 is an example of a D-type flip-flop circuit (hereinafter referred to as a "D-FF circuit") configured with six inverter circuits 1 (inverter circuits 1-1 to 1-6) and four transmission gates TMG (transmission gates TMG-1 to TMG-4). The D-FF circuit 4 shown in FIG. 8 is configured by replacing each inverter circuit (NOT circuit) in a general D-type flip-flop circuit configured with six inverter circuits (NOT circuits) and four transmission gates TMG with the inverter circuit 1 of the first embodiment. In FIG. 8, each component included in the inverter circuits 1-1 to 1-6 is indicated by a logic gate symbol. The D-FF circuit 4 shown in FIG. 8 is an example in which each transistor is formed on a P-type single crystal semiconductor substrate.

[0040] In the normal operation, the D-FF circuit 4 also delays the state change of the input signal input to the input terminal D according to the clock signal CLK, outputs it to the output terminal Q, and holds the state of the output terminal Q, as in the case of a general D-type flip-flop circuit. More specifically, the D-FF circuit 4 takes in the input signal of the input terminal D at the timing of the falling edge of the clock signal CLK, outputs it to the output terminal Q at the timing of the rising edge of the clock signal CLK, and holds the output state of the output signal to the output terminal Q when the clock signal CLK is in another state. In FIG. 8, the clock signal CLKB is an inverted clock signal of the clock signal CLK. In the D-FF circuit 4, in each inverter circuit 1, an internal signal including a single event transient generated in any of the transistors in the OFF state in response to the incident high-energy charged particle E is prevented or reduced from being transmitted (output) to the output terminal Q by a transmission gate circuit that is turned off by the incident charged particle E. This makes it possible to prevent a single event upset in which erroneous data is stored in the D-FF circuit 4. FIG. 8 shows the D-FF circuit 4 configured to prevent a single event upset by replacing six inverter circuits (NOT circuits) with the inverter circuit 1, but the four transmission gates TMG provided in the D-FF circuit 4 may also be configured to be connected to transmission gate circuits that are turned off by the incident charged particle E.

[0041] The operation of each CMOS circuit shown in FIG. 6 to FIG. 8 when eliminating or reducing a single event transient can be easily understood by considering it as the operation when a high-energy charged particle is incident on the inverter circuit 1 shown in FIG. 3 to FIG. 5. Therefore, detailed description of the operation of each CMOS circuit shown in FIG. 6 to FIG. 8 when eliminating or reducing a single event transient is omitted. Furthermore, as described above, various configurations of the CMOS circuit are conceivable in addition to the respective CMOS circuits shown in FIG. 6 to FIG. 8. These configurations may be configured to be equivalent to the configuration of the inverter circuit 1 shown in FIG. 1 and the CMOS circuits (NAND circuit 2, NOR circuit 3, D-FF circuit 4) shown in FIG. 6 to FIG. 8. Furthermore, as described above, the CMOS circuit may be configured as a memory that stores data (signal level) by combining a plurality of independent logic operation circuits, flip-flop circuits, transmission gate circuits, etc., such as SRAM. The transmission gate circuit that constitutes this memory is a component for realizing the function of the memory. For this reason, a transmission gate circuit for eliminating or reducing a single event transient may also be connected to the transmission gate circuit that constitutes the memory. These operations can be easily understood by considering them as operations occurring when high-energy charged particles are incident on the inverter circuit 1 shown in Figures 3 to 5. Therefore, detailed descriptions of various possible configurations and operations in a CMOS circuit will be omitted.

[0042] As described above, in the CMOS circuit of the first embodiment, a transmission gate circuit that is turned off by an incident charged particle E is connected to the output terminal of the logic operation circuit of the basic configuration, and the output terminal of the transmission gate circuit is the output terminal of the CMOS circuit. With this configuration, in the CMOS circuit of the first embodiment, the single event transient generated in the logic operation circuit in response to the incident charged particle E is prevented or reduced from being transmitted (output) to the output terminal. As a result, in the CMOS circuit of the first embodiment, it is possible to prevent a single event transient generated inside the CMOS circuit from being propagated to, for example, another CMOS circuit connected in the subsequent stage of the CMOS circuit. Furthermore, in the CMOS circuit of the first embodiment, it is possible to prevent a single event upset in which a single event transient generated inside the CMOS circuit is propagated and erroneous data is stored. In other words, it is possible to realize a CMOS circuit with improved resistance to the incidence of charged particles E.

[0043] As a result, the semiconductor integrated circuit having the function realized by the CMOS circuit of the first embodiment can reduce the possibility of malfunction even when used in an environment where high-energy charged particles E are incident, such as outer space. In other words, by realizing the function with the CMOS circuit of the first embodiment, a highly reliable semiconductor integrated circuit can be realized that is less likely to malfunction due to the influence of the usage environment. Therefore, the semiconductor integrated circuit having the function realized by the CMOS circuit of the first embodiment can obtain the same effect even when used in environments where high reliability is required, such as for example, industrial equipment, automotive use, and medical use, other than outer space.

[0044] In the CMOS circuit of the first embodiment, the gate terminals of the respective transistors in the transmission gate circuit are connected to wells of transistors of different conductivity types in the logic operation circuit of the basic configuration, so that the transmission gate circuit is turned off by the incident charged particles E. However, the configuration for turning off the transmission gate circuit by the incident charged particles E may be other configurations.

[0045] <Second embodiment> Hereinafter, a CMOS circuit according to the second embodiment will be described. In the following description, for ease of explanation, a logical negation circuit (inverter circuit), which is a logical operation circuit with the simplest configuration, will be described as an example of the CMOS circuit according to the second embodiment.

[0046] [Inverter circuit configuration] Fig. 9 is a diagram showing an example of the configuration of a CMOS circuit (inverter circuit) according to the second embodiment. The inverter circuit 1A includes a P-channel MOS transistor P1, an N-channel MOS transistor N1, a P-channel MOS transistor P2, an N-channel MOS transistor N2, a P-channel MOS transistor P3, an N-channel MOS transistor N3, a P-channel MOS transistor P4, and an N-channel MOS transistor N4. The inverter circuit 1A shown in Fig. 9 is an example in which each transistor is formed on a P-type single crystal semiconductor substrate.

[0047] In the inverter circuit 1A, the configuration of the P-channel MOS transistor P1 and the N-channel MOS transistor N1, the configuration of the P-channel MOS transistor P3 and the N-channel MOS transistor N3, and the configuration of the P-channel MOS transistor P4 and the N-channel MOS transistor N4 are each a general logical NOT circuit (NOT circuit). The input terminal of the NOT circuit composed of the P-channel MOS transistor P1 and the N-channel MOS transistor N1 is connected to the input terminal IN, similar to the NOT circuit included in the inverter circuit 1 of the first embodiment. The internal node Io of the output terminal of this NOT circuit is connected to the input terminal of the transmission gate circuit composed of the P-channel MOS transistor P2 and the N-channel MOS transistor N2. The input terminal of the NOT circuit composed of the P-channel MOS transistor P3 and the N-channel MOS transistor N3 (hereinafter referred to as "NOT circuit A") is connected to the ground GND, and the output terminal is connected to the gate terminal of the N-channel MOS transistor N2 that constitutes the transmission gate circuit. An input terminal of a NOT circuit (hereinafter referred to as "NOT circuit B") constituted by a P-channel MOS transistor P4 and an N-channel MOS transistor N4 is connected to a power supply VDD, and an output terminal is connected to a gate terminal of a P-channel MOS transistor P2 constituting a transmission gate circuit. The wells of the P-channel MOS transistor P1, the P-channel MOS transistor P3, and the P-channel MOS transistor P4 are a common N-well Nw. The wells of the N-channel MOS transistor N1, the N-channel MOS transistor N3, and the N-channel MOS transistor N4 are a common P-well Pw. The connection between the gate terminal of the N-channel MOS transistor N2 and the output terminal of the NOT circuit A, and the connection between the gate terminal of the P-channel MOS transistor P2 and the output terminal of the NOT circuit B may be performed, for example, in a wiring process in a manufacturing process of a CMOS type semiconductor integrated circuit.The output terminal of the transmission gate circuit formed by the P-channel MOS transistor P2 and the N-channel MOS transistor N2 is connected to the output terminal OUT, similar to the transmission gate circuit provided in the inverter circuit 1 of the first embodiment.

[0048] The P-channel MOS transistor P3 is an example of a "fifth transistor" in the claims, and the N-channel MOS transistor N3 is an example of a "sixth transistor" in the claims. The NOT circuit A is an example of a "second logic operation circuit" in the claims. The P-channel MOS transistor P4 is an example of a "seventh transistor" in the claims, and the N-channel MOS transistor N4 is an example of an "eighth transistor" in the claims. The NOT circuit B is an example of a "second logic operation circuit" in the claims.

[0049] In normal operation of the inverter circuit 1A, the input terminal of the NOT circuit A is fixed to the ground GND and therefore always outputs a "High" level (e.g., VDD level), and the input terminal of the NOT circuit B is fixed to the power supply VDD and therefore always outputs a "Low" level (e.g., GND level). Therefore, the P-channel MOS transistor P2 and the N-channel MOS transistor N2 provided in the transmission gate circuit are always in the ON state. For this reason, in normal operation of the inverter circuit 1A, the internal signal output to the internal node Io by the NOT circuit is transmitted with a timing delayed by a predetermined delay time in the transmission gate circuit and output to the output terminal OUT.

[0050] On the other hand, in the inverter circuit 1A, when a high-energy charged particle E is incident, a single event transient occurs in any of the transistors in the inverter circuit 1A that are in an off state in response to the charge of the incident charged particle E. For this reason, in the inverter circuit 1A, for the same reason as described in the first embodiment, the potential level of the N-well Nw common to the P-channel MOS transistors drops, and the potential level of the P-well Pw common to the N-channel MOS transistors rises. As a result, in the inverter circuit 1A, the NOT circuit A outputs a "Low" level, and the NOT circuit B outputs a "High" level. As a result, in the inverter circuit 1A, as in the inverter circuit 1 of the first embodiment, the transmission gate circuit is turned off in response to the incident high-energy charged particle E. As a result, in the inverter circuit 1A, as in the inverter circuit 1 of the first embodiment, the transmission (output) of an internal signal including a single event transient generated in any of the transistors in an off state in response to the incident high-energy charged particle E to the output terminal OUT is eliminated or reduced by the transmission gate circuit turned off by the incident charged particle E.

[0051] [Another configuration of the inverter circuit] Fig. 10 is a diagram showing another example of the configuration of a CMOS circuit (inverter circuit) according to the second embodiment. The inverter circuit 1B includes a P-channel MOS transistor P1, an N-channel MOS transistor N1, an N-channel MOS transistor N2, a P-channel MOS transistor P3, and an N-channel MOS transistor N3. The inverter circuit 1B shown in Fig. 10 is an example in which each transistor is formed on a P-type single crystal semiconductor substrate.

[0052] In the inverter circuit 1B, the transmission gate circuit of the inverter circuit 1A is configured only with an N-channel MOS transistor N2, and accordingly the NOT circuit B is eliminated. Therefore, the inverter circuit 1B can be configured as a CMOS circuit with a smaller circuit scale than the inverter circuit 1A.

[0053] The inverter circuit 1B has a different configuration of the transmission gate circuit, but its operation is the same as that of the inverter circuit 1A. Therefore, in the inverter circuit 1B, as in the inverter circuits 1 and 1A, an internal signal including a single event transient generated in any of the transistors in the off state in response to the incident high-energy charged particle E is prevented or reduced from being transmitted (output) to the output terminal OUT by the transmission gate circuit that is turned off by the incident charged particle E.

[0054] As described above, in the CMOS circuit of the second embodiment, a transmission gate circuit that is turned off by the output signal of the NOT circuit A and / or the NOT circuit B, which are composed of transistors having a common well, is connected to the output terminal of the logic operation circuit of the basic configuration, and the output terminal of the transmission gate circuit is the output terminal of the CMOS circuit. With this configuration, in the CMOS circuit of the second embodiment, the single event transient generated in the logic operation circuit in response to the incident charged particle E is prevented or reduced from being transmitted (output) to the output terminal. Here, the operation of the transmission gate circuit in the CMOS circuit of the second embodiment to the off state can be considered to be an operation caused by indirectly detecting a change in the potential level of the well. This is because, in the inverter circuit 1 of the first embodiment, the well is directly connected to the gate terminal of each transistor included in the transmission gate circuit, and therefore the transmission gate circuit is turned off by directly detecting a change in the potential level of the well, whereas in the CMOS circuit of the second embodiment, the transmission gate circuit is turned off by a change in the potential level of the output signal of the NOT circuit A and / or the NOT circuit B, which have a common well. Thus, although there is a difference between direct and indirect, in the CMOS circuit of the second embodiment as well, the transmission gate circuit is turned off upon detecting a fluctuation in the potential level of the well due to the incident high-energy charged particle E. As a result, in the CMOS circuit of the second embodiment as well, like the CMOS circuit of the first embodiment, an internal signal including a single event transient generated in any of the transistors in the off state in response to the charged particle E incident on the CMOS circuit is prevented or reduced from being transmitted (output) to the output terminal OUT.

[0055] As a result, in the CMOS circuit of the second embodiment, like the CMOS circuit of the first embodiment, it is possible to prevent a single event transient generated inside the CMOS circuit from being propagated to, for example, another CMOS circuit connected in a subsequent stage of the CMOS circuit, and it is possible to prevent a single event upset in which an generated single event transient is propagated and erroneous data is stored. In other words, like the CMOS circuit of the first embodiment, the CMOS circuit of the second embodiment can also increase resistance to the incidence of charged particles E. As a result, the CMOS circuit of the second embodiment can also realize a highly reliable semiconductor integrated circuit that is less likely to malfunction due to the influence of the usage environment.

[0056] As described above, according to the CMOS circuit of each embodiment, even if a single event transient occurs in the logic operation circuit due to incidence of high-energy charged particles of radiation from the usage environment, the occurrence of the single event transient can be prevented or reduced from being transmitted (output) to the output terminal OUT. As a result, a semiconductor integrated circuit having the function realized by the CMOS circuit of each embodiment can reduce the possibility of malfunction even when used in an environment where high-energy charged particles are incident, and can obtain high reliability.

[0057] In each of the above-mentioned embodiments, an example in which the transistors included in the CMOS circuit are formed on a P-type single crystal semiconductor substrate (bulk substrate) has been described. However, in addition to the P-type single crystal substrate, there are various other structures of semiconductor substrates, such as an N-type single crystal substrate and a P-type or N-type SOI structure substrate. The configuration and operation of the CMOS circuit in this case may be equivalent to the configuration and operation of the CMOS circuit formed on the above-mentioned P-type single crystal semiconductor substrate. Therefore, detailed description of the configuration and operation of the CMOS circuit formed on a semiconductor substrate other than the P-type single crystal semiconductor substrate will be omitted.

[0058] The above describes the form for carrying out the present invention using an embodiment, but the present invention is not limited to such an embodiment, and various modifications and substitutions can be made within the scope that does not deviate from the gist of the present invention. [Explanation of symbols]

[0059] 1, 1-1, 1-2, 1-3, 1-4, 1-5, 1-6, 1A, 1B... Inverter circuit 2. NAND circuit 3. NOR circuit 4...D-FF circuit P1, P1A, P1B, P2, P3, P4...P-channel MOS transistors N1, N1A, N1B, N2, N3, N4...N-channel MOS transistors Pw...P well Nw...N-well Io...Internal Node

Claims

1. A CMOS circuit comprising: a first logic operation circuit formed on a substrate of a first conductivity type; and a transmission circuit that transmits a signal of an output terminal of the first logic operation circuit, the first logic operation circuit includes a combination of a first transistor of the first conductivity type having a first well of a second conductivity type different from the first conductivity type, and a second transistor of the second conductivity type having a second well of the first conductivity type; the transmission circuit is connected to an output terminal of the first logic operation circuit, and includes a third transistor of the first conductivity type and a fourth transistor of the second conductivity type; a gate terminal of the third transistor is connected to the gate terminal of the third transistor by a well contact corresponding to the second well so that a fluctuation in potential of the second well of the second transistor, which is fixed to a ground potential and may occur due to a charge of the charged particle when the high-energy charged particle is incident on the first logic operation circuit, is directly input thereto; a gate terminal of the fourth transistor is connected to the gate terminal of the fourth transistor by a well contact corresponding to the first well so that a fluctuation in potential of the first well of the first transistor, which is fixed to a potential of a power supply and may occur due to a charge of the charged particle when the high-energy charged particle is incident on the first logic operation circuit, is directly input thereto; the transmission circuit is turned off when a fluctuation in the potential of the well is input, and prevents or reduces the signal of the output terminal, including a single event transient generated in the first logic operation circuit by the incidence of the charged particle, from being transmitted to the output of the CMOS circuit; CMOS circuit.

2. the transistor of the first conductivity type is a P-channel MOS transistor, The second conductivity type transistor is an N-channel MOS transistor.

2. The CMOS circuit of claim 1.

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