Semiconductor package and method for forming same

Abstract

To provide a semiconductor package which prevents warpage of the semiconductor package and peeling of a thermal interface material (TIM) layer on an interposer module, and to provide a method of forming the semiconductor package.SOLUTION: A semiconductor package 100 includes: an interposer module 120 on a package substrate 110; a TIM layer 140 on the interposer module; a TIM layer protective structure 170 on a side surface of the TIM layer and a side surface of the interposer module; and a package lid 130 on the interposer module, the TIM layer, and the TIM layer protection structure. The TIM layer protection structure comprises a TIM layer protection structure interface portion, the TIM layer protection structure interface portion is in contact with the side surface of the TIM layer and a side surface of a molding material layer 127 at an interface between the TIM layer and the molding material layer, continuously extends from the side surface of the TIM layer to the side surface of the molding material layer, and prevents the TIM layer from being peeled off from the molding material layer.SELECTED DRAWING: Figure 1A

Description

[Technical field]

[0001] This application claims priority from U.S. Provisional Patent Application No. 18 / 110009, filed February 15, 2023, all of which are incorporated herein by reference.

[0002] The present invention relates to semiconductor technology, and more particularly to semiconductor packages and methods of forming same. [Background technology]

[0003] A semiconductor package may include one or more semiconductor dies that are stacked or mounted on an interposer. During operation, the semiconductor dies may generate large amounts of heat. To improve performance, the generated heat can be dissipated.

[0004] The semiconductor package may include a thermal interface material (TIM) layer that aids in heat dissipation. In particular, the TIM layer may aid in transporting heat from the interposer (e.g., from the semiconductor chip on the interposer) to the package lid of the semiconductor package. The TIM layer may be particularly beneficial in large and advanced semiconductor packages. Summary of the Invention [Problem to be solved by the invention]

[0005] Thermal changes (e.g., heating, cooling) can cause a typical semiconductor package to warp (e.g., bow due to thermal stress). This package warpage can cause the TIM layer to delaminate from the interposer module, which can result in failure of the semiconductor package. In such package warpage, the TIM layer can delaminate from the top surface of the interposer module at the corners of the interposer module. [Means for solving the problem]

[0006] In some embodiments, a semiconductor package is provided that includes an interposer module on a package substrate, a thermal interface material (TIM) layer on the interposer module, a TIM layer protective structure on sides of the TIM layer and on sides of the interposer module, and a package lid on the interposer module, the TIM layer, and the TIM layer protective structure.

[0007] In some embodiments, a method of forming a semiconductor package is provided, the method including mounting an interposer module on a package substrate, disposing a thermal interface material (TIM) layer on the interposer module, disposing a package lid on the interposer module and the TIM layer, and forming a TIM layer protection structure on sides of the TIM layer and sides of the interposer module.

[0008] In some embodiments, a semiconductor package is provided, the semiconductor package comprising an interposer module on a package substrate, a thermal interface material (TIM) layer on the interposer module, a TIM layer protection structure located on the package substrate and around the interposer module and the TIM layer, the TIM layer protection structure having a thermal expansion coefficient in a range between 3 ppm / °C and 20 ppm / °C and a thermal conductivity of 1 W / m·K or greater, bonded to the package substrate and disposed around the interposer module, the TIM layer protection structure being formed within a volume bounded by the stiffener ring and the interposer module. the package lid includes a reinforcing ring disposed on the interposer module, a TIM layer, and a package lid located on the reinforcing ring, the interposer module, the TIM layer, and the TIM layer protection structure and in contact with an upper surface of the TIM layer and an upper surface of the TIM layer protection structure, the package lid includes a filling hole on the TIM layer protection structure and having a diameter in the range of 3 mm to 10 mm, a filling plug that closes the filling hole, a vent hole located on the TIM layer protection structure and having a diameter in the range of 3 mm to 10 mm, and a vent plug used to close the vent hole, the filling hole being located on a side of the interposer module opposite to the vent hole. Effect of the Invention

[0009] One or more embodiments of the present disclosure may include a TIM layer protection structure. The TIM layer protection structure may help protect the TIM layer and inhibit (e.g., prevent) the TIM layer from peeling off from the interposer module. Thus, the TIM layer protection structure may provide improved reliability and better heat dissipation performance of the entire semiconductor package. [Brief description of the drawings]

[0010] Aspects of embodiments of the present disclosure can be clearly understood through the following detailed description and the accompanying drawings, in which, in accordance with standard industry practice, various features are not drawn to scale and are used for illustrative purposes only, and in fact, dimensions of various features may be arbitrarily expanded or reduced to allow for clarity of illustration. [Figure 1A] FIG. 1A illustrates a side cross-sectional view of a semiconductor package in accordance with one or more embodiments. [Figure 1B] FIG. 1B illustrates an enlarged side cross-sectional view of a fill hole in a package lid according to one or more embodiments. [Figure 1C] FIG. 1C shows an enlarged side cross-sectional view of a vent hole in a package lid according to one or more embodiments. [Figure 1D] FIG. 1D illustrates a top view of the package lid shown in FIG. 1A according to one or more embodiments. [Figure 2A] FIG. 2A is a side cross-sectional view of an intermediate structure including a package substrate top bond pad and a package substrate bottom bond pad in accordance with one or more embodiments. [Figure 2B] FIG. 2B is a side cross-sectional view of an intermediate structure including a package substrate top layer and a package substrate bottom layer according to one or more embodiments. [Figure 2C]FIG. 2C is a side cross-sectional view of an intermediate structure including an opening in a top package substrate layer and an opening in a bottom package substrate layer in accordance with one or more embodiments. [Figure 2D] FIG. 2D illustrates a vertical cross-sectional view of an intermediate structure in which an interposer module can be mounted onto a packaging substrate (eg, via a flip-chip bonding (FCB) process) in accordance with one or more embodiments. [Figure 2E] FIG. 2E illustrates a vertical cross-sectional view of an intermediate structure where a package underfill layer may be formed on a package substrate according to one or more embodiments. [Figure 2F] FIG. 2F illustrates a vertical cross-sectional view of an intermediate structure in which a TIM layer can be attached to the top surface of an interposer module, according to one or more embodiments. [Figure 2G] FIG. 2G shows a side cross-sectional view of an intermediate structure where adhesive can be applied to a package substrate according to one or more embodiments. [Figure 2H] FIG. 2H illustrates a vertical cross-sectional view of an intermediate structure where a stiffener ring can be attached (eg, mounted) to a packaging substrate, in accordance with one or more embodiments. [Figure 2I] FIG. 2I shows a vertical cross-sectional view of an intermediate structure where a package lid can be attached to a stiffener ring, according to one or more embodiments. [Figure 2J] FIG. 2J illustrates a vertical cross-sectional view of an intermediate structure where a TIM layer protection structure has been applied to a semiconductor package, according to one or more embodiments. [Figure 2K] FIG. 2K illustrates a top view of an intermediate structure including a TIM layer protection structure on a package substrate according to one or more embodiments. [Figure 2L] FIG. 2L shows a vertical cross-sectional view of an intermediate structure including a fill plug and a vent plug, according to one or more embodiments. [Figure 2M] FIG. 2M illustrates a side cross-sectional view of an intermediate structure in which multiple solder balls may be formed on a package substrate according to one or more embodiments. [Diagram 3] FIG. 3 is a flow chart illustrating a method of forming a semiconductor package in accordance with one or more embodiments. [Figure 4A] FIG. 4A illustrates a top view of a first alternative design for a package lid according to one or more embodiments. [Figure 4B] FIG. 4B illustrates a top view of a second alternative design of a package lid according to one or more embodiments. [Figure 4C] FIG. 4C illustrates a top view of a third alternative design of a package lid according to one or more embodiments. [Diagram 5] FIG. 5 illustrates a side cross-sectional view of a fourth alternative design of a package lid according to one or more embodiments. [Figure 6] FIG. 6 illustrates a side cross-sectional view of a fifth alternative design of a package lid according to one or more embodiments. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0011] The following disclosure provides many different embodiments or examples for implementing different features of the provided subject matter. In order to briefly explain the present disclosure, specific embodiments of elements and arrangements are described below. These are, of course, merely for illustration and are not intended to be limiting. For example, in the following disclosure, a first feature formed above or on a second feature can include embodiments in which the first and second features are formed in direct contact, and can also include embodiments in which an additional feature is formed between the first and second features such that the first and second features are not in direct contact. The present disclosure may also repeatedly use the same component symbols or letters in multiple examples. The purpose of repetition is to provide a simplified and clear description, and not to limit the relationship of the various embodiments and / or configurations described.

[0012] Additionally, spatially relative terms such as "lower," "below," "bottom," "top," "upper," "top" and the like are used for simplicity of description to describe the relationship of one element or feature to another element(s) and feature(s) in the figures. The spatially relative terms are intended to encompass different orientations of the device for use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptions used herein may be interpreted accordingly. Unless otherwise noted, elements having the same reference number are presumed to have the same material composition and thickness within the same thickness range.

[0013] Thermal changes (e.g., heating, cooling) can cause a typical semiconductor package to warp (e.g., bow due to thermal stress). This package warpage can cause the TIM layer to delaminate from the interposer module, which can result in failure of the semiconductor package. In such package warpage, the TIM layer can delaminate from the top surface of the interposer module at the corners of the interposer module.

[0014] One or more embodiments of the present disclosure may include a TIM layer protection structure. The TIM layer protection structure may help protect the TIM layer and inhibit (e.g., prevent) the TIM layer from peeling off from the interposer module. Thus, the TIM layer protection structure may provide improved reliability and better heat dissipation performance of the overall semiconductor package. The TIM layer protection structure may be disposed in an air gap surrounding an interposer module (e.g., a semiconductor die / chip, an integrated fan-out chiplet, an integrated multiple logic chiplets, etc.), and between a package lid and a package substrate (e.g., an integrated circuit (IC) substrate).

[0015] In one or more embodiments, the TIM layer protective structure can be added to the semiconductor package after the package lid is attached to the package substrate on the interposer module. In one or more embodiments, the package lid can include a fill hole and a vent hole. A TIM layer protective structure material (e.g., a liquid material) can be injected into the fill hole, and gas (e.g., air, nitrogen, etc.) can be vented from the semiconductor package through the vent hole.

[0016] The TIM layer protection structure material can include, for example, a material such as an underfill material or a material similar to an underfill material. The TIM layer protection structure can have a coefficient of thermal expansion (CTE) between 3 ppm / °C and 20 ppm / °C. The TIM layer protection structure can have a thermal conductivity of 1 W / m·K or greater.

[0017] The TIM layer protection structure material can be cured to form a solid TIM layer protection structure. The TIM layer protection structure can form a strong bond between the package lid, the package substrate, and the interposer module (which can include, for example, a semiconductor die / chip). The TIM layer protection structure can be formed below the package lid, above the package substrate, and surrounding the interposer module.

[0018] A ratio of a thickness of the TIM layer protection structure to a thickness of the interposer module (e.g., a thickness of a chip) can be greater than 1.0 and less than 3.0. Additionally, the package lid can have a package lid length in a first direction, and the TIM layer protection structure can have a TIM layer protection structure length in a first horizontal direction. A ratio of the length of the TIM layer protection structure to the length of the package lid can range between 0.3 and 1.0. The package lid can also have a package lid width in a second horizontal direction perpendicular to the first horizontal direction, and the TIM layer protection structure can have a TIM layer protection structure width in the second horizontal direction. A ratio of the width of the TIM layer protection structure to the width of the package lid can range between 0.3 and 1.0.

[0019] 1A-1D provide different views of a semiconductor package 100 (e.g., an organic / silicon interposer package) in accordance with one or more embodiments. FIG. 1A shows a vertical cross-sectional view of the semiconductor package 100 in accordance with one or more embodiments. FIG. 1B shows an enlarged vertical cross-sectional view of a fill hole 131 in the package lid 130 in accordance with one or more embodiments. FIG. 1C shows an enlarged vertical cross-sectional view of a vent hole 133 in the package lid 130 in accordance with one or more embodiments. FIG. 1D shows a top view of the package lid 130 in accordance with one or more embodiments.

[0020] The semiconductor package 100 may include a package substrate 110, an interposer module 120 mounted on the package substrate 110, and a package lid 130 over the interposer module 120 and attached to the package substrate 110. The semiconductor package 100 may also include a TIM layer 140 on the interposer module 120. The semiconductor package 100 may also include a TIM layer protection structure 170 that may protect the TIM layer 140. In particular, the TIM layer protection structure 170 may inhibit or reduce peeling of the TIM layer 140 from a surface of the interposer module 120.

[0021] The package substrate 110 may include, for example, a core 112, a package substrate upper dielectric layer 114 formed on the core 112 (e.g., a first side or chip side of the package substrate 110), and a package substrate lower dielectric layer 116 formed on the core 112 (e.g., a second side or substrate side of the package substrate 110). In particular, the package substrate 110 may include a build-up film substrate, such as an Ajinomoto Build-up Film (ABF) substrate. That is, in at least one embodiment, each of the package substrate upper dielectric layer 114 and the package substrate lower dielectric layer 116 may be described as an ABF layer.

[0022] The core 112 can provide rigidity to the package substrate 110. The core 112 can include, for example, an epoxy resin, such as bismaleimide triazine epoxy (BT epoxy), and / or a woven glass laminate. The core 112 can alternatively or additionally include an organic material, such as a polymer material. In particular, the core 112 can include a dielectric polymer material, such as polyimide (PI), benzocyclobutene (BCB), or polybenzobisoxazole (PBO). Other suitable dielectric materials are within the contemplated scope of the present disclosure.

[0023] The core 112 may include one or more through vias 112a. The one or more through vias 112a may extend from a lower surface of the core 112 to an upper surface of the core 112. The one or more through vias 112a may enable electrical connection between the package substrate upper dielectric layer 114 and the package substrate lower dielectric layer 116. The one or more through vias 112a may include, for example, one or more layers and may include metals, metal alloys, and / or other metal-containing compounds (e.g., Cu, Al, Mo, Co, Ru, W, TiN, TaN, WN, etc.). Other suitable metal materials are within the contemplated scope of the present disclosure.

[0024] The package substrate lower dielectric layer 116 may include multiple layers, and may include a build-up film (e.g., ABF) in particular. The package substrate lower dielectric layer 116 may include an organic material, such as a polymer material. In particular, the package substrate lower dielectric layer 116 may include one or more layers of a dielectric polymer material, such as polyimide (PI), benzocyclobutene (BCB), or polybenzobisoxazole (PBO). Other suitable dielectric materials are also within the contemplated scope of the present disclosure.

[0025] The package substrate lower dielectric layer 116 may include one or more package substrate lower bonding pads 116a on the substrate-side surface of the package substrate lower dielectric layer 116. In particular, the package substrate lower bonding pads 116a may be exposed on the substrate-side surface of the package substrate lower dielectric layer 116. The package substrate lower dielectric layer 116 may also include one or more metal interconnect structures 116b. The metal interconnect structures 116b may be connected to the package substrate lower bonding pads 116a and the through vias 112a in the core 112. The metal interconnect structures 116b may include metal layers (e.g., copper traces) and metal vias connecting the metal layers. The package substrate lower bonding pads 116a and the metal interconnect structures 116b may include, for example, one or more layers and may include metals, metal alloys, and / or other metal-containing compounds (e.g., Cu, Al, Mo, Co, Ru, W, TiN, TaN, WN, etc.). Other suitable metal materials for the metal interconnect structure 116b are within the contemplated scope of the present invention.

[0026] The package substrate lower surface layer 110b can be formed on the substrate-side surface of the package substrate lower dielectric layer 116. The package substrate lower surface layer 110b can partially cover the package substrate lower bonding pad 116a. The package substrate lower surface layer 110b can include one or more of a passivation layer and a protective layer. The package substrate lower surface layer 110b can include a dielectric polymer material, such as, for example, polyimide (PI), benzocyclobutene (BCB), or polybenzobisoxazole (PBO). The package substrate lower surface layer 110b may alternatively or additionally include a low-k dielectric material, such as silicon oxide, silicon nitride, carbon-doped oxide, an extremely low-k dielectric material, such as porous carbon-doped silicon dioxide, or a combination thereof. Other suitable dielectric materials are within the intended scope of the present disclosure.

[0027] A ball grid array (BGA) including a plurality of solder balls 110c may be formed on the substrate-side surface of the package substrate lower dielectric layer 116. The solder balls 110c may allow the semiconductor package 100 to be securely mounted on a substrate such as a printed circuit board (PCB) and electrically coupled to the PCB substrate. The solder balls 110c may be in contact with the package substrate lower bonding pads 116a, respectively.

[0028] The package substrate upper dielectric layer 114 can be formed on the upper surface of the core 112. "The package substrate upper dielectric layer 114 may include multiple layers, and in particular may include a build-up film (e.g., ABF)" is omitted. The package substrate upper dielectric layer 114 can also include an organic material such as a polymer material. In particular, the package substrate upper dielectric layer 114 can include a dielectric polymer material such as polyimide (PI), benzocyclobutene (BCB), or polybenzobisoxazole (PBO). Other suitable dielectric materials are also within the intended scope of the present disclosure.

[0029] The package substrate top dielectric layer 114 may include one or more package substrate top bonding pads 114a on a chip-side surface of the package substrate top dielectric layer 114. In particular, the package substrate top bonding pads 114a may be exposed on the chip-side surface of the package substrate top dielectric layer 114. In at least one embodiment, a bonding pad surface layer (not shown) (e.g., one or more layers of metal (e.g., tin, nickel, palladium, gold, etc.) and / or other materials) may be formed on the package substrate top bonding pads 114a to improve solder joint reliability.

[0030] The package substrate top dielectric layer 114 may also include one or more metal interconnect structures 114b. The metal interconnect structures 114b may include metal layers (e.g., copper traces) and metal vias connecting the metal layers. The package substrate top bond pads 114a may be electrically connected to the solder balls 110c of the BGA through the metal interconnect structures 114b, the through vias 112a, the metal interconnect structures 116b, and the package substrate bottom bond pads 116a. The package substrate top bond pads 114a and the metal interconnect structures 114b may include, for example, one or more layers and may include metals, metal alloys, and / or other metal-containing compounds (e.g., Cu, Al, Mo, Co, Ru, W, TiN, TaN, WN, etc.). Other suitable metal materials are within the contemplated scope of the present invention.

[0031] The package substrate top surface layer 110a may be formed on the chip side of the package substrate top dielectric layer 114. The package substrate top surface layer 110a may include a coating layer, a laminate layer, etc. The package substrate top surface layer 110a may be formed to at least partially cover the package substrate top bonding pads 114a.

[0032] In at least one embodiment, the package substrate top surface layer 110a can include a solder resist layer (e.g., a solder mask layer). The solder resist layer can include a thin layer of a polymeric material (e.g., an epoxy polymer). The solder resist layer can have a thickness in the range of about 5 μm to 50 μm. In at least one embodiment, the solder resist layer can have a thickness in the range of about 10 μm to 30 μm. Thicker or thinner layers of the solder resist layer can be used. The solder resist layer can be formed to cover the package substrate top bonding pads 114a and other metal features (e.g., conductive lines, copper traces) on the chip-side surface of the package substrate 110. The solder resist layer can protect the package substrate top bonding pads 114a and other metal features from oxidation. The solder resist layer can also inhibit (e.g., prevent) the formation of solder bridges (e.g., unintended electrical connections) between closely spaced metal features. The solder resist layer may include solder resist openings (SROs) over the package substrate top bonding pads 114a, respectively. The top surfaces of the package substrate top bonding pads 114a may be exposed by the SROs. The SROs may have tapered sidewalls such that the diameter (in the XY plane) of the SROs decreases in a direction toward the package substrate top bonding pads 114a.

[0033] The package substrate top surface layer 110a may alternatively or additionally include layers other than a solder resist layer, such as a passivation layer or a protective layer. In particular, the package substrate top surface layer 110a may alternatively or additionally include a dielectric polymer material, such as polyimide (PI), benzocyclobutene (BCB), or polybenzobisoxazole (PBO), a low-k dielectric material, such as silicon oxide, silicon nitride, carbon-doped oxide, an ultra-low-k dielectric material, such as porous carbon-doped silicon dioxide, a combination thereof, or other suitable materials. The package substrate top surface layer 110a may alternatively or additionally be formed by, for example, chemical vapor deposition (CVD), physical vapor deposition (PVD), spin-coating, lamination, or other suitable deposition techniques.

[0034] The interposer module 120 may be mounted by controlled collapse chip connection (C4) bumps 121 on package substrate top bond pads 114a in the package substrate 110. The interposer module 120 may include an interposer dielectric layer 122 that may include metal interconnects 122a electrically connected to the C4 bumps 121. The interposer module 120 may also include a first semiconductor die 123 and a second semiconductor die 124 that may each be mounted on the interposer dielectric layer 122. It should be noted that any number of semiconductor dies may be mounted on the interposer dielectric layer 122.

[0035] The first semiconductor die 123 and the second semiconductor die 124 can be mounted on the interposer dielectric layer 122 by micro-bumps 128, which can be electrically connected to the metal interconnects 122a. A package underfill layer 129 can be formed under and around the interposer module 120 and the C4 bumps 121 to secure the interposer module 120 to the package substrate 110. The package underfill layer 129 can be formed of an epoxy-based polymer material.

[0036] Each of the first semiconductor die 123 and the second semiconductor die 124 may be, for example, a semiconductor chip or chiplet for high performance computing (HPC) applications, artificial intelligence (AI) applications, and 5G cellular network applications, a logic die (e.g., a mobile application processor, a microcontroller, etc.), or a memory die (e.g., a dynamic random access memory (DRAM) die, a wide I / O die, an M-RAM die, an R-RAM die, a NAND die, a static random access memory (SRAM), etc.), a central processing unit (CPU) chip, a graphics processing unit (GPU) chip, a field programmable gate array (FPGA) chip, a networking chip, an application specific integrated circuit (IC), or the like. The die may include application specific integrated circuits (ASIC) chips, artificial intelligence / deep neural network (AI / DNN) accelerator chips, co-processors, accelerators, on-chip memory buffers, memory cubes (e.g., HBM, HMC, etc.), high data rate transceiver dies, I / O interface dies, IPD dies (e.g., integrated passive devices), power management dies (e.g., power management integrated circuit (PMIC) dies), radio frequency (RF) dies, sensor dies, microelectromechanical systems (MEMS) dies, signal processing dies (e.g., digital signal processing (DSP) dies), front-end dies (e.g., analog front-end (AFE) dies), monolithic 3D heterogeneous chiplet stacking dies, and the like.

[0037] Each of the first semiconductor die 123 and the second semiconductor die 124 may include, for example, an active area (not shown). The active area may include a front-end-of-line (FEOL) area including electronic circuits including various electronic devices (e.g., transistors, resistors, etc.). In particular, the FEOL area may include one or more logic circuits including logic devices (e.g., logic gates), and / or one or more memory circuits including memory devices (e.g., volatile memory (VM) devices and / or non-volatile memory (NVM) devices). In particular, the active area may also include a back-end-of-line (BEOL) area that may include an interlayer dielectric having multiple dielectric layers. The dielectric layers may include, for example, SiO2, a dielectric polymer, or other suitable dielectric material. The interlayer dielectric may include one or more metal interconnect structures formed therein. The metal interconnect structures may include metal traces and metal vias formed in the dielectric layers to provide electrical connections to the electronic circuits in the FEOL area.

[0038] The interposer underfill layer 126 may be formed around the microbumps 128, between the first semiconductor die 123 and the interposer dielectric layer 122, and between the second semiconductor die 124 and the interposer dielectric layer 122. The interposer underfill layer 126 may be continuously formed under both the first semiconductor die 123 and the second semiconductor die 124, as shown in FIG. 1A. Alternatively, the interposer underfill layer 126 may be formed as separate portions under each of the first semiconductor die 123 and the second semiconductor die 124. The interposer underfill layer 126 may be formed between the first semiconductor die 123 and the second semiconductor die 124. The interposer underfill layer 126 may be formed of an epoxy-based polymer material.

[0039] A molding material layer 127 may be formed on the first semiconductor die 123, the second semiconductor die 124, the interposer underfill layer 126, and the interposer dielectric layer 122. The molding material layer 127 may be formed of an epoxy molding compound (EMC).

[0040] The TIM layer 140 can include, for example, gel TIM, graphite TIM, metal TIM, solder TIM, and carbon nanotube TIM. Other types of TIM are within the contemplated scope of the present disclosure. In at least one embodiment, the TIM layer 140 can be in the range of 30 μm to 150 μm. The TIM layer 140 can be formed on the interposer module 120 and can dissipate heat generated during operation of the semiconductor package 100 (e.g., operation of the first semiconductor die 123 and the second semiconductor die 124). The TIM layer 140 can be attached to the interposer module 120 by, for example, a thermally conductive adhesive. In particular, the TIM layer 140 can be in contact with a top surface of the first semiconductor die 123, a top surface of the second semiconductor die 124, a top surface of the molding material layer 127, and / or a top surface of the interposer underfill layer 126. The TIM layer 140 can have a low bulk thermal impedance and a high thermal conductivity. The bond-line-thickness (BLT) (eg, the distance between the package lid 130 and the interposer module 120) may be about 100 μm or less, although larger or smaller distances may be used.

[0041] The semiconductor package 100 may also include a stiffening ring 150 that may be secured to the package substrate 110 by an adhesive 160, such as a silicone adhesive or an epoxy adhesive. Other adhesives are within the contemplated scope of the present disclosure. The stiffening ring 150 may be formed of a metal, such as nickel-coated copper or an aluminum alloy. Alternatively, the stiffening ring 150 may be formed of a ceramic material or a hard plastic (polymer) material. The stiffening ring 150 may be formed on the package substrate 110 to surround the interposer module 120 in the xy plane. The stiffening ring 150 may extend substantially vertically (e.g., in the z direction) from the package substrate 110. The stiffening ring 150 may help provide rigidity to the package substrate 110 and the interposer module 120.

[0042] The package lid 130 may be connected to the stiffening ring 150 to cover the interposer module 120. The package lid 130 may be fixed to the stiffening ring 150 by an adhesive 161 (e.g., a silicone adhesive or an epoxy adhesive). The package lid 130 may contact at least a portion of the TIM layer 140. In one or more embodiments, the package lid 130 may directly contact the entire top surface of the TIM layer 140. The package lid 130 may be formed of, for example, a metal, a ceramic, or a polymer material. The package lid 130 may have a plate shape (e.g., a planar shape) and may be substantially parallel to the top surface of the package substrate 110. The package lid 130 may extend, for example, in the xy plane of FIG. 1A. The package lid 130 may include a central portion substantially aligned in the z-direction with a central portion of the interposer module 120.

[0043] The package lid 130 may include a bottom surface 130a and a top surface 130b opposite to the bottom surface 130a in the z direction. The package lid 130 may have a thickness T 130The bottom surface 130a of the package lid 130 may extend across the package lid 130 between opposing sides of the stiffening ring 150 and contact the TIM layer 140. The TIM layer 140 may be compressed between the bottom surface 130a of the package lid 130 and a top surface of the interposer module 120. The bottom surface 130a of the package lid 130 may be secured to the stiffening ring 150 by an adhesive 161. The bottom surface 130a may be substantially planar. In particular, the height (e.g., in the z-direction) of the bottom surface 130a from the package substrate top surface layer 110a may be substantially uniform across the entire bottom surface 130a. Alternatively, the package lid 130 may include a bottom step region (not shown) that may protrude from the bottom surface 130a and contact the TIM layer 140. The bottom step region may extend substantially vertically from the bottom surface 130a. A bottom step region may be formed around the central region of the package lid 130 .

[0044] The semiconductor package 100 may also include a TIM layer protection structure 170. The TIM layer protection structure 170 may help protect the TIM layer 140, and in particular, help inhibit (e.g., prevent) the TIM layer 140 from peeling off from the interposer module 120. Thus, the TIM layer protection structure 170 may provide improved reliability and better heat dissipation performance of the semiconductor package 100.

[0045] The TIM layer protection structure 170 can include a material substantially similar to the package underfill layer 129 and / or the interposer underfill layer 126. In at least one embodiment, the TIM layer protection structure 170 can include a polymer material, in particular an epoxy-based polymer material. In at least one embodiment, the TIM layer protection structure 170 can include additional materials (e.g., filler materials) to improve the properties (e.g., thermal conductivity, CTE, etc.) of the TIM layer protection structure 170. The added materials can include, for example, metal powders, metal oxide powders, etc. Other materials in the TIM layer protection structure 170 are within the intended scope of the present disclosure.

[0046] The TIM layer protection structure 170 may be located in the space surrounding the interposer module 120 (e.g., the air gap), between the interposer module 120 and the stiffener ring 150, and between the package lid 130 and the package substrate 110. In at least one embodiment, the TIM layer protection structure 170 may substantially fill the space surrounding the interposer module 120 (e.g., the air gap).

[0047] In at least one embodiment, the TIM layer protection structure 170 can have a coefficient of thermal expansion (CTE) between 3 ppm / °C and 20 ppm / °C. In at least one embodiment, the TIM layer protection structure can have a thermal conductivity of 1 W / m·K or greater. In at least one embodiment, the TIM layer protection structure can have a CTE greater than the CTE of the TIM layer. In at least one embodiment, the TIM layer protection structure can have a thermal conductivity greater than the thermal conductivity of the TIM layer. In at least one embodiment, the TIM layer protection structure 170 can be formed of a curable material that can be cured to form a hard, solid structure. The thickness T of the TIM layer protection structure 170 can be 0.01 to 0.01 mm. 170 and the thickness T of the interposer module 120 120 The ratio (e.g., chip thickness) can be greater than 1.0 and less than 3.0. The TIM layer protection structure 170 can form a strong bond between the package lid 130, the package substrate 110, and the interposer module 120. In at least one embodiment, the TIM layer protection structure 170 can be bonded to one or more of the bottom surface 130a of the package lid 130, the top surface of the package substrate 110, the outer surface (sidewall) of the TIM layer 140, the outer surface (sidewall) of the interposer module 120, the inner surface (sidewall) of the stiffener ring 150, the package underfill layer 129, the adhesive 160, and the adhesive 161.

[0048] In at least one embodiment, the TIM layer protection structure 170 can be added to the semiconductor package 100 through a fill hole 131 in the package lid 130. The package lid 130 can also include a vent hole 133 to facilitate the addition of the TIM layer protection structure 170. The package lid 130 can further include a fill plug 132 and a vent plug 134 for blocking the fill hole 131 and the vent hole 133, respectively. The fill plug 132 and the vent plug 134 can include a polymer material, in particular an epoxy-based polymer material. Other materials are within the contemplated scope of the present disclosure.

[0049] As shown in FIG. 1B, the filling hole 131 has a diameter D in the range of 3 mm to 10 mm. 131 (e.g., width). 131 can be substantially uniform across the height (in the z-direction) of the fill hole 131. In at least one embodiment, the diameter D 131 1B, the fill hole 131 can extend in the z-direction substantially perpendicular to the package lid 130. Alternatively, the fill hole 131 can be angled relative to the package lid 130.

[0050] The fill hole 131 can be located in a central region of the TIM layer protective structure 170. The fill hole 131 has an inner length L 131i The fill hole 131 can be separated from the interposer module 120 by an outer length L 131o In at least one embodiment, the fill holes 131 can be equidistant between the interposer module 120 and the stiffening ring 150 (e.g., L 131i =L 131o ).

[0051] The fill plug 132 may extend from a bottom surface 130a of the package lid 130 to a top surface 130b of the package lid 130. The top surface of the fill plug 132 may be substantially flush with the top surface 130b of the package lid 130. The bottom surface of the fill plug 132 may be substantially flush with the bottom surface 130a of the package lid 130. Thus, the thickness of the fill plug 132 may be less than the thickness T of the package lid 130. 130 The fill plug 132 can fill the entire fill hole 131 and completely seal the fill hole 131. The fill plug 132 can be adhesively bonded to the walls of the fill hole 131 throughout the fill hole 131.

[0052] 1B, the TIM layer protection structure 170 can include a TIM layer protection structure interface portion 170i. The TIM layer protection structure interface portion 170i can contact a side of the TIM layer 140 and a side of the molding material layer 127 (e.g., interposer module 120) at an interface between the TIM layer 140 and the molding material layer 127. The TIM layer protection structure interface portion 170i can extend continuously from the side of the TIM layer 140 to the side of the molding material layer 127, thereby helping to inhibit (e.g., prevent) the TIM layer 140 from peeling off from the molding material layer 127.

[0053] As shown in FIG. 1C, the gas vent hole 133 has a diameter D in the range of 3 mm to 10 mm. 133 (e.g., width). 133 can be substantially uniform across the height (in the z-direction) of the vent hole 133. In at least one embodiment, the diameter D 133 can vary over the height (in the z-direction) of the vent hole 133. In at least one embodiment, the diameter D of the vent hole 133 133 is the diameter D of the filling hole 131 1311C, the vent holes 133 can extend in a z-direction that is substantially perpendicular to the package lid 130. Alternatively, the vent holes 133 can be angled relative to the package lid 130.

[0054] The vent hole 133 can be located in a central region of the TIM layer protective structure 170. The vent hole 133 has an inner length L 133i The gas vent hole 133 can be separated from the interposer module 120 by an outer length L 133o In at least one embodiment, the vent holes 131 can be equidistant between the interposer module 120 and the stiffening ring 150 (e.g., L 131i =L 131o In at least one embodiment, the inner length L 131i is the outer length L 133o It may be larger (e.g., L 131i >L 131o That is, the vent holes 133 can be located in the package lid 130 closer to the stiffening ring 150 than to the interposer module 120 .

[0055] The venting plug 134 may also extend from the bottom surface 130a of the package lid 130 to the top surface 130b of the package lid 130. The top surface of the venting plug 134 may be substantially flush with the top surface 130b of the package lid 130. The bottom surface of the venting plug 134 may be substantially flush with the bottom surface 130a of the package lid 130. Thus, the thickness of the venting plug 134 is less than the thickness T of the package lid 130. 130 The vent plug 134 can fill the entire vent hole 133 and completely seal the vent hole 133. The vent plug 134 can be adhesively bonded to the wall of the vent hole 133 throughout the entire vent hole 133.

[0056] As shown in Figure 1D, package lid 130 is shown with stiffener ring 150, interposer module 120 (and TIM layer 140), and TIM layer protective structure 170 shown in dashed lines. As shown in Figure 1D, package lid 130 can have a rectangular shape. Other shapes are within the contemplated scope of the present disclosure.

[0057] In particular, the package lid 130 has a length L in a first horizontal direction (i.e., the x-direction). 130 and a width W in a second horizontal direction (i.e., the y direction). 130 The TIM layer protection structure 170 may be formed to surround the entire periphery of the interposer module 120 and the TIM layer 140. The TIM layer protection structure 170 may have a length L in a first horizontal direction (i.e., the x-direction). 170 and a width W in a second horizontal direction (i.e., the y direction). 170 The TIM layer protection structure 170 may have a length L 170 and the length L of the package lid 130 130 The ratio R1 of the width W of the TIM layer protection structure 170 can be in the range of 0.3 to 1.0. 170 and package lid width W 130 130 The ratio R1 and the ratio R2 can be in a range between 0.3 and 1.0 to ensure that the TIM layer protection structure 170 provides sufficient bonding between the package lid 130, the package substrate 110 and the interposer module 120.

[0058] As shown in FIG. 1D , the fill holes 131 (and fill plug 132) and the vent holes 133 (and vent plug 134) can be substantially aligned with opposing corners of the package lid 130 and / or opposing corners of the interposer module 120. Other locations of the fill holes 131 (and fill plug 132) and the vent holes 133 (and vent plug 134) are within the contemplated scope of the present invention. Each of the fill holes 131 and the vent holes 133 can have a circular cross-sectional shape. Other shapes (e.g., elliptical, linear, rectangular) are also within the contemplated scope of the present disclosure. In at least one embodiment, the cross-sectional shape of the fill holes 131 (and fill plug 132) can be different from the cross-sectional shape of the vent holes 133 (and vent plug 134).

[0059] Diameter D of the filling hole 131 131 and the diameter D of the gas vent hole 133 133 It should be noted that the diameter D may depend on the thickness of the package lid 130. In at least one embodiment, the diameter D 131 and diameter D 133 can increase as the thickness of the package lid 130 increases. 131 and diameter D 133 may also be determined by the volume of the space filled by the TIM layer protective structure 170 (i.e., the volume defined by the inner stiffening ring 150 and the interposer 120, the top surface of the package substrate 110, and the bottom surface of the package lid 130). 131 and diameter D 133 can increase as the volume of the space increases.

[0060] 2A-2I illustrate a method of forming a semiconductor package 100 according to one or more embodiments. FIG. 2A is a vertical cross-sectional view of an intermediate structure including a package substrate top bond pad 114a and a package substrate bottom bond pad 116a according to one or more embodiments. The package substrate top bond pad 114a can be formed, for example, on the top dielectric layer of the package substrate top dielectric layer 114. The package substrate top bond pad 114a can be formed to contact a metal interconnect structure 114b. The package substrate top bond pad 114a can be formed by depositing a metal layer (e.g., copper, aluminum, or other suitable conductive material) on the top dielectric layer of the package substrate top dielectric layer 114. The metal layer can then be patterned by etching (e.g., wet etching, dry etching, etc.), thereby forming the package substrate top bond pad 114a. Other suitable metal layer materials and etching processes can also be within the intended scope of the present disclosure.

[0061] The package substrate bottom bonding pad 116a can be formed, for example, on the bottom dielectric layer of the package substrate bottom dielectric layer 116. The package substrate bottom bonding pad 116a can be formed to contact the metal interconnect structure 116b. The package substrate bottom bonding pad 116a can be formed by depositing a metal layer (e.g., copper, aluminum, or other suitable conductive material) on the bottom dielectric layer of the package substrate top dielectric layer 114. The metal layer can then be patterned by etching (e.g., wet etching, dry etching, etc.) to form the package substrate bottom bonding pad 116a. Other suitable metal layer materials and etching processes can also be within the intended scope of the present disclosure.

[0062] After formation, the package substrate upper bonding pad 114a and the package substrate lower bonding pad 116a can be optionally subjected to a surface roughening treatment (e.g., a copper surface roughening treatment, which can also be referred to as a copper roughening (CZ) treatment). In the surface roughening treatment, the surface (e.g., a copper surface) of the package substrate upper bonding pad 114a and the surface (e.g., a copper surface) of the package substrate lower bonding pad 116a can be etched by an organic acid-based micro-etching solution to form an ultra-roughened surface (e.g., a copper surface). The uniquely-roughened copper surface topography of the package substrate upper bonding pad 114a and the package substrate lower bonding pad 116a can help achieve high adhesion between copper and resin.

[0063] 2B is a vertical cross-sectional view of an intermediate structure including a package substrate top surface layer 110a and a package substrate bottom surface layer 110b, according to one or more embodiments. In at least one embodiment, the package substrate top surface layer 110a can include a solder resist layer (e.g., a polymeric material), also referred to as a solder mask. The package substrate top surface layer 110a can also be referred to as the upper solder resist layer 110a, and the package substrate bottom surface layer 110b can also be referred to as the lower solder resist layer 110b.

[0064] The package substrate top layer 110a and the package substrate bottom layer 110b may be applied simultaneously. The package substrate top layer 110a and the package substrate bottom layer 110b may be applied, for example, as a liquid photo-imageable film. The liquid photo-imageable film may be applied, for example, by silk-screening or spraying the liquid photo-imageable film onto the surface of the package substrate 110. The liquid photo-imageable film may be applied onto the package substrate top bonding pads 114a and the package substrate bottom bonding pads 116a. The package substrate top layer 110a and the package substrate bottom layer 110b may alternatively be applied as a dry film photo-imageable film that may be vacuum-laminated onto the surface of the package substrate 110 and onto the package substrate top bonding pads 114a and the package substrate bottom bonding pads 116a, respectively.

[0065] Package substrate top surface layer 110a and package substrate bottom surface layer 110b can be applied to have a thickness that is slightly greater than the thicknesses of package substrate top bond pad 114a and package substrate bottom bond pad 116a, respectively, or package substrate top surface layer 110a and package substrate bottom surface layer 110b can be applied to have a top surface that is substantially coplanar with the top surfaces of package substrate top bond pad 114a and package substrate bottom bond pad 116a, respectively.

[0066] FIG. 2C illustrates an opening O in the package substrate top layer 110a in accordance with one or more embodiments. 110a and an opening O in the package substrate lower layer 110b. 110b FIG. 2 is a vertical cross-sectional view of an intermediate structure including

[0067] Opening O 110a An opening O may be formed in the package substrate top layer 110a to expose the top surface of the package substrate top bonding pad 114a. 110bAn opening O may be formed in the package substrate lower layer 110b to expose the upper surface of the package substrate lower bonding pad 116a. 110b and aperture O 110b can be formed, for example, by using a photolithography process. In at least one embodiment, the opening O 110b and aperture O 110b can be formed in a separate photolithography process.

[0068] Opening O 110a The photolithography process (e.g., multiple processes) used to form the package substrate top surface layer 110a may include forming a patterned photoresist mask (not shown) on the package substrate top surface layer 110a and etching (e.g., wet etching, dry etching, etc.) the top surface of the package substrate top surface layer 110a exposed by the openings in the photoresist mask. The photoresist mask may then be removed by ashing, dissolving the photoresist mask, or consuming the photoresist mask during an etching process.

[0069] Opening O 110b The photolithography process (e.g., multiple processes) used to form the package substrate lower surface layer 110b may include forming a patterned photoresist mask (not shown) on the package substrate lower surface layer 110b and etching (e.g., wet etching, dry etching, etc.) the top surface of the package substrate lower surface layer 110b exposed by the openings in the photoresist mask. The photoresist mask may then be removed by ashing, dissolving the photoresist mask, or consuming the photoresist mask during an etching process.

[0070] Opening O 110a is formed in the package substrate top layer 110a, and an opening O 110bAfter the upper solder resist layer 110a (top solder resist layer) is formed on the lower package substrate layer 110b, the upper package substrate layer 110a (top solder resist layer) and the lower package substrate layer 110b may be cured, for example, by thermal curing or ultraviolet (UV) curing.

[0071] 2D illustrates a vertical cross-sectional view of an intermediate structure in which interposer module 120 can be mounted (e.g., via a flip chip bonding (FCB) process) onto package substrate 110, according to one or more embodiments. As shown in FIG. 2D, C4 bumps 121 of interposer module 120 can be positioned on package substrate top bond pads 114a of package substrate 110 and heated to bond C4 bumps 121 to package substrate top bond pads 114a.

[0072] 2E illustrates a vertical cross-sectional view of an intermediate structure in which a package underfill layer 129 can be formed on the package substrate 110, according to one or more embodiments. The package underfill layer 129 can be formed of an epoxy-based polymeric material. As shown in FIG. 2E, the package underfill layer 129 can be formed (e.g., injected) under and around the interposer module 120 and the C4 bumps 121 to secure the interposer module 120 to the package substrate 110. The package underfill layer 129 can then be cured, for example, in a box oven at a temperature ranging from 120° C. to 180° C. for about 60 minutes to 120 minutes to provide the package underfill layer 129 with sufficient rigidity and mechanical strength.

[0073] 2F shows a vertical cross-sectional view of an intermediate structure to which a TIM layer 140 can be attached to the top surface of an interposer module 120, according to one or more embodiments. The TIM layer 140 can include, for example, a gel TIM, a graphite TIM, a metal TIM, a solder TIM, and a carbon nanotube TIM. The TIM layer 140 can be attached to the top surface of the interposer module 120 by applying a thermally conductive adhesive to the top surface of the interposer module 120 (or to the bottom surface of the TIM layer 140) and then pressing the TIM layer 140 onto the interposer module 120.

[0074] 2G shows a vertical cross-sectional view of an intermediate structure in which adhesive 160 can be applied to package substrate 110, according to one or more embodiments. The adhesive can include, for example, a silicone adhesive or an epoxy adhesive. The adhesive can be positioned on package substrate 110 at a location corresponding to the location of stiffening ring 150, and in an amount sufficient to securely bond stiffening ring 150 to package substrate 110.

[0075] 2H illustrates a vertical cross-sectional view of an intermediate structure where a stiffening ring 150 may be attached (e.g., mounted) to a package substrate 110, according to one or more embodiments. As mentioned above, the stiffening ring 150 may be constructed of metal, ceramic, or plastic. The stiffening ring 150 may be formed, for example, by milling using a computer numerically controlled (CNC) milling machine, or by molding or stamping.

[0076] In FIG. 2H, the package substrate 110 with the interposer module 120 can be placed on a surface and the stiffening ring 150 can be lowered onto the package substrate 110 over the interposer module 120. The stiffening ring 150 can then be aligned with an adhesive 160 (e.g., a ring of adhesive material) formed on the package substrate 110. The stiffening ring 150 can then be pressed downwards with a downward pressure on the top surface of the stiffening ring 150, thereby securely fastening the stiffening ring 150 to the package substrate 110 by the adhesive 160. Alternatively, the stiffening ring 150 can be placed on a surface (e.g., a flat surface) and the interposer module 120 on the package substrate 110 can be inverted and inserted into the stiffening ring 150. A downward force can then be applied to the package substrate bottom layer 110b of the package substrate 110 to bond the package substrate 110 to the stiffening ring 150.

[0077] 2I illustrates a vertical cross-sectional view of an intermediate structure where package lid 130 can be attached to stiffener ring 150, according to one or more embodiments. As shown in FIG. 2I, at this point in the method of forming a semiconductor package, package lid 130 can include fill hole 131 and vent hole 133. At this time, fill plug 132 and vent plug 134 can be absent from package lid 130.

[0078] The adhesive 161 can be applied to the top surface (e.g., the entire top surface) of the stiffening ring 150. Alternatively, the adhesive 161 can be applied to the bottom surface 130a of the package lid 130 at a location corresponding to the location of the stiffening ring 150. The package lid 130 can then be aligned with the stiffening ring 150 and lowered onto the stiffening ring 150 and the TIM layer 140. The package lid 130 can then be clamped to the package substrate 110 for a period of time to cure the adhesive 161 and the adhesive 160 and form a secure bond between the package substrate 110, the stiffening ring 150, and the package lid 130. For example, the clamping of the package lid 130 to the package substrate 110 can be performed using a heat clamp module. The heat clamp module can apply a uniform force across the top surface of the package lid 130. As shown in FIG. 5, and as illustrated and described in more detail below, in some embodiments, the stiffening ring 150 can be integrally formed with the package lid 130 in a unitary structure.

[0079] 2J illustrates a vertical cross-sectional view of an intermediate structure in which a TIM layer protection structure 170 has been added to a semiconductor package 100, according to one or more embodiments. In at least one embodiment, a material (e.g., a curable material, a liquid material) for forming the TIM layer protection structure 170 can be added to the semiconductor package through the fill hole 131. In particular, the material can be injected (e.g., manually injected) into the semiconductor package 100, thereby filling a volume (e.g., an air gap) around the interposer module 120 and constrained by the stiffener ring 150 and the package lid 130. Concurrent with the injection of the material, gas (e.g., air, nitrogen, etc.) can exit the semiconductor package 100 through the vent hole 133 in the package lid 130.

[0080] In at least one embodiment, the material of the TIM layer protection structure 170 can be injected into the fill holes 131 until the material of the TIM layer protection structure 170 reaches the vent holes 133. That is, when the material of the TIM layer protection structure 170 reaches the vent holes 133, the injection of the material can be stopped. In at least one embodiment, the injection of the material can be stopped when the top surface of the TIM layer protection structure 170 is substantially flush with the bottom surface 130a, the bottom ends of the fill holes 131, and the bottom ends of the vent holes 133. In at least one embodiment, the injection of the material can be stopped when the TIM layer protection structure 170 fills the entire volume between the interposer module 120 and the stiffening ring 150.

[0081] 2K shows a top view of an intermediate structure including a TIM layer protection structure 170 on a package substrate 100, according to one or more embodiments. The package lid 130 has been omitted from FIG. 2K for ease of illustration. The locations of the fill holes 131 and the vent holes 133 are indicated by dashed lines in FIG. 2K.

[0082] The directional arrows in FIG. 2K indicate the direction of flow of the material of the TIM layer protection structure 170 as it is injected into the fill hole 131. As further illustrated, the material can initially spread locally around the fill hole 131. The material can initially spread along the package substrate top surface layer 110a towards the interposer module 120. A first portion of the material can initially flow around the interposer module 120 in the x-direction by the interposer module 120. A second portion of the material can initially flow around the interposer module 120 in the y-direction by the interposer module 120. The flow rates of the first portion and the second portion can be substantially the same. The first portion and the second portion can reach the vent hole 133 at substantially the same time.

[0083] In at least one embodiment, the filling of the material of the TIM layer protective structure 170 can be automated. In particular, various aspects of the filling process can be computer controlled by a control system (e.g., an electronic control system, a central processing unit (CPU)). In at least one embodiment, the start of the injection of the material, the flow rate of the injection of the material, and the stop of the injection of the material can be controlled by the control system.

[0084] In at least one embodiment, a vacuum line can be connected to the vent hole 133 such that a vacuum is applied to the volume around the interposer module 120. An imaging device (e.g., a camera) can be connected to a portion of the vacuum line inserted into the vent hole 133. The vacuum line and imaging device can also be controlled by a control system. The imaging device can detect the level of material in the TIM layer protective structure 170. The output of the imaging device can be transmitted (e.g., by wired or wireless signal) to the control system. The control system can stop the injection of material and turn off the vacuum in the vacuum line when the output of the imaging device indicates that the material has reached a certain level in the semiconductor package 100 (e.g., when the material reaches the vent hole 133).

[0085] Alternatively, the control system may be programmed to inject a predetermined amount of material based on various input parameters, which may include, for example, the volume of space surrounding the interposer module 120, the size of the interposer module 120, the size of the package lid 130, the size of the stiffening ring 150, etc.

[0086] In at least one embodiment, the material (e.g., an epoxy-based polymeric material) for forming the TIM layer protection structure 170 can include a capillary material (e.g., a capillary underfill type material). The material can have a low viscosity. In particular, the viscosity of the material can be lower than the viscosity of the material of the package underfill layer 129. In at least one embodiment, the viscosity can be about 5,000 cP or less at 10 rpm. In at least one embodiment, the material can include a low viscosity suspension of a thermally conductive material (e.g., metal, metal oxide) in a prepolymer. The low viscosity can help facilitate transport of the material around the interposer module 120 and throughout the space around the interposer module 120. The low viscosity can also help avoid the formation of voids in the TIM layer protection structure 170. In at least one embodiment, the TIM layer protection structure 170 can be substantially void-free.

[0087] In the process of adding the material of the TIM layer protection structure 170, the material can contact and flow over the surface of the package substrate top surface layer 110a (e.g., solder resist layer). The surface of the package substrate top surface layer 110a can have a low surface roughness. In particular, the surface roughness of the package substrate top surface layer 110a can be less than the surface roughness of the bottom surface 130a of the package lid 130. In at least one embodiment, the surface roughness (arithmetic mean roughness (Ra)) of the package substrate top surface layer 110a can be 1.0 nm or less (Ra<1.0 nm). The low surface roughness can help promote the flow (transport) of the material in the space around the interposer module 120. Surface roughness values ​​can include, for example, the arithmetic mean roughness (Ra), the ten-point mean roughness (Rz), the root-mean-square (rms) value of the departures of the profile from the mean line (Rq), and / or the maximum height or depth (Rmax). However, other measures of roughness can be within the scope of the present disclosure (e.g., the mean spacing of profile irregularities (Sm), the mean spacing of local peaks of the profile (S), and the profile bearing length ratio (tp)).

[0088] FIG. 2L illustrates a vertical cross-sectional view of an intermediate structure including a fill plug 132 and a vent plug 134, according to one or more embodiments. After the material for forming the TIM layer protection structure 170 is added (e.g., filled in a space), the fill plug 132 can be added (e.g., injected, inserted) into the fill hole 131. The vent plug 134 can also be added (e.g., injected, inserted) into the vent hole 133 of the package lid 130. The fill plug 132 and the vent plug 134 can include the same material as that of the TIM layer protection structure 170. In at least one embodiment, the fill plug 132 can be formed in the fill hole 131 by injecting a plug material (an epoxy-based polymer material) into the fill hole 131. The vent plug 134 can be formed in the vent hole 133 by injecting a plug material (an epoxy-based polymer material) into the vent hole 133. In at least one embodiment, the fill plug 132 and the vent plug 134 can be formed simultaneously with the formation of the TIM layer protective structure 170 .

[0089] In alternative embodiments, the material of the fill plug 132 may be different from the material of the venting plug 134. For example, the material of one of the fill plug 132 and the venting plug 134 may include a silicon-based material and the material of the other of the fill plug 132 and the venting plug 134 may include an epoxy-based polymer material. In another alternative embodiment, the material of the fill plug 132 and / or the degassing plug 134 may be different from the material of the TIM layer protective structure 170.

[0090] FIG. 2M illustrates a vertical cross-sectional view of an intermediate structure in which a plurality of solder balls 110c can be formed on the package substrate 110, according to one or more embodiments. The plurality of solder balls 110c can be formed on the lower bonding pads 116a by openings in the package substrate lower surface layer 110b. The solder balls 110c can be formed, for example, by an electroplating process. The solder balls 110c can be formed, for example, to be located under the stiffener ring 150 and under the interposer module 120. The plurality of solder balls 110c can constitute a ball grid array (BGA) that can allow the semiconductor package 100 to be securely mounted (e.g., by surface mount technology (SMT)) on a substrate, such as a printed circuit board, and electrically coupled to the substrate. The formation of the solder balls 110c can complete the formation of the semiconductor package 100.

[0091] 3 is a flow chart illustrating a method of forming a semiconductor package according to one or more embodiments. Step 310 includes mounting an interposer module on a package substrate. Step 320 includes disposing a thermal interface material (TIM) layer on the interposer module. Step 330 includes disposing a package lid on the interposer module and the TIM layer. Step 340 includes forming a TIM layer protection structure on the TIM layer and the side of the interposer module through a fill hole in the package lid.

[0092] 4A-4C show plan views of alternative designs of the package lid 130, according to one or more embodiments. In particular, FIG. 4A shows a plan view of a first alternative design of the package lid 130, according to one or more embodiments. In the first alternative design, the distance between the vent hole 133 and the adjacent corner of the stiffening ring 150 may be smaller than the distance between the fill hole 131 and the adjacent corner of the stiffening ring 150. This design can help ensure that the space between the interposer module 120 and the stiffening ring 150 is filled with more of the material of the TIM layer protection structure 170 before the material reaches the vent hole 133.

[0093] 4B illustrates a plan view of a second alternative design of package lid 130 according to one or more embodiments. In the second alternative design, fill holes 131 and vent holes 133 can be located on opposite sides of interposer module 120 (and TIM layer 140) in the x-direction. The x-direction can include the longitudinal direction of package lid 130. In at least one embodiment, fill holes 131 and vent holes 133 can be substantially aligned with a central region of interposer module 120 (and TIM layer 140).

[0094] 4C shows a plan view of a third alternative design of package lid 130 according to one or more embodiments. In the third alternative design, fill hole 131 and fill plug 132 can have an elliptical or oval cross-sectional shape. The longitudinal direction of fill hole 131 and fill plug 132 may be substantially perpendicular to a diagonal line intersecting opposite corners of package lid 130. Vent hole 133 (and vent plug 134) may have a circular cross-sectional shape.

[0095] FIG. 5 illustrates a vertical cross-sectional view of a fourth alternative design of the package lid 130 according to one or more embodiments. As illustrated in FIG. 5, the two-piece unit of the package lid 130 and the stiffening ring 150 in the original design of FIG. 1A can be replaced with a one-piece package lid 130 having an outer leg 130c instead of the stiffening ring 150. In particular, the package lid 130 of the fourth alternative design (e.g., the one-piece package lid 130) can include a plate portion 130p and an outer leg 130c extending from the plate portion 130p. The outer leg 130c can be integrally formed as a unit with the plate portion 130p (e.g., by a CNC process) and can surround the periphery of the plate portion 130p and protrude vertically from the plate portion 130p.

[0096] 5, the fill hole 131 and the vent hole 133 can be located inside (e.g., in the x-direction) of the outer leg 130c. Thus, the TIM layer protection structure 170 can be formed within a space bounded by the outer leg 130c, the plate portion 130p, the package substrate 110, and the interposer module 120 (and the TIM layer 140). The fourth alternative design can omit the step of bonding the package lid 130 to the stiffening ring 150, which can reduce the processing time required compared to the original design of the package lid 130 of FIG. 1A.

[0097] 6 illustrates a vertical cross-sectional view of a fifth alternative design of a package lid 130, according to one or more embodiments. As illustrated in FIG. 6, the package lid 130 in the fifth alternative design may be similar to the fourth alternative design, but may additionally include an inner leg 130d. In particular, the package lid 130 in the fifth alternative design may include a plate portion 130p and an outer leg 130c integrally formed as a unit with the plate portion 130p. The outer leg 130c may surround the periphery of the plate portion 130p and protrude vertically from the plate portion 130p.

[0098] The package lid 130 in the fifth alternative design may also include an inner leg 130d formed inside the outer leg 130c. The inner leg 130d may protrude substantially perpendicularly from the plate portion 130p. The inner leg 130d may have the same or a different length in the z-direction as the outer foot 130c. The inner leg 130d may also be connected to the package substrate 110 by an adhesive 160.

[0099] 6, the fill hole 131 and the vent hole 133 can be located inside (e.g., in the x-direction) of the inner leg 130d. Thus, the TIM layer protection structure 170 can be formed within a volume bounded by the inner leg 130d, the plate portion 130p, the package substrate 110, and the interposer module 120 (and the TIM layer 140). As a result, the fifth alternative design can require less material to fill the volume around the interposer module 120 and reduce the time required to fill the volume, compared to the original design of the package lid 130 of FIG. 1A.

[0100] 1A to 6, the semiconductor package 100 may include an interposer module 120 on a package substrate 110, a thermal interface material (TIM) layer 140 on the interposer module 120, a TIM layer protection structure 170 on a side of the TIM layer 140 and a side of the interposer module 120, a package lid 130 on the interposer module 120, the TIM layer 140, and the TIM layer protection structure 170. The ratio of the thickness of the TIM layer protection structure 170 to the thickness of the interposer module 120 may be within a range of 1.0 to 3.0. The package lid 130 has a package lid length L 130 and the TIM layer protection structure 170 can have a TIM layer protection structure length L 170 and the TIM layer protective structure has a length L 170 and package lid length L 130The ratio R1 can be in the range of 0.3 to 1.0. The package lid 130 has a width W of the package lid in a second horizontal direction perpendicular to the first horizontal direction. 130 and the TIM layer protection structure 170 can have a width W 170 and the TIM layer protective structure has a width W 170 and package lid width W 130 The ratio R2 can be in the range between 0.3 and 1.0. The TIM layer protection structure 170 can have a thermal expansion coefficient in the range between 3 ppm / °C and 20 ppm / °C. The TIM layer protection structure 170 can have a thermal conductivity of 1 W / m·K or more. The package lid 130 can contact the top surface of the TIM layer 140 and the top surface of the TIM layer protection structure 170. The TIM layer protection structure 170 can be formed around the periphery of the TIM layer 140. The TIM layer protection structure 170 can extend across the interface between the TIM layer 140 and the molding material layer 127 of the interposer module 120. The semiconductor package 100 can further include a stiffening ring 150 bonded to the package substrate 110 around the periphery of the interposer module 120, and the TIM layer protection structure 170 can be formed within a volume bounded by the stiffening ring 150 and the interposer module 120. The TIM layer protection structure 170 can be bonded to the stiffening ring 150 and can extend continuously from the stiffening ring 150 to the interposer module 120. The TIM layer protection structure 170 can be bonded to the package lid 130 and the package substrate 110 and can extend continuously from the package lid 130 to the package substrate 110. The package lid 130 can include a fill plug 132 on the TIM layer protection structure 170 and a degassing plug 134 on the TIM layer protection structure 170. The package lid 130 can include a plate portion 130p and legs 130c, 130d extending from the plate portion 130p and surrounding the periphery of the interposer module 120 to contact the package substrate 110, and the TIM layer protection structure 170 can be formed in a space between the legs 130c, 130d and the interposer module 120.

[0101] 1A-6, the method of forming the semiconductor package 100 may include mounting the interposer module 120 on the package substrate 110, disposing a thermal interface material (TIM) layer on the interposer module 120, disposing a package lid 130 on the interposer module 120 and the TIM layer 140, and forming a TIM layer protection structure 170 on a side of the TIM layer 140 and a side of the interposer module 120 by a filling hole 131 in the package lid 130. The formation of the TIM layer protection structure 170 may include venting a space between the stiffening ring 150 and the interposer module 120 by a venting hole 133 in the package lid 130. The method may further include blocking the filling hole 131 in the package lid 130, and blocking the venting hole 133 in the package lid 130. Forming the TIM layer protection structure 170 can include injecting the TIM layer protection structure material into the fill hole 131 until the TIM layer protection structure material reaches the vent hole 133. Forming the TIM layer protection structure 170 can include injecting the TIM layer protection structure material into the fill hole 131 such that an upper surface of the TIM layer protection structure material surrounds the periphery of the TIM layer 140 and contacts the bottom surface of the package lid 130.

[0102] 1A-6, the semiconductor package 100 may include an interposer module 120 on a package substrate 110, a thermal interface material (TIM) layer on the interposer module 120, and a TIM layer protection structure 170 on the package substrate and around the interposer module and the TIM layer, where the TIM layer protection structure 170 may have a thermal expansion coefficient in a range between 3 ppm / ° C. and 20 ppm / ° C. and a thermal conductivity of 1 W / m·K or greater, a reinforcement ring 150 is bonded to the package substrate 110 around the interposer module 120, where the TIM layer protection structure 170 may be formed within a volume bounded by the reinforcement ring 150 and the interposer module 120, and a package lid 130 is positioned over the reinforcement ring 150, the interposer module 120, the TIM layer 140, and the TIM layer protection structure 170, where the package lid 130 may contact an upper surface of the TIM layer 140 and an upper surface of the TIM layer protection structure 170. The package lid 130 may include a fill hole 131 having a diameter in the range of 3 mm to 10 mm on the TIM layer protection structure 170, a fill plug 132 is used to block the fill hole 131, a vent hole 133 is located on the TIM layer protection structure 170 and has a diameter in the range of 3 mm to 10 mm, a vent plug 134 is used to block the vent hole 133, and the fill hole 131 may be located on the side of the interposer module 120 which may be located opposite the vent hole 133.

[0103] The foregoing outlines features of some embodiments to enable those skilled in the art to better understand aspects of the present disclosure. Those skilled in the art will appreciate that the present disclosure can be readily used as a basis for designing or modifying other processes and structures to carry out the same purposes and / or achieve the same advantages of the embodiments introduced herein. Those skilled in the art should also appreciate that such equivalent structures do not depart from the spirit and scope of the present disclosure, and that various changes, substitutions, and alterations can be made herein without departing from the spirit and scope of the present disclosure. [Explanation of symbols]

[0104] 100 Semiconductor Packages 110 Package Substrate 110a Package substrate top layer 110b Package substrate top layer 110c solder ball 112 cores 112a Through Via 114 Package substrate top dielectric layer 114a Package substrate top bonding pad 114b Metal interconnect structures 116 Package Substrate Lower Dielectric Layer 116a Package substrate bottom bonding pad 116b Metal interconnect structures 120 Interposer Module 121 Controlled Collapse Chip Connection Bump 122 Interposer Dielectric Layer 122a Metal Interconnects 123 First Semiconductor Die 124 Second Semiconductor Die 126 Interposer Underfill Layer 127 Molding material layer 128 Microbump 129 Package Underfill Layer 130 Package Lid 130a Bottom 130b top surface 130c, 130d legs 130p Plate section 131 Filling hole 132 Filling plug 133 Gas vent hole 134 Gas vent plug 140 TIM layers 150 Reinforcement Ring 160, 161 Adhesive 170 TIM layer protection structure 170i TIM layer protection structure interface part 310, 320, 330, 340 steps D 131 , D 133 diameter L 130 , L 131i , L 131o , L 133i , L 133o , L 170 length O 110a , O 110b opening T 120 , T 130 , T 170 Thickness W 130 , W 170 width X, Y, Z Axes

Claims

1. An interposer module on a package substrate; a thermal interface material (TIM) layer on the interposer module; a TIM layer protection structure on a side of the TIM layer and a side of the interposer module; a package lid over the interposer module, the TIM layer and the TIM layer protection structure; and A semiconductor package including a stiffening ring bonded to the package substrate and disposed around the interposer module, the TIM layer protective structure being formed within a volume bounded by the stiffening ring and the interposer module.

2. 2. The semiconductor package of claim 1, wherein a ratio of a thickness of the TIM layer protection structure to a thickness of the interposer module is in a range of 1.0 to 3.

0.

3. 2. The semiconductor package of claim 1, wherein the package lid has a package lid length in a first horizontal direction, the TIM layer protection structure has a TIM layer protection structure length in the first horizontal direction, and a ratio of the length of the TIM layer protection structure to the length of the package lid is in the range between 0.3 and 1.

0.

4. The semiconductor package of claim 3, wherein the package lid has a package lid width in a second horizontal direction perpendicular to the first horizontal direction, the TIM layer protection structure has a TIM layer protection structure width in the second horizontal direction, and a ratio of the TIM layer protection structure width to the package lid width is in the range between 0.3 and 1.

0.

5. The semiconductor package of claim 1 , wherein the package lid includes a fill plug on the TIM layer protective structure and a degassing plug on the TIM layer protective structure.

6. 2. The semiconductor package of claim 1, wherein the package lid includes a plate portion and a leg portion extending from the plate portion and surrounding the periphery of the interposer module to contact the package substrate, and the TIM layer protection structure is formed in a volume between the leg portion and the interposer module.

7. 1. A method of forming a semiconductor package, the method comprising: mounting the interposer module on a package substrate; disposing a thermal interface material (TIM) layer over the interposer module; placing a package lid over the interposer module and the TIM layer; and The method includes forming a TIM layer protection structure on a side of the TIM layer and a side of the interposer module.

8. 8. The method of claim 7, wherein forming the TIM layer protective structure includes venting a volume bounded by a stiffener ring and the interposer module through a vent hole in the package lid.

9. An interposer module on a package substrate; a thermal interface material (TIM) layer on the interposer module; a TIM layer protection structure located on the package substrate and around the interposer module and the TIM layer, the TIM layer protection structure having a thermal expansion coefficient in a range between 3 ppm / ° C. and 20 ppm / ° C. and a thermal conductivity of 1 W / m·K or greater; a TIM layer protection structure bonded to the package substrate and disposed around the interposer module, the TIM layer protection structure comprising a stiffener ring and a stiffener ring formed within a volume bounded by the interposer module; a package lid located on the stiffener ring, the interposer module, the TIM layer, and the TIM layer protection structure and in contact with a top surface of the TIM layer and a top surface of the TIM layer protection structure; the package lid has a fill hole on the TIM layer protective structure, the fill hole having a diameter in the range of 3 mm to 10 mm; a fill plug for blocking the fill hole; a vent hole located on the TIM layer protective structure and having a diameter in the range of 3 mm to 10 mm; and a gas vent plug adapted to close the gas vent hole; The fill hole is located on a side of the interposer module opposite the vent hole.

Images