Semiconductor device and its manufacturing method

Abstract

To increase the reliability of a semiconductor device.SOLUTION: A semiconductor device includes a semiconductor substrate, a semiconductor layer, a first insulating film, and a conductive film. The semiconductor layer is formed on the semiconductor substrate. In the semiconductor layer, a first groove that reaches the semiconductor substrate is formed. The first insulating film is formed on an inner side surface of the first groove so that a part of the semiconductor substrate is exposed in the first groove. The conductive film is connected electrically to the semiconductor substrate and is formed on the inner side surface of the first groove through the first insulating film. In a plan view, a first length of the first groove in an extension direction of the first groove is larger than a second length of the first groove in a width direction perpendicular to the extension direction and is 30 μm or less.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to a semiconductor device and a manufacturing method thereof. [Background technology]

[0002] A semiconductor device having a conductive film embedded in a groove formed in an insulating layer or a semiconductor layer is known. For example, a semiconductor device having contacts such as a substrate contact and a via is known (see, for example, Patent Document 1). The semiconductor device described in Patent Document 1 has a semiconductor substrate, a semiconductor layer formed on the semiconductor substrate, and an interlayer insulating layer formed on the semiconductor layer. A groove reaching the semiconductor substrate is formed in the interlayer insulating layer and the semiconductor layer. An insulating film is formed on the inner side surface of the groove. The semiconductor device further has a conductive film formed on the insulating film so as to fill the groove. The conductive film is formed, for example, by forming a conductive layer on the interlayer insulating layer so as to fill the groove, and then removing a portion of the conductive layer located outside the groove by a CMP method.

[0003] In the semiconductor device, the conductive film formed in the trench constitutes a contact, and in Patent Document 1, for example, the contact fixes the GND potential of the semiconductor substrate. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] JP 2015-037099 A Summary of the Invention [Problem to be solved by the invention]

[0005] However, depending on the material and size of the conductive film, when the conductive film is formed, a void (gap) may be formed in the conductive film due to stress caused by the contact. Then, the cleaning solution used in the CMP process enters the void, and a reaction product between the material of the conductive film and a component of the cleaning solution is formed on the conductive film. For this reason, in a conventional semiconductor device, a short circuit may occur between two wirings that are close to each other through the reaction product. Thus, in the conventional semiconductor device, there is room for improvement in terms of increasing the reliability of the semiconductor device.

[0006] An object of the embodiments is to improve the reliability of a semiconductor device. Other objects and novel features will become apparent from the description of this specification and the drawings. [Means for solving the problem]

[0007] A semiconductor device according to an embodiment includes a semiconductor substrate, a semiconductor layer, a first insulating film, and a conductive film. The semiconductor layer is formed on the semiconductor substrate. A first trench is formed in the semiconductor layer, the first insulating film being formed on an inner side surface of the first trench such that a part of the semiconductor substrate is exposed in the first trench. The conductive film is electrically connected to the semiconductor substrate and is formed on the inner side surface of the first trench via the first insulating film. In a plan view, a first length of the first trench in an extension direction of the first trench is greater than a second length of the first trench in a width direction perpendicular to the extension direction, and is 30 μm or less.

[0008] A method for manufacturing a semiconductor device according to an embodiment includes the steps of forming a first trench penetrating a semiconductor layer to reach a semiconductor substrate, forming an insulating film on an inner side surface of the first trench to expose a part of the semiconductor substrate in the first trench, and forming a conductive film on the insulating film formed on the inner side surface of the first trench to be electrically connected to the semiconductor substrate. In a plan view, a first length of the first trench in an extension direction of the first trench is greater than a second length of the first trench in a width direction perpendicular to the extension direction and is equal to or less than 30 μm.

[0009] A semiconductor device according to another embodiment includes a first wiring, an insulating layer formed on the first wiring and having a groove exposing a part of the first wiring, a conductive film formed in the groove, and a second wiring formed on the insulating layer and electrically connected to the first wiring via the conductive film, wherein in a plan view, a length of the groove in an extension direction of the groove is greater than a second length of the groove in a width direction perpendicular to the extension direction and is 30 μm or less. Effect of the Invention

[0010] According to the embodiment, the reliability of the semiconductor device can be improved. [Brief description of the drawings]

[0011] [Figure 1] FIG. 1 is a plan view showing an example of a configuration of a main part of a semiconductor device according to an embodiment. [Diagram 2] FIG. 2 is a cross-sectional view showing an example of a configuration of a main part of a semiconductor device according to an embodiment. [Diagram 3] FIG. 3 is a cross-sectional view of a main part showing an example of a process included in a method for manufacturing a semiconductor device according to an embodiment. [Figure 4] FIG. 4 is a cross-sectional view of a main part showing an example of a process included in a method for manufacturing a semiconductor device according to an embodiment. [Diagram 5] FIG. 5 is a cross-sectional view of a main part showing an example of a process included in a method for manufacturing a semiconductor device according to an embodiment. [Figure 6] FIG. 6 is a cross-sectional view of a main part showing an example of a process included in a method for manufacturing a semiconductor device according to an embodiment. [Figure 7] FIG. 7 is a cross-sectional view of a main part showing an example of a process included in a method for manufacturing a semiconductor device according to an embodiment. [Figure 8] FIG. 8 is a cross-sectional view of a main part showing an example of a process included in a method for manufacturing a semiconductor device according to an embodiment. [Figure 9] FIG. 9 is a cross-sectional view of a main part showing an example of a process included in a method for manufacturing a semiconductor device according to an embodiment. [Figure 10] FIG. 10 is a cross-sectional view of a main part showing an example of a process included in a method for manufacturing a semiconductor device according to an embodiment. [Figure 11] FIG. 11 is a graph showing the relationship between the stress caused by the substrate contact and the size of the substrate contact. [Figure 12] FIG. 12 is a graph showing the relationship between the stress caused by the substrate contact and the distance from the substrate contact. [Figure 13] FIG. 13 is an enlarged perspective view showing an example of a configuration of a main part of a semiconductor device according to a modified example. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0012] Hereinafter, a semiconductor device according to an embodiment and a manufacturing method thereof will be described in detail with reference to the drawings. In the specification and drawings, the same or corresponding components are denoted by the same reference numerals or the same hatching, and duplicated explanations are omitted. In addition, in the drawings, components may be omitted or simplified for convenience of explanation. Cross-sectional views may be shown as end views.

[0013] [Configuration of semiconductor device] Fig. 1 is a plan view showing an example of the configuration of a main part of a semiconductor device SD according to the present embodiment. Fig. 2 is a cross-sectional view showing an example of the configuration of a main part of a semiconductor device SD according to the present embodiment. Fig. 2 is a cross-sectional view taken along line AA in Fig. 1.

[0014] The semiconductor device SD has a semiconductor substrate SUB, a semiconductor layer SL, a semiconductor element SE, and a multilayer wiring layer MWL. Although details will be described later, the semiconductor device SD has a first element isolation part EI1, a second element isolation part EI2, and a substrate contact SC, which are made up of some of the components of the multilayer wiring layer MWL. Note that in FIG. 1, components of the multilayer wiring layer MWL that are located above the first wiring WR1 are omitted.

[0015] The semiconductor substrate SUB supports the semiconductor layer SL. The semiconductor substrate SUB has a first conductivity type. The first conductivity type is P type or N type. Examples of impurities contained in a P type semiconductor substrate include boron (B) and indium (In). Examples of impurities contained in an N type semiconductor substrate include phosphorus (P), arsenic (As), and antimony (Sb).

[0016] The semiconductor layer SL is formed on the semiconductor substrate SUB. The semiconductor layer SL has a first epitaxial layer EL1, a buried layer BL, a second epitaxial layer EL2, and a buried insulating film BIF. The first epitaxial layer EL1, the buried layer BL, and the second epitaxial layer EL2 are formed in this order from the semiconductor substrate SUB side.

[0017] The first epitaxial layer EL1 is formed on the surface of the semiconductor substrate SUB. The first epitaxial layer EL1 is a semiconductor layer having the above-mentioned first conductivity type. The impurity concentration of the first epitaxial layer EL1 is, for example, 1×10 13 cm -3 Greater than or equal to 1×10 19 cm -3 It is preferable that the value is less than 1×10 13 cm -3 Greater than or equal to 1×10 16 cm -3 It is more preferable that the following is true. Note that the first epitaxial layer EL1 is not an essential component. The first epitaxial layer EL1 may be a so-called SOI (Silicon On Insulator) layer of a SOI substrate.

[0018] The buried layer BL is formed on all or a part of the first epitaxial layer EL1. From the viewpoint of electrically isolating the semiconductor element SE formed on the buried layer BL from the semiconductor substrate SUB, the semiconductor layer SL preferably has the buried layer BL. The buried layer BL is a semiconductor layer having a second conductivity type opposite to the first conductivity type. The impurity concentration of the buried layer BL is, for example, 1×10 18 cm -3 Greater than or equal to 1×10 21 cm -3 It is preferable that:

[0019] The second epitaxial layer EL2 is an epitaxial layer formed on the buried layer BL. When the buried layer BL is formed on the entire first epitaxial layer EL1, the second epitaxial layer EL2 is formed on the buried layer BL. When the buried layer BL is formed on a portion of the first epitaxial layer EL1, the second epitaxial layer EL2 is formed on the buried layer BL and the first epitaxial layer EL1. The impurity concentration of the second epitaxial layer EL2 is, for example, 1×10 13 cm -3 Greater than or equal to 1×10 19 cm -3 It is preferable that the value is less than 1×10 13 cm -3 Greater than or equal to 1×10 16 cm -3 It is more preferable that:

[0020] The semiconductor layer SL may further include one or more buried layers as necessary. The buried layers may be formed in the first epitaxial layer EL1 or in the second epitaxial layer EL2. The buried layers may be formed so as to overlap the entire buried layer BL in plan view, or may be formed so as to overlap a part of the buried layer BL. The conductivity type of the buried layer may be P type or N type.

[0021] The buried insulating film BIF is formed in the second epitaxial layer EL2 of the semiconductor layer SL. The buried insulating film BIF is formed so as to surround the semiconductor element SE in a plan view. The buried insulating film BIF is an insulating film formed on the main surface of the semiconductor layer SL. The position, number and size of the buried insulating films BIF are not particularly limited as long as they can electrically insulate the semiconductor element SE from other semiconductor elements (not shown). The material of the buried insulating film BIF is, for example, silicon oxide (SiO2).

[0022] A first trench TR1, a second trench TR2, and a third trench TR3 are formed in the main surface of the semiconductor layer SL, each of which reaches the semiconductor substrate. That is, the first trench TR1, the second trench TR2, and the third trench TR3 open to the main surface of the semiconductor layer SL. The first trench TR1 defines the position, size, and shape of the first element isolation portion EI1. The second trench TR2 defines the position, size, and shape of the second element isolation portion EI2. The third trench TR3 defines the position, size, and shape of the substrate contact SC.

[0023] The semiconductor element SE is formed on the main surface of the semiconductor layer SL. The semiconductor element SE is not particularly limited and may be a so-called planar MOSFET or a laterally diffused MOSFET (LDMOSFET). In this embodiment, the semiconductor element SE is a planar MOSFET. The semiconductor element SE has a source region SR, a drain region DR, a gate insulating film GI, and a gate electrode GE. The main surface of the semiconductor substrate SUB is the surface on which the semiconductor element SE is formed.

[0024] The multilayer wiring layer MWL is formed on the semiconductor layer SL so as to cover the semiconductor element SE. The multilayer wiring layer MWL is composed of two or more wiring layers. The wiring layer is a layer having an interlayer insulating layer and one or both of wiring and vias formed in the interlayer insulating layer. The vias are conductors that electrically connect two wirings formed in different layers.

[0025] The multilayer wiring layer MWL has a first interlayer insulating layer IIL1, a first via V1, a conductive film CF, a first wiring WR1, a second interlayer insulating layer IIL2, a second via V2, a second wiring WR2, and a third interlayer insulating layer IIL3. As will be described in detail later, a first portion of the first interlayer insulating layer IIL1 constitutes a first element isolation portion EI1. A second portion of the first interlayer insulating layer IIL1 constitutes a second element isolation portion EI2. A third portion of the first interlayer insulating layer IIL1 and the conductive film CF constitute a substrate contact SC.

[0026] The first interlayer insulating layer IIL1 is formed on the semiconductor layer SL so as to cover the semiconductor element SE. The first interlayer insulating layer IIL1 may be composed of a single layer or may be composed of multiple layers. In the present embodiment, the first interlayer insulating layer IIL1 has a first insulating film IF1, a second insulating film IF2, and a third insulating film IF3.

[0027] The first insulating film IF1 is formed on the semiconductor layer SL so as to cover the semiconductor element SE. Examples of materials for the first insulating film IF1 include silicon oxide and silicon nitride. The thickness of the first insulating film IF1 is, for example, 10 nm or more and 100 nm or less.

[0028] The second insulating film IF2 is formed on the first insulating film IF1. Examples of materials for the second insulating film IF2 include silicon oxide and silicon nitride. The thickness of the second insulating film IF2 is, for example, 50 nm or more and 1 μm or less.

[0029] The third insulating film IF3 is formed in the first groove TR1, the second groove TR2, and the third groove TR3 and on the second insulating film IF2.

[0030] A first portion of the third insulating film IF3 is formed on the inner side surface and bottom surface of the first trench TR1. The first portion of the third insulating film IF3 constitutes a first element isolation portion EI1. The first element isolation portion EI1 insulates, for example, the substrate contact SC from the semiconductor element SE. The first portion of the third insulating film IF3 is preferably formed in the first trench TR1 so that a first void VD1 is formed in the first trench TR1. In this embodiment, the first void VD1 is formed in the first portion of the third insulating film IF3. This enhances the insulating characteristics of the first element isolation portion EI1.

[0031] As shown in FIG. 1, the first element isolation portion EI1 (the first portion) is formed so as to surround the substrate contact SC in a plan view. In the first element isolation portion EI1, the first void VD1 is formed in the first portion of the third insulating film IF3. From the viewpoint of improving the insulating characteristics of the first element isolation portion EI1, it is preferable that a first length of the first void VD1 in the depth direction of the first trench TR1 is large. Also, from the viewpoint of improving the insulating characteristics of the first element isolation portion EI1, it is preferable that a second length of the first void VD1 in the width direction of the first trench TR1 is large. The depth direction of the first trench TR1 is the same as the thickness direction of the semiconductor layer SL.

[0032] The second portion of the third insulating film IF3 is formed on the inner side surface and bottom surface of the second trench TR2. The second portion of the third insulating film IF3 constitutes a second element isolation portion EI2. The second element isolation portion EI2 insulates, for example, the semiconductor element SE from other semiconductor elements (not shown). The second portion of the third insulating film IF3 is preferably formed in the second trench TR2 so that a second void VD2 is formed in the second trench TR2. In this embodiment, the second void VD2 is formed in the second portion of the third insulating film IF3. This further enhances the insulating characteristics of the second element isolation portion EI2.

[0033] As shown in FIG. 1, the second element isolation portion EI2 (the second portion) is formed so as to surround the semiconductor element SE in plan view. In the second element isolation portion EI2, the second void VD2 is formed in the second portion of the third insulating film IF3. From the viewpoint of improving the insulating characteristics of the second element isolation portion EI2, it is preferable that a first length of the second void VD2 in the depth direction of the second groove TR2 is large. Also, from the viewpoint of improving the insulating characteristics of the second element isolation portion EI2, it is preferable that a second length of the second void VD2 in the width direction of the second groove TR2 is large. The depth direction of the second groove TR2 is the same as the thickness direction of the semiconductor layer SL.

[0034] The first length of the second void VD2 may be the same as or different from the first length of the first void VD1, and the second length of the second void VD2 may be the same as or different from the second length of the first void VD1.

[0035] The third portion of the third insulating film IF3 is formed on the inner side surface of the third groove TR3 so that a part of the semiconductor substrate SUB is exposed from the third insulating film IF3 in the third groove TR3. The third portion of the third insulating film IF3 prevents the semiconductor layer SL and the conductive film CF from shorting each other. Although details will be described later, the third portion of the third insulating film IF3 constitutes a substrate contact SC together with the conductive film CF.

[0036] An example of the material of the third insulating film IF3 includes silicon oxide. The thickness of the portion of the third insulating film IF3 formed on the second insulating film IF2 is, for example, 0.1 μm or more and 1 μm or less. The thickness of the portion of the third insulating film IF3 formed on the inner side surfaces of the first groove TR1 and the second groove TR2 is, for example, 0.1 μm or more and 1 μm or less. The thickness of the portion of the third insulating film IF3 formed on the inner side surface of the third groove TR3 is, for example, 0.1 μm or more and 1 μm or less.

[0037] The first via V1 is formed in the first interlayer insulating layer IIL1 so as to reach the semiconductor element SE. More specifically, the first via V1 is formed in the first interlayer insulating layer IIL1 so as to reach the source region SR, the drain region DR, or the gate electrode GE. The first via V1 electrically connects the source region SR, the drain region DR, or the gate electrode GE to the first wiring WR1. The first via V1 has, for example, a barrier film and a conductive film formed on the barrier film. Examples of the material of the barrier film include titanium (Ti), titanium nitride (TiN), tantalum (Ta), and tantalum nitride (TaN). Examples of the material of the conductive film include tungsten (W) and aluminum (Al). Note that the barrier film is not an essential component.

[0038] The conductive film CF is formed on the inner side surface of the third groove TR3 via the third insulating film IF3. The conductive film CF is electrically connected to a portion of the semiconductor substrate SUB that is exposed from the third insulating film IF3 in the third groove TR3. As described above, the conductive film CF constitutes the substrate contact SC together with the third portion of the third insulating film IF3.

[0039] In the width direction of the third groove TR3, the proportion of the conductive film CF occupying the third groove TR3 (thickness of the conductive film CF / width of the third groove TR3) is, for example, preferably 1 / 10 or more and 4 / 5 or less, and more preferably 1 / 10 or more and 2 / 3 or less.

[0040] In plan view, the first length L1 (see FIG. 1) of the third groove TR3 in the extension direction of the third groove TR3 is greater than the second length L2 of the third groove TR3 in the width direction perpendicular to the extension direction, and is 30 μm or less. If the first length L1 of the conductive film CF exceeds 30 μm, the reliability of the semiconductor device SD becomes insufficient. For this reason, it is preferable that the first length L1 of the third groove TR3 is small. Although the details will be described later, from the viewpoint of further improving the reliability of the semiconductor device SD, it is preferable that the first length L1 of the third groove TR3 is greater than the second length L2 and is 10 μm or less in plan view. Here, the first length L1 of the third groove TR3 is, for example, the length of the third groove TR3 in the main surface of the semiconductor layer SL.

[0041] The extension direction of the third groove TR3 is a direction perpendicular to the width direction of the third groove TR3 in a plan view. In a plan view, a first length L1 of the third groove TR3 in the extension direction of the third groove TR3 is greater than a second length L2 of the third groove TR3 in the width direction of the third groove TR3.

[0042] The second length L2 of the third groove TR3 in the width direction of the third groove TR3 (see FIGS. 1 and 2) is set appropriately depending on the embeddability of the conductive film CF and the conductivity of the substrate contact SC. For example, the second length L2 of the third groove TR3 is not less than 0.1 μm and not more than 2 μm. Here, the second length L2 of the third groove TR3 is, for example, the length of the third groove TR3 in the main surface of the semiconductor layer SL.

[0043] The depth D of the third groove TR3 (see FIG. 2) is appropriately set according to the thickness of the semiconductor layer SL. The depth of the third groove TR3 is, for example, preferably 1 μm or more and 100 μm or less, and more preferably 6 μm or more and 30 μm or less.

[0044] The number of conductive films CF (substrate contacts SC) is not particularly limited. In the present embodiment, the number of conductive films CF surrounded by one first element isolation part EI1 in plan view is five. In the present embodiment, the extension direction of the third trench TR3 is the arrangement direction of the five conductive films CF. Note that the conductive films CF do not have to be surrounded by the first element isolation part EI1 in plan view.

[0045] In the width direction of the third groove TR3, the distance d (see FIGS. 1 and 2) between the third groove TR3 (substrate contact SC) and the first groove TR1 (first element isolation portion EI1) is preferably small from the viewpoint of miniaturizing the semiconductor device SD. From this viewpoint, the distance d is preferably 5 μm or less, more preferably 2 μm or less, and further preferably 1 μm or less. Here, the distance d is, for example, the distance between the third groove TR3 and the first groove TR1 in the main surface of the semiconductor layer SL.

[0046] On the other hand, from the viewpoint of suppressing the occurrence of cracks in the first interlayer insulating layer IIL1 due to deformation of the first element isolation unit EI1 caused by stress due to the substrate contact SC, it is preferable that the distance d is large. From this viewpoint, the distance d is preferably 1 μm or more, more preferably 2 μm or more, and further preferably 5 μm or more.

[0047] From the viewpoint of achieving both the insulating characteristics of the first element isolation portion EI1 and the crack resistance of the first interlayer insulating layer IIL1, the distance d is preferably 1 μm or more and 2 μm or less.

[0048] The planar shape and position of the third groove TR3 are not particularly limited. The planar shape of the third groove TR3 may be, for example, a substantially rectangular shape, an elliptical shape, or a rounded rectangular shape. In the present embodiment, the third groove TR3 extends along the first groove TR1 in the planar view and is surrounded by the first groove TR1.

[0049] In this embodiment, the conductive film CF is formed in the third groove TR3 such that a third void VD3 is formed in the third groove TR3. The third void VD3 is formed in the third portion of the third insulating film IF3. From the viewpoint of increasing the conductivity of the substrate contact SC, it is preferable that a first length of the third void VD3 in the depth direction of the third groove TR3 is small. Also, from the viewpoint of increasing the conductivity of the substrate contact SC, it is preferable that a second length of the third void VD3 in the width direction of the third groove TR3 is small. The depth direction of the third groove TR3 is the same as the thickness direction of the semiconductor layer SL.

[0050] From the viewpoint of achieving both the conductivity of the substrate contact SC and the insulating properties of the first element isolation portion EI1 and the second element isolation portion EI2, it is preferable that the size of the third void VD3 in the substrate contact SC is smaller than the size of the first void VD1 in the first element isolation portion EI1 and the size of the second void VD2 in the second element isolation portion EI2. More specifically, in the depth direction of the third groove TR3, the first length of the third void VD3 is smaller than the first length of the first void VD1 and the first length of the second void VD2. In addition, in the width direction of the third groove TR3, it is preferable that the second length of the third void VD3 is smaller than the second length of the first void VD1 and the second length of the second void VD2.

[0051] The material of the conductive film CF is, for example, a metal having electrical conductivity. Examples of the material of the conductive film CF include tungsten (W), titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), aluminum (Al), copper (Cu), and nickel (Ni).

[0052] The first wiring WR1 is formed on the first interlayer insulating layer IIL1. The first wiring WR1 is electrically connected to the semiconductor substrate SUB via a conductive film CF. A known configuration used as wiring in semiconductor technology can be adopted for the first wiring WR1. The first wiring WR1 is, for example, a laminated film in which a barrier metal, a conductive film, and a barrier metal are laminated in this order. Examples of materials constituting the barrier metal include titanium (Ti), titanium nitride (TiN), tantalum (Ta), and tantalum nitride (TaN). Examples of materials constituting the conductive film include aluminum, copper, and tungsten.

[0053] The second interlayer insulating layer IIL2 is formed on the first interlayer insulating layer IIL1 so as to cover the first wiring WR1. An example of a material for the second interlayer insulating layer IIL2 is silicon oxide.

[0054] The second via V2 is formed in the second interlayer insulating layer IIL2 so that the first wiring WR1 and the second wiring WR2 are electrically connected to each other. An example of the material of the second via V2 is the same as that of the first via V1.

[0055] The second wiring WR2 is formed on the second interlayer insulating layer IIL2. An example of the material of the second wiring WR2 is the same as that of the first wiring WR1.

[0056] The third interlayer insulating layer IIL3 is formed on the second interlayer insulating layer IIL2 so as to cover the second wiring WR2. An example of a material for the third interlayer insulating layer IIL3 is silicon oxide.

[0057] [Method of manufacturing semiconductor device] 3 to 10 are cross-sectional views of a main part showing an example of steps included in the manufacturing method of the semiconductor device SD according to the present embodiment.

[0058] The manufacturing method of the semiconductor device SD in this embodiment includes: (1) a step of preparing a semiconductor wafer SW; (2) a step of forming a semiconductor element SE; (3) a step of forming a first insulating film IF1 and a second insulating film IF2; (4) a step of forming a first groove TR1, a second groove TR2, and a third groove TR3; (5) a step of forming a third insulating film IF3; (6) a step of forming a groove TRcf for a conductive film and a through hole CTv1 for a first via; (7) a step of forming a conductive film CF and a first via V1; and (8) a step of forming the remaining part of the multilayer wiring layer MWL.

[0059] (1) Preparation of semiconductor wafer SW As shown in Fig. 3, a semiconductor wafer SW is prepared. The semiconductor wafer SW has a semiconductor substrate SUB and a semiconductor layer SL formed on the semiconductor substrate SUB. The semiconductor wafer SW may be purchased as a ready-made product or may be manufactured, for example. The prepared semiconductor substrate SUB is held by an electrostatic chuck.

[0060] The semiconductor substrate SUB is, for example, a semiconductor substrate of the first conductivity type or the second conductivity type.

[0061] The semiconductor layer SL includes a first epitaxial layer EL1, a buried layer BL, a second epitaxial layer EL2, and a buried insulating film BIF. The semiconductor layer SL can be formed by a method known in the semiconductor technology as a method for forming a semiconductor layer.

[0062] The first epitaxial layer EL1 is formed on the semiconductor substrate SUB by epitaxial growth. The buried layer BL is formed on the first epitaxial layer EL1 by ion implantation and activation annealing. The second epitaxial layer EL2 is formed on the buried layer BL by epitaxial growth.

[0063] The buried insulating film BIF may be formed by forming a recess in the main surface of the second epitaxial layer EL2 by an etching technique and then filling the recess with an insulating film. The buried insulating film BIF may also be formed by oxidizing a part of the main surface of the second epitaxial layer EL2 by a LOCOS method.

[0064] (2) Formation of semiconductor element SE 4, a semiconductor element SE is formed on the main surface of the semiconductor layer SL. The method for forming the semiconductor element SE is not particularly limited, and a method known as a method for forming a semiconductor element may be adopted. In the present embodiment, the semiconductor element SE has a source region SR, a drain region DR, a gate insulating film GI, and a gate electrode GE.

[0065] The source region SR and the drain region DR are formed by, for example, ion implantation and activation annealing. The gate insulating film GI is formed on a portion of the main surface of the semiconductor layer SL that is located between the source region SR and the drain region DR in a plan view. The gate electrode GE is formed on the gate insulating film GI.

[0066] (3) Formation of First Insulating Film IF1 and Second Insulating Film IF2 5, a first insulating film IF1 and a second insulating film IF2 are formed on the semiconductor layer SL so as to cover the semiconductor element SE. The first insulating film IF1 and the second insulating film IF2 are formed by, for example, a CVD method.

[0067] (4) Formation of the first groove TR1, the second groove TR2, and the third groove TR3 6, a first groove TR1, a second groove TR2, and a third groove TR3 are formed so as to extend along the thickness direction of the semiconductor layer SL to reach the semiconductor substrate SUB and penetrate the second insulating film IF2, the first insulating film IF1, and the semiconductor layer SL. In this embodiment, the first groove TR1, the second groove TR2, and the third groove TR3 penetrate the buried insulating film BIF, the second epitaxial layer EL2, the buried layer BL, and the first epitaxial layer EL1 in the semiconductor layer SL. The first groove TR1, the second groove TR2, and the third groove TR3 are formed by, for example, a dry etching method.

[0068] (5) Formation of third insulating film IF3 7, a third insulating film IF3 is formed in the first groove TR1, the second groove TR2, and the third groove TR3 and on the second insulating film IF2, thereby forming a first interlayer insulating layer IIL1.

[0069] A first void VD1 is formed in the first trench TR1. This forms a first element isolation portion EI1. A second void VD2 is formed in the second trench TR2. This forms a second element isolation portion EI2. A fourth void VD4 is formed in the third trench TR3. The sizes of the first void VD1, the second void VD2, and the fourth void VD4 are appropriately adjusted according to the aspect ratios (ratios of groove depth to groove width) of the first trench TR1, the second trench TR2, and the third trench TR3, and the material of the third insulating film IF3. The third insulating film IF3 is formed by, for example, a CVD method.

[0070] (6) Formation of the conductive film groove TRcf and the first via hole CTv1 8, a conductive film groove TRcf and a first via through hole CTv1 are formed. The conductive film groove TRcf is a through hole formed in the third insulating film IF3 so as to communicate with the fourth void VD4 and expose a part of the semiconductor substrate SUB. The first via through hole CTv1 is a through hole penetrating the first interlayer insulating layer IIL1 so as to reach each of the source region SR, the drain region DR, and the gate electrode GE. The conductive film groove TRcf and the first via through hole CTv1 are formed by, for example, a dry etching method.

[0071] (7) Formation of Conductive Film CF and First Via V1 Next, as shown in FIG. 9, a conductive film CF and a first via V1 are formed. Specifically, a conductive layer is formed in the conductive film groove TRcf and the first via through hole CTv1 and on the third insulating film IF3, and the conductive layer formed outside the conductive film groove TRcf and the first via through hole CTv1 is removed. The conductive film CF is formed on the third insulating film IF3 formed on the inner side surface of the third groove TR3 so as to be electrically connected to the semiconductor substrate SUB. The conductive layer is formed, for example, by a CVD method. The conductive layer is removed, for example, by a CMP method. The conductive layer is removed (polished) in a state where a slurry for CMP is provided on the conductive layer. After the process by the CMP method, a cleaning liquid is provided on the surface to be polished.

[0072] (8) Formation of the Remaining Multilayer Wiring Layer (MWL) Next, as shown in FIG. 10, the first wiring WR1, the second interlayer insulating layer IIL2, the second via V2, the second wiring WR2, and the third interlayer insulating layer IIL3 are formed.

[0073] The second interlayer insulating layer IIL2 and the third interlayer insulating layer IIL3 are formed by, for example, a CVD method. The first wiring WR1 is formed by forming a conductive layer on the first interlayer insulating layer IIL1 by a sputtering method, and then patterning the conductive layer into a desired shape. The second wiring WR2 is formed by forming a conductive layer on the second interlayer insulating layer IIL2 by a sputtering method, and then patterning the conductive layer into a desired shape. The second via V2 is formed by forming a through hole in the second interlayer insulating layer IIL2, and then filling the through hole with a conductive material.

[0074] Next, the structure obtained by the above process is detached from the electrostatic chuck and diced to obtain a plurality of individual semiconductor devices SD.

[0075] The semiconductor device SD according to the present embodiment is manufactured by the above manufacturing method. The manufacturing method of the semiconductor device SD according to the present embodiment may further include other processes as necessary. The other processes may be appropriately adopted from methods known in the semiconductor technology.

[0076] [simulation] A simulation was performed to investigate the relationship between the stress caused by the substrate contact SC and the size of the substrate contact SC. This simulation was performed using a viscoelastic model, taking into account the process temperature in the process of forming each component. The conditions for this simulation are as follows:

[0077] The material of the semiconductor layer SL is silicon (Si). The material of the first insulating film IF1 is silicon nitride (SiN). The material of the second insulating film IF2 and the third insulating film IF3 is silicon oxide (SiO2). The material of the conductive film CF is tungsten (W).

[0078] The width of the third groove TR3 is 0.90 μm. In the width direction of the third groove TR3, the length of the conductive film CF is 0.60 μm. In the width direction of the third groove TR3, the thickness of the third insulating film IF3 formed on the inner side surface of the third groove TR3 is 0.15 μm.

[0079] The simulation was performed for each of the cases where the depth of the third groove TR3 was 4 μm, 8 μm, 12 μm, and 16 μm.

[0080] 11 is a graph showing the relationship between the stress caused by the substrate contact SC and the size of the substrate contact SC. The horizontal axis indicates the length L1 [μm] of the third groove TR3 in the extension direction of the third groove TR3. The vertical axis indicates the width ΔW of the third void VD3 at the upper end of the conductive film CF. The width of the third void VD3 is the length of the third void VD3 in the width direction of the third groove TR3. The larger the width of the third void VD3, the greater the stress caused by the substrate contact SC.

[0081] In Fig. 11, black circles (●) indicate simulation results when the depth of the third groove TR3 is 16 μm. Black squares (■) indicate simulation results when the depth of the third groove TR3 is 12 μm. Black triangles (▲) indicate simulation results when the depth of the third groove TR3 is 8 μm. Black diamonds (◆) indicate simulation results when the depth of the third groove TR3 is 4 μm.

[0082] 11, regardless of the depth of the third groove TR3, as the length L1 of the third groove TR3 decreases, the width ΔW of the third void VD3 decreases. In particular, it can be seen that the width ΔW of the third void VD3 decreases sharply when the length L1 of the third groove TR3 is 30 μm or less. Also, the width ΔW of the third void VD3 becomes negligibly small when the length L1 of the third groove TR3 is 10 μm or less. This shows that when the length L1 of the third groove TR3 is 10 μm or less, the third void VD3 in the conductive film CF is substantially blocked, that is, becomes negligibly small.

[0083] From the simulation results, it is found that when the length L1 of the third groove TR3 is 30 μm or less, the cleaning liquid used in the CMP process is less likely to penetrate into the third void VD3 of the conductive film CF. This improves the reliability of the semiconductor device SD. Also, it is found that when the length L1 of the third groove TR3 is 10 μm or less, the cleaning liquid used in the CMP process is even less likely to penetrate into the third void VD3 of the conductive film CF. This improves the reliability of the semiconductor device SD.

[0084] [Reference experiment] Next, a reference experiment was performed to examine the relationship between the stress caused by the substrate contact SC and the distance from the substrate contact SC. Here, the distance from the substrate contact SC is the distance from the opening end of the third groove TR3 in the width direction of the third groove TR3.

[0085] In this reference experiment, the current characteristics of a MOSFET formed at a position a certain distance away from the substrate contact SC were evaluated. Next, based on the results obtained in the above simulation (the relationship between the stress due to the substrate contact SC and the size of the substrate contact SC), the effects on the above current characteristics were estimated for the cases where the length L1 of the third trench TR3 was 5 μm and 50 μm.

[0086] 12 is a graph showing the relationship between the stress caused by the substrate contact SC and the distance from the substrate contact SC. The horizontal axis indicates the distance d [μm] from the third trench TR3 in the width direction of the third trench TR3. The vertical axis indicates the rate of change ΔI [%] of the current characteristics of the MOSFET. A larger rate of change of the current characteristics of the MOSFET means a larger stress caused by the substrate contact SC.

[0087] 12, the solid line indicates the simulation result when the length L1 of the third groove TR3 is 5 μm, and the dashed line indicates the simulation result when the length L1 of the third groove TR3 is 50 μm.

[0088] 12, the smaller the length L1 of the third groove TR3, the smaller the rate of change ΔI in the current characteristics of the MOSFET. For example, when the length L1 of the third groove TR3 is 50 μm, if the distance d from the substrate contact SC is reduced from 5 μm to 1 μm, the rate of change ΔI decreases by about 10%. In contrast, when the length L1 of the third groove TR3 is 5 μm, even if the distance d from the substrate contact SC is reduced from 5 μm to 1 μm, the rate of change ΔI decreases by only about 3%.

[0089] From the results of the reference experiment, it is found that when the length L1 of the third groove TR3 is small, the stress occurring in the vicinity of the substrate contact SC can be reduced. As a result, in the semiconductor device SD according to this embodiment, the first element isolation portion EI1, the second element isolation portion EI2, the semiconductor element SE, and the like can be formed even in the vicinity of the substrate contact SC. For example, when the first void VD1 is formed in the first element isolation portion EI1, stress is concentrated at the top of the first void VD1, and cracks are likely to occur in the first interlayer insulating layer IIL1. However, in the semiconductor device SD according to this embodiment, since the length L1 of the third groove TR3 is 30 μm or less, the first element isolation portion EI1 can also be formed in the vicinity of the substrate contact SC. For example, the first element isolation portion EI1 can be formed within a range in which the distance from the third groove TR3 in the width direction of the third groove TR3 is 1 μm or more and 2 μm or less.

[0090] (effect) In the semiconductor device SD according to the present embodiment, the first length L1 of the third groove TR3 in the extending direction of the third groove TR3 is greater than the second length L2 of the third groove TR3 in the width direction perpendicular to the extending direction, and is 30 μm or less. When the length L1 of the third groove TR3 is 30 μm or less, the stress caused by the third insulating film IF3 and the conductive film CF formed in the third groove TR3 drops sharply. Therefore, the third void VD3 in the conductive film CF is likely to be formed in a state of being blocked by the conductive film CF. This makes it difficult for the cleaning solution to enter the third void VD3 in the conductive film CF in the CMP process for forming the conductive film CF. The generation of a reaction product between the material of the conductive film CF and the cleaning solution is suppressed. As a result, a short circuit caused between adjacent wirings through the reaction product is suppressed. For example, the first wiring WR1 and the second wiring WR2 are suppressed from being short-circuited through the reaction product. As described above, according to the present embodiment, the reliability of the semiconductor device SD can be improved.

[0091] [Variations] Fig. 13 is an enlarged perspective view showing an example of the configuration of a main part of a semiconductor device according to a modified example. More specifically, Fig. 13 is an enlarged perspective view showing an example of the configuration of a via mV according to a modified example. For example, Fig. 13 shows an area corresponding to the area surrounded by the dashed line in Fig. 2. In Fig. 13, the second interlayer insulating layer IIL2 and the third interlayer insulating layer IIL3 are omitted from the viewpoint of ease of viewing.

[0092] In the above embodiment, the stress of the substrate contact SC has been described, but the present invention is not limited to this aspect. For example, as shown in FIG. 13, a semiconductor device according to a modified example has a second via mV2 formed in a via groove mTR formed in a multilayer wiring layer MWL. That is, the first length mL1 of the via groove mTR in the extension direction of the via groove mTR may be larger than the second length mL2 of the via groove mTR in the width direction perpendicular to the extension direction and may be 30 μm or less. In this case, the second via mV2 is a so-called slit via. The first length mL1 of the via groove mTR in the extension direction is larger than the second length mL2 of the groove mTR in the width direction. Since the via groove mTR is formed in an interlayer insulating layer, an insulating film on the inner side surface of the groove mTR is not an essential component.

[0093] As is clear from the results of the above simulation, regardless of the depth of the groove in which the conductive film is formed, the stress caused by the conductive film decreases as the length of the groove in the extension direction of the groove decreases. For example, regardless of the depth of the groove in which the conductive film is formed, when the length of the groove becomes 30 μm or less, the stress caused by the conductive film decreases rapidly. Thus, from the results of the above simulation, it is clear that the present invention can be applied not only to the substrate contact SC but also to the second via mV2 in the multilayer wiring layer MWL.

[0094] The present invention is not limited to the above-described embodiment, and may be modified in various ways without departing from the spirit of the present invention. For example, the insulating film formed in the first groove TR1, the insulating film formed in the second groove TR2, and the insulating film formed in the third groove TR3 may be made of the same material or different materials.

[0095] In addition, even if a specific numerical example is described, the numerical value may be greater than or less than the specific numerical value, unless it is theoretically clearly limited to that numerical value. In addition, the component means "B containing A as a main component," and does not exclude embodiments containing other components.

[0096] Furthermore, at least a part of the embodiment and at least a part of the modified example may be combined with each other in any manner. That is, the semiconductor device may have a substrate contact SC formed in the third groove TR3 and a second via mV2 formed in the via groove mTR. [Explanation of symbols]

[0097] BIF buried insulating film BL Embedding Layer CF conductive film CTv1 First via hole DR Drain region EI1 First element isolation section EI2 Second element isolation section EL1 First epitaxial layer EL2 Second epitaxial layer GE gate electrode GI Gate Insulator IF1 First insulating film IF2 Second insulating film IF3 Third insulating film IIL1 First interlayer insulation layer IIL2 Second interlayer insulation layer IIL3 Third interlayer insulation layer SC Board Contact SD Semiconductor Device SE semiconductor element SL Semiconductor layer SR Source Region SUB Semiconductor Substrate SW Semiconductor Wafer TR1 1st groove TR2 2nd groove TR3 3rd groove TRcf Conductive film groove mTR via groove V1 First via V2, mV2 2nd via VD1 First void VD2 Second void VD3 Third Void VD4 4th Void WR1 First wiring WR2 Second wiring

Claims

1. A semiconductor substrate; a semiconductor layer formed on the semiconductor substrate; a first trench formed in the semiconductor layer and having a first length in an extension direction in a plan view; a second groove formed in the semiconductor layer and having a second length in the extending direction in a plan view; a third trench formed in the semiconductor layer and surrounding the first trench and the second trench in a plan view; a first insulating film formed on each of the inner side surfaces of the first trench and the second trench; a second insulating film formed in the third trench; a conductive film electrically connected to the semiconductor substrate and formed on the inner side surfaces of the first trench and the second trench via the first insulating film; having The first groove and the second groove are disposed adjacent to each other in the extension direction, Each of the first length of the first groove and the second length of the second groove is greater than a third length of the first groove in a width direction perpendicular to the extension direction and is equal to or less than 30 μm. Semiconductor device.

2. The semiconductor device according to claim 1 , wherein, in a plan view, the first length and the second length are greater than the third length of the first groove and are equal to or less than 10 μm.

3. 2. The semiconductor device according to claim 1, wherein said second insulating film is formed in said third trench so that a first void is formed in said second insulating film.

4. The semiconductor device according to claim 1 , wherein said first trench and said second trench extend along said third trench in a plan view.

5. 5 . The semiconductor device according to claim 4 , wherein, in a plan view, a distance between said first groove and said third groove is not less than 1 μm and not more than 2 μm in said width direction of said first groove.

6. 2 . The semiconductor device according to claim 1 , wherein a distance between said first groove and said third groove in said width direction of said first groove is not less than 1 μm and not more than 2 μm in plan view.

7. A third insulating film is formed on the semiconductor layer, the first trench and the second trench penetrate the third insulating film and the semiconductor layer to reach the semiconductor substrate; The semiconductor device according to claim 1 .

8. A third insulating film is formed on the semiconductor layer, the first trench, the second trench, and the third trench penetrate the third insulating film and the semiconductor layer so as to reach the semiconductor substrate; The semiconductor device according to claim 1 .

9. Further, the semiconductor device includes a wiring formed on the third insulating film, the wiring is electrically connected to the semiconductor substrate via the conductive film; The semiconductor device according to claim 7.

10. the conductive film is formed in the first groove and the second groove such that a second void is formed in the conductive film; In the thickness direction of the semiconductor layer, the length of the second void is smaller than the length of the first void. The semiconductor device according to claim 3 .

11. The semiconductor device according to claim 1 , wherein the material of the conductive film includes tungsten.

12. the semiconductor substrate has a first conductivity type; The semiconductor layer is a first buried layer having a second conductivity type opposite to the first conductivity type; a second epitaxial layer formed on the first buried layer; having The semiconductor device according to claim 1 .

13. (a) providing a semiconductor wafer having a semiconductor substrate and a semiconductor layer formed on the semiconductor substrate; (b) forming a first groove having a first length in an extension direction in a plan view in the semiconductor layer and forming a second groove having a second length in the extension direction in a plan view; (c) forming a third trench in the semiconductor layer so as to surround the first trench and the second trench in a plan view; (d) forming a first insulating film on inner side surfaces of the first trench and the second trench such that a portion of the semiconductor substrate is exposed in the first trench and the second trench; (e) forming a second insulating film in the third trench; (f) forming a conductive film on the first insulating film formed on the inner side surfaces of the first trench and the second trench so as to be electrically connected to the semiconductor substrate; Including, The first groove and the second groove are disposed adjacent to each other in the extension direction, Each of the first length of the first groove and the second length of the second groove is greater than a third length of the first groove in a width direction perpendicular to the extension direction and is equal to or less than 30 μm. A method for manufacturing a semiconductor device.

14. 14. The method for manufacturing a semiconductor device according to claim 13, wherein, in a plan view, the first length and the second length are greater than the third length of the first groove and are equal to or less than 10 μm.

15. When viewed in a plan view, a distance between the first groove and the third groove is 1 μm or more and 2 μm or less in the width direction of the first groove. The method for manufacturing a semiconductor device according to claim 13.

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