Semiconductor device, imaging unit and endoscope

Abstract

To stabilize a voltage supplied to an imaging unit to realize a stable image signal.SOLUTION: A semiconductor device includes a semiconductor substrate, a trench capacitor arranged on the semiconductor substrate, a first wiring layer, a second wiring layer, a first TSV which penetrates the semiconductor substrate outside the trench capacitor, a second TSV which penetrates the semiconductor substrate outside the trench capacitor, a first connecting terminal connected to the first TSV, a second connecting terminal connected to the first TSV, a third connecting terminal connected to the second TSV, and a fourth connecting terminal connected to the second TSV. A plurality of connecting terminals including the first connecting terminal, the second connecting terminal, the third connecting terminal, and the fourth connecting terminal are arranged so as to be distributed over the entire area of the first and second wiring layers.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present disclosure relates to a semiconductor device, an imaging unit, and an endoscope using the semiconductor device, and more particularly to a semiconductor device having a trench capacitor, an imaging unit, and an endoscope using the semiconductor device. [Background technology]

[0002] A semiconductor device having a trench capacitor typically includes a trench capacitor in a semiconductor substrate (see, for example, Patent Document 1). The semiconductor device uses the trench capacitor to store electric charge in order to stabilize the value of the VDD voltage supplied to an electric circuit of an imaging unit such as an image sensor. The semiconductor device can form a trench capacitor by having a plurality of trenches on its surface and a plurality of electrodes respectively embedded in the plurality of trenches. The trench capacitor stores electric charge by supplying a VDD voltage and a GND voltage to the electrodes.

[0003] An endoscope system using a semiconductor device typically includes an endoscope and a processor unit. The processor unit controls a voltage source to supply a VDD voltage (power supply voltage) and a GND voltage (ground voltage) to the endoscope. The endoscope includes an image sensor provided at a tip component of the endoscope. The image sensor is used to generate an image signal by using the VDD voltage and the GND voltage supplied from the voltage source. The VDD voltage supplied to the image sensor has a constant value (e.g., 3.3V) in normal operation. However, the value of the VDD voltage may drop due to external disturbances or the like. In this situation, the image sensor cannot generate a stable image signal. Therefore, it is necessary to provide a semiconductor device that can stabilize the VDD voltage supplied to the image sensor.

[0004] A semiconductor device having a trench capacitor and an image sensor are usually stacked to stabilize the VDD voltage supplied to the image sensor. In this case, a TSV (Through Silicon Via) is disposed in the semiconductor device to supply the VDD voltage and the GND voltage to the semiconductor device and the image sensor, respectively.

[0005] In the related art, multiple semiconductor substrates utilizing TSVs are stacked together. For example, when multiple DRAM (Dynamic Random Access Memory) substrates are stacked, TSVs are typically disposed in the edge regions of these DRAM substrates. The edge regions are the outer regions of the DRAM on the surface of the semiconductor substrate. Multiple semiconductor substrates are stacked and connected to each other at the TSV positions. GND and VDD voltages are provided to each DRAM substrate by using TSVs. Each semiconductor substrate has TSVs to transmit GND, VDD, and signals. However, when semiconductor substrates having TSVs in their edge regions are connected at the TSV positions, there is a problem that the semiconductor substrates are damaged due to stress concentration at the TSV positions due to the bump connection process or the like. This problem is particularly likely to occur when small and thin semiconductor substrates are stacked and connected to each other. [Prior art documents] [Patent documents]

[0006] [Patent Document 1] US Patent Application Publication No. 2013 / 0161792A1 Summary of the Invention [Problem to be solved by the invention]

[0007] Accordingly, the present disclosure aims to provide a semiconductor device, an imaging unit, and an endoscope having a trench capacitor that substantially obviates one or more of the problems resulting from limitations and shortcomings of the related art. [Means for solving the problem]

[0008] A semiconductor device according to the present disclosure includes a semiconductor substrate having a first surface and a second surface located opposite to each other, a trench capacitor disposed on the first surface of the semiconductor substrate, a first wiring layer disposed on the first surface of the semiconductor substrate and covering the trench capacitor, a second wiring layer disposed on the second surface of the semiconductor substrate, a first TSV (Through Silicon Via) penetrating the semiconductor substrate outside the trench capacitor, a second TSV penetrating the semiconductor substrate outside the trench capacitor, a first connection terminal disposed on the first wiring layer and connected to the first TSV, a second connection terminal disposed on the second wiring layer and connected to the first TSV, a third connection terminal disposed on the first wiring layer and connected to the second TSV, and a fourth connection terminal disposed on the second wiring layer and connected to the second TSV, Except that the first TSV and the second TSV do not overlap when the semiconductor device is viewed from above, The first wiring layer and the second wiring layer are disposed in a distributed manner over the entire area.

[0009] The imaging unit according to the present disclosure includes an image sensor and a semiconductor device. The image sensor has pixels on a first surface and a ground terminal and a VDD terminal on a second surface. The semiconductor device has a first connection terminal and a third connection terminal respectively connected to the VDD terminal and the ground terminal of the image sensor.

[0010] The endoscope according to the present disclosure includes an imaging unit.

[0011] Additional features and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or will be learned by the practice of the present disclosure. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings. Effect of the Invention

[0012] According to the present disclosure, it is possible to stabilize the voltage supplied to the imaging unit and realize a stable image signal. [Brief description of the drawings]

[0013] [Figure 1] FIG. 1 is a cross-sectional view that illustrates a schematic configuration of a semiconductor device according to a first embodiment. [Figure 2A] FIG. 2A is a perspective view that illustrates a schematic of certain components of the semiconductor device of FIG. [Figure 2B] FIG. 2B is a perspective view that illustrates a schematic representation of certain components of the semiconductor device of FIG. [Figure 2C] FIG. 2C is a perspective view that illustrates a schematic representation of certain components of the semiconductor device of FIG. [Figure 3A] FIG. 3A is a schematic plan view of the components of FIG. 2A. [Figure 3B] FIG. 3B is a schematic plan view of the components of FIG. 2B. [Figure 3C] FIG. 3C is a plan view that shows the components of FIG. 2C in a simplified manner. [Figure 4] FIG. 4 is a cross-sectional view that illustrates a schematic configuration of an imaging unit according to the second embodiment. [Diagram 5] FIG. 5 is a cross-sectional view that illustrates a schematic configuration of an imaging unit according to the third embodiment. [Figure 6] FIG. 6 is a cross-sectional view illustrating a semiconductor device according to the fourth embodiment. [Figure 7A] FIG. 7A is a perspective view that illustrates, in schematic form, certain components of the semiconductor device of FIG. [Figure 7B] FIG. 7B is a perspective view that illustrates a schematic representation of certain components of the semiconductor device of FIG. [Figure 7C] FIG. 7C is a perspective view that illustrates a schematic representation of certain components of the semiconductor device of FIG. [Figure 8A] FIG. 8A is a plan view that illustrates components of the semiconductor device of FIG. 7A. [Figure 8B]FIG. 8B is a plan view that illustrates components of the semiconductor device of FIG. 7B. [Figure 8C] FIG. 8C is a plan view that illustrates components of the semiconductor device of FIG. 7C. [Figure 9] FIG. 9 is a perspective view illustrating an endoscope system according to the fifth embodiment. [Figure 10] FIG. 10 is a cross-sectional view that shows a schematic view of a tip component part of the endoscope system of FIG. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0014] Details of preferred embodiments of the present invention are given reference numerals, examples of which are illustrated in the accompanying drawings. Figure 1 is a cross-sectional view that shows a schematic representation of a semiconductor device according to a first embodiment. Figures 2A, 2B, and 2C are perspective views that show schematic representations of certain components of the semiconductor device of Figure 1, respectively. Figures 3A, 3B, and 3C are plan views that show schematic representations of the components of Figures 2A, 2B, and 2C, respectively.

[0015] Fig. 3A shows a plan view of arrow AA' in Fig. 1 and Fig. 2A. Fig. 3B shows a plan view of arrow BB' in Fig. 1 and Fig. 2B. Fig. 3C shows a plan view of arrow CC' in Fig. 1 and Fig. 2C.

[0016] As shown in FIG. 1, the semiconductor device 1 may include a semiconductor substrate 2, a trench capacitor 3 embedded in the semiconductor substrate 2, a first wiring layer 4 covering the front surface of the semiconductor substrate 2, and a second wiring layer 5 covering the rear surface of the semiconductor substrate 2. The semiconductor device 1 may also include a first TSV (Through Silicon Via) 11 and a second TSV 12 penetrating the semiconductor substrate 2 in an area outside the trench capacitor 3, which is outside the trench capacitor area. The semiconductor device 1 may further include a plurality of connection terminals. As shown in FIG. 1, the plurality of connection terminals may include, for example, at least a first connection terminal 21, a second connection terminal 22, a third connection terminal 23, and a fourth connection terminal 24, and these terminals may be distributed and disposed on the front and rear surfaces of the semiconductor substrate 2. For example, the first connection terminal 21 and the third connection terminal 23 may be disposed on the front surface of the semiconductor substrate 2, and the second connection terminal 22 and the fourth connection terminal 24 may be disposed on the rear surface of the semiconductor substrate 2. Furthermore, the first connection terminal 21 and the third connection terminal 23 together with additional connection terminals may be evenly arranged on the front side of the semiconductor substrate 2 at regular distances from each other. The second connection terminal 22 and the fourth connection terminal 24 together with different additional connection terminals may be evenly arranged on the rear side of the semiconductor substrate 2 at regular distances from each other.

[0017] The semiconductor substrate 2 may be a square or rectangular plate, or may be formed into any shape suitable for the electronic device utilizing the semiconductor substrate 2. The semiconductor substrate 2 may have horizontal and vertical widths, each of which may range from 500 micrometers to 1500 micrometers. The thickness of the semiconductor substrate 2 may range from 40 micrometers to 60 micrometers.

[0018] The semiconductor substrate 2 includes a first surface 2a and a second surface 2b located opposite to each other. As shown in FIG. 1, the first surface 2a may be the front surface of the semiconductor substrate 2, and the second surface 2b may be the rear surface of the semiconductor substrate 2. Also, a plurality of trench capacitors 3 may be disposed on the first surface 2a. In this embodiment, the plurality of trench capacitors 3 may be spaced apart from each other at regular distances, and substantially uniformly occupy the entire area of ​​the first surface 2a except for the peripheral region of the first surface 2a. Each trench capacitor 3 may include a first electrode 3a, a dielectric layer 3B, and a second electrode (buried electrode) 3c.

[0019] The trench capacitor 3 can be formed as follows: A plurality of trenches are formed on the first surface 2a by a dry etching process or the like; A film-like metal layer is formed as a first electrode 3a for each trench capacitor 3 by a vapor phase deposition process or the like; The first electrode 3a covers the plurality of trenches; A film-like dielectric layer 3b is then formed on the first electrode 3a so as to cover the first electrode 3a; Then, the second electrode 3c is partially embedded in the trench covered by the first electrode 3a and the dielectric layer 3b so as to sandwich the dielectric layer 3b between the first electrode 3a and the second electrode 3c. The depth of the trench capacitor 3 can be, for example, in the range of 5 micrometers to 20 micrometers. The pitch of each trench capacitor 3, or the distance between the trench capacitors 3, can be in the range of 1 micrometer to 3 micrometers.

[0020] The trench capacitors 3 may be divided into groups when these trench capacitors 3 are arranged. For example, each group of trench capacitors 3 may include at least 3 to 10 trench capacitors 3. In this embodiment, the left side of FIG. 1 shows a first group of trench capacitors 3 (only three trench capacitors 3 are shown on the left side of the cross-sectional view). The first group of trench capacitors 3 may share one second electrode 3c. The right side of FIG. 1 shows a second group of trench capacitors 3 (only three trench capacitors 3 are shown on the right side of the cross-sectional view). The second group of trench capacitors 3 may share a different second electrode 3c. The first electrode 3a and the dielectric layer 3b are also shared in the same or similar manner as the second electrode 3c. The first wiring layer 4 may include a plurality of gate contacts 7 and a plurality of substrate contacts 8. The gate contacts 7 and the substrate contacts 8 are connected to the plurality of trench capacitors 3. As shown in FIG. 1, the gate contact 7 may be connected to the second electrode 3c by contacting a portion of the second electrode 3c exposed outside the trench capacitor 3. The first electrode 3a includes a first portion formed inside the trench and a second portion disposed outside the trench on the first surface 2a. The substrate contact 8 may be connected to the first electrode 3a by directly contacting the second portion of the first electrode 3a disposed outside the trench. As described below, a VDD voltage may be supplied to the substrate contact 8 and a GND voltage may be supplied to the gate contact 7.

[0021] 2A, 2B, and 2C are each a perspective view that shows a schematic representation of certain components of the semiconductor device 1 of FIG. 1. As shown in FIG. 2B, a plurality of trench capacitors 3 are formed in parallel with each other. The longitudinal length of each trench capacitor 3 can be in the range of 5 micrometers to 10 micrometers. Reference numeral 51 refers to a trench capacitor area in which the trench capacitors 3 are formed in the first surface 2a of the semiconductor substrate 2. The trench capacitor area 51 corresponds to a first region of the first surface 2a. The first region 51 of the first surface 2a can be sized to 80% of the total area of ​​the first surface 2a to increase the amount of charge. The second region 52 of FIG. 2B of the first surface 2a surrounds the first region 51 and provides an area that can be used by the first TSV 11, the second TSV 12, and other components required for the semiconductor device 1.

[0022] Returning to FIG. 1, the first wiring layer 4 is formed on the first surface 2a of the semiconductor substrate 2. The first wiring layer 4 covers the trench capacitor 3. The second wiring layer 5 is formed on the second surface 2b of the semiconductor substrate 2. The first wiring layer 4 includes an insulator layer having a plurality of wirings, such as wirings 4a and 4b, embedded therein. The second wiring layer 5 includes an insulator layer having a plurality of wirings, such as wirings 5a and 5b, embedded therein.

[0023] The first TSV 11 and the second TSV 12 penetrate the semiconductor substrate 2 in the thickness direction between the first surface 2a and the second surface 2b. As shown in Figures 2B and 3B, the first TSV 11 and the second TSV 12 are disposed outside the trench capacitor area 51. This area is called the outer area of ​​the trench capacitor area 51 and corresponds to the second region of the first surface 2a of the semiconductor substrate 2.

[0024] The first TSV 11 and the second TSV 12 may be configured in the semiconductor substrate 2 as follows. First, a plurality of TSV holes are formed in the semiconductor substrate 2 in the thickness direction by a dry etching process or the like. Then, a conductive material such as Cu metal is filled in the TSV holes by a plating process or the like. The diameter of the first TSV 11 may be in the range of 10 to 50 micrometers, for example. The distance d1 from the edge of the semiconductor substrate 2 to the outer end of the first TSV 11 may be set in the range of 10 to 20 micrometers.

[0025] 1, the first connection terminal 21 and the third connection terminal 23 may be disposed on the outer surface (exposed surface) of the first wiring layer 4. The second connection terminal 22 and the fourth connection terminal 24 may be disposed on the outer surface (exposed surface) of the second wiring layer 5.

[0026] The first TSV 11 can be connected to the first connection terminal 21 by a wire 4a in the first wiring layer 4. The second TSV 12 can be connected to the third connection terminal 23 by a wire 4b in the first wiring layer 4. The first TSV 11 can be connected to the second connection terminal 22 by a wire 5a in the second wiring layer 5. The second TSV 12 can be connected to the fourth connection terminal 24 by a wire 5b in the second wiring layer 5.

[0027] Next, a description of the arrangement of the TSVs and the connection terminals is provided below. As shown in FIG. 3B, the first TSV 11 and the second TSV 12 can be arranged in the outer area of ​​the trench capacitor area 51. The outer area of ​​the trench capacitor area 51 includes the peripheral areas 52, 53 surrounding the trench capacitor area 51 occupied by the trench capacitor 3 on the first surface 2a. In other words, the trench capacitor area 51 may substantially occupy the entire area of ​​the first surface 2a of the semiconductor substrate 2 except the peripheral areas 52, 53.

[0028] 3B, in this embodiment, the surrounding areas 52, 53 may be left and right edge regions of the semiconductor substrate 2. In particular, the surrounding area 52 may be a left region from the left edge of the semiconductor substrate 2 to the outer end of the trench capacitor area 51. The surrounding area 53 may be a right region from the right edge of the semiconductor substrate 2 to the outer end of the trench capacitor area 51. A distance d2 from the edge of the semiconductor substrate 2 to the outer end of the trench capacitor area 51 may be set in the range of, for example, 20 to 70 micrometers.

[0029] On the other hand, the multiple connection terminals including the first connection terminal 21, the second connection terminal 22, the third connection terminal 23 and the fourth connection terminal 24 can be distributed over the entire area of ​​the first wiring layer 4 and the second wiring layer 5 of the semiconductor device 1. For example, the multiple connection terminals may be evenly arranged at a predetermined distance from each other. These connection terminals may also be arranged in a certain pattern on the first wiring layer 4 and in a different pattern on the second wiring layer 5. These connection terminals may also be arranged in different patterns on any one of the first wiring layer 4 and the second wiring layer 5. The arrangement of these connection terminals needs to be made to effectively utilize the entire area of ​​the first wiring layer 4 and the second wiring layer 5 of the semiconductor device 1 without overlapping with other components arranged in the edge areas of the semiconductor substrate 2. For example, as shown in FIGS. 2A, 2B, and 2C, the multiple connection terminals 21, 22, 23, and 24 do not overlap the first TSV 11 and the second TSV 12 when the semiconductor device 1 is viewed from above.

[0030] 3A, the first connection terminals 21 and the third connection terminals 23 are "distributedly disposed" on the first wiring layer 4 over the entire area of ​​the first wiring layer 4. A manner in which the first connection terminals 21 and the third connection terminals 23 are disposed on the first wiring layer 4 in a distributed manner (meaning "distributedly disposed") will be described below.

[0031] The first connection terminal 21 and the third connection terminal 23 may be disposed on the first wiring layer 4 at equal intervals over the entire area of ​​the first wiring layer 4. The region in which the first connection terminal 21 and the third connection terminal 23 are disposed on the first wiring layer 4 corresponds to the region (trench capacitor area 51) in which the trench capacitor 3 occupies the first surface 2a of the semiconductor substrate 2, and overlaps with the trench capacitor area 51.

[0032] The manner in which the connection terminals are evenly arranged on the first wiring layer 4 is defined as follows. As shown in FIG. 3A, in this embodiment, the surface of the first wiring layer 4 is substantially evenly divided into two by a virtual line X, so that the first connection terminal 21 and the third connection terminal 23 are evenly arranged on the first wiring layer 4. The virtual points X1 and X2 are the center points of the divided areas, respectively. The first connection terminal 21 is arranged on the center point X1. The third connection terminal 23 is arranged on the center point X2. When there are three connection terminals on the first wiring layer 4, in a similar manner, the three connection terminals can be arranged on the center points of the areas obtained by equally dividing the first wiring layer 4 into three. When there are four connection terminals on the first wiring layer 4, the four connection terminals can be arranged on the center points of the areas obtained by equally dividing the first wiring layer 4 into four.

[0033] Another aspect of arranging the connection terminals is defined by the distance between the connection terminals and the edge portion of the wiring layer, and between the TSV and the semiconductor substrate 2. In this embodiment, the arrangement of the first connection terminal 21 and the third connection terminal 23 may be defined by two different distances, a first distance L1 and a second distance L2. As shown in FIG. 3A, the first distance L1 is the distance between the first connection terminal 21 and the edge portion of the first wiring layer 4, and this distance may be in the range of 50 micrometers to 100 micrometers. As shown in FIG. 3B, the second distance L2 is the distance between the first TSV 11 and the edge portion of the semiconductor substrate 2, and this distance may be in the range of 10 micrometers to 20 micrometers. Similarly, as shown in FIG. 3A, the first distance L1 is the shortest distance between the third connection terminal 23 and the edge portion of the first wiring layer 4, and this distance may be in the range of 50 micrometers to 100 micrometers. 3B, the second distance L2 is the shortest distance between the second TSV 12 and the edge portion of the semiconductor substrate 2, and this distance may be in the range of 10 micrometers to 20 micrometers (the second distance L2 may be the same distance as the above-mentioned distance d1). The first distance L1 and the second distance L2 are set such that the first distance L1 is longer than the second distance L2.

[0034] The second connection terminals 22 and the fourth connection terminals 24 may also be distributed and evenly arranged in the second wiring layer 5 in the same manner as the first connection terminals 21 and the third connection terminals 23, or in a different manner from the first connection terminals 21 and the third connection terminals 23 (if there is an additional different arrangement).

[0035] As described above, the multiple connection terminals including the first connection terminal 21, the second connection terminal 22, the third connection terminal 23, and the fourth connection terminal 24 are distributed over the entire area of ​​the first wiring layer 4 and the second wiring layer 5 of the semiconductor device 1. With this structural arrangement, when the semiconductor device 1 is connected to another substrate or another cable, stress caused by the connection process is distributed over the entire area of ​​the first wiring layer 4 and the second wiring layer 5 of the semiconductor device 1. As a result, damage that typically occurs due to stress concentration on the semiconductor device 1 during the connection process can be minimized, if not prevented.

[0036] On the other hand, the first TSV 11 and the second TSV 12 penetrate the semiconductor substrate 2 in the outer area of ​​the trench capacitor area 51. As shown in Fig. 3B, the first TSV 11 and the second TSV 12 are disposed in the peripheral areas 52, 53, respectively. With this structural arrangement, the trench capacitor area 51 occupies a larger portion of the first surface 2a, preferably occupies at least 75% or more of the total area of ​​the first surface 2a, thereby increasing the amount of charge of the semiconductor device 1.

[0037] Second embodiment 4 is a cross-sectional view of an imaging unit 100 according to a second embodiment. The imaging unit 100 can include a semiconductor device 1 and an image sensor 30. The image sensor 30 can be a square or rectangular plate-like shape, or any suitable shape that matches the semiconductor device 1. The image sensor 30 can have the same vertical and horizontal widths as the semiconductor device 1, ranging from 500 micrometers to 1500 micrometers. The image sensor 30 includes pixels 31 on a front surface of the image sensor 30. The image sensor 30 includes a VDD terminal 32 and a GND terminal 33 on a rear surface of the image sensor 30.

[0038] When the image sensor 30 and the semiconductor device 1 are stacked together, the rear surface of the image sensor 30 and the first surface 2a of the semiconductor substrate 2 may face each other. Thus, the VDD terminal 32 is connected to the first connection terminal 21, and the GND terminal 33 is connected to the third connection terminal 23, such as by a bump bonding process.

[0039] The VDD cable 41 and the GND cable 42 may be disposed on one side of the second surface 2b of the semiconductor substrate 2. The VDD cable 41 transmits a VDD voltage, and the GND cable 42 transmits a GND voltage. The VDD cable 41 includes a chip terminal 41a connected to the second connection terminal 22. The GND cable 42 includes a chip terminal 42a connected to the fourth connection terminal 24.

[0040] The VDD voltage may be supplied from an external voltage source (not shown) to a VDD cable 41. The GND voltage may be supplied to a GND cable 42 from the same external voltage source or a different external voltage source.

[0041] The VDD voltage passes through the VDD cable 41, the second connection terminal 22, the wire 5a of the second wiring layer 5, the first TSV 11, the wire 4a of the first wiring layer 4, and the substrate contact 8. The substrate contact 8 supplies the VDD voltage to the first electrode 3a.

[0042] The GND voltage passes through the GND cable 42, the fourth connection terminal 24, the wire 5b of the second wiring layer 5, the second TSV 12, the wire 4b of the first wiring layer 4, and the gate contact 7. The gate contact 7 supplies the GND voltage to the second electrode 3c. By supplying the VDD voltage and the GND voltage to the substrate contact 8 and the gate contact 7, respectively, the trench capacitor 3 accumulates charge.

[0043] The VDD voltage also passes through the first TSV 11, the wire 4a of the first wiring layer 4, and the first connection terminal 21. The first connection terminal 21 supplies the VDD voltage to a VDD terminal 32 of the image sensor 30. The GND voltage also passes through the second TSV 12, the wire 4b of the first wiring layer 4, and the third connection terminal 23. The third connection terminal 23 supplies the GND voltage to a GND terminal 33 of the image sensor 30. The image sensor 30 drives the pixels 31 by using the VDD voltage and the GND voltage to stably generate image signals.

[0044] The process of stabilizing the VDD voltage by the semiconductor device 1 is described below. An external voltage source (not shown) may supply a VDD voltage to the VDD cable 41. The value of the VDD voltage supplied to the VDD cable 41 may be a predetermined value (a first value, such as 3.3V) in normal operation. The VDD voltage having the first value is supplied to the image sensor 30, and the image sensor 30 generates an image signal by using the VDD voltage having the first value. However, the value of the VDD voltage may drop from the first value to a second value (e.g., 3.0V) due to disturbances or other factors. The VDD voltage supplied to the image sensor 30 may also drop similarly. In this situation, the trench capacitor 3 of the semiconductor device 1 accumulates charges according to the first value of the VDD voltage before the voltage drops. The trench capacitor 3 of the semiconductor device 1 also increases the value of the VDD voltage supplied to the image sensor 30 by using the accumulated charges so as to maintain the value of the VDD voltage at the first value. As a result, the trench capacitor 3 stabilizes the value of the VDD voltage supplied to the image sensor 30. The image sensor 30 can generate a stable image signal even if the value of the VDD voltage drops.

[0045] In another embodiment when the semiconductor device 1 and the image sensor 30 are stacked together, the rear surface of the image sensor 30 and the second surface 2b of the semiconductor substrate 2 face each other. In this case, the VDD terminal 32 is connected to the second connection terminal 22, and the GND terminal 33 is connected to the fourth connection terminal 24 (not shown).

[0046] (Third embodiment) 5 is a cross-sectional view that shows a schematic diagram of an imaging unit according to a third embodiment. As shown in FIG. 5, a semiconductor device 1a is stacked on an adjacent semiconductor device 1b. The exposed surface of the second wiring layer 5 of the semiconductor device 1a and the exposed surface of the first wiring layer 4 of the semiconductor device 1b face each other. In this situation, the second connection terminal 22 and the fourth connection terminal 24 of the semiconductor device 1a are connected to the first connection terminal 21 and the third connection terminal 23 of the adjacent semiconductor device 1b, respectively.

[0047] In addition, the rear surface of the image sensor 30 and the exposed surface of the first wiring layer 4 of the semiconductor device 1a face each other. The VDD terminal 32 is connected to the first connection terminal 21. The GND terminal 33 is connected to the third connection terminal 23.

[0048] The VDD cable 41 and the GND cable 42 are disposed on the exposed surface side of the second wiring layer 5 of the semiconductor device 1b. The chip terminal 41a of the VDD cable 41 is connected to the second connection terminal 22. The chip terminal 42a of the GND cable 42 is connected to the fourth connection terminal 24.

[0049] In another embodiment where the semiconductor devices 1a and 1b are stacked, the exposed surface of the second wiring layer 5 of the semiconductor device 1a and the exposed surface of the second wiring layer 5 of the semiconductor device 1b face each other (not shown). In this case, the second connection terminal 22 and the fourth connection terminal 24 of the semiconductor device 1a are connected to the second connection terminal 22 and the fourth connection terminal 24 of the adjacent semiconductor device 1b, respectively.

[0050] In another embodiment in which the semiconductor devices 1a and 1b are stacked, the exposed surface of the first wiring layer 4 of the semiconductor device 1a and the exposed surface of the first wiring layer 4 of the semiconductor device 1b face each other (not shown). In this case, the first connection terminal 21 and the third connection terminal 23 of the semiconductor device 1a are connected to the first connection terminal 21 and the third connection terminal 23 of the adjacent semiconductor device 1b, respectively.

[0051] As mentioned above, the semiconductor device 1a can be stacked on the adjacent semiconductor device 1b in various ways. The amount of charge to the image sensor 30 is increased by stacking multiple semiconductor devices. As a result, the VDD voltage supplied to the image sensor 30 is more stable, thereby generating a stable image signal from the image sensor 30.

[0052] (Fourth embodiment) Fig. 6 is a cross-sectional view of the semiconductor device 1 according to the fourth embodiment. Figs. 7A, 7B, and 7C are perspective views of certain components of the semiconductor device 1. Figs. 8A, 8B, and 8C are plan views of these components of the semiconductor device 1.

[0053] Figure 8A shows a plan view along arrow AA' in Figures 6 and 7A. Figure 8B shows a plan view along arrow BB' in Figures 6 and 7B. Figure 8C shows a plan view along arrow CC' in Figures 6 and 7C.

[0054] 7A to 7C and 8A to 8C, the semiconductor substrate 2 may further include third TSVs 13a, 13b, 13c, and 13d. The first wiring layer 4 may further include fifth connection terminals 25a, 25b, 25c, and 25d. The second wiring layer 5 may further include sixth connection terminals 26a, 26b, 26c, and 26d.

[0055] The third TSVs 13a, 13b, 13c and 13d may transmit an image signal, a clock signal, a synchronization signal and a second VDD voltage. The image signal generated by the image sensor 30 may be transmitted to a processor unit (not shown) via the third TSV 13a. The processor unit may transmit a clock signal to the image sensor 30 via the third TSV 13b. The clock signal is used by the image sensor 30 to control the timing of generating the image signal. The processor unit transmits a synchronization signal to the image sensor 30 via the third TSV 13c. The synchronization signal is used by the image sensor 30 to synchronize the image signal with the processor unit. An external voltage source supplies a second VDD voltage to the image sensor 30 via the third TSV 13d. The second VDD voltage may be used by the image sensor 30.

[0056] As shown in FIG. 6, the third TSV 13a and the fifth connection terminal 25a are connected by the wiring 4c of the first wiring layer 4. The third TSV 13a and the sixth connection terminal 26a are connected by the wiring 5c ​​of the second wiring layer 5. The third TSVs 13b, 13c, and 13d are connected to the fifth connection terminals 25b, 25c, and 25d, respectively, by the wiring 4c of the first wiring layer 4 in the same manner as the third TSV 13a (FIG. 7A). The third TSVs 13b, 13c, and 13d are connected to the sixth connection terminals 26b, 26c, and 26d, respectively, by the wiring 5c ​​of the second wiring layer 5 (FIG. 7C).

[0057] The image sensor 30 includes an image signal terminal 34a and a clock signal terminal 34b. The image sensor 30 may further include a synchronization signal terminal 34c and a second VDD terminal 34d (not shown).

[0058] When the rear surface of the image sensor 30 and the first surface 2a of the semiconductor substrate 2 face each other, the image signal terminal 34a is connected to the fifth connection terminal 25a, and the clock signal terminal 34b is connected to the fifth connection terminal 25b. The synchronization signal terminal 34c and the second VDD terminal 34d are connected to the fifth connection terminals 25c and 25d, respectively (not shown).

[0059] As shown in FIG. 8B, the first TSV 11, the second TSV 12, and the third TSVs 13a, 13b, 13c, and 13d may be disposed outside the area (outer area) of the trench capacitor area 51. The outer area of ​​the trench capacitor area 51 may include peripheral areas 52, 53 that surround or sandwich the trench capacitor area 51, which is the area on the semiconductor substrate 2 occupied by the trench capacitor 3. As an example, the peripheral areas 52, 53 may be disposed at diagonal edge portions of the semiconductor substrate 2, respectively. The peripheral areas 52, 53 may be rectangular in shape or various shapes suitable for disposing TSVs and allowing the trench capacitor area 51 to be as large as possible. The peripheral areas 52, 53 may have a horizontal width (W1) in the range of 10 micrometers to 50 micrometers and a vertical width (W2) in the range of 50 micrometers to 200 micrometers. The first TSV 11, the third TSVs 13a and 13c may be disposed in the peripheral area 52. The second TSV 12, the third TSVs 13b and 13d may be disposed in the peripheral area 53.

[0060] 8A and 8C, a plurality of connection terminals including the first connection terminal 21 to the sixth connection terminals 26a, 26b, 26c, and 26d can be distributed and disposed over the entire area of ​​the first wiring layer 4 and the second wiring layer 5 of the semiconductor device 1. These connection terminals may be disposed in various patterns suitable for arrangement, except that these connection terminals do not overlap with the TSVs when the semiconductor device 1 is viewed from above.

[0061] 8A, the first connection terminal 21, the third connection terminal 23, and the fifth connection terminals 25a, 25b, 25c, and 25d are "distributed" in the first wiring layer 4. The manner in which the first connection terminal 21, the third connection terminal 23, and the fifth connection terminals 25a, 25b, 25c, and 25d are disposed in the first wiring layer 4 (meaning "distributed") will be described below.

[0062] The first connection terminal 21, the third connection terminal 23, and the fifth connection terminals 25a, 25b, 25c, and 25d may be arranged, for example, at equal intervals in the region of the first wiring layer 4. The region in which the first connection terminal 21, the third connection terminal 23, and the fifth connection terminals 25a, 25b, 25c, and 25d are arranged in the first wiring layer 4 corresponds to and overlaps with the region of the first surface 2a where the trench capacitor 3 occupies the semiconductor substrate 2 (trench capacitor area 51).

[0063] Another embodiment in which the first connection terminal 21, the third connection terminal 23, and the fifth connection terminals 25a, 25b, 25c, and 25d are evenly arranged on the first wiring layer 4 is defined below. As shown in FIG. 8A, the surface of the first wiring layer 4 may be substantially evenly divided into six areas by a virtual line X. Virtual points X1, X2, X3, X4, X5, and X6 are the center points of each of the six divided areas. The first connection terminal 21, the third connection terminal 23, and the fifth connection terminals 25a, 25b, 25c, and 25d may be arranged on the center points X1, X2, X3, X4, X5, and X6, respectively.

[0064] Yet another embodiment of disposing the first connection terminal 21, the third connection terminal 23 and the fifth connection terminals 25a, 25b, 25c and 25d is defined by the distance between the connection terminals and the edge portion of the first wiring layer 4 and between the TSVs and the edge portion of the semiconductor substrate 2. The first distance L1 may be, for example, a distance between the connection terminals and the edge portion of the first wiring layer 4 in the range of 50 micrometers to 100 micrometers. The second distance L2 may be a distance between the TSVs 11, 12 and 13a to 13d and the edge portion of the semiconductor substrate 2 in the range of 10 micrometers to 20 micrometers. The first distance L1 and the second distance L2 are set such that the first distance L1 is longer than the second distance L2.

[0065] Further arrangements of the first connection terminal 21, the third connection terminal 23, and the fifth connection terminals 25a, 25b, 25c, and 25d may be defined by the distances between adjacent connection terminals and between adjacent TSVs. The third distance L3 may be, for example, a distance between adjacent connection terminals in the range of 50 micrometers to 80 micrometers. The fourth distance L4 may be a distance between adjacent TSVs in the range of 10 micrometers to 20 micrometers. The third distance L3 and the fourth distance L4 are set such that the third distance L3 is longer than the fourth distance L4.

[0066] The second connection terminal 22, the fourth connection terminal 24, and the sixth connection terminals 26a, 26b, 26c, and 26d can also be arranged in a distributed and even manner on the second wiring layer 5, in the same manner as the first connection terminal 21, the third connection terminal 23, and the fifth connection terminals 25a, 25b, 25c, and 25d are arranged.

[0067] As described above, a plurality of connection terminals including the first connection terminal 21 to the sixth connection terminals 26a, 26b, 26c, and 26d can be distributed and disposed over the entire area of ​​the first wiring layer 4 and the second wiring layer 5 of the semiconductor device 1. With such a structural arrangement, when the semiconductor device 1 is connected to another board or another cable, stress caused by the connection process is distributed over the entire area of ​​the first wiring layer 4 and the second wiring layer 5 of the semiconductor device 1. As a result, damage caused by stress concentration on the semiconductor device 1 due to the connection process can be minimized or mitigated.

[0068] 8B, the first TSV 11, the second TSV 12, and the third TSVs 13a, 13b, 13c, and 13d penetrate the semiconductor substrate 2 in the outer area of ​​the trench capacitor area 51. The first TSV 11, the second TSV 12, and the third TSVs 13a, 13b, 13c, and 13d may be disposed in the peripheral areas 52, 53. According to this exemplary structure arrangement, the trench capacitor area 51 occupies a larger portion of the first surface 2a, preferably occupies at least 70% of the total area of ​​the first surface 2a, thereby increasing the amount of charge of the semiconductor device 1. Furthermore, the third TSVs 13a, 13b, 13c, and 13d may be used to transmit image signals, clock signals, synchronization signals, and the second VDD voltage, respectively, in the thickness direction of the semiconductor device 1.

[0069] Fifth embodiment Fig. 9 is a perspective view of an endoscope system 200 according to a fifth embodiment. As shown in Fig. 9, the endoscope system 200 includes an endoscope 201, a processor 206, and a display device 207. The endoscope 201 includes a transmission cable 203, an operation unit 204, a connector unit 205, and an insertion component portion 202.

[0070] The insertion component 202 is a part of the transmission cable 203. The insertion component 202 is inserted into a subject. The insertion component 202 includes a flexible bending component 212 and a tip component 211. The flexible bending component 212 can be bent in a desired direction by operating the operation unit 204.

[0071] Any of the imaging units 100 disclosed in the above embodiments can be disposed in the tip component 211. FIG. 10 is a cross-sectional view of the tip component 211 of the endoscope 201. The tip component 211 includes an optical waveguide 216, an illumination lens 213, an imaging lens 214, a treatment tool passage 215, and the imaging unit 100. The optical waveguide 216 transmits illumination light from a light source device (not shown). The illumination lens 213 irradiates an object (not shown) with the illumination light. A treatment tool (not shown) is inserted into the treatment tool passage 215.

[0072] The imaging unit 100 may be disposed within the tip component 211. The front surface of the image sensor 30 having the pixels 31 faces the imaging lens 214. The imaging lens 214 forms an image of the subject on the pixels 31 of the image sensor 30.

[0073] The VDD cable 41, the GND cable 42, and the image signal cable 43 may be disposed in the transmission cable 203. Each of the VDD cable 41, the GND cable 42, and the image signal cable 43 has one end component part connected to the semiconductor device 1 of the imaging unit 100. Each of the VDD cable 41, the GND cable 42, and the image signal cable 43 has another end component part connected to the connector unit 205.

[0074] The clock signal cable, the synchronization signal cable, and the second VDD cable may be disposed inside the transmission cable 203 (not shown). Each of the clock signal cable, the synchronization signal cable, and the second VDD cable has one end component connected to the semiconductor device 1 of the imaging unit 100. Each of the clock signal cable, the synchronization signal cable, and the second VDD cable has another end component connected to the connector unit 205.

[0075] The imaging unit 100 of the endoscope 201 generates an image signal (image data) by capturing an internal image of a subject. The imaging unit 100 outputs the generated image signal to an image signal cable 43 in the transmission cable 203. The processor 206 receives the image signal from the image signal cable 43.

[0076] The connector unit 205 connects the endoscope 201 and the processor 206. The connector unit 205 performs predetermined signal processing of the image signal output from the imaging unit 100. The connector unit 205 also performs A / D conversion to convert an analog image signal into a digital image signal. The connector unit 205 outputs the digital image signal to the processor 206.

[0077] The processor 206 performs predetermined image processing on the image signal output from the connector unit 205. The processor 206 also controls the endoscope system 200. The processor 206 may include a voltage source. The voltage source may supply a VDD voltage and a GND voltage to the VDD cable 41 and the GND cable 42, respectively.

[0078] The display device 207 displays an image corresponding to the image signal processed by the processor 206. The display device 207 may also display various types of information of the endoscope system 200. The endoscope system 200 includes a light source device (not shown) for generating illumination light that illuminates an object.

[0079] As described above, the imaging unit 100 may be disposed in the tip component 211. The semiconductor device 1 of the imaging unit 100 stabilizes the VDD voltage supplied to the image sensor 30. As a result, the image sensor 30 generates a stable image signal. The semiconductor device 1 and the image sensor 30 may also be stacked in the longitudinal direction of the tip component 211. With such a structural arrangement, the semiconductor device 1 does not increase the diameter of the imaging unit 100, thereby ensuring a smaller diameter of the endoscope 201.

[0080] It will be apparent to those skilled in the art that various modifications and variations can be made in the semiconductor device, the imaging unit, and the endoscope system using the semiconductor device of the present invention without departing from the spirit or scope of the present invention. Therefore, the present invention is intended to cover the modifications and variations of the present invention as long as they come within the scope of the appended claims and their equivalents. [Explanation of symbols]

[0081] 1, 1a, 1b Semiconductor device 2. Semiconductor Substrate 2a 1st surface 2b 2nd surface 3. Trench Capacitor 3a 1st electrode 3b dielectric layer 3c 2nd electrode 4 1st wiring layer 5 2nd wiring layer 7 Gate Contact 8 Board Contacts 11 1st TSV 12 2nd TSV 13a, 13b, 13c, 13d 3rd TSV 21 First connection terminal 22 Second connection terminal 23 Third connection terminal 24 4th connection terminal 25a, 25b, 25c, 25d 5th connection terminal 26a, 26b, 26c, 26d 6th connection terminal 30 Image Sensor 31 pixels 32 VDD pin 33 GND terminal 100 Imaging unit 201 Endoscope

Claims

1. a semiconductor substrate having opposed first and second surfaces; a trench capacitor disposed on the first surface of the semiconductor substrate; a first wiring layer disposed on the first surface of the semiconductor substrate and covering the trench capacitor; a second wiring layer disposed on the second surface of the semiconductor substrate; a first TSV (Through Silicon Via) penetrating the semiconductor substrate outside the trench capacitor; a second TSV penetrating the semiconductor substrate outside the trench capacitor; a first connection terminal disposed in the first wiring layer and connected to the first TSV; a second connection terminal disposed in the second wiring layer and connected to the first TSV; a third connection terminal disposed in the first wiring layer and connected to the second TSV; a fourth connection terminal disposed in the second wiring layer and connected to the second TSV; a semiconductor device, wherein a plurality of connection terminals including the first connection terminal, the second connection terminal, the third connection terminal, and the fourth connection terminal are distributed and arranged over the entire area of ​​the first wiring layer and the second wiring layer, except for not overlapping with the first TSV and the second TSV.

2. 2 . The semiconductor device according to claim 1 , wherein the first surface of the semiconductor substrate includes a first region occupied by the trench capacitor and a second region through which the first TSV and the second TSV pass.

3. The semiconductor device according to claim 2 , wherein the first region of the first surface is larger than the second region of the first surface.

4. The semiconductor device of claim 1 , wherein the first wiring layer includes a substrate contact and a gate contact.

5. 5. The semiconductor device of claim 4, wherein the trench capacitor includes a first electrode, a second electrode and a dielectric layer, the first electrode and the second electrode sandwiching the dielectric layer, the gate contact being connected to the second electrode, and the substrate contact being connected to the first electrode.

6. The semiconductor device according to claim 4 , wherein the substrate contact is connected to the first TSV and the gate contact is connected to the second TSV by a wiring in the first wiring layer.

7. 3. The semiconductor device according to claim 2, wherein a plurality of connection terminals including at least the first connection terminal and the third connection terminal are evenly spaced apart in a region of the first wiring layer, and the region of the first wiring layer overlaps with the first region of the first surface of the semiconductor substrate occupied by the trench capacitor.

8. 3. The semiconductor device according to claim 2, wherein a plurality of connection terminals including at least the second connection terminal and the fourth connection terminal are evenly spaced apart in a region of the second wiring layer, the region of the second wiring layer corresponding to the first region of the first surface of the semiconductor substrate occupied by the trench capacitor.

9. 2. The semiconductor device of claim 1, stacked on an adjacent semiconductor device such that the second connection terminal and the fourth connection terminal of the semiconductor device are connected to the first connection terminal and the third connection terminal of the adjacent semiconductor device, respectively.

10. 2. The semiconductor device of claim 1, stacked on an adjacent semiconductor device such that the second connection terminal and the fourth connection terminal of the semiconductor device are connected to the second connection terminal and the fourth connection terminal of the adjacent semiconductor device, respectively.

11. 2. The semiconductor device of claim 1, stacked on an adjacent semiconductor device such that the first and third connection terminals of the semiconductor device are connected to the first and third connection terminals of the adjacent semiconductor device, respectively.

12. An image sensor having pixels on a front surface and a ground terminal and a VDD terminal on a rear surface; The semiconductor device according to claim 1, the first connection terminal and the third connection terminal of the semiconductor device are connected to the VDD terminal and the ground terminal of the image sensor, respectively.

13. An image sensor having pixels on a front surface and a ground terminal and a VDD terminal on a rear surface; The semiconductor device according to claim 1, the second connection terminal and the fourth connection terminal of the semiconductor device are connected to the VDD terminal and the ground terminal of the image sensor, respectively.

14. the plurality of connection terminals include at least a fifth connection terminal on the first wiring layer and a sixth connection terminal on the second wiring layer; The fifth connection terminal is connected to the sixth connection terminal via a third TSV. The imaging unit according to claim 13.

15. The imaging unit according to claim 14 , wherein the third TSV transmits at least one of an image signal, a clock signal, and a synchronization signal.

16. An endoscope comprising the imaging unit according to claim 12.

17. An endoscope comprising the imaging unit according to claim 13.

Images