Power Management Advisor to support power management controls

Abstract

To provide an apparatus, method, and processing unit equipped with a power management advisor circuit and a power management controller circuit for supporting power management control.SOLUTION: An apparatus 100 includes a plurality of registers to store sets of state information that represent a state history of a processing unit (GPU115, CPU130). The GPU also includes a power management advisor (PMA) 160 to generate a signal based on the sets of state information, wherein the signal indicates a probability that a power state transition of the processing unit achieves a target outcome. In some cases, the signal is provided to a power management controller (PMC150, PMC155) including a hardware circuit that initiates a power state transition of the processing unit based on the signal and inputs to the power management controller that represent a subset of the state information corresponding to a current power state of the processing unit.SELECTED DRAWING: Figure 1

Description

[Background technology]

[0001] Processing units, such as central processing units (CPUs), graphics processing units (GPUs), and accelerated processing units (APUs), can improve performance or save power by transitioning between different power management states. For example, a processing unit can save power by idling when the processing unit has no instructions to execute. If the processing unit is idle for a relatively long period of time, the power supplied to the processing unit is power gated so that no current is supplied to the processing unit, thereby reducing standby and leakage power consumption. For example, a processor core in a CPU may be power gated if the processor core is idle for longer than a predetermined time interval. However, power management techniques that change the power management state of a processing unit may consume a large amount of system resources compared to the resources saved by the state change. For example, power gating a processor core requires flushing caches in the processor core and saving information that defines the state of the processor core, which consumes both time and power. A transition from a low power state (such as an idle state or a power gating state) to an active state requires a performance cost to return the processor core to the active state, such as when saved state information needs to be copied back to registers within the processor core. Summary of the Invention [Means for solving the problem]

[0002] In one aspect, an apparatus includes a plurality of registers that store a set of state information representative of a state history of a processing unit. The apparatus further includes a power management advisor (PMA) that generates a signal based on the set of state information, the signal indicating a probability that a power state transition of the processing unit will achieve a target outcome. In one embodiment, a first register of the plurality of registers stores a first set of state information representative of a current state of the processing unit, and at least one second register of the plurality of registers stores a second set of at least one state information representative of at least one previous state of the processing unit. In this case, the first set of state information may be copied to the at least one second register in response to the processing unit transitioning to a new power state, and a new set of state information corresponding to the new power state may be stored in the first register in response to the processing unit transitioning to the new power state. In one embodiment, the set of state information includes at least one of a power state of the processing unit, values ​​of performance counters implemented in the processing unit, characteristics of instructions or draw call commands queued for execution on the processing unit, inputs to a power management controller that determine whether to initiate a power state transition of the processing unit, information indicative of the decision made by the power management controller, a type of application executing on the processing unit, hints provided by the application, and a signal generated by the PMA. In one embodiment, the PMA generates a value for the signal by comparing the set of state information in the multiple registers with a previous result of a power state transition corresponding to the set of state information. In this case, the target result can be at least one of a performance gain or power savings due to the power state transition that exceeds at least one of a performance cost or increased energy usage due to the power state transition. Additionally, the previous result associated with the set of state information can indicate whether the performance gain or power savings due to the previous power state transition exceeded the corresponding performance cost or increased energy usage due to the previous power state transition.In one embodiment, the PMA includes a neural network that generates a probability that a power state transition of the processing unit from a current power state to a plurality of available power states will achieve a target outcome. In one embodiment, the signal is provided to a power management controller that initiates a power state transition of the processing unit, and the apparatus further includes a state machine indicating weights to be applied to the signal provided by the PMA and the power state transition decision made by the power management controller to determine whether to initiate a power state transition of the processing unit.

[0003] In another aspect, the power management controller includes a hardware circuit configured to receive a signal generated by a power management advisor (PMA), the PMA generating a signal based on a first set of state information representative of a current state of the processing unit and a second set of at least one state information representative of at least one previous state of the processing unit, the signal indicating a probability that a power state transition of the processing unit will achieve a target outcome. Further, the hardware circuit is configured to initiate a power state transition of the processing unit based on the signal and an input representative of a subset of the first set of state information. In one embodiment, the first and second sets of state information include at least one of a power state of the processing unit, values ​​of performance counters implemented in the processing unit, characteristics of instructions or draw call commands queued for execution on the processing unit, inputs to the power management controller, information indicative of a decision to be made by the power management controller, a type of application executing on the processing unit, hints provided by the application, and a signal generated by the PMA. The hardware circuit can generate a prediction of a subsequent power state after a power state transition of the processing unit based on these inputs. In one embodiment, the hardware circuitry is configured to receive information indicating weights to be applied to signals provided by the PMA and predictions made by the power management controller, and the hardware circuitry applies these weights to the signals and predictions to determine whether to initiate a power state transition of the processing unit.

[0004] According to yet another aspect, the processing unit includes a power management controller that generates a prediction of a subsequent power state after a power state transition of the processing unit from a current power state based on an input representative of a current power state of the processing unit and from a plurality of available power states. The processing unit further includes a power management advisor (PMA) that generates a signal based on a set of state information representative of a state history of the processing unit, the signal indicating a probability that a power state transition of the processing unit to the plurality of available power states will achieve a target outcome. The power management controller selects a subsequent power state based on the prediction and the signal. In one embodiment, the processing unit further includes a plurality of registers, a first register of the plurality of registers storing a first set of state information representative of a current state of the processing unit, and at least one second register of the plurality of registers storing a second set of at least one state information representative of at least one previous state of the processing unit, and the PMA accesses the first set and the at least one second set of state information from the plurality of registers. In one embodiment, the first set of state information is copied to at least one second register in response to the processing unit transitioning to a subsequent power state, and a new set of state information corresponding to the subsequent power state is stored in the first register in response to the processing unit transitioning to the subsequent power state. In one embodiment, the set of state information includes at least one of a power state of the processing unit, values ​​of performance counters implemented in the processing unit, characteristics of instructions or draw call commands queued for execution on the processing unit, inputs to a power management controller, information indicative of decisions made by the power management controller, a type of application executing on the processing unit, hints provided by the application, and signals generated by the PMA.In one embodiment, the PMA includes a neural network that generates a probability that a power state transition of the processing unit from a current power state to a plurality of available power states will achieve a target outcome, and the processing unit further includes a state machine that indicates weights to be applied to signals provided by the PMA and power state transition decisions made by the power management controller to determine whether to initiate a power state transition of the processing unit.

[0005] The present disclosure can be better understood, and its numerous features and advantages made apparent to those skilled in the art by referencing the following drawings, in which: The use of the same reference numbers in different drawings indicates similar or identical elements. [Brief description of the drawings]

[0006] [Figure 1] FIG. 1 is a block diagram of a processing system, according to some embodiments. [Diagram 2] 1 is a block diagram of a power management system according to some embodiments. [Diagram 3] 1 is a block diagram of a circuit including a power management advisor according to some embodiments. [Figure 4] FIG. 4 is a state diagram illustrating a state sequence of a processing unit according to some embodiments. [Diagram 5] FIG. 1 is a block diagram of a power management control system according to some embodiments. [Figure 6] FIG. 2 is a block diagram of a state machine that determines the weights to be applied, according to some embodiments. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0007] The power management controller in the processing unit is implemented as a reactive controller that decides whether to change the power state of the processing unit based on the current state without regard to the state history of the processing unit. A conventional power management controller monitors the activity in the GPU computational unit, the value of the power consumed by the GPU, the value of the current drawn by the GPU, the temperature and other state information to decide whether to change the power state by modifying the clock frequency or voltage supplied to the components. For example, a Markov chain model can be used to predict power state transitions, which are probabilistic models that describe a sequence of possible events where the probability of each event depends only on the state achieved in the previous event. Conventional power management controllers make incorrect decisions in some situations, for example, by inducing power state transitions that incur a performance cost or a large increase in energy usage without resulting in power savings or performance gains.

[0008] 1-6 disclose a power management advisor that supports a conventional local power management controller in a processing unit. The power management advisor generates a signal (referred to herein as "advice") based on the current state of the processing unit and one or more previous states of the processing unit. The advice indicates the probability that the power state transition determined by the local power management controller will achieve a target result (e.g., the performance gain or power savings due to the power state transition exceeds the cost of the power state transition). In some embodiments, the current and previous states are defined by the corresponding power states, values ​​of performance counters, characteristics of instructions or draw call commands queued for execution in the processing unit, inputs to the local power management controller, decisions made by the local power management controller, application types, application hints, and advice generated by the power management advisor. The power management advisor determines a value for the advice by comparing the state information sequence represented by the current and previous states of the processing unit with previous results of the corresponding power state transitions triggered by the power management controller. In some embodiments, the previous results indicate whether the performance gain or power savings from the previous power state transition outweighed the corresponding performance cost or increase in energy usage.

[0009] Some embodiments of the power management advisor implement a neural network that generates a probability indicating which of the available power states is the next power state based on the current and previous state sequences of the processing unit. The probability indicates the likelihood that a power state transition of the processing unit to each available power state will achieve a target outcome (e.g., the likelihood that the performance gain or power savings will outweigh the corresponding performance cost or increase in energy usage, etc.). The neural network can be trained using a training data set generated by simulation or on-the-fly feedback indicating the effectiveness of previous power state changes. The power management advisor can also implement a state machine indicating weights. These weights are applied to advice generated by the power management advisor and to decisions made by the local power management controller. Some embodiments of the local power management controller apply the weights to the advice and to the decision to determine the next power state.

[0010] 1 is a block diagram of a processing system 100 according to some embodiments. The processing system 100 includes or has access to a memory 105 or other storage component implemented using a non-transitory computer-readable medium, such as dynamic random access memory (DRAM). However, the memory 105 may be implemented using other types of memory, including static random access memory (SRAM), non-volatile RAM, etc. The processing system 100 includes a bus 110 for supporting communication between entities implemented within the processing system 100, such as the memory 105. Some embodiments of the processing system 100 include other buses, bridges, switches, routers, etc. that are not shown in FIG. 1 for clarity.

[0011] The processing system 100 includes a graphics processing unit (GPU) 115 configured to render an image that is presented to a display 120. For example, the GPU 115 may render an object to generate pixel values ​​that are provided to the display 120, which uses the pixel values ​​to display an image that represents the rendered object. Some embodiments of the GPU 115 may also be used for general-purpose computing. In the illustrated embodiment, the GPU 115 implements multiple processing elements (not shown in FIG. 1 for clarity) configured to execute instructions simultaneously or in parallel. In the illustrated embodiment, the GPU 115 communicates with the memory 105 via a bus 110. However, some embodiments of the GPU 115 communicate with the memory 105 via a direct connection or via other buses, bridges, switches, routers, etc. The GPU 115 may execute instructions stored in the memory 105, and the GPU 115 may store information in the memory 105, such as results of executed instructions. For example, the memory 105 may store a copy 125 of instructions from a program code that has been executed by the GPU 115 .

[0012] The processing system 100 also includes a central processing unit (CPU) 130, which is connected to a bus 110 and communicates with a GPU 115 and a memory 105 via the bus 110. The CPU 130 can execute instructions such as program code 135 stored in the memory 105, and the CPU 130 can store information such as results of the executed instructions in the memory 105. The CPU 130 can also start graphics processing by issuing a draw call to the GPU 115.

[0013] An input / output (I / O) engine 140 processes input / output operations related to the display 120 and other elements of the processing system 100, such as a keyboard, a mouse, a printer, and an external disk. The I / O engine 140 is coupled to the bus 110 such that the I / O engine 140 can communicate with the memory 105, the GPU 115, or the CPU 130. In the illustrated embodiment, the I / O engine 140 is configured to read information stored in an external storage component 145 implemented using a non-transitory computer-readable medium, such as a compact disc (CD), a digital video disc (DVD), or the like. The I / O engine 140 can also write information, such as results of processing by the GPU 115 or the CPU 130, to the external storage component 145.

[0014] Some embodiments of the GPU 115 implement a power management controller (PMC) 150 that executes power management policies, such as policies provided by an operating system (OS) implemented in the CPU 130. The PMC 150 may also be referred to as (or implemented as part of) a system management unit. Some embodiments of the PMC 150 manage the thermal and power conditions of the GPU 115 according to policies set by the OS, using information provided to the PMC 150, such as power consumption by entities within the GPU 115 or temperatures at different locations within the GPU 115. The PMC 150 controls the power state of the GPU 115, for example, by changing the operating frequency or operating voltage supplied to the GPU 115 or to the computational units implemented in the GPU 115. Some embodiments of the CPU 130 also implement a separate PMC 155 for controlling the power state of the CPU 130.

[0015] PMC 150 initiates power state transitions between power management states of GPU 115 to save power, improve performance, or achieve other desired results. The power management states may include an active state, an idle state, a power gating state, and several other states that consume different amounts of power. For example, power states of GPU 115 may include an operating state, a halt state, a clock halt state, a sleep state in which all internal clocks are halted, a low-voltage sleep state, and a powered-down state. In some embodiments, additional power states are also available and are defined by different combinations of clock frequency, clock interruption, and supply voltage.

[0016] PMC 150 determines whether to initiate a transition between power management states by comparing the performance or power cost of the transition to the performance gain or power savings of the transition. For example, PMC 150 may apply a Markov chain model to determine whether to transition between power states based on the current state of GPU 115. However, PMC 150 uses only local information about the current state of GPU 115 to determine whether to initiate a power state transition. PMC 150 does not utilize state history (e.g., knowledge of previous states of GPU 115) to initiate a power state transition. For example, a Markov chain model determines the probability of a transition from one power state to another power state based only on states achieved in previous power state transitions.

[0017] Power state transitions are performed to achieve a target result, such as improved performance or reduced power consumption, but also incur a corresponding cost, such as reduced performance or temporary increased power consumption. For example, transitioning from a low clock frequency state to a high clock frequency state is expected to improve performance at the cost of increased power consumption. For example, powering down GPU 115 to save power requires flushing caches used by GPU 115 as well as restoring some caches when GPU 115 is powered on again. Due at least in part to the requirement to initiate power state transitions based only on local information, PMC 150 makes incorrect decisions in some situations (e.g., by triggering a power state transition that incurs a significant performance cost or by triggering a power state transition that increases energy consumption without corresponding power savings or performance gains).

[0018] GPU 115 includes a power management advisor (PMA) 160 that supports the operation of PMC 150 by generating signals (referred to herein as "advice") indicating probabilities of power state transitions to achieve a target result. PMA 160 is subordinate to GPU 115. As used herein, the term "subordinate" indicates that PMA 160 operates under the control of GPU 115, such as in response to instructions or signaling from GPU 115. Furthermore, signals generated by PMA 160 are provided to GPU 115 and do not pass through an intermediate device, such as bus 110. In the illustrated embodiment, PMA 160 is integrated into GPU 115. However, some embodiments of PMA 160 are implemented external to GPU 115 and interconnected with GPU 115 using wires, traces, or other connections. By implementing PMA 160 slaved to GPU 115, the latency of signals exchanged between PMA 160 and GPU 115 is significantly reduced compared to signals exchanged between GPU 115 and CPU 130, for example, via bus 110.

[0019] PMA 160 generates advice based on the current state of GPU 115 and state information about one or more previous states of GPU 115. In some embodiments, PMA 160 includes or has access to a register set used to store a set of power state information corresponding to the current state and previous states that represent the state history of GPU 115. This advice is provided to PMC 150, which uses the advice along with a prediction of a power state transition to determine whether to initiate a power state transition and, if so, the subsequent power state. Some embodiments of CPU 130 also implement PMA 165, which supports the operation of PMC 155 by generating advice based on the state history of CPU 130. PMA 165 is subordinate to CPU 130.

[0020] Some embodiments of the PMA 160 or PMA 165 are implemented using an artificial neural network, as described herein. The artificial neural network, which may be implemented as a recurrent neural network, a residual neural network, or other type of reinforcement learning structure, is represented as program code 170 configured with a corresponding set of parameters. Thus, the artificial neural network may run on the GPU 115 or CPU 130, or on other processing units, including field programmable gate arrays (FPGAs), application specific integrated circuits (ASICs), processing in memory (PIMs), etc. If the artificial neural network implements a known function that may be trained using a corresponding known data set, the artificial neural network is trained (i.e., values ​​of parameters defining the artificial neural network are established) by providing the artificial neural network running on the GPU 115 or CPU 130 with input values ​​of the known training data set and comparing the output values ​​of the artificial neural network with the labeled output values ​​of the known training data set. An error value is determined based on the comparison and back-propagated to change the values ​​of the parameters that define the artificial neural network. This process is repeated until the values ​​of the parameters meet a convergence criterion.

[0021] In some embodiments, CPU 130 implements additional software advisors that supplement the advice provided to PMC 150 by PMA 160 associated with GPU 115. For example, CPU 130 can implement additional neural networks that can estimate the validity of a prediction of a power state transition. With the additional processing power of CPU 130, the additional advisors can consider a longer state history, more state information, or a combination of these to determine whether a predicted power state transition is likely to achieve a target result. The additional advisors may be implemented external to processing system 100 (e.g., on a cloud system in communication with processing system 100, etc.).

[0022] 2 is a block diagram of a power management system 200 according to some embodiments. The power management system 200 includes a power management controller 205 and a power management advisor 210 that may be used to implement some embodiments of the PMCs 150, 155 and PMAs 160, 165 shown in FIG.

[0023] The power management controller 205 is referred to as a local power management controller 205 because it generates a signal 215 representative of a subsequent power state based on "local" information corresponding to a current power state of the processing unit implementing the power management system 200. The local information includes information indicative of one or more temperatures within the processing unit, power consumed by the processing unit, current drawn by the processing unit, and other activity. The local information is provided as an input 220. The power management controller 205 does not consider previous state information related to the power state history of the processing unit. For example, the power management controller 205 may implement a Markov chain model to determine the signal 215 based on the current state of the processing unit.

[0024] The power management advisor 210 is referred to as a global power management advisor 210 because it generates advice 225 that indicates one or more probabilities that one or more state transitions of the processing unit will achieve a goal outcome. For example, if the goal outcome is improved performance and the processing unit has multiple available power states, the advice 225 indicates the probability that a transition to each available power state will achieve the goal performance improvement. As described herein, other goal outcomes or combinations of goal outcomes, such as reduced power consumption, may also be used. The power management advisor 210 generates the advice 225 based on global information that characterizes the state of the processing unit and the state history of the processing unit. Thus, the power management advisor 210 receives the same inputs 220 as the local power management controller 205, as well as additional inputs 230 that include additional global state information that characterizes the current state of the processing unit and information that characterizes the state history of the processing unit. Information characterizing the current and previous states of the processing unit includes, but is not limited to, the power state of the processing unit, values ​​of performance counters implemented in the processing unit, characteristics of instructions or draw call commands queued for execution on the processing unit, inputs 220 to the power management controller 205 that determine whether to initiate a power state transition of the processing unit, information indicative of decisions made by the power management controller, such as signals 215, the types of applications running on the processing unit, hints provided by the applications, and signals generated by power management advisor 210 about the previous state of the processing unit.

[0025] The advice 225 generated by the global power management advisor 210 is provided as an additional input to the power management controller 205, which uses the advice 225 along with the input 220 to generate the signal 215 indicating the subsequent power state of the processing unit. Some embodiments of the power management controller 205 generate a prediction of the subsequent power state based on the input 220. The power management controller 205 then accepts or rejects the prediction and generates a new prediction based on the advice 225. For example, if the power management controller 205 predicts that a transition to an idle state will save power, but the advice 225 indicates that a previous transition from the current state to the idle state did not result in a net power saving, the power management controller 205 can reject the prediction and maintain the processing unit in the current active state. In another example, if the advice 225 indicates that there is at least a 50% probability that the state change will not achieve the target result, the power management controller 205 rejects the prediction. Some embodiments of power management advisor 210 include a state machine that indicates weights to be applied to predictions made by power management controller 205 and advice 225. These weights are communicated to power management controller 205 via signal 225. As described below, power management controller 205 uses the weights to determine whether to initiate a power state transition of a processing unit.

[0026] Figure 3 is a block diagram of a circuit 300 including a power management advisor 305, according to some embodiments. The power management advisor 305 may be used to implement some embodiments of the PMAs 160, 165 shown in Figure 1 and the global power management advisor 210 shown in Figure 2. Some embodiments of the power management advisor 305 implement a neural network, such as a convolutional neural network (CNN), as described below.

[0027] Circuit 300 includes a set of registers 310, 311, and 312, collectively referred to herein as "registers 310-312." Each of registers 310-312 stores state information relating to a corresponding power state of the processing unit. Register 310 stores state information relating to a current power state of the processing unit, register 311 stores state information relating to a previous power state of the processing unit, and register 312 stores state information relating to another previous power state of the processing unit that precedes the previous power state corresponding to the state information stored in register 311. The state information stored in registers 310-312 includes values ​​of performance counters associated with the current power state of the processing unit, inputs to a corresponding local power management controller, information indicative of a subsequent power state selected by the power management controller, values ​​of advice generated by power management advisor 305, application hints related to energy, power, and performance, etc. Although three registers 310-312 are shown in FIG. 3, some embodiments of circuit 300 include more or fewer registers used to store more or fewer sets of state information for the corresponding processing unit.

[0028] The performance counters stored in the registers 310-312 are implemented in hardware blocks within the processing unit associated with the power management advisor 305. In some embodiments, values ​​of performance counters from blocks that consume a relatively large amount of power are stored in the registers 310-312. For example, the registers 310-312 can store values ​​of performance counters from a shader array, a texture cache hierarchy, a DRAM, etc. The performance counters are used as features input to the power management advisor 305, and these values ​​are used as training samples for a neural network implemented in the power management advisor 305. During the inference of the neural network, or during the prediction stage of the neural network, the current values ​​of the performance counters are used as inputs to the neural network. The performance counters provide information indicative of system level status and performance. For example, a performance counter monitoring draw packets in the input command buffer of a processing unit may affect power state decisions. If the performance counter indicates a large number of draw packets, it is better not to change the power state to a lower power state. The processing unit needs to be in a higher power state to process the draw packets. This performance counter information is not available to the local performance management controller.

[0029] The state information stored in registers 310-312 is updated in response to update signal 314. In some embodiments, update signal 314 triggers the updating of registers 310-312 in response to a power state transition. Updating registers 310-312 involves shifting information from registers 310-312 to a register representing the next previous state. For example, state information in register 310 is shifted to register 311, state information in register 311 is shifted to register 312, and state information in register 312 is deleted or shifted to another register (not shown in FIG. 3). State information regarding the "new" current state, i.e., the state of the processing unit following the power state transition that triggered update signal 314, is stored in register 310.

[0030] The state information in registers 310-312 is provided to an input vector circuit 315, which generates an input vector 320 based on the provided state information. The input vector 320 includes state information from a sequence of corresponding power states of the processing unit over a sequence of time intervals, and thus represents a state history of the processing unit. Some embodiments of the input vector circuit 315 generate the input vector 320 by concatenating the values ​​of the state information stored in registers 310-312. However, other embodiments of the input vector circuit 315 generate the input vector 320 using various combinations of the state information stored in registers 310-312. The input vector 320 is provided to a power management advisor 305.

[0031] The information 325 representing the calculated validity of the previous state transition is provided to a training label circuit 330, which generates a label 335 indicating whether the previous state transition was valid. Some embodiments of the label 335 include a label indicating whether the previous state transition resulted in a target outcome, such as a performance gain, a reduction in energy usage, a combination of these, or other outcome. The training label circuit 330 provides the label 335 to the power management advisor 305, which uses the label 335 along with the input vector 320 to determine the probability that different power state transitions will result in the target outcome. As described herein, some embodiments of the power management advisor 305 are implemented as a neural network of a reinforcement learning structure. Examples of neural networks implemented in the power management advisor 305 include, but are not limited to, a recurrent neural network or a residual neural network. The neural network learns patterns of power state transitions and the probability that those patterns will result in the target outcome. Thus, power management advisor 305 can generate signal 340 representing the probability of achieving a goal outcome by comparing the state history represented by input 320 to the learned pattern. Training of the neural network can be performed using a training data set, feedback of signal 340 generated by power management advisor 305, or a combination thereof.

[0032] FIG. 4 is a state diagram 400 illustrating a sequence of states for a processing unit, according to some embodiments. State diagram 400 represents the states of some embodiments of GPU 115 or CPU 130 shown in FIG. 1. State diagram 400 shows a current state 401, a previous state 402, a previous previous state 403, an even previous previous state 404, and other states 405, 406, collectively referred to herein as "states 401-406." State diagram 400 shows transitions between states, such as transition 410 from previous state 402 to current state 401. Transitions, such as transition 415, that return the processing unit to current state 401 are also shown in FIG. 4. States 401-406 are characterized by values ​​of performance counters and other state information, as described herein. States 401-406 are also associated with control of clock speed, voltage, frequency, etc. Thus, a transition such as transition 410 may cause a change in a control signal to change a clock speed, voltage, frequency, other parameter value, or a combination thereof. In some embodiments, the state information characterizes multiple domains of the processing unit, such as a clock speed domain, a frequency / voltage domain, a power domain, etc.

[0033] A power management controller, such as the PMC 150, 155 shown in FIG. 1 or the local power management controller 205 shown in FIG. 2, uses local information to predict transitions between states 401-406. For example, the power management controller may implement a Markov chain model to predict probabilities of power state transitions. A Markov chain is a probabilistic model that describes possible event sequences where the probability of each event depends only on the state achieved by the previous event. These events are the states of hardware blocks of the chip (such as the GPU 115 or CPU 130 shown in FIG. 1) or other entities related to the power management controller. The power management controller generates the Markov chain model to predict a subsequent state given a current state 401 and a set of probabilities of transitions from the current state 401 to the subsequent state. The predictions (e.g., probabilities) of state transitions are updated at run-time.

[0034] FIG. 5 is a block diagram of a power management control system 500 according to some embodiments. The power management control system 500 is implemented in some embodiments of the processing system 100 shown in FIG. 1. The power management control system 500 includes a local power management controller 505 and a power management advisor implemented using a neural network 510. The local power management controller 505 is used to implement some embodiments of the PMCs 150 and 155 shown in FIG. 1 and the local power management controller 205 shown in FIG. 2. The neural network 510 is used to implement some embodiments of the PMAs 160 and 165 shown in FIG. 1, the global power management advisor 210 shown in FIG. 2, and the PMA 305 shown in FIG. 3. The processing unit implementing the power management control system 500 includes eight available power states 511, 512, 513, 514, 515, 516, 517, and 518, collectively referred to herein as "power states 511-518."

[0035] The power management controller 505 generates a prediction 520 that includes probabilities of state transitions between power states 511-518 based on local state information about the current power state (power state 511 in the illustrated embodiment). In some embodiments, the power management controller 505 generates the prediction 520 using Markov chain state transition probabilities (X[0..N-1]) from the current power state 511 to the available power states 511-518 of the processing unit. The value of N is the number of power states, such as eight power states, available in some GPU implementations.

[0036] Neural network 510 generates advice 525 that represents the probabilities of transitions to subsequent states. For example, these probabilities may be expressed as:

number

[0037] The total probability of transitions between power states 511-518 is given by the probability X (generated by the power management controller 505 using a conventional Markov chain) and P NN (generated by the neural network 510 based on state history). The state transition probabilities generated by the power management controller 505 using the local and global information are expressed as follows:

number

[0038] In some embodiments, the probabilities are weighted equally (e.g., the total probability is weighted to probabilities P and P NN In some embodiments, different weights, such as weights predicted using a state machine implemented in power management system 500, are used to estimate these probabilities P and P NN applies to.

[0039] FIG. 6 is a block diagram of a state machine 600 that determines the weights to be applied, according to some embodiments. The state machine 600 may be implemented in some embodiments of the PMAs 160, 165 shown in FIG. 1, the global power management advisor 210 shown in FIG. 2, the PMA 305 shown in FIG. 3, or the neural network 510 shown in FIG. 5. The state machine 600 includes four states 601, 602, 603, and 604, collectively referred to herein as "states 601-604." State 601 includes a first weighting with a value of 1 that is applied to predictions generated by a local power management controller (e.g., Markov chain probabilities X[0..N-1]) and a second weighting with a value of 0 that is applied to advice generated by the global power management advisor (e.g., probabilities P generated by the neural network 510 based on state history). NN ) and . In state 602, the first weight has a value of 0.5 that is applied to predictions generated by the local power management controller, and the second weight has a value of 0.5 that is applied to advice generated by the global power management advisor. In state 603, the first weight has a value of 0 and the second weight has a value of 1. In state 604, the first weight has a value of 0.5 and the second weight has a value of 0.5.

[0040] Transitions between states 601-604 are determined based on whether a goal result was achieved in the previous state transition. For example, the goal result is achieved if the performance gain or power savings is increased by an amount that exceeds the cost of the power state transition. The goal result is not achieved if the performance gain or power savings does not exceed the cost of the power state transition. If the goal result is achieved, as shown by transition 610, state machine 600 remains in state 601. If the goal result is not achieved, as shown by transition 611, state machine 600 transitions from state 601 to state 602. If the goal result is achieved, as shown by transition 612, state machine 600 remains in state 602. If the goal result is not achieved, as shown by transition 613, state machine 600 transitions from state 602 to state 603. If the goal result is achieved, as shown by transition 614, state machine 600 remains in state 603. If the goal outcome is not achieved, as indicated by transition 615, state machine 600 transitions from state 603 to state 604. If the goal outcome is achieved, as indicated by transition 616, state machine 600 remains in state 604. If the goal outcome is not achieved, as indicated by transition 617, state machine 600 transitions from state 601 to state 601.

[0041] The weights defined by the states 601 to 604 are the ratio of the probability P predicted by the local power management controller to the probability P of the advice generated by the global power management advisor. NN In some embodiments, the global power management advisor provides weights along with (or as part of) the advice to the local power management controller. The local power management controller determines whether to initiate a power state transition by applying the weights to the probabilities. The overall probability of transitioning to different power states is given by:

number

[0042] Some embodiments of state machine 600 implement more or fewer states that represent different combinations of weightings applied to the probabilities generated by the local power management controller and the global power management advisor.

[0043] In some embodiments, the above apparatus and techniques are implemented in a system that includes one or more integrated circuit (IC) devices (also referred to as integrated circuit packages or microchips), such as the power management systems described above with reference to FIGS. 1-6. Electronic design automation (EDA) and computer-aided design (CAD) software tools are used to design and manufacture these IC devices. These design tools are typically represented as one or more software programs. The one or more software programs include code executable by a computer system that operates the computer system to operate on the code representing the circuits of the one or more IC devices to perform at least a portion of the processing to design or adapt a manufacturing system for manufacturing the circuits. This code may include instructions, data, or a combination of instructions and data. The software instructions representing the design or manufacturing tools are typically stored in a computer readable storage medium accessible by the computing system. Similarly, the code representing one or more phases of the design or manufacture of the IC devices may be stored in or accessed from the same or different computer readable storage medium.

[0044] A computer-readable storage medium includes any non-transitory storage medium or combination of non-transitory storage media that can be accessed by a computer system during use to provide instructions and / or data to the computer system. Such storage media may include, but are not limited to, optical media (e.g., compact discs (CDs), digital versatile discs (DVDs), Blu-ray discs), magnetic media (e.g., floppy disks, magnetic tape, magnetic hard drives), volatile memory (e.g., random access memory (RAM) or cache), non-volatile memory (e.g., read-only memory (ROM) or flash memory), or microelectromechanical system (MEMS)-based storage media. A computer-readable storage medium may be internal to a computer system (e.g., system RAM or ROM), fixedly attached to a computer system (e.g., magnetic hard drives), removably attached to a computer system (e.g., optical disks or Universal Serial Bus (USB)-based flash memory), or connected to a computer system via a wired or wireless network (e.g., network-accessible storage (NAS)).

[0045] In some embodiments, some aspects of the above techniques may be implemented by one or more processors of a processing system executing software. The software includes one or more sets of executable instructions stored in or tangibly embodied on a non-transitory computer-readable storage medium. The software may include instructions and specific data that, when executed by one or more processors, operate the one or more processors to perform one or more aspects of the above techniques. The non-transitory computer-readable storage medium may include, for example, a magnetic or optical disk storage device, a solid-state storage device such as a flash memory, a cache, a random access memory (RAM), or one or more other non-volatile memory devices, etc. The executable instructions stored on the non-transitory computer-readable storage medium may be source code, assembly language code, object code, or other instruction formats that can be interpreted or executed by one or more processors.

[0046] In addition to the above, it should be noted that not all activities or elements described in the summary description are required, some of the specific activities or devices may not be required, one or more additional activities may be performed, and one or more additional elements may be included. Furthermore, the order in which the activities are listed is not necessarily the order in which they are performed. Also, the concepts have been described with reference to specific embodiments. However, those skilled in the art will appreciate that various changes and modifications can be made without departing from the scope of the invention as set forth in the claims. Thus, the specification and drawings should be regarded in an illustrative rather than a restrictive sense, and all such modifications are intended to be included within the scope of the invention.

[0047] Benefits, other advantages, and solutions to problems have been described above with respect to specific embodiments. However, the benefits, advantages, solutions to problems, and features by which any benefit, advantage, or solution may occur or be manifested are not to be construed as critical, essential, or essential features of any or all claims. Moreover, the specific embodiments described above are illustrative only, as the disclosed invention may be modified and practiced in different but similar manners apparent to those skilled in the art having the benefit of the teachings herein. No limitations are intended to the details of construction or design herein shown, other than as set forth in the appended claims. It is therefore apparent that the specific embodiments described above may be altered or modified, and all such variations are considered to be within the scope of the disclosed invention. Accordingly, the protection sought herein is set forth in the appended claims.

Claims

1. a power management advisor circuit (PMAC) that provides an indication of a probability that a performance gain or power savings resulting from a power state transition of the processing unit outweighs at least one cost of the power state transition based on at least one outcome of at least one previous state transition of the processing unit; and a power management controller circuit configured to select a subsequent power state transition of the processing unit based on the probability. Device.

2. a plurality of registers configured to store a set of state information representative of at least one result of at least one previous state transition of the processing unit; a first register of the plurality of registers stores a first set of state information representative of a current state of the processing unit, and at least one second register of the plurality of registers stores a second set of at least one state information representative of at least one result of at least one previous state transition of the processing unit; 2. The apparatus of claim 1.

3. the first set of state information is copied to the at least one second register in response to the processing unit transitioning to a new power state, and a new set of state information corresponding to the new power state is stored in the first register in response to the processing unit transitioning to the new power state.

3. The apparatus of claim 2.

4. the set of state information includes at least one of: a power state of the processing unit, values ​​of performance counters implemented in the processing unit, characteristics of instructions or draw call commands queued for execution on the processing unit, inputs to the power management controller circuit that determine whether to initiate a power state transition of the processing unit, information indicative of a decision made by the power management controller circuit, a type of application executing on the processing unit, hints provided by the application, and signals generated by the PMAC.

3. The apparatus of claim 2.

5. the PMAC generates the indicator by comparing the set of state information in the plurality of registers with at least one result of at least one previous state transition of the processing unit.

3. The apparatus of claim 2.

6. the at least one cost of the power state transition includes at least one of a performance cost or increased energy usage due to the power state transition.

6. The apparatus of claim 5.

7. at least one result of the at least one previous state transition indicates whether a performance gain or power savings due to a previous power state transition outweighs a corresponding performance cost or increase in energy usage due to the previous power state transition; 7. The apparatus of claim 6.

8. the PMAC comprises a neural network that generates a probability that a performance cost or power savings resulting from a power state transition from a current power state of the processing unit to a plurality of available power states exceeds a cost of at least one of the power state transitions.

2. The apparatus of claim 1.

9. a state machine indicating the weighting to be applied to the indication provided by the PMAC and the power state transition decision made by the power management controller circuit to determine whether to initiate a power state transition of the processing unit; 2. The apparatus of claim 1.

10. the PMAC is configured to generate the indicator based on the at least one previous state transition and at least one previous result indicating whether the at least one previous state transition results in at least one of: a performance gain due to the at least one previous state transition outweighing a performance cost of the at least one previous state transition; and a power savings due to the at least one previous state transition outweighing an increase in energy usage due to the at least one previous state transition.

2. The apparatus of claim 1.

11. providing advice to a power management controller circuit, in a power management advisor circuit (PMAC), based on a first set of state information representative of a current state of a processing unit and a second set of at least one state information representative of at least one previous result of at least one previous power state transition of the processing unit, the advice indicating a probability that a performance gain or power savings resulting from a power state transition of the processing unit will outweigh at least one cost of the power state transition; and selecting, in the power management controller circuitry, a subsequent power state transition of the processing unit based on the advice. method.

12. the first set of state information and the second set of at least one state information include at least one of a power state of the processing unit, values ​​of performance counters implemented in the processing unit, characteristics of instructions or draw call commands queued for execution on the processing unit, inputs to the power management controller circuitry, information indicative of decisions made by the power management controller circuitry, a type of application executing on the processing unit, hints provided by the application, and signals generated by the PMAC.

12. The method of claim 11.

13. generating a prediction of a subsequent power state following a power state transition of the processing unit based on an input representing a subset of the first set of state information.

12. The method of claim 11.

14. receiving information indicative of weights to be applied to the advice and the prediction; and applying the weights to the advice and the prediction to determine whether to initiate a power state transition of the processing unit.

14. The method of claim 13.

15. A processing unit comprising: a power management controller circuit configured to generate, based on an input representing a current power state of the processing unit and from a plurality of available power states, a prediction of a subsequent power state following a power state transition from the current power state of the processing unit; a power management advisor circuit (PMAC) that generates advice based on a set of state information representative of at least one outcome of at least one previous power state transition of the processing unit, the advice indicating a probability that a performance gain or power savings resulting from a power state transition of the processing unit to the plurality of available power states will outweigh at least one cost resulting from the power state transition; the power management controller circuit selecting the subsequent power state based on the prediction and the advice. Processing unit.

16. a plurality of registers, a first register of the plurality of registers storing a first set of state information representative of a current state of the processing unit, and at least one second register of the plurality of registers storing a second set of at least one state information representative of at least one result of at least one previous power state transition of the processing unit; the PMAC accessing the first set of state information and the second set of state information of the plurality of registers; 16. The processing unit of claim 15.

17. the first set of state information is copied to the at least one second register in response to the processing unit transitioning to the subsequent power state, and a new set of state information corresponding to the subsequent power state is stored in the first register in response to the processing unit transitioning to the subsequent power state.

17. The processing unit of claim 16.

18. the set of state information includes at least one of: a power state of the processing unit, values ​​of performance counters implemented in the processing unit, characteristics of instructions or draw call commands queued for execution in the processing unit, inputs to the power management controller circuit, information indicative of decisions made by the power management controller circuit, types of applications executing on the processing unit, hints provided by the applications, and signals generated by the PMAC.

16. The processing unit of claim 15.

19. the PMAC comprises a neural network that generates a probability that a performance cost or power savings due to a power state transition from a current power state of the processing unit to a plurality of available power states exceeds at least one cost due to the power state transition.

16. The processing unit of claim 15.

20. a state machine indicating the weighting to be applied between the advice provided by the PMAC and the power state transition decisions made by the power management controller circuitry to determine whether to initiate a power state transition of the processing unit; 20. The processing unit of claim 19.

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