Semiconductor memory device

Abstract

To provide a preferably operating semiconductor storage device.SOLUTION: A semiconductor storage device comprises: a first wiring extending in a first direction; a first semiconductor layer connected to the first wiring and extending in a second direction crossing the first direction; a first electrode extending in a third direction crossing the first direction and the second direction and connected to the first semiconductor layer; a second electrode provided between the first electrode and the first wiring, extending in the third direction, and facing the first semiconductor layer; a third electrode provided between the second electrode and the first wiring and extending in the third direction; a second semiconductor layer provided between the third electrode and the first semiconductor layer and facing the third electrode; and a charge storage layer electrically connected to the first wiring via the second semiconductor layer and facing the first semiconductor layer.SELECTED DRAWING: Figure 2

Description

[Technical field]

[0001] The present embodiment relates to a semiconductor memory device. [Background technology]

[0002] 2. Description of the Related Art A semiconductor memory device is known in which a plurality of memory cells are stacked in a direction intersecting a surface of a substrate. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] U.S. Patent No. 10,607,995 Summary of the Invention [Problem to be solved by the invention]

[0004] A semiconductor memory device that operates favorably is provided. [Means for solving the problem]

[0005] A semiconductor memory device according to one embodiment includes a first wiring extending in a first direction, a first semiconductor layer connected to the first wiring and extending in a second direction intersecting the first direction, a first electrode extending in a third direction intersecting the first and second directions and connected to the first semiconductor layer, a second electrode provided between the first electrode and the first wiring, extending in the third direction and facing the first semiconductor layer, a third electrode provided between the second electrode and the first wiring and extending in the third direction, a second semiconductor layer provided between the third electrode and the first semiconductor layer and facing the third electrode, and a charge storage layer electrically connected to the first wiring via the second semiconductor layer and facing the first semiconductor layer.

[0006] A semiconductor memory device according to one embodiment includes a first wiring extending in a first direction, a first semiconductor layer connected to the first wiring and extending in a second direction intersecting the first direction, a first electrode extending in a third direction intersecting the first and second directions and connected to the first semiconductor layer, a second electrode provided between the first electrode and the first wiring, extending in the third direction and facing the first semiconductor layer, a third electrode aligned with the first electrode in the first direction via the first semiconductor layer and extending in the third direction, a second semiconductor layer provided between the third electrode and the first semiconductor layer and facing the third electrode, and a charge storage layer electrically connected to the first electrode via the second semiconductor layer and facing the first semiconductor layer.

[0007] A semiconductor memory device according to one embodiment includes a bit line, a source line, a first transistor and a second transistor connected in series between the bit line and the source line, a first wiring connected to a gate electrode of the second transistor, a third transistor connected between the first wiring and the bit line, a capacitor connected to the first wiring, a first signal line connected to a gate electrode of the first transistor, a second signal line connected to the capacitor, and a third signal line connected to a gate electrode of the third transistor. The semiconductor memory device also supplies a first voltage to the bit line, a second voltage to the first signal line, a third voltage to the second signal line, and a fourth voltage to the third signal line at a first timing. The semiconductor memory device also supplies a fifth voltage different from the first voltage to the source line, a sixth voltage higher than the second voltage to the first signal line, and a seventh voltage higher than the third voltage to the second signal line at a second timing. Moreover, the semiconductor memory device supplies a fourth voltage to the third signal line, and at a third timing, supplies a second voltage to the first signal line, supplies a third voltage to the second signal line, and supplies an eighth voltage higher than the fourth voltage to the third signal line. [Brief description of the drawings]

[0008] [Figure 1] 1 is a schematic perspective view showing a configuration of a portion of a semiconductor memory device according to a first embodiment. [Diagram 2]1 is a schematic plan view showing a configuration of a portion of a semiconductor memory device according to an embodiment of the present invention. [Diagram 3] 1 is a schematic circuit diagram showing a configuration of a portion of a semiconductor memory device according to an embodiment of the present invention. [Figure 4] 5A to 5C are schematic cross-sectional views for illustrating a method for manufacturing the semiconductor memory device according to the first embodiment. [Diagram 5] 5A to 5C are schematic cross-sectional views for explaining the same manufacturing method. [Figure 6] 5A to 5C are schematic cross-sectional views for explaining the same manufacturing method. [Figure 7] 5A to 5C are schematic cross-sectional views for explaining the same manufacturing method. [Figure 8] 5A to 5C are schematic cross-sectional views for explaining the same manufacturing method. [Figure 9] 5A to 5C are schematic cross-sectional views for explaining the same manufacturing method. [Figure 10] 5A to 5C are schematic cross-sectional views for explaining the same manufacturing method. [Figure 11] 5A to 5C are schematic cross-sectional views for explaining the same manufacturing method. [Figure 12] 5A to 5C are schematic cross-sectional views for explaining the same manufacturing method. [Figure 13] 5A to 5C are schematic cross-sectional views for explaining the same manufacturing method. [Figure 14] 5A to 5C are schematic cross-sectional views for explaining the same manufacturing method. [Figure 15] 5A to 5C are schematic cross-sectional views for explaining the same manufacturing method. [Figure 16] 5A to 5C are schematic cross-sectional views for explaining the same manufacturing method. [Figure 17] 5A to 5C are schematic cross-sectional views for explaining the same manufacturing method. [Figure 18] 5A to 5C are schematic cross-sectional views for explaining the same manufacturing method. [Figure 19] 5A to 5C are schematic cross-sectional views for explaining the same manufacturing method. [Figure 20]5A to 5C are schematic cross-sectional views for explaining the same manufacturing method. [Figure 21] 5A to 5C are schematic cross-sectional views for explaining the same manufacturing method. [Figure 22] 5A to 5C are schematic cross-sectional views for explaining the same manufacturing method. [Figure 23] 5A to 5C are schematic cross-sectional views for explaining the same manufacturing method. [Figure 24] 5A to 5C are schematic cross-sectional views for explaining the same manufacturing method. [Diagram 25] 5A to 5C are schematic cross-sectional views for explaining the same manufacturing method. [Figure 26] 5A to 5C are schematic cross-sectional views for explaining the same manufacturing method. [Figure 27] 5A to 5C are schematic cross-sectional views for explaining the same manufacturing method. [Figure 28] 5A to 5C are schematic cross-sectional views for explaining the same manufacturing method. [Figure 29] 5A to 5C are schematic cross-sectional views for explaining the same manufacturing method. [Diagram 30] 5A to 5C are schematic cross-sectional views for explaining the same manufacturing method. [Diagram 31] 5A to 5C are schematic cross-sectional views for explaining the same manufacturing method. [Diagram 32] 5A to 5C are schematic cross-sectional views for explaining the same manufacturing method. [Diagram 33] 5A to 5C are schematic cross-sectional views for explaining the same manufacturing method. [Diagram 34] 5A to 5C are schematic cross-sectional views for explaining the same manufacturing method. [Diagram 35] 5A to 5C are schematic cross-sectional views for explaining the same manufacturing method. [Diagram 36] 5A to 5C are schematic cross-sectional views for explaining the same manufacturing method. [Figure 37] 5A to 5C are schematic cross-sectional views for explaining the same manufacturing method. [Figure 38] 5A to 5C are schematic cross-sectional views for explaining the same manufacturing method. [Figure 39] 5A to 5C are schematic cross-sectional views for explaining the same manufacturing method. [Diagram 40] 5A to 5C are schematic cross-sectional views for explaining the same manufacturing method. [Diagram 41] 4 is a schematic circuit diagram for explaining a read operation of the semiconductor memory device according to the first embodiment. FIG. [Diagram 42] 4 is a schematic circuit diagram for explaining a write operation of the semiconductor memory device according to the first embodiment. FIG. [Diagram 43] 5A to 5C are schematic waveform diagrams for explaining the data inversion operation of the semiconductor memory device according to the first embodiment. [Diagram 44] FIG. 13 is a schematic circuit diagram for explaining the data inversion operation. [Diagram 45] FIG. 13 is a schematic circuit diagram for explaining the data inversion operation. [Diagram 46] FIG. 13 is a schematic circuit diagram for explaining the data inversion operation. [Figure 47] 5 is a schematic waveform diagram for explaining the self-refresh operation of the semiconductor memory device according to the first embodiment. FIG. [Figure 48] FIG. 11 is a schematic circuit diagram for explaining the self-refresh operation. [Figure 49] FIG. 11 is a schematic circuit diagram for explaining the self-refresh operation. [Figure 50] FIG. 11 is a schematic circuit diagram for explaining the self-refresh operation. [Figure 51] FIG. 11 is a schematic plan view showing a configuration of a portion of a semiconductor memory device according to a second embodiment. [Figure 52] FIG. 2 is a schematic circuit diagram showing a configuration of a portion of the semiconductor memory device. [Figure 53] FIG. 11 is a schematic circuit diagram for explaining a read operation of the semiconductor memory device according to the second embodiment. [Figure 54] FIG. 11 is a schematic circuit diagram for explaining a write operation of the semiconductor memory device according to the second embodiment. [Figure 55] FIG. 11 is a schematic plan view showing a configuration of a portion of a semiconductor memory device according to a third embodiment. [Figure 56] FIG. 2 is a schematic circuit diagram showing a configuration of a portion of the semiconductor memory device. [Figure 57] FIG. 11 is a schematic circuit diagram for explaining a read operation of the semiconductor memory device according to the third embodiment. [Figure 58] FIG. 13 is a schematic plan view showing a configuration of a portion of a semiconductor memory device according to a fourth embodiment. [Figure 59] FIG. 2 is a schematic circuit diagram showing a configuration of a portion of the semiconductor memory device. [Figure 60] FIG. 13 is a schematic plan view showing a configuration of a portion of a semiconductor memory device according to a fifth embodiment. [Figure 61] FIG. 13 is a schematic plan view for explaining a read operation of the semiconductor memory device according to the fifth embodiment. [Figure 62] FIG. 11 is a schematic energy band diagram for explaining the read operation. [Figure 63] FIG. 11 is a schematic energy band diagram for explaining the read operation. [Figure 64] FIG. 13 is a schematic plan view for explaining a write operation of the semiconductor memory device according to the fifth embodiment. [Figure 65] FIG. 13 is a schematic plan view showing a configuration of a portion of a semiconductor memory device according to a sixth embodiment. [Figure 66] FIG. 2 is a schematic circuit diagram showing a configuration of a portion of the semiconductor memory device. [Figure 67] FIG. 13 is a schematic circuit diagram for explaining a read operation of the semiconductor memory device according to the sixth embodiment. [Figure 68] FIG. 13 is a schematic circuit diagram for explaining a write operation of the semiconductor memory device according to the sixth embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0009] Next, a semiconductor memory device according to an embodiment will be described in detail with reference to the drawings. Note that the following embodiment is merely an example, and is not intended to limit the present invention. Also, the following drawings are schematic, and for the sake of explanation, some configurations may be omitted. Also, parts common to multiple embodiments may be given the same reference numerals, and explanations may be omitted.

[0010] In addition, in this specification, the term "semiconductor memory device" may refer to a memory die, or may refer to a memory system including a controller die, such as a memory chip, a memory card, or an SSD (Solid State Drive). Furthermore, it may refer to a configuration including a host computer, such as a smartphone, a tablet terminal, or a personal computer.

[0011] In addition, in this specification, when it is said that a first configuration is "electrically connected" to a second configuration, the first configuration may be directly connected to the second configuration, or the first configuration may be connected to the second configuration via wiring, a semiconductor member, a transistor, etc. For example, when three transistors are connected in series, the first transistor is "electrically connected" to the third transistor even if the second transistor is in an OFF state.

[0012] Furthermore, in this specification, when it is said that a first configuration is "connected between" a second configuration and a third configuration, it may mean that the first configuration, the second configuration, and the third configuration are connected in series, and that the second configuration is connected to the third configuration via the first configuration.

[0013] In addition, in this specification, when it is said that a circuit or the like "conducts" two wirings or the like, it may mean, for example, that the circuit or the like includes a transistor or the like, that the transistor or the like is provided in a current path between the two wirings, and that the transistor or the like is in an ON state.

[0014] In this specification, a predetermined direction parallel to the upper surface of the substrate is called the X direction, a direction parallel to the upper surface of the substrate and perpendicular to the X direction is called the Y direction, and a direction perpendicular to the upper surface of the substrate is called the Z direction.

[0015] In this specification, a direction along a predetermined plane may be referred to as a first direction, a direction along this predetermined plane that intersects with the first direction may be referred to as a second direction, and a direction that intersects with this predetermined plane may be referred to as a third direction. These first, second, and third directions may or may not correspond to any of the X, Y, and Z directions.

[0016] In this specification, expressions such as "upper" and "lower" are based on the substrate. For example, the direction away from the substrate along the Z direction is called "up," and the direction toward the substrate along the Z direction is called "down." Furthermore, when referring to a certain configuration, the lower surface or lower end refers to the surface or end of the configuration facing the substrate, and when referring to the upper surface or upper end, refers to the surface or end of the configuration facing away from the substrate. Furthermore, surfaces that intersect with the X or Y direction are called side surfaces, etc.

[0017] [First embodiment] [composition] Fig. 1 is a schematic perspective view showing a configuration of a portion of the semiconductor memory device according to the first embodiment. Fig. 2 is a schematic plan view showing a configuration of a portion of the semiconductor memory device according to the present embodiment. Fig. 3 is a schematic circuit diagram showing a configuration of a portion of the semiconductor memory device according to the present embodiment.

[0018] 1, the semiconductor memory device according to this embodiment includes a semiconductor substrate Sub. The semiconductor substrate Sub is a semiconductor substrate such as silicon (Si) containing a P-type impurity such as boron (B). The semiconductor memory device according to this embodiment also includes a plurality of memory layers ML arranged in the Z direction. An insulating layer 101 such as silicon oxide (SiO2) is provided between two memory layers ML adjacent to each other in the Z direction.

[0019] As shown in FIG. 2, the memory layer ML includes a plurality of memory cell regions R arranged in the X direction. MCand these multiple memory cell regions R MC and a conductive layer 110 extending in the X direction along the line 110. In addition, two memory cell regions R MC An insulating layer 102 such as silicon nitride (Si3N4) is provided between them.

[0020] Memory cell region R MC In the memory layer ML, the memory layer ML includes two semiconductor layers 120 spaced apart in the X direction. The memory layer ML also includes an insulating layer 121 provided on a side surface of the semiconductor layer 120 in the X direction, and a semiconductor layer 122 provided on a side surface of the insulating layer 121 in the X direction. Four electrodes 130, 140, 150, and 160 arranged in the Y direction are provided between the two semiconductor layers 120. The electrode 140 is closer to the conductive layer 110 than the electrode 130. The electrode 150 is closer to the conductive layer 110 than the electrode 140. The electrode 160 is closer to the conductive layer 110 than the electrode 150. These four electrodes 130, 140, 150, and 160 extend in the Z direction through a plurality of memory layers ML, as shown in FIG. 1, for example. The three electrodes 140, 150, and 160 are provided on their outer peripheral surfaces with insulating layers 141, 151, and 161, respectively. Between the four electrodes 130, 140, 150, and 160, an insulating layer 103 such as silicon oxide (SiO2) is provided.

[0021] Memory cell region R MC The components in the figure constitute a memory cell MC as shown in FIG. 3. The memory cell MC includes transistors Tr1 and Tr2 connected in series between a bit line BL and a source line SL. The transistors Tr1 and Tr2 are N-channel type field effect transistors. The gate electrode of the transistor Tr1 is connected to a select gate line SG. The gate electrode of the transistor Tr2 is connected to a control gate line CG via a node N1 and a capacitor Cap. The memory cell MC also includes a transistor Tr3 connected between the node N1 and the bit line BL. The transistor Tr3 is an N-channel type field effect transistor. The gate electrode of the transistor Tr3 is connected to a transfer gate line TG.

[0022] The conductive layer 110 functions as a bit line BL. The conductive layer 110 may include a conductive layer such as titanium nitride (TiN).

[0023] The semiconductor layer 120 functions as a channel region of the transistors Tr1 and Tr2. The semiconductor layer 120 includes a semiconductor layer made of, for example, polycrystalline silicon (Si). The semiconductor layer 120 extends in the Y direction, and one end of the semiconductor layer 120 in the Y direction is connected to the conductive layer 110. A part of one side surface of the semiconductor layer 120 in the X direction is connected to the electrode 130, and the other portion is covered with the insulating layer 121.

[0024] An impurity region 123 is provided at a connection portion of the semiconductor layer 120 with the conductive layer 110. An impurity region 124 is provided at a connection portion of the semiconductor layer 120 with the electrode 130. The impurity regions 123 and 124 contain, for example, an N-type impurity such as phosphorus (P).

[0025] The insulating layer 121 functions as a gate insulating layer for the transistors Tr1 and Tr2. The insulating layer 121 includes, for example, an insulating layer such as silicon oxide (SiO2). A part of one side surface of the insulating layer 121 in the X direction is connected to the insulating layer 141, and the other part is covered with the semiconductor layer 122.

[0026] The semiconductor layer 122 functions as a gate electrode of the transistor Tr2, a node N1, and one electrode of the capacitor Cap. The semiconductor layer 122 also functions as a charge storage layer capable of storing charges. The semiconductor layer 122 may include a semiconductor layer such as polycrystalline silicon (Si) containing an N-type impurity such as phosphorus (P) or a P-type impurity such as boron (B), or may include a metal such as tungsten (W). The semiconductor layer 122 extends in the Y direction. One end of the semiconductor layer 122 in the Y direction is electrically connected to the conductive layer 110 via the semiconductor layer 125 and the impurity region 126. A part of a side surface on one side in the X direction of the semiconductor layer 122 is connected to the insulating layer 151, and the other part is covered by the insulating layer 103.

[0027] The semiconductor layer 125 functions as a channel region of the transistor Tr3. The semiconductor layer 125 faces the electrode 160.

[0028] The semiconductor layer 125 may include, for example, a metal oxide (oxide semiconductor) that functions as a semiconductor. The semiconductor layer 125 may include, for example, indium gallium zinc oxide (InGaZnO), indium oxide (InO), indium zinc oxide (InZnO), zinc oxide (ZnO), indium gallium silicon oxide (InGaSiO), indium aluminum zinc oxide (InAlZnO), indium tungsten oxide (InWO), indium tin oxide (InSnO), tin oxide (SnO), copper oxide (CuO), titanium oxide (TiO), or tungsten oxide (WO). The semiconductor layer 125 may also include a laminated film of these.

[0029] The impurity region 126 includes a semiconductor layer such as polycrystalline silicon (Si) that includes an N-type impurity such as phosphorus (P).

[0030] The electrode 130 functions as a source line SL. The electrode 130 includes, for example, a conductive layer 131 made of titanium nitride (TiN) or the like, and a conductive layer 132 made of tungsten (W) or the like.

[0031] The electrode 140 functions as a gate electrode of the transistor Tr1 and a selection gate line SG. The electrode 140 includes, for example, a conductive layer such as titanium nitride (TiN) and a conductive layer such as tungsten (W). The electrode 140 faces the semiconductor layer 120 with the insulating layers 121 and 141 interposed therebetween.

[0032] The insulating layer 141 functions as, for example, a gate insulating layer of the transistor Tr1. The insulating layer 141 includes, for example, an insulating layer such as silicon oxide (SiO2).

[0033] The electrode 150 functions as the other electrode of the capacitor Cap and as a control gate line CG. The electrode 150 includes, for example, a conductive layer such as titanium nitride (TiN) and a conductive layer such as tungsten (W). The electrode 150 faces the semiconductor layer 122 via an insulating layer 151.

[0034] The insulating layer 151 functions, for example, as an insulating layer between the electrodes of the capacitor Cap. The insulating layer 151 includes, for example, an insulating layer such as silicon oxide (SiO2).

[0035] The electrode 160 functions as a gate electrode of the transistor Tr3 and a transfer gate line TG. The electrode 160 includes, for example, a conductive layer made of titanium nitride (TiN) or the like and a conductive layer made of tungsten (W) or the like. The electrode 160 faces the semiconductor layer 125 with an insulating layer 161 interposed therebetween.

[0036] The insulating layer 161 functions as, for example, a gate insulating layer of the transistor Tr3. The insulating layer 161 includes, for example, an insulating layer such as silicon oxide (SiO2).

[0037] [Manufacturing method] 4 to 40 are schematic cross-sectional views for explaining the manufacturing method of the semiconductor memory device according to the first embodiment. FIG. 5, FIG. 7, FIG. 9, FIG. 11, FIG. 13, FIG. 15, FIG. 17, FIG. 19, FIG. 21, FIG. 23, FIG. 25, FIG. 27, FIG. 29, FIG. 31, FIG. 33, FIG. 35, FIG. 37, and FIG. 39 show XY cross sections corresponding to FIG. 2. FIG. 4, FIG. 6, FIG. 8, FIG. 10, FIG. 12, FIG. 14, FIG. 16, FIG. 20, FIG. 22, and FIG. 24 show XZ cross sections at positions corresponding to the electrode 130. FIG. 18 shows YZ cross sections at positions corresponding to the insulating layer 102. FIG. 26, FIG. 28, and FIG. 30 show XZ cross sections at positions corresponding to the electrode 140. FIG. 32 and FIG. 34 show XZ cross sections at positions corresponding to the electrode 150. 36, 38, and 40 show XZ cross sections at a position corresponding to the electrode 160. FIG.

[0038] In this manufacturing method, for example, as shown in Fig. 4, a plurality of insulating layers 101 and a plurality of insulating layers 102 are alternately formed. This process is performed by, for example, CVD (Chemical Vapor Deposition) or the like.

[0039] Next, an opening 103A is formed, for example, as shown in Figures 5 and 6. The opening 103A extends in the Y direction and is aligned in the X direction as shown in Figure 5. The opening 103A also extends in the Z direction as shown in Figure 6, penetrating the multiple insulating layers 101 and the multiple insulating layers 102 aligned in the Z direction. This process is performed, for example, by RIE (Reactive Ion Etching) or the like.

[0040] 7 and 8, a part of the insulating layer 102 is removed to expose a part of the upper surface and the lower surface of the insulating layer 101. This step is performed by, for example, wet etching or the like.

[0041] 9 and 10, the semiconductor layer 120, the insulating layer 121, and the semiconductor layer 122 are formed. This process is performed by, for example, CVD, wet etching, oxidation treatment, or the like.

[0042] 11 and 12, an insulating layer 103 is formed inside the opening 103A. This process is performed by, for example, CVD or the like.

[0043] 13 and 14, for example, an opening 130A is formed at a position corresponding to the electrode 130. An opening 140A is formed at a position corresponding to the electrode 140. An opening 150A is formed at a position corresponding to the electrode 150. An opening 160A is formed at a position corresponding to the electrode 160. These openings 130A, 140A, 150A, and 160A extend in the Z direction as shown in FIG. 14, and expose the X-direction side surfaces of the multiple insulating layers 101 and semiconductor layers 122 aligned in the Z direction. This process is performed by, for example, RIE or the like.

[0044] 15 and 16, sacrificial layers 130B, 140B, 150B, and 160B are formed inside the openings 130A, 140A, 150A, and 160A. This process is performed by, for example, CVD or the like.

[0045] 17 and 18, a sacrificial layer 110B is formed at a position corresponding to the conductive layer 110. In this process, for example, an opening extending in the X direction is formed. Furthermore, a part of the insulating layer 102 is removed by a method such as wet etching. Furthermore, a sacrificial layer 110B is formed by a method such as CVD.

[0046] 19 and 20, the sacrificial layer 130B is removed. This step is performed by, for example, wet etching.

[0047] 21 and 22, for example, the semiconductor layer 122 and the insulating layer 121 are partially removed to expose parts of the upper and lower surfaces of the insulating layer 101 and the side surfaces in the X direction of the semiconductor layer 120. This step is performed by, for example, wet etching or the like.

[0048] 23 and 24, the impurity region 124 and the electrode 130 are formed. This process is performed by, for example, CVD or the like.

[0049] Next, the sacrificial layer 140B is removed, for example, as shown in Figures 25 and 26. This step is performed by, for example, wet etching or the like.

[0050] 27 and 28, a part of the semiconductor layer 122 is removed to expose a part of the upper and lower surfaces of the insulating layer 101 and the side surfaces in the X direction of the insulating layer 121. This step is performed by, for example, wet etching or the like.

[0051] 29 and 30, an insulating layer 141 and an electrode 140 are formed. This process is performed by, for example, CVD or the like.

[0052] Next, the sacrificial layer 150B is removed, for example, as shown in Figures 31 and 32. This step is performed by, for example, wet etching or the like.

[0053] Next, as shown in Figures 33 and 34, for example, an insulating layer 151 and an electrode 150 are formed. This process is performed by, for example, CVD or the like.

[0054] Next, the sacrificial layer 160B is removed, for example, as shown in Figures 35 and 36. This step is performed by, for example, wet etching or the like.

[0055] 37 and 38, a part of the semiconductor layer 122 is removed to expose a part of the upper and lower surfaces of the insulating layer 101 and the side surfaces in the X direction of the insulating layer 121. This step is performed by, for example, wet etching or the like.

[0056] 39 and 40, the semiconductor layer 125, the insulating layer 161, and the electrode 160 are formed. This process is performed by, for example, ALD (Atomic Layer Deposition), CVD, wet etching, or the like.

[0057] 1 and 2, the conductive layer 110 is formed. In this step, the sacrificial layer 110B is removed by a method such as wet etching. The conductive layer 110 is formed by a method such as CVD.

[0058] [Read operation] Next, a read operation of the semiconductor memory device according to this embodiment will be described with reference to Fig. 41. Fig. 41 is a schematic circuit diagram for explaining the read operation.

[0059] In the semiconductor memory device according to this embodiment, charge is accumulated at node N1 according to the data stored in memory cell MC. For example, when data "1" is stored in memory cell MC, positive charge may be accumulated at node N1. On the other hand, when data "0" is stored in memory cell MC, no charge may be accumulated at node N1, or negative charge may be accumulated.

[0060] In the read operation of the semiconductor memory device according to this embodiment, the ground voltage V SS supplies.

[0061] Also, the transfer gate line TG is connected to the voltage V TG_Off Supply voltage V TG_Off and ground voltage V SS The difference between the voltage V and the threshold voltage V of the transistor Tr3 is smaller than the threshold voltage V of the transistor Tr3. TG_Off For example, the ground voltage V SS The voltage may be approximately the same as that of the transistor Tr3, or may be a negative voltage. This causes the transistor Tr3 to be turned off.

[0062] Also, the control gate line CG is connected to a voltage V CGR As a result, when a positive charge has been accumulated at the node N1, the transistor Tr2 is turned on. On the other hand, when no charge has been accumulated at the node N1, the transistor Tr2 is turned off.

[0063] In addition, a voltage V SG_On Supply voltage V SG_On and ground voltage V SS The difference between these is greater than the threshold voltage of the transistor Tr1. As a result, the transistor Tr1 in the selected memory cell MC is turned on.

[0064] In addition, the voltage V SG_Off Supply voltage V SG_Off and ground voltage V SS The difference between the voltage V and the threshold voltage V is smaller than the threshold voltage of the transistor Tr1.SG_Off For example, the ground voltage V SS The voltage may be approximately the same as that of the non-selected memory cell MC, or may be a negative voltage. This causes the transistor Tr1 in the non-selected memory cell MC to be turned off.

[0065] Also, the source line SL is supplied with a voltage V DD supplies.

[0066] Here, if a positive charge is stored in node N1, transistor Tr2 is turned on, and a current flows through bit line BL. On the other hand, if no charge is stored in node N1, transistor Tr2 is turned off, and no current flows through bit line BL. Therefore, by detecting the current or voltage of bit line BL, the data stored in the selected memory cell MC can be detected.

[0067] [Write operation] Next, a write operation of the semiconductor memory device according to this embodiment will be described with reference to Fig. 42. Fig. 42 is a schematic circuit diagram for explaining the write operation.

[0068] In the write operation of the semiconductor memory device according to this embodiment, when data “1” is to be recorded in the memory cell MC, a voltage V BLH On the other hand, when data “0” is to be stored in the memory cell MC, a voltage V BLL Supply voltage V BLL For example, the voltage V BLH Less than.

[0069] In addition, a voltage V TG_On Supply voltage V TG_On and voltage V BLH ,V BLL The difference between these is greater than the threshold voltage of the transistor Tr3. As a result, the transistor Tr3 in the selected memory cell MC is turned on.

[0070] In addition, the voltage V TG_Off supplies.

[0071] Also, the control gate line CG is connected to a voltage V CGW Supply voltage V CGW For example, the voltage V CGR A voltage smaller than V CGW For example, the voltage V BLL It may be a voltage of about the same magnitude as the voltage V BLL Larger than voltage V BLH A smaller voltage may also be used.

[0072] Here, the bit line BL is applied with a voltage V BLH When a voltage V is applied to the bit line BL, a charge is stored in the capacitor Cap. BLL is supplied, no charge is stored in the capacitor Cap, or a charge of the opposite polarity is stored in the capacitor Cap.

[0073] Also, the select gate line SG is connected to a voltage V SG_Off is supplied, turning the transistor Tr1 to the OFF state.

[0074] [Data inversion operation] Next, the data inversion operation of the semiconductor memory device according to this embodiment will be described with reference to Fig. 43 to Fig. 46. Fig. 43 is a schematic waveform diagram for explaining the data inversion operation. Fig. 44 to Fig. 46 are schematic circuit diagrams for explaining the data inversion operation.

[0075] 44 to 46 show the configuration of the memory cell MC, as well as a node N2 and a transistor Tr4. The node N2 is connected to the bit line BL and a capacitor Cap BL A signal line PC is connected to the gate electrode of the transistor Tr4.

[0076] In the semiconductor memory device according to this embodiment, it is possible to invert the data recorded in the memory cell MC without using a sense amplifier circuit, a latch circuit, etc. That is, it is possible to record data "0" in the memory cell MC in which data "1" is recorded, and to record data "1" in the memory cell MC in which data "0" is recorded.

[0077] At timing t101 (FIG. 43) of the data inversion operation, as shown in FIG. 44, a voltage V BLH Also, the signal line PC is supplied with a voltage V DD Supply voltage V DD and voltage V BLH The difference between the voltage V and the threshold voltage V is greater than the threshold voltage of the transistor Tr4. Therefore, the transistor Tr4 is turned on, and the voltage of the bit line BL is V BLH Also, the transfer gate line TG is charged to the voltage V TG_Off The control gate line CG is supplied with a voltage V CGW In addition, the selection gate line SG is supplied with a voltage V SG_Off is supplied, turning the transistor Tr1 to the OFF state.

[0078] At timing t102 (FIG. 43) of the data inversion operation, as shown in FIG. 45, the source line SL is supplied with a voltage V BLL Also, the select gate line SG is supplied with a voltage V SG_On Supply voltage V SG_On and voltage V BLL The difference between the voltage V and the threshold voltage V is greater than the threshold voltage of the transistor Tr1. Therefore, the transistor Tr1 is turned on. Also, the control gate line CG is supplied with a voltage V CGR Here, if a positive charge is stored in the node N1, the transistor Tr2 is turned on. On the other hand, if no charge is stored in the node N1, the transistor Tr2 is turned off. Also, a voltage V TG_Off The transistor Tr3 is turned off. Also, the signal line PC is connected to the ground voltage V SSis supplied to turn off the transistor Tr4.

[0079] In this state, if a positive charge is stored in the node N1, the transistor Tr2 is turned on, and the voltage V BLL On the other hand, if no charge is stored in the node N1, the transistor Tr2 is turned off, and the voltage of the bit line BL is the voltage V BLH is maintained.

[0080] At timing t103 (Figure 43) of the data inversion operation, the voltage V SG_Off The transistor Tr1 is turned off. Also, the control gate line CG is supplied with a voltage V CGW In addition, the voltage V TG_Off The transistor Tr3 is turned off. Also, the signal line PC is connected to the ground voltage V SS is supplied to turn off the transistor Tr4.

[0081] At timing t104 (FIG. 43) of the data inversion operation, as shown in FIG. 46, the select gate line SG is applied with a voltage V SG_Off The transistor Tr1 is turned off. Also, the control gate line CG is supplied with a voltage V CGW In addition, the voltage V TG_On The transistor Tr3 is turned on. Also, the signal line PC is connected to the ground voltage V SS is supplied to turn off the transistor Tr4.

[0082] Here, if a positive charge is stored in node N1 at the time when the data inversion operation starts, the voltage of bit line BL becomes equal to voltage V BLL Therefore, the positive charge in the node N1 is discharged to the bit line BL. On the other hand, if no charge is stored in the node N1 at the time when the data inversion operation starts, the voltage of the bit line BL becomes the voltage V BLHTherefore, a positive charge is stored in the node N1.

[0083] [Self-refresh operation] Next, the self-refresh operation of the semiconductor memory device according to this embodiment will be described with reference to Figures 47 to 50. Figure 47 is a schematic waveform diagram for explaining the self-refresh operation. Figures 48 to 50 are schematic circuit diagrams for explaining the self-refresh operation. In addition to the configuration in memory cell MC, Figures 48 to 50 also show node N2 and transistor Tr4.

[0084] The operation at timing t111 (FIG. 47) of the self-refresh operation is basically the same as the operation at timing t101 of the data inversion operation. However, at timing t111, as shown in FIG. 48, the voltage V BLH Instead, the voltage V BLL supplies.

[0085] The operation at timing t112 (FIG. 47) of the self-refresh operation is basically the same as the operation at timing t102 of the data inversion operation. However, at timing t112, as shown in FIG. 49, the source line SL is supplied with a voltage V BLL Instead, the voltage V BLH supplies.

[0086] In this state, if a positive charge is stored in the node N1, the transistor Tr2 is turned on, and the voltage V BLH On the other hand, if no charge is stored in the node N1, the transistor Tr2 is turned off, and the voltage of the bit line BL is the voltage V BLL is maintained.

[0087] The operation at timing t113 (FIG. 47) of the self-refresh operation is similar to the operation at timing t103 of the data inversion operation.

[0088] The operation at timing t114 (FIG. 47) of the self-refresh operation is similar to the operation at timing t104 of the data inversion operation, as shown in FIG.

[0089] If a positive charge is stored in node N1 at the start of the self-refresh operation, the voltage of bit line BL will be V BLH Therefore, a positive charge is stored in the node N1. On the other hand, if no charge is stored in the node N1 at the start of the self-refresh operation, the voltage of the bit line BL becomes equal to the voltage V BLL Therefore, the positive charge in node N1 is discharged to bit line BL, and node N1 remains in an uncharged state.

[0090] [Second embodiment] [composition] Fig. 51 is a schematic plan view showing a configuration of a portion of the semiconductor memory device according to the second embodiment, and Fig. 52 is a schematic circuit diagram showing a configuration of a portion of the semiconductor memory device according to this embodiment.

[0091] The semiconductor memory device according to the second embodiment is basically configured in the same manner as the semiconductor memory device according to the first embodiment. However, the semiconductor memory device according to the second embodiment includes a memory layer ML2 instead of the memory layer ML.

[0092] As shown in Fig. 51, the memory layer ML2 is basically configured in the same manner as the memory layer ML. However, the memory layer ML2 has a memory cell region R MC Instead of the memory cell region R MC2 The memory cell region R MC2 Basically, the memory cell region R MC However, the memory cell region R MC2 The semiconductor device has an impurity region 226 instead of the impurity region 126. The impurity region 226 is basically configured in the same manner as the impurity region 126. However, the impurity region 126 contains an N-type impurity such as phosphorus (P). On the other hand, the impurity region 226 contains a P-type impurity such as boron (B).

[0093] Memory cell region R MC2 The components in the figure constitute a memory cell MC2 as shown in FIG. 52. Memory cell MC2 is basically configured in the same way as memory cell MC. However, memory cell MC2 has a transistor Tr3' instead of transistor Tr3. Transistor Tr3' is basically configured in the same way as transistor Tr3. However, while transistor Tr3 is an N-channel type field effect transistor, transistor Tr3' is a P-channel type field effect transistor.

[0094] [Read operation] Next, a read operation of the semiconductor memory device according to this embodiment will be described with reference to Fig. 53. Fig. 53 is a schematic circuit diagram for explaining the read operation.

[0095] The read operation of the semiconductor memory device according to this embodiment is basically performed in the same manner as the read operation of the semiconductor memory device according to the first embodiment.

[0096] However, in the read operation of the semiconductor memory device according to this embodiment, a voltage V DD and the source line SL is supplied with the ground voltage V SS supplies.

[0097] In the read operation of the semiconductor memory device according to this embodiment, a voltage V TG_Off2 Supply voltage V TG_Off2 and voltage V DD The difference between these is greater than the threshold voltage of the transistor Tr3', which turns the transistor Tr3' off.

[0098] [Write operation] Next, the write operation of the semiconductor memory device according to this embodiment will be described with reference to Fig. 54. Fig. 54 is a schematic circuit diagram for explaining the write operation.

[0099] The write operation of the semiconductor memory device according to this embodiment is basically performed in the same manner as the write operation of the semiconductor memory device according to the first embodiment.

[0100] However, when data “1” is to be recorded in the memory cell MC during the write operation of the semiconductor memory device according to this embodiment, a voltage V BLH2 On the other hand, when data “0” is to be stored in the memory cell MC, a voltage V BLL2 Supply voltage V BLL2 For example, the voltage V BLH2 Less than.

[0101] In addition, a voltage V TG_On2 Supply voltage V TG_On2 and voltage V BLH2 ,V BLL2 The difference between these is equal to or smaller than the threshold voltage of the transistor Tr3'. This causes the transistor Tr3' to be turned on.

[0102] Also, the control gate line CG is connected to a voltage V CGW2 Supply voltage V CGW2 For example, the voltage V CGR Larger than the voltage V DD A voltage smaller than the voltage V CGW2 For example, the voltage V BLL2 It may be a voltage of about the same magnitude as the voltage V BLL2 Larger than voltage V BLH2 A smaller voltage may also be used.

[0103] [Third embodiment] [composition] Fig. 55 is a schematic plan view showing a configuration of a portion of the semiconductor memory device according to the third embodiment, and Fig. 56 is a schematic circuit diagram showing a configuration of a portion of the semiconductor memory device according to this embodiment.

[0104] The semiconductor memory device according to the third embodiment is basically configured similarly to the semiconductor memory device according to the second embodiment, except that the semiconductor memory device according to the third embodiment includes a memory layer ML3 instead of the memory layer ML2.

[0105] As shown in Fig. 55, the memory layer ML3 is basically configured in the same manner as the memory layer ML2. However, the memory layer ML3 has a memory cell region R MC2 Instead of the memory cell region R MC3 The memory cell region R MC3 Basically, the memory cell region R MC2 However, the memory cell region R MC3 The semiconductor device includes impurity regions 323 and 324 instead of the impurity regions 123 and 124. The impurity regions 323 and 324 are basically configured in the same manner as the impurity regions 123 and 124. However, the impurity regions 123 and 124 contain N-type impurities such as phosphorus (P). On the other hand, the impurity regions 323 and 324 contain P-type impurities such as boron (B).

[0106] Memory cell region R MC3 The components in the figure constitute a memory cell MC3 as shown in FIG. 56. Memory cell MC3 is basically configured in the same way as memory cell MC2. However, memory cell MC3 has transistors Tr1' and Tr2' instead of transistors Tr1 and Tr2. Transistors Tr1' and Tr2' are basically configured in the same way as transistors Tr1 and Tr2. However, transistors Tr1 and Tr2 are N-channel type field effect transistors, while transistors Tr1' and Tr2' are P-channel type field effect transistors.

[0107] [Read operation] Next, a read operation of the semiconductor memory device according to this embodiment will be described with reference to Fig. 57. Fig. 57 is a schematic circuit diagram for explaining the read operation.

[0108] The read operation of the semiconductor memory device according to this embodiment is basically performed in the same manner as the read operation of the semiconductor memory device according to the second embodiment.

[0109] However, in the read operation of the semiconductor memory device according to this embodiment, a voltage V CGR3 As a result, when a positive charge has been accumulated at the node N1, the transistor Tr2' is turned off. On the other hand, when no charge has been accumulated at the node N1, the transistor Tr2' is turned on.

[0110] In addition, in the read operation of the semiconductor memory device according to this embodiment, a voltage V SG_On3 Supply voltage V SG_On3 and voltage V DD The difference between the voltage V and the threshold voltage V of the transistor Tr1' is equal to or less than the threshold voltage V of the transistor Tr1'. SG_On3 For example, the voltage Vcc may be a negative voltage, which turns on the transistor Tr1' in the selected memory cell MC3.

[0111] In the read operation of the semiconductor memory device according to this embodiment, the other select gate lines SG are supplied with a voltage V SG_Off3 Supply voltage V SG_Off3 and voltage V DD The difference between the voltage V and the threshold voltage V of the transistor Tr1' is greater than the threshold voltage V of the transistor Tr1'. SG_Off3 For example, the ground voltage V SS This causes the transistor Tr1' in the selected memory cell MC3 to be turned off.

[0112] [Write operation] The write operation of the semiconductor memory device according to this embodiment is performed in the same manner as the write operation of the semiconductor memory device according to the second embodiment.

[0113] [Fourth embodiment] [composition] Fig. 58 is a schematic plan view showing a configuration of a portion of the semiconductor memory device according to the fourth embodiment, and Fig. 59 is a schematic circuit diagram showing a configuration of a portion of the semiconductor memory device according to this embodiment.

[0114] The semiconductor memory device according to the fourth embodiment is basically configured in the same manner as the semiconductor memory device according to the first embodiment. However, the semiconductor memory device according to the fourth embodiment includes a memory layer ML4 instead of the memory layer ML.

[0115] As shown in FIG. 58, the memory layer ML4 includes a plurality of memory cell regions R MC4 and these multiple memory cell regions R MC4 and a conductive layer 110 extending in the X direction along the line 110. In addition, two memory cell regions R adjacent to each other in the X direction MC An insulating layer 102 such as silicon nitride (Si3N4) is provided between them.

[0116] Memory cell region R MC4 The structure in the memory cell region R MC However, the structure in the memory cell region R MC4 In this embodiment, the electrode 150 and the insulating layer 151 are not provided.

[0117] Memory cell region R MC4 The components in the figure constitute a memory cell MC4 as shown in Figure 59. The memory cell MC4 is basically configured in the same way as the memory cell MC. However, the memory cell MC4 is not connected to a control gate line CG. In addition, the gate electrode of the transistor Tr2 is connected to a bit line BL via a capacitor Cap and a transistor Tr3.

[0118] [Manufacturing method] The method for manufacturing the semiconductor memory device according to the fourth embodiment is basically the same as the method for manufacturing the semiconductor memory device according to the first embodiment. However, in the method for manufacturing the semiconductor memory device according to the fourth embodiment, the opening 150A is not formed in the steps described with reference to Figures 13 and 14. Furthermore, the steps described with reference to Figures 31 to 34 are not performed.

[0119] [Operation] The read operation, write operation, data inversion operation, and self-refresh operation of the semiconductor memory device according to the fourth embodiment can be performed in the same manner as the semiconductor memory device according to the first embodiment.

[0120] [effect] The semiconductor memory device according to the fourth embodiment does not include the electrodes 150 and the insulating layer 151. Therefore, compared to the semiconductor memory device according to the first embodiment, high integration can be easily achieved.

[0121] [Fifth embodiment] [composition] FIG. 60 is a schematic plan view showing a configuration of a portion of the semiconductor memory device according to the fifth embodiment.

[0122] The semiconductor memory device according to the fifth embodiment is basically configured in the same manner as the semiconductor memory device according to the first embodiment. However, the semiconductor memory device according to the fifth embodiment includes a memory layer ML5 instead of the memory layer ML.

[0123] As shown in FIG. 60, the memory layer ML5 includes a plurality of memory cell regions R MC5 and these multiple memory cell regions R MC5 and a conductive layer 110 extending in the X direction along the line 110. In addition, two memory cell regions R adjacent to each other in the X direction MC An insulating layer 102 such as silicon nitride (Si3N4) is provided between them.

[0124] Memory cell region R MC5 The structure in the memory cell region R MC The structure is similar to that in

[0125] However, the memory cell region R MC5 Between the two semiconductor layers 120, five electrodes 130, 510, 520, 150, 160 are provided aligned in the Y direction. The electrode 510 is closer to the conductive layer 110 than the electrode 130. The electrode 520 is closer to the conductive layer 110 than the electrode 510. The electrode 150 is closer to the conductive layer 110 than the electrode 520. The electrodes 510, 520 extend in the Z direction penetrating the multiple memory layers ML. Insulating layers 511, 521 are provided on the outer circumferential surfaces of the electrodes 510, 520, respectively.

[0126] The electrodes 510 and 520 are configured similarly to the electrode 140 according to the first embodiment. Moreover, the insulating layers 511 and 521 are configured similarly to the insulating layer 141 according to the first embodiment.

[0127] In addition, the memory cell region R MC5 5, an impurity region 501 is provided at a connection portion of the semiconductor layer 120 with the conductive layer 110. The impurity region 501 contains a P-type impurity such as boron (B).

[0128] [Manufacturing method] The method for manufacturing the semiconductor memory device according to the fifth embodiment is basically the same as the method for manufacturing the semiconductor memory device according to the first embodiment. However, in the method for manufacturing the semiconductor memory device according to the fifth embodiment, openings 150A are formed at positions corresponding to electrodes 510, 520 in the process described with reference to FIGS.

[0129] [Read operation] Next, a read operation of the semiconductor memory device according to this embodiment will be described with reference to Figures 61 to 63. Figure 61 is a schematic plan view for explaining the read operation. Figures 62 and 63 are schematic energy band diagrams for explaining the read operation.

[0130] In addition, in Fig. 61, a region of the semiconductor layer 120 facing the electrode 510 is shown as a region 1201. Also, a region of the semiconductor layer 120 facing the electrode 520 is shown as a region 1202. Also, a region of the semiconductor layer 120 facing the semiconductor layer 122 is shown as a region 1203. Also, Figs. 62 and 63 show the potentials of each region in the semiconductor layer 120. Note that Fig. 62 corresponds to the semiconductor layer 120 in an unselected memory cell. Also, Fig. 63 corresponds to the semiconductor layer 120 in a selected memory cell.

[0131] As shown in FIGS. 61 to 63, in the read operation of the semiconductor memory device according to this embodiment, for example, a ground voltage V SS supplies.

[0132] Also, a voltage V R1 For example, in the case of an N-channel field effect transistor in which the electrode 510 is used as a gate electrode and the semiconductor layer 120 is used as a channel region, a voltage V R1 and ground voltage V SS The difference between these is smaller than the threshold voltage of this transistor. Therefore, a potential gradient for electrons is formed between the impurity region 124 of the semiconductor layer 120 and the region 1201, and no electron channel is formed in the region 1201.

[0133] In addition, a voltage V R5 Supply voltage V R5 is the ground voltage V SS Greater than.

[0134] Also, a voltage V R4 For example, in the case of an N-channel field effect transistor in which the electrode 160 is used as a gate electrode and the semiconductor layer 125 is used as a channel region, a voltage V R4 and voltage V R5 The difference between the potential difference and the threshold voltage of the transistor is less than the threshold voltage of the transistor, so that the semiconductor layer 122 is electrically isolated from the conductive layer 110.

[0135] Also, a voltage VR3 For example, a P-channel field effect transistor is considered, in which the electrode 150 is used as a gate electrode and the semiconductor layer 120 is used as a channel region. In this case, for example, when data "0" is stored in the memory cell, the voltage V R3 and voltage V R5 The difference between the voltage V and the threshold voltage V is smaller than the threshold voltage of the transistor. Therefore, in the portion corresponding to the memory cell in which data "0" is stored, a hole channel is formed in the region 1203 of the semiconductor layer 120. On the other hand, if data "1" is stored in the memory cell, for example, the voltage V R3 and voltage V R5 The difference between these is greater than the threshold voltage of this transistor. Therefore, in the portion corresponding to the memory cell in which data "1" is stored, a potential gradient for holes is formed between the impurity region 501 of the semiconductor layer 120 and the region 1203, and no hole channel is formed in the region 1203. Therefore, no current flows through the memory cell in which data "1" is stored.

[0136] In addition, a voltage V R2U For example, in the case of a P-channel field effect transistor in which the electrode 520 is used as a gate electrode and the semiconductor layer 120 is used as a channel region, a voltage V R2U and voltage V R5 The difference between these is greater than the threshold voltage of this transistor. Therefore, in the portion corresponding to the unselected memory cell in which data "0" is stored, a potential gradient for holes is formed between region 1203 and region 1202 of semiconductor layer 120, and no hole channel is formed in region 1202. Therefore, no current flows through the unselected memory cell.

[0137] Also, a voltage V R2S For example, in the case of a P-channel field effect transistor in which the electrode 520 is used as a gate electrode and the semiconductor layer 120 is used as a channel region, a voltage V R2S and voltage V R5The difference between the voltages is smaller than the threshold voltage of this transistor. Therefore, in the portion corresponding to the selected memory cell in which data "0" is recorded, a hole channel is formed in the regions 1203 and 1202 of the semiconductor layer 120. As a result, the holes supplied from the conductive layer 110 reach the region 1201 through the impurity region 501 and the regions 1203 and 1202 and are accumulated. The accumulated holes increase the potential of the region 1201, which causes electrons to flow from the electrode 130 into the region 1203, lowering the potential of the region 1203. In this way, the positive feedback operation in which the holes and electrons lower each other's barriers causes the entire semiconductor layer 120 to ultimately operate as a forward-biased PIN diode. Therefore, a current flows through the selected memory cell in which data "0" is recorded.

[0138] Before the read operation is performed, the electrode 130 is applied with a ground voltage V SS A higher voltage may be supplied, which makes it possible to discharge the charge stored in the semiconductor layer 120 and improve the accuracy of the read operation.

[0139] [Write operation] Next, a write operation of the semiconductor memory device according to this embodiment will be described with reference to Fig. 64. Fig. 64 is a schematic plan view for explaining the write operation.

[0140] As shown in FIG. 64, in the write operation of the semiconductor memory device according to this embodiment, for example, a voltage V W1 For example, in the case of the N-channel field effect transistor having the electrode 510 as the gate electrode, a voltage V W1 is smaller than the threshold voltage of this transistor. Therefore, a potential gradient for electrons is formed between the impurity region 124 of the semiconductor layer 120 and the region 1201, and no electron channel is formed in the region 1201.

[0141] When data “1” is to be recorded in the selected memory cell, a voltage V BLH In addition, when data “0” is to be recorded in the selected memory cell, a voltage VBLL supplies.

[0142] Also, a voltage V W4S For example, in the case of the N-channel field effect transistor having the electrode 160 as the gate electrode, the voltage V W4S and voltage V BLH ,V BLL The difference between the potential difference and the threshold voltage of the transistor is greater than the threshold voltage of the transistor. Therefore, the semiconductor layer 122 is electrically connected to the conductive layer 110.

[0143] In addition, the other electrodes 160 are applied with a voltage V W4U For example, in the case of the N-channel field effect transistor having the electrode 160 as the gate electrode, the voltage V W4U and voltage V BLH ,V BLL The difference between the potential difference and the threshold voltage of the transistor is less than the threshold voltage of the transistor, so that the semiconductor layer 122 is electrically isolated from the conductive layer 110.

[0144] Also, a voltage V W3S Supply voltage V W3S For example, the voltage V BLL It may be a voltage of about the same magnitude as the voltage V BLL Larger than voltage V BLH Accordingly, the conductive layer 110 is applied with a voltage V BLH When a voltage V is applied to the conductive layer 110, a positive charge is stored in a capacitor having the electrode 150 as one electrode and the semiconductor layer 122 as the other electrode. BLL When a positive voltage is applied to the capacitor, the capacitor stores no charge or stores a negative charge.

[0145] In addition, the other electrodes 150 are applied with a voltage V W3U Supply voltage V W3U For example, the voltage V BLL It may be a voltage of about the same magnitude as the voltage V BLH The voltage may be of the same magnitude as

[0146] Also, a voltage V W2 Supply voltage V W2 For example, in the case of the P-channel type field effect transistor having the electrode 520 as the gate electrode, the voltage V W2 and voltage V BLH ,V BLL The difference between these is greater than the threshold voltage of this transistor. Therefore, a potential gradient for holes is formed between the impurity region 124 of the semiconductor layer 120 and the region 1201, and no hole channel is formed in the region 1201.

[0147] [effect] In the semiconductor memory device according to the first embodiment, a part of the semiconductor layer 120 (in the example of FIG. 2, the impurity region 123) faces the semiconductor layer 125 via the insulating layer 121. In such a configuration, when a voltage is supplied to the semiconductor layer 120 in a read operation, an electron channel may be formed in the semiconductor layer 125, causing the charge in the semiconductor layer 122 to be discharged. This may destroy the data recorded in the memory cell MC (FIG. 3).

[0148] In order to suppress such a phenomenon, for example, it is considered to adjust the impurity concentration in the semiconductor layer 122 or to increase the voltage of the electrode 150 during the read operation, thereby increasing the potential of the semiconductor layer 122 during the read operation and increasing the energy barrier between the semiconductor layer 122 and the semiconductor layer 125. However, when the potential of the semiconductor layer 122 during the read operation is increased, an N-channel type field effect transistor (transistor Tr2 in FIG. 3) having the region 1203 of the semiconductor layer 120 as its channel region is easily turned on. In such a case, there is a risk that a leak current will occur in the selected memory cell MC in which data "0" is recorded. In order to suppress such a leak current, for example, it is considered to increase the threshold voltage of this N-channel type field effect transistor (transistor Tr2 in FIG. 3) by injecting a P-type impurity such as boron (B) into the semiconductor layer 120 and increasing the concentration of this impurity relatively. However, in such a case, there is a risk that the current flowing through the selected memory cell in which data "1" is recorded will be reduced, making it difficult to distinguish the data.

[0149] Therefore, in the semiconductor memory device according to the fifth embodiment, as described with reference to FIG. 60, the conductive layer 110 and the semiconductor layer 120 are connected via an impurity region 501 containing a P-type impurity, and the electrode 130 and the semiconductor layer 120 are connected via an impurity region 124 containing an N-type impurity. In addition, two electrodes 510 and 520 are arranged between the electrodes 130 and 150. In such a configuration, during a read operation, a positive feedback operation occurs in which the electron current and the hole current amplify each other in the selected memory cell. This makes it possible to pass a relatively large current through the selected memory cell. In addition, the two electrodes 510 and 520 can suitably adjust the potentials of the regions 1201 and 1202 of the semiconductor layer 120, thereby suitably suppressing the leak current in the unselected memory cells. Therefore, it is possible to realize a semiconductor memory device that can more easily determine the data of the selected memory cell and operate suitably.

[0150] [Sixth embodiment] [composition] Fig. 65 is a schematic plan view showing a configuration of a portion of the semiconductor memory device according to the sixth embodiment, and Fig. 66 is a schematic circuit diagram showing a configuration of a portion of the semiconductor memory device according to this embodiment.

[0151] The semiconductor memory device according to the sixth embodiment is basically configured in the same manner as the semiconductor memory device according to the first embodiment. However, the semiconductor memory device according to the sixth embodiment includes a memory layer ML6 instead of the memory layer ML.

[0152] As shown in FIG. 65, the memory layer ML6 includes a pair of conductive layers 610 extending in the X direction and arranged in the Y direction. O ,610 E The memory layer ML6 also includes a plurality of channel semiconductor regions R arranged alternately in the X direction in the region between the two. CE ,R CO In addition, two channel semiconductor regions R adjacent to each other in the X direction are CE ,R CO Between them, the electrode area R EO or electrode area R EE The electrode area R EO ,R EE are arranged alternately in the X direction.

[0153] Channel semiconductor region R CO In the memory layer ML6, the memory layer ML6 includes a semiconductor layer 620 extending in the Y direction. The memory layer ML6 also includes an insulating layer 621 provided on a side surface in the X direction of the semiconductor layer 620, and a semiconductor layer 622 provided on a side surface in the X direction of the insulating layer 621. An impurity region 623 is provided at one end of the semiconductor layer 620 in the Y direction. The semiconductor layer 620 is connected to the conductive layer 610 via the impurity region 623. O6. An impurity region 624 is provided at the other end of the semiconductor layer 620 in the Y direction. One end of the semiconductor layer 622 in the Y direction is insulated from the semiconductor layer 620 via an insulating layer 621. A semiconductor layer 625 is provided at the other end of the semiconductor layer 620 in the Y direction. A conductive layer 626 is provided at the other ends of the semiconductor layers 620 and 622, connected to these. The semiconductor layer 620 is connected to the conductive layer 626 via the impurity region 624. The semiconductor layer 622 is connected to the conductive layer 626 via the semiconductor layer 625.

[0154] Channel semiconductor region R CE The configuration of the memory layer ML6 in CO The configuration of the memory layer ML6 in the embodiment is the same as that in the embodiment except that the channel semiconductor region R CE The semiconductor layer 620 in the conductive layer 610 O Instead, conductive layer 610 E is connected to

[0155] Electrode area R EO Two electrodes 630, 640 arranged side by side in the Y direction are provided on the semiconductor layer 620. An insulating layer 641 is provided on the outer circumferential surface of the electrode 640. The electrode 630 is connected to an impurity region 624 of the semiconductor layer 620. The electrode 640 faces the semiconductor layer 620 via the insulating layer 641. The electrodes 630, 640 extend in the Z direction, penetrating the multiple memory layers ML6.

[0156] Electrode area R EE An electrode 660 is provided on the semiconductor layer 620. An insulating layer 661 is provided on the outer peripheral surface of the electrode 660. The electrode 660 faces two semiconductor layers 625 aligned in the Y direction via the insulating layer 661. The electrode 660 is aligned in the X direction with the electrode 630, the impurity region 624 of the semiconductor layer 620, and the semiconductor layer 625. The electrode 660 extends in the Z direction penetrating the multiple memory layers ML6.

[0157] Conductive layer 610 O ,610 Eare configured similarly to the conductive layer 110. The semiconductor layer 620 is basically configured similarly to the semiconductor layer 120. However, the impurity regions 623 and 624 of the semiconductor layer 620 may contain N-type impurities such as phosphorus (P) or P-type impurities such as boron (B). The insulating layer 621 is configured similarly to the insulating layer 121. The semiconductor layer 622 is configured similarly to the semiconductor layer 122. The semiconductor layer 625 is configured similarly to the semiconductor layer 125. The electrodes 630, 640, and 660 are configured similarly to the electrodes 130, 140, and 160. Moreover, the insulating layers 641 and 661 are configured similarly to the insulating layers 141 and 161.

[0158] Channel semiconductor region R CE or channel semiconductor region R CO Each of the components in and a pair of adjacent electrode regions R EO ,R EE The components in the figure constitute a memory cell MC6 as shown in FIG. 66. The memory cell MC6 includes transistors Tr1' and Tr2' connected in series between a bit line BL and a source line SL. The gate electrode of the transistor Tr1' is connected to a selection gate line SG. The memory cell MC6 also includes a node N1 connected to the gate electrode of the transistor Tr2', a transistor Tr3' connected between the node N1 and the source line SL, and a capacitor Cap connected between the node N1 and the bit line BL. The gate electrode of the transistor Tr3' is connected to a transfer gate line TG.

[0159] [Read operation] Next, a read operation of the semiconductor memory device according to this embodiment will be described with reference to Fig. 67. Fig. 67 is a schematic circuit diagram for explaining the read operation.

[0160] In the read operation of the semiconductor memory device according to this embodiment, a voltage V DD supplies.

[0161] When positive charges are accumulated at the node N1, the transistor Tr2' is turned off, whereas when no charges are accumulated at the node N1, the transistor Tr2' is turned on.

[0162] Also, a voltage V SG_On6 Supply voltage V SG_On6 and voltage V DD The difference between these is smaller than the threshold voltage of the transistor Tr1'. As a result, the transistor Tr1' in the selected memory cell MC6 is turned on.

[0163] In addition, the voltage V SG_Off6 Supply voltage V SG_Off6 and voltage V DD The difference between these is greater than the threshold voltage of the transistor Tr1'. As a result, the transistor Tr1' in the unselected memory cell MC6 is turned off.

[0164] In addition, the source line SL is connected to the ground voltage V SS supplies.

[0165] Also, the transfer gate line TG is connected to the voltage V TG_Off6 Supply voltage V TG_Off6 and ground voltage V SS The difference between these is greater than the threshold voltage of the transistor Tr3', which turns the transistor Tr3' off.

[0166] [Write operation] Next, a write operation of the semiconductor memory device according to this embodiment will be described with reference to Fig. 68. Fig. 68 is a schematic circuit diagram for explaining the write operation.

[0167] In the write operation of the semiconductor memory device according to this embodiment, when data “1” is to be recorded in the memory cell MC, a voltage V BLL6 On the other hand, when data “0” is to be stored in the memory cell MC, a voltage V BLH6Supply voltage V BLL6 For example, the voltage V BLH6 Less than.

[0168] Also, the select gate line SG is connected to the voltage V SG_Off6 is supplied, turning the transistor Tr1' off.

[0169] In addition, the source line SL is connected to the ground voltage V SS supplies.

[0170] In addition, a voltage V TG_On6 Supply voltage V TG_On6 and ground voltage V SS The difference between these is smaller than the threshold voltage of the transistor Tr3'. As a result, the transistor Tr3' in the selected memory cell MC6 is turned on.

[0171] In addition, the voltage V TG_Off6 is supplied, turning off the transistor Tr3' in the unselected memory cell MC6.

[0172] Now, the bit line BL is applied with a voltage V BLL6 When a voltage V is applied to the bit line BL, a charge is stored in the capacitor Cap between the node N1 and the bit line BL (between the semiconductor layers 620 and 622 in FIG. 65). BLH6 is supplied, no charge is stored in the capacitor Cap, or a charge of the opposite polarity is stored in the capacitor Cap.

[0173] [effect] As described above, in the semiconductor memory device according to the first embodiment (FIG. 2), when a voltage is supplied to the semiconductor layer 120 during a read operation, an electron channel may be formed in the semiconductor layer 125, resulting in the data recorded in the memory cell being destroyed.

[0174] 65, one side surface of the semiconductor layer 625 in the X direction faces the electrode 660, and the other side surface of the semiconductor layer 625 in the X direction faces the impurity region 624 of the semiconductor layer 620. In this configuration, for example, in a read operation, a ground voltage V SS By supplying the voltage Vcc, it is possible to suppress the formation of a channel in the semiconductor layer 125 during a read operation. Therefore, it is possible to realize a semiconductor memory device that operates appropriately.

[0175] [others] The semiconductor memory devices according to the first to sixth embodiments have been described above. However, these configurations are merely examples, and the specific configurations can be adjusted as appropriate.

[0176] For example, the semiconductor memory device according to the third embodiment may include the impurity region 126 similar to that of the first embodiment, instead of the impurity region 226 similar to that of the second embodiment.

[0177] Also, for example, the semiconductor memory device according to the fourth embodiment may include an impurity region 226 similar to that of the second embodiment, instead of the impurity region 126 similar to that of the first embodiment. Also, the semiconductor memory device according to the fourth embodiment may include impurity regions 323, 324 similar to that of the third embodiment, instead of the impurity regions 123, 124 similar to that of the first embodiment.

[0178] [others] Although some embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included in the scope and spirit of the invention, and are included in the scope of the invention and its equivalents described in the claims. [Explanation of symbols]

[0179] 110...conductive layer, 120...semiconductor layer, 121...insulating layer, 122...semiconductor layer, 123, 124...impurity region, 125...semiconductor layer, 126...impurity region, 130, 140, 150, 160...electrodes, 141, 151, 161...insulating layer.

Claims

1. A first wiring extending in a first direction; a first semiconductor layer connected to the first wiring and extending in a second direction intersecting the first direction; a first electrode extending in a third direction intersecting the first direction and the second direction and connected to the first semiconductor layer; a second electrode provided between the first electrode and the first wiring, extending in the third direction, and facing the first semiconductor layer; a third electrode provided between the second electrode and the first wiring and extending in the third direction; a second semiconductor layer provided between the third electrode and the first semiconductor layer and facing the third electrode; a charge storage layer electrically connected to the first wiring via the second semiconductor layer and facing the first semiconductor layer; A semiconductor memory device comprising:

2. a fourth electrode provided between the second electrode and the third electrode, extending in the third direction, and facing the charge storage layer; 2. The semiconductor memory device according to claim 1.

3. the first semiconductor layer is connected to the first wiring and the first electrode via an N-type semiconductor layer; During a read operation, applying a first voltage to the first electrode; applying a second voltage to the second electrode; A third voltage is supplied to the first wiring; the first voltage is different from the third voltage; The second voltage is greater than the smaller of the first voltage and the third voltage.

3. The semiconductor memory device according to claim 1.

4. the first semiconductor layer is connected to the first wiring and the first electrode via a P-type semiconductor layer; During a read operation, applying a first voltage to the first electrode; applying a second voltage to the second electrode; A third voltage is supplied to the first wiring; the first voltage is different from the third voltage; The second voltage is smaller than the greater of the first voltage and the third voltage.

3. The semiconductor memory device according to claim 1.

5. the second semiconductor layer is connected to the first wiring via an N-type semiconductor layer, During a write operation, A fourth voltage is supplied to the first wiring; applying a fifth voltage to the third electrode; The fifth voltage is greater than the fourth voltage.

5. The semiconductor memory device according to claim 1.

6. the second semiconductor layer is connected to the first wiring via a P-type semiconductor layer, During a write operation, A fourth voltage is supplied to the first wiring; applying a fifth voltage to the third electrode; The fifth voltage has a magnitude equal to or less than the fourth voltage.

5. The semiconductor memory device according to claim 1.

7. a fifth electrode provided between the first electrode and the second electrode, extending in the third direction, and facing the first semiconductor layer; 3. The semiconductor memory device according to claim 2.

8. The first semiconductor layer is connected to the first wiring via a P-type semiconductor layer; The first electrode is connected to the N-type semiconductor layer.

8. The semiconductor memory device according to claim 7.

9. During a read operation, applying a first voltage to the first electrode; applying a second voltage to the fourth electrode; applying a third voltage to the fifth electrode; A fourth voltage is supplied to the first wiring; the second voltage is greater than the fourth voltage and the first voltage; The third voltage is less than the fourth voltage and the first voltage.

9. The semiconductor memory device according to claim 7.

10. Prior to the read operation, a fifth voltage greater than the first voltage is applied to the first electrode.

10. The semiconductor memory device according to claim 9.

11. A first wiring extending in a first direction; a first semiconductor layer connected to the first wiring and extending in a second direction intersecting the first direction; a first electrode extending in a third direction intersecting the first direction and the second direction and connected to the first semiconductor layer; a second electrode provided between the first electrode and the first wiring, extending in the third direction, and facing the first semiconductor layer; a third electrode arranged next to the first electrode in the first direction with the first semiconductor layer interposed therebetween and extending in the third direction; a second semiconductor layer provided between the third electrode and the first semiconductor layer and facing the third electrode; a first charge storage layer electrically connected to the first electrode via the second semiconductor layer and facing the first semiconductor layer; A semiconductor memory device comprising:

12. The first semiconductor layer is connected to the first wiring and the first electrode via a P-type semiconductor layer.

12. The semiconductor memory device according to claim 11.

13. A second wiring extending in the first direction and aligned with the first wiring in the second direction; a third semiconductor layer connected to the second wiring and extending in the second direction; a fourth electrode extending in the third direction and connected to the third semiconductor layer; a fifth electrode provided between the fourth electrode and the second wiring, extending in the third direction, and facing the third semiconductor layer; a fourth semiconductor layer provided between the third electrode and the third semiconductor layer and facing the third electrode; a second charge storage layer electrically connected to the fourth electrode via the fourth semiconductor layer and facing the third semiconductor layer; 13. The semiconductor memory device according to claim 11, further comprising:

14. The second semiconductor layer includes an oxide semiconductor.

14. The semiconductor memory device according to claim 1.

15. The second semiconductor layer includes at least one of indium gallium zinc oxide (InGaZnO), indium oxide (InO), indium zinc oxide (InZnO), zinc oxide (ZnO), indium gallium silicon oxide (InGaSiO), indium aluminum zinc oxide (InAlZnO), indium tungsten oxide (InWO), indium tin oxide (InSnO), tin oxide (SnO), copper oxide (CuO), titanium oxide (TiO), and tungsten oxide (WO).

15. The semiconductor memory device according to claim 1.

16. A bit line; A source line; a first transistor and a second transistor connected in series between the bit line and the source line; a first wiring connected to a gate electrode of the second transistor; a third transistor connected between the first wiring and the bit line; a capacitor connected to the first wiring; a fourth transistor connected to the bit line; a voltage supply line connected to the bit line via the fourth transistor; a first signal line connected to a gate electrode of the first transistor; a second signal line connected to the capacitor; a third signal line connected to a gate electrode of the third transistor; a fourth signal line connected to a gate electrode of the fourth transistor; Equipped with At the first timing, Supplying a first voltage to the voltage supply line; supplying a second voltage to the first signal line; supplying a third voltage to the second signal line; supplying a fourth voltage to the third signal line; supplying a fifth voltage to the fourth signal line; At the second timing, supplying a sixth voltage different from the first voltage to the source line; supplying a seventh voltage greater than the second voltage to the first signal line; supplying an eighth voltage greater than the third voltage to the second signal line; supplying the fourth voltage to the third signal line; supplying a ninth voltage smaller than the fifth voltage to the fourth signal line; At the third timing, supplying the second voltage to the first signal line; supplying the third voltage to the second signal line; supplying an eighth voltage greater than the fourth voltage to the third signal line; The ninth voltage is supplied to the fourth signal line. Semiconductor memory device.

17. the sixth voltage is less than the first voltage; The data recorded before the first timing is defined as first data; If the data recorded after the third timing is defined as third data, The third data is the inversion of the first data.

17. The semiconductor memory device according to claim 16.

18. the sixth voltage is greater than the first voltage; The data recorded before the first timing is defined as first data; If the data recorded after the third timing is defined as third data, The third data is identical to the first data.

17. The semiconductor memory device according to claim 16.

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