Thin film transistor and manufacturing method, memory and manufacturing method, and electronic device

Abstract

The embodiments of the present application provide a thin film transistor and manufacturing method, a memory and manufacturing method, and an electronic device, which relate to the field of memory technology, and reduce the size of the thin film transistor, improve the area utilization rate, and reduce the difficulty of routing. The thin film transistor includes a gate, a first electrode, a second electrode, a first dielectric layer, a second dielectric layer, and a semiconductor layer. The gate includes a gate base located at the top and a gate body extending from the gate base to the bottom. The first electrode is located at the bottom. The second electrode is located between the first electrode and the gate base. The first dielectric layer is disposed between the second electrode and the first electrode, and the first dielectric layer is configured to separate the first electrode from the second electrode. The second dielectric layer covers the surface of the gate base and the surface of the gate body. The semiconductor layer is disposed along the side of the gate body, and the second dielectric layer separates the semiconductor layer from the gate. The first electrode and the second electrode are each electrically connected to the semiconductor layer.

Description

[Technical field]

[0002] Technical Field The present application relates to the field of memory technology, in particular to thin film transistors and manufacturing methods, memories and manufacturing methods, and electronic devices. [Background technology]

[0003] 2. Description of the Related Art Thin film transistors (TFTs) have the advantages of low leakage current, low growth temperature, and high mobility, and therefore thin film transistors have been widely used in various devices such as memories.

[0004] The structure of an existing thin film transistor is shown in Figure 1. The thin film transistor 10 includes a semiconductor layer (sometimes referred to as an active layer) 102 disposed on a substrate 101, a source 103 and a drain 104 disposed on and in contact with the semiconductor layer 102, a gate insulating layer 105 disposed on the semiconductor layer 102, and a gate 106 disposed on the gate insulating layer 105.

[0005] The semiconductor layer 102 of the existing thin film transistor 10 extends along a plane parallel to the gate 106, and the source 103 and the drain 104 are located in the same layer, so that the size of the thin film transistor 10 is relatively large and the area utilization rate is low. In addition, since the source electrode 103 and the drain electrode 104 are located in the same layer, a short circuit easily occurs during routing of the signal line electrically connected to the source electrode 103 and the signal line electrically connected to the drain electrode 104, which is not conducive to routing and increases the difficulty of the process. Summary of the Invention [Problem to be solved by the invention]

[0006] SUMMARY OF THE DISCLOSURE The embodiments of the present application provide a thin film transistor and manufacturing method, a memory and manufacturing method, and an electronic device for reducing the size of the thin film transistor, improving the area utilization rate, and reducing the difficulty of routing. [Means for solving the problem]

[0007] To achieve the aforementioned objectives, the present application uses the following technical solutions:

[0008] According to a first aspect, a thin film transistor is provided. The thin film transistor includes a gate, a first electrode, a second electrode, a first dielectric layer, a second dielectric layer, and a semiconductor layer. The gate includes a gate base located at a top and a gate body extending from the gate base to a bottom. The first electrode is located at the bottom. The second electrode is located between the first electrode and the gate base. The first dielectric layer is disposed between the second electrode and the first electrode, and the first dielectric layer is configured to separate the first electrode from the second electrode. The semiconductor layer is disposed along a side of the gate body, and the second dielectric layer separates the semiconductor layer from the gate. The first electrode and the second electrode are each electrically connected to the semiconductor layer.

[0009] Compared with the prior art, the semiconductor layer is arranged along a plane parallel to the gate (the gate in the prior art is equivalent to the gate base in this embodiment of the present application), and the second electrode and the first electrode are arranged in the same layer. In this embodiment of the present application, the semiconductor layer is arranged along the side of the gate body, the first electrode is located at the bottom, the second electrode is located between the first electrode and the gate base, and the first electrode and the second electrode are electrically connected to the semiconductor layer respectively. Therefore, the thin film transistor provided in this embodiment of the present application has a relatively small size on the plane parallel to the gate base. Therefore, in this embodiment of the present application, the size of the thin film transistor is reduced and the area utilization rate is improved. In addition, since the second electrode and the first electrode of the thin film transistor in this embodiment of the present application are located in different layers, it is possible to avoid a short circuit occurring during the routing of the signal line electrically connected to the second electrode and the signal line electrically connected to the first electrode, thereby reducing the difficulty of the process.

[0010] In one possible implementation, the second electrode is disposed near the gate base, which can avoid direct electrical contact between the first electrode and the second electrode when the first electrode and the second electrode are fabricated.

[0011] In one possible implementation, the boundary of the projection of the gate body on the gate base lies within the boundary of the gate base, in which case the gate body is located in a central region of the gate base.

[0012] In one possible implementation, the boundary of the projection of the gate body on the gate base overlaps with the boundary of the gate base, in which case the gate body is disposed in an edge region of the gate base.

[0013] In one possible implementation, the gate body is a hollow structure, and an outer boundary of the projection of the gate body on the gate base overlaps with a boundary of the gate base. Because the gate body is a hollow structure, the second dielectric layer, the semiconductor layer, the second electrode, and the first dielectric layer can be disposed within the hollow structure.

[0014] In one possible implementation, the semiconductor layer further includes an extension extending along the surface of the gate base, thus increasing the area of ​​the semiconductor layer, thereby increasing the electrical connection area between the semiconductor layer and the second electrode, and improving the switching speed of the thin film transistor.

[0015] In one possible implementation, the semiconductor layer further includes an extension portion located between the gate body and the first electrode, thus increasing the area of ​​the semiconductor layer, thereby increasing the electrical connection area between the semiconductor layer and the first electrode, and improving the switching speed of the thin film transistor.

[0016] In one possible implementation, the semiconductor layer is disposed around the entire side of the gate body, thus increasing the area of ​​the semiconductor layer and improving the switching speed of the thin film transistor.

[0017] In one possible implementation, the semiconductor layer surrounds the entire side of the gate body.

[0018] In one possible implementation, the second electrode is disposed on a side of the semiconductor layer remote from the second dielectric layer.

[0019] In one possible implementation, the second electrode is disposed between the semiconductor layer and the second dielectric layer.

[0020] In one possible implementation, the material of the second dielectric layer is a ferroelectric material, and the thin film transistor further includes a third dielectric layer disposed between the semiconductor layer and the second dielectric layer. The gate, the second dielectric layer, and the third dielectric layer can form a composite gate structure. By using the composite gate structure, the thin film transistor can realize the performance of a negative capacitance transistor, and the gate control ability of the thin film transistor can be improved by using the negative capacitance. When the thin film transistor is used in a memory, the performance of the memory can be improved.

[0021] In one possible implementation, the thin film transistor further comprises a first conductive layer disposed between the second dielectric layer and the third dielectric layer. The composite gate structure comprising the gate, the second dielectric layer, the first conductive layer and the third dielectric layer can enable the thin film transistor to realize the performance of a negative capacitance transistor, and the gate control ability of the thin film transistor can be improved by using the negative capacitance. When the thin film transistor is used in a memory, the performance of the memory can be improved.

[0022] In one possible implementation, the thin film transistor further includes a fourth dielectric layer disposed between the second electrode and the semiconductor layer, and / or a fifth dielectric layer disposed between the first electrode and the semiconductor layer. The fourth dielectric layer is disposed between the second electrode and the semiconductor layer so as to avoid diffusion problems of the second electrode in the contact area with the semiconductor layer and to reduce Fermi level pinning problems of the contact between the second electrode and the semiconductor layer. The fifth dielectric layer is disposed between the first electrode and the semiconductor layer so as to avoid diffusion problems of the first electrode in the contact area with the semiconductor layer and to reduce Fermi level pinning problems of the contact between the first electrode and the semiconductor layer.

[0023] In one possible implementation, the thickness of both the fourth and fifth dielectric layers ranges from 0.1 nm to 2 nm, which ensures that when a voltage is applied to the gate, the second electrode and the first electrode are electrically connected through the semiconductor layer, without affecting the performance of the thin film transistor.

[0024] In one possible implementation, the thin film transistor further includes a modulating gate electrode disposed between the first electrode and the second electrode, the modulating gate electrode being disposed on a side of the semiconductor layer away from the gate body, and the modulating gate electrode being surrounded by the first dielectric layer such that the modulating gate electrode is spaced apart from the first electrode, the second electrode, and the semiconductor layer. The modulating gate electrode can be utilized to adjust a threshold voltage of the thin film transistor.

[0025] In one possible implementation, the first electrode is a drain and the second electrode is a source; or the first electrode is a source and the second electrode is a drain.

[0026] According to a second aspect, a memory is provided. The memory includes at least one layer of a memory array arranged on a substrate, and each layer of the memory array includes a plurality of memory cells, a write word line, a write bit line, a read word line and a read bit line distributed in the array; the memory cell includes a second thin film transistor and a first thin film transistor stacked together, the gate of the second thin film transistor is electrically connected to the write word line, and the second electrode is electrically connected to the write bit line; the second electrode and the first electrode of the first thin film transistor are electrically connected to the read word line and the read bit line, respectively. The second thin film transistor and the first thin film transistor are the thin film transistors described above. The first electrode of the second thin film transistor is adjacent to the gate of the first thin film transistor, and the first electrode of the second thin film transistor is electrically connected to the gate of the first thin film transistor. The second thin film transistor and the first thin film transistor in the memory are the thin film transistors described above, and the second thin film transistor and the first thin film transistor have the same technical effects as those in the above-mentioned embodiment, so the details will not be described again here.

[0027] In one possible implementation, the memory cell further includes a connecting electrode disposed between the first thin film transistor and the second thin film transistor, and the gate of the first thin film transistor is electrically connected to the first electrode of the second thin film transistor by using the connecting electrode.

[0028] In one possible implementation, the gates of the second thin film transistors in the plurality of storage cells arranged sequentially in each layer of the storage array along a first direction are electrically connected to the same write word line, and the second electrodes of the second thin film transistors in the plurality of storage cells arranged sequentially in each layer of the storage array along a second direction are electrically connected to the same write bit line, and the first direction crosses the second direction. In each layer of the storage array, the gates of the second thin film transistors in the plurality of storage cells arranged sequentially along the first direction are electrically connected to the same write word line, and the second electrodes of the second thin film transistors in the plurality of storage cells arranged sequentially along the second direction are electrically connected to the same write bit line. Thus, in the write operation process, the first switch signal can be provided to the plurality of write word lines row by row, whereby the plurality of rows of the second thin film transistors are turned on row by row. When a first switch signal is provided to the write word line of the current row, logical information is simultaneously written to multiple memory cells electrically connected to the write word line of the current row by using multiple write bit lines, thereby writing logical information to the memory cells row by row, thereby enabling rapid writing of multiple memory cells in the storage array.

[0029] In one possible implementation, the second electrodes of the first thin film transistors in the plurality of memory cells arranged sequentially in each layer of the storage array along the first direction are electrically connected to the same read bit line, and the first electrodes of the first thin film transistors in the plurality of memory cells arranged sequentially in each layer of the storage array along the second direction are electrically connected to the same read word line; the second electrodes of the first thin film transistors in the plurality of memory cells arranged sequentially in each layer of the storage array along the first direction are electrically connected to the same read word line, and the first electrodes of the first thin film transistors in the plurality of memory cells arranged sequentially in each layer of the storage array along the second direction are electrically connected to the same read bit line. the second electrodes of the first thin film transistors in the plurality of memory cells arranged sequentially in each layer of the storage array along the second direction are electrically connected to the same read bit line, and the first electrodes of the first thin film transistors in the plurality of memory cells arranged sequentially in each layer of the storage array along the first direction are electrically connected to the same read word line; or the second electrodes of the first thin film transistors in the plurality of memory cells arranged sequentially in each layer of the storage array along the second direction are electrically connected to the same read word line, and the first electrodes of the first thin film transistors in the plurality of memory cells arranged sequentially in each layer of the storage array along the first direction are electrically connected to the same read bit line. Here, the first direction intersects with the second direction. In the read operation process, a third level signal can be provided to the plurality of read word lines row by row. When the third level signal is provided to the read word line of the current row, a current on each read bit line is detected. In this way, the logical information stored in the plurality of memory cells electrically connected to the read word line of the current row can be read out simultaneously. This allows the logical information stored in the memory cells to be read out row by row, thereby implementing rapid reading of multiple memory cells in the memory array.

[0030] In one possible implementation, the first direction and the second direction are orthogonal.

[0031] In one possible implementation, the first thin film transistor further includes a first modulation gate electrode disposed between the first electrode and the second electrode, the first modulation gate electrode being disposed on a side of the semiconductor layer away from the gate body, and the first modulation gate electrode being surrounded by the first dielectric layer of the first thin film transistor so as to be spaced apart from the second electrode, the first electrode and the semiconductor layer; the first modulation gate electrodes of the plurality of first thin film transistors located in the same layer are electrically connected together; and / or the second thin film transistor further includes a second modulation gate electrode disposed between the first electrode and the second electrode, the second modulation gate electrode being disposed on a side of the semiconductor layer away from the gate body, and the second modulation gate electrode being surrounded by the first dielectric layer of the second thin film transistor so as to be spaced apart from the second electrode, the first electrode and the semiconductor layer; the second modulation gate electrodes of the plurality of second thin film transistors located in the same layer are electrically connected together. Since the first thin film transistor includes a first modulation gate electrode, the threshold voltage of the first thin film transistor can be adjusted using the first modulation gate electrode. In addition, the first modulation gate electrodes of the plurality of first thin film transistors are electrically connected together, so that the collective modulation of the plurality of first thin film transistors can be realized. The second thin film transistor includes a second modulation gate electrode, so that the threshold voltage of the second thin film transistor can be adjusted using the second modulation gate electrode. In addition, the second modulation gate electrodes of the plurality of second thin film transistors are electrically connected together, so that the collective modulation of the plurality of second thin film transistors can be realized. Based on this, the memory performance of the memory can be adjusted more flexibly.

[0032] In one possible implementation, the memory further includes an integrated circuit and the storage array is located on the integrated circuit, in which case the memory is an on-chip memory.

[0033] In one possible implementation, the storage cells are electrically connected to an integrated circuit, in this manner the integrated circuit can be used to control the storage cells.

[0034] According to a third aspect, an electronic device is provided. The electronic device includes a circuit board and a memory electrically connected to the circuit board, and the memory is the above-mentioned memory. The electronic device has the same technical effects as those in the above-mentioned embodiment, and the details are not described again here.

[0035] According to a fourth aspect, a method for manufacturing a thin film transistor is provided. The method for manufacturing a thin film transistor includes: first, forming a first electrode, a first dielectric layer, a second electrode, and a semiconductor layer on a substrate, where the first electrode, the first dielectric layer, and the second electrode are stacked in order, the first dielectric layer separates the first electrode from the second electrode, and a semiconductor layer is formed on a side of the first dielectric layer, and the second electrode and the first electrode are both electrically connected to the semiconductor layer; and then, sequentially forming a second dielectric layer and a gate, where the gate includes a gate base located at the top and a gate body extending from the gate base to the bottom, and the second dielectric layer separates the gate from the semiconductor layer, the first electrode, and the second electrode. The method for manufacturing a thin film transistor has the same technical effect as that in the previous embodiment, and the details will not be described again here.

[0036] In one possible implementation, the first electrode is formed as a drain and the second electrode is formed as a source; or the first electrode is formed as a source and the second electrode is formed as a drain.

[0037] In one possible implementation, the step of forming a first electrode, a first dielectric layer, a second electrode, and a semiconductor layer on a substrate includes: first, sequentially forming a first conductive thin film, a first dielectric thin film, and a second conductive thin film stacked on the substrate; then, patterning the first conductive thin film, the first dielectric thin film, and the second conductive thin film to form a first electrode, a first dielectric layer, and a second electrode stacked sequentially; and then, forming a semiconductor layer on a side of the first dielectric layer and a side of the second electrode.

[0038] In one possible implementation, the step of forming the first electrode, the first dielectric layer, the second electrode, and the semiconductor layer on the substrate includes: first forming a first conductive thin film and a third dielectric thin film sequentially stacked on the substrate; then forming a modulating gate electrode on the third dielectric thin film; then forming a fourth dielectric thin film surrounding the modulating gate electrode; then forming a second conductive thin film on the fourth dielectric thin film; then patterning the first conductive thin film to form the first electrode, patterning the fourth dielectric thin film and the third dielectric thin film to form the first dielectric layer, patterning the second conductive thin film to form the second electrode; and forming a semiconductor layer on a side of the first dielectric layer and a side of the second electrode. The modulating gate electrode can be used to adjust the threshold voltage of the thin film transistor.

[0039] In one possible implementation, the step of forming a first electrode, a first dielectric layer, a second electrode, and a semiconductor layer on a substrate includes: first forming a first conductive thin film and a first dielectric thin film that are sequentially stacked on the substrate; then patterning the first conductive thin film and the first dielectric thin film to form a first electrode and a first dielectric layer that are sequentially stacked; then forming a semiconductor layer on a side of the first dielectric layer; and then forming a second electrode on the first dielectric layer.

[0040] In one possible implementation, the material of the second dielectric layer is a ferroelectric material; after the semiconductor layer is formed and before the second dielectric layer is formed, the manufacturing method further includes the steps of: forming a third dielectric layer, the third dielectric layer being formed on the side of the first dielectric layer. The third dielectric layer has the same technical effect as in the previous embodiment, and the details are not described again here.

[0041] In one possible implementation, after the third dielectric layer is formed and before the second dielectric layer is formed, the manufacturing method further includes the steps of: forming a first conductive layer, the first conductive layer being formed on a side of the first dielectric layer. The first conductive layer has the same technical effect as in the previous embodiment, and the details are not described again here.

[0042] In one possible implementation, after the first electrode is formed and before the semiconductor layer is formed, the manufacturing method further includes the steps of: forming a fifth dielectric layer, the fifth dielectric layer contacting the first electrode and the semiconductor layer respectively. In this way, the problem of diffusion of the first electrode in the contact area with the semiconductor layer can be avoided, and the Fermi level pinning problem of the contact between the first electrode and the semiconductor layer can be reduced.

[0043] In one possible implementation, after the second electrode is formed and before the semiconductor layer is formed; or after the semiconductor layer is formed and before the second electrode is formed, the manufacturing method further includes: forming a fourth dielectric layer, the fourth dielectric layer contacting the second electrode and the semiconductor layer respectively. In this way, the problem of diffusion of the second electrode in the contact area with the semiconductor layer can be avoided, and the Fermi level pinning problem of the contact between the second electrode and the semiconductor layer can be reduced.

[0044] According to a fifth aspect, there is provided a memory manufacturing method. The memory manufacturing method includes forming at least one layer of a storage array on a substrate. The method for manufacturing any layer of the storage array includes the steps of: first, forming a plurality of first signal lines arranged in parallel on the substrate; then, forming a plurality of first thin film transistors distributed in an array and a plurality of second signal lines arranged in parallel on the plurality of first signal lines, the first thin film transistors being manufactured by using the above-mentioned thin film transistor manufacturing method, a first electrode of the first thin film transistor being electrically connected to the first signal line, and a second electrode of the first thin film transistor being electrically connected to the second signal line; the first signal line being one of a read bit line and a read word line, and the second signal line being the other of the read bit line and the read word line ... The method includes the steps of: forming a plurality of second thin film transistors distributed in an array and a plurality of write bit lines arranged in parallel on the thin film transistor, the second electrodes of the second thin film transistors being electrically connected to the write bit lines, the second thin film transistors being manufactured by the above-mentioned thin film transistor manufacturing method, one second thin film transistor corresponds to one first thin film transistor, and the first electrodes of the second thin film transistors are electrically connected to the gates of the corresponding first thin film transistors; forming a plurality of write word lines arranged in parallel on the second thin film transistors, the gates of the second thin film transistors being electrically connected to the write word lines. Both the first thin film transistor and the second thin film transistor in the memory are manufactured by the above-mentioned thin film transistor manufacturing method, so that the sizes of the first thin film transistor and the second thin film transistor in the manufactured memory are relatively small, thereby improving the area utilization rate.

[0045] In one possible implementation, after forming a plurality of first thin film transistors distributed in an array and a plurality of second signal lines arranged in parallel on a plurality of first signal lines, and before forming a plurality of second thin film transistors distributed in an array and a plurality of write bit lines arranged in parallel on the first thin film transistors, a manufacturing method for any layer of a memory array further includes the step of: forming a plurality of connecting electrodes distributed in an array, and a gate of the first thin film transistor is electrically connected to a first electrode of a corresponding second thin film transistor by using the connecting electrode. [Brief description of the drawings]

[0046] [Figure 1] FIG. 1 is a schematic diagram of a structure of a thin film transistor in the prior art;

[0047] [Figure 2a] 1 is a schematic diagram of a memory cell structure in a 2T0C memory.

[0048] [Figure 2b] 4 is a schematic diagram of the structure of a second thin film transistor and a first thin film transistor in a memory cell. FIG.

[0049] [Figure 2c] 11 is a schematic diagram showing the structures of a second thin film transistor and a first thin film transistor in another memory cell. FIG.

[0050] [Diagram 3] 1 is a schematic diagram of a structure of an electronic device according to an embodiment of the present application.

[0051] [Figure 4] FIG. 2 is a schematic diagram of a memory structure according to an embodiment of the present application.

[0052] [Diagram 5] FIG. 2 is a schematic diagram of a storage array structure according to an embodiment of the present application.

[0053] [Figure 6a] FIG. 2 is a schematic diagram of a storage array structure according to another embodiment of the present application.

[0054] [Figure 6b] FIG. 6b is a schematic cross-sectional view along a first direction of FIG. 6a;

[0055] [Figure 6c] FIG. 6b is a schematic cross-sectional view along a second direction of FIG. 6a.

[0056] [Figure 6d] FIG. 6B is a schematic cross-sectional view taken along the direction AA of FIG. 6B or FIG. 6C.

[0057] [Figure 6e] FIG. 6B is another schematic cross-sectional view taken along the direction AA of FIG. 6B or FIG. 6C.

[0058] [Figure 7] FIG. 2 is a schematic diagram of a memory structure according to another embodiment of the present application.

[0059] [Figure 8a] 1 is a schematic diagram of a structure of a thin film transistor according to an embodiment of the present application.

[0060] [Figure 8b] FIG. 8b is a schematic cross-sectional view along direction BB of FIG. 8a.

[0061] [Figure 8c] FIG. 8b is another schematic cross-sectional view along direction BB of FIG. 8a.

[0062] [Figure 9] FIG. 2 is a schematic diagram of a structure of a thin film transistor according to another embodiment of the present application.

[0063] [Figure 10] FIG. 2 is a schematic diagram of a structure of a thin film transistor according to yet another embodiment of the present application.

[0064] [Figure 11] FIG. 2 is a schematic diagram of a structure of a thin film transistor according to yet another embodiment of the present application.

[0065] [Figure 12a] FIG. 2 is a schematic diagram of a structure of a thin film transistor according to another embodiment of the present application.

[0066] [Figure 12b] FIG. 2 is a schematic diagram of a structure of a thin film transistor according to yet another embodiment of the present application.

[0067] [Figure 12c] FIG. 2 is a schematic diagram of a structure of a thin film transistor according to yet another embodiment of the present application.

[0068] [Figure 13] FIG. 2 is a schematic diagram of a structure of a thin film transistor according to another embodiment of the present application.

[0069] [Figure 14] FIG. 2 is a schematic diagram of a structure of a thin film transistor according to yet another embodiment of the present application.

[0070] [Figure 15] FIG. 2 is a schematic diagram of a structure of a thin film transistor according to yet another embodiment of the present application.

[0071] [Figure 16] FIG. 2 is a schematic diagram of a structure of a thin film transistor according to another embodiment of the present application.

[0072] [Figure 17a] FIG. 2 is a schematic diagram of a storage array structure according to yet another embodiment of the present application.

[0073] [Figure 17b] FIG. 17b is a schematic cross-sectional view along direction CC of FIG. 17a.

[0074] [Figure 17c]FIG. 17b is another schematic cross-sectional view along direction CC of FIG. 17a.

[0075] [Figure 18] 1 is a schematic flow chart of a thin film transistor manufacturing method according to an embodiment of the present application.

[0076] [Figure 19] 1A-1D are schematic diagrams of the structure of a thin film transistor fabrication process according to an embodiment of the present application.

[0077] [Figure 20] 1 is a schematic diagram of the structure of another thin film transistor preparation process according to an embodiment of the present application.

[0078] [Figure 21] 1 is a schematic diagram of the structure of yet another thin film transistor preparation process according to an embodiment of the present application.

[0079] [Figure 22] 1 is a schematic diagram of the structure of yet another thin film transistor preparation process according to an embodiment of the present application.

[0080] [Diagram 23] 1 is a schematic diagram of the structure of yet another thin film transistor preparation process according to an embodiment of the present application.

[0081] [Figure 24] 1 is a schematic diagram of the structure of yet another thin film transistor preparation process according to an embodiment of the present application.

[0082] [Diagram 25] 1 is a schematic diagram of the structure of yet another thin film transistor preparation process according to an embodiment of the present application.

[0083] [Figure 26] 1 is a schematic diagram of the structure of yet another thin film transistor preparation process according to an embodiment of the present application.

[0084] [Figure 27] 1 is a schematic diagram of the structure of yet another thin film transistor preparation process according to an embodiment of the present application.

[0085] [Figure 28] 1 is a schematic diagram of the structure of yet another thin film transistor preparation process according to an embodiment of the present application.

[0086] [Figure 29] 1 is a schematic diagram of the structure of yet another thin film transistor preparation process according to an embodiment of the present application.

[0087] [Diagram 30] 1 is a schematic flow chart of a memory tuning method according to an embodiment of the present application;

[0088] Reference Number:

[0089] 1 - antenna, 2 - antenna, 10 - thin film transistor, 100 - electronic device, 101 - substrate, 102 - semiconductor layer, 103 - source, 104 - drain, 105 - gate insulating layer, 106 - gate, 107 - interlayer dielectric layer, 108 - second electrode, 109 - first electrode, 110 - processor, 111 - connecting electrode, 112 - second dielectric layer, 113 - first dielectric layer, 114 - fourth dielectric layer, 115 - fifth dielectric layer, 116 - third dielectric layer, 117 - first conductive layer, 118 - modulating gate electrode, 118a - first modulating gate electrode, 118b - second modulating gate electrode, 120 - external memory interface, 121 - internal memory, 130 - USB interface, 140 - charging management module, 141 - power management module, 142 - battery, 150 - mobile communication module, 160 - wireless communication module, 170 - audio module, 180 - sensor module, 190 - button, 191 - motor, 192 - indicator, 193 - camera, 194 - display screen, 195 - SIM card interface, 200 - memory, 201 - memory array, 201A - memory cell, 202 - sixth dielectric layer, 203 - integrated circuit, 1080 - second conductive thin film, 1090 - first conductive thin film, 1121 - first dielectric portion, 1122 - second dielectric portion, 1130 - first dielectric thin film, 1131 - third dielectric thin film, and 1132 - fourth dielectric thin film. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0090] The following describes the technical solutions in the embodiments of the present application with reference to the accompanying drawings in the embodiments of the present application. It is obvious that the described embodiments are only some, but not all, of the embodiments of the present application.

[0091] The terms "first," "second," etc. below are intended merely for ease of description and should not be understood as an indication or implication of the relative importance or quantity of the indicated technical features. Thus, features qualified by "first," "second," etc. may explicitly or implicitly include one or more of those features. In the present description, unless otherwise specified, "plurality" means two or more.

[0092] In the embodiments of the present application, unless otherwise clearly specified and limited, the term "connected" should be understood in a broad sense. For example, "connected" may be a fixed connection, a detachable connection, or an integral connection; or a direct connection; or an indirect connection through an intermediate medium. Also, the term "electrically connected" may be a direct electrical connection or an indirect electrical connection through an intermediate medium. In addition, the term "coupled" may indicate that two or more components are in direct physical contact or electrical contact, or may indicate that two or more components are not in direct contact with each other but are electrically connected or interact with each other through an intermediate medium.

[0093] In the embodiments of the present application, the words "example" or "for example" and the like are used to denote providing an example, illustration, or explanation. Any embodiment or design solution described in the embodiments of the present application as an "example" or "for example" should not be described as being preferred or having more advantages over another embodiment or design solution. Rather, the words "example", "for example", and the like are intended to concretely present a relative concept.

[0094] In the embodiments of the present application, the term "and / or" describes an association relationship between associated objects and may indicate that a three-way relationship exists. For example, A and / or B may indicate the following cases: only A is present, both A and B are present, and only B is present, where A and B may be singular or plural. The symbol " / " generally indicates an "or" relationship between associated objects.

[0095] In the embodiments of the present application, the description of the accompanying drawings is based on the directions shown in the accompanying drawings. When the directions shown in the accompanying drawings are changed, the corresponding description is changed accordingly.

[0096] With the continuous development of integrated circuit technology, the number of transistors placed on a chip per unit area in electronic products such as computers or mobile phones is continuously increasing, so that the performance of electronic products is continuously optimized. On the one hand, the amount of data that can be operated by the processor on the chip in a unit time is constantly increasing, and on the other hand, the storage density of the memory on the chip is also constantly increasing, thereby meeting people's demand for data processing in the information age. However, since the logic units in the processor and the storage cells in the memory have different structures and technologies, the degree of performance improvement of the processor and memory is different. Specifically, the storage density and read / write speed of the memory cannot keep up with the operating speed of the processor, and a "storage wall" appears, which ultimately limits the overall performance improvement of electronic products.

[0097] In order to solve the above problems, various types of memories have emerged. In various types of memories, gain cell memories are widely used, and the main target application scenario of gain cell memories is high-speed and high-density memories. Gain cell memories with 2T0C structure can realize nanosecond-level read / write speeds and millisecond-level memory times. Memory time refers to the time to retain information stored in the memory, that is, the time from when information is written to when the information is correctly read. However, the memory time of 2T0C gain cell memories is relatively short, and 2T0C gain cell memories need to be continuously refreshed in practical applications. This causes relatively large dynamic power consumption.

[0098] Based on the above description, in order to improve the retention duration of the memory with 2T0C structure and solve the problem that the power consumption of the gain cell memory with 2T0C structure is relatively large, currently, the gain cell memory with 2T0C structure can be prepared based on TFT. On the one hand, the advantage of the ultra-low leakage current of TFT can be used, so that the retention time of the memory with 2T0C structure is greatly increased and the dynamic power consumption is reduced; on the other hand, the advantage of the low temperature of the TFT manufacturing process can be used, so that three-dimensional (3D) memory integration can be implemented and the memory density can be improved.

[0099] Referring to FIG. 2a, FIG. 2a is a schematic diagram of the structure of a memory cell in a memory with a 2T0C structure. The memory cell includes a first thin film transistor Tr0 and a second thin film transistor Tr1. The gate of the second thin film transistor Tr1 is electrically connected to a write word line WWL, the source of the second thin film transistor Tr1 is electrically connected to a write bit line WBL, the drain of the second thin film transistor Tr1 is electrically connected to the gate of the first thin film transistor Tr0, and the source of the first thin film transistor Tr0 is electrically connected to a read word line RWL. The drain of the first thin film transistor Tr0 is electrically connected to a read bit line RBL.

[0100] 2b and 2c are schematic diagrams of the structure of the first thin film transistor Tr0 and the second thin film transistor Tr1 in the storage cell of the TFT-based memory with 2T0C structure, respectively. Referring to FIG. 2b and FIG. 2c, both the first thin film transistor Tr0 and the second thin film transistor Tr1 include a semiconductor layer 102 disposed on a substrate 101, a source 103 and a drain 104 disposed on the semiconductor layer 102 and in contact with the semiconductor layer 102, a gate insulating layer 105 disposed on the semiconductor layer 102, and a gate 106 disposed on the gate insulating layer 105. In addition, the interlayer dielectric layer 107 in FIG. 2b and FIG. 2c is configured to separate different conductive film layers, and the signal lines are electrically connected to the corresponding electrodes by using vias. For example, the read word line RWL is electrically connected to the source 103 of the first thin film transistor Tr0 using a via.

[0101] However, the semiconductor layer 102 in the first thin film transistor Tr0 and the second thin film transistor Tr1 shown in Figures 2b and 2c both extend along a plane parallel to the gate 106, and the source 103 and the drain 104 are located in the same layer. Thus, the size of the first thin film transistor Tr0 and the second thin film transistor Tr1 is relatively large, and the area utilization rate of the first thin film transistor Tr0 and the second thin film transistor Tr1 is low. In addition, since the source 103 and the drain 104 are located in the same layer, a short circuit is easily generated in the signal line electrically connected to the source electrode 103 and the signal line electrically connected to the drain electrode 104, which does not contribute to routing and increases the difficulty of the process.

[0102] In order to solve the above-mentioned problems, an embodiment of the present application provides a memory. The memory can be used in an electronic device. The electronic device can be a mobile phone, a tablet computer, a desktop computer, a laptop computer, a handheld computer, a notebook computer, an ultra-mobile personal computer (UMPC), a netbook, a mobile phone, a personal digital assistant (PDA), an augmented reality (AR) device, a virtual reality (VR) device, an artificial intelligence (AI) device, a wearable device, an in-vehicle device, a smart home device, and / or a smart city device, and the specific type of the electronic device is not particularly limited in the embodiment of the present application.

[0103] 3 is a schematic diagram of the structure of an electronic device. The electronic device 100 may include a processor 110, an external memory interface 120, an internal memory 121, a universal serial bus (USB) interface 130, a charging management module 140, a power management module 141, a battery 142, an antenna 1, an antenna 2, a mobile communication module 150, a wireless communication module 160, an audio module 170, a sensor module 180, a button 190, a motor 191, an indicator 192, a camera 193, a display screen 194, and a subscriber identity module (SIM) card interface 195.

[0104] It may be understood that the structure shown in this embodiment of the present application does not constitute a specific limitation on the electronic device 100. In some other embodiments of the present application, the electronic device 100 may include more or fewer components than those shown in the figures, or some components may be combined, or some components may be divided, or a different component deployment may be used. The components shown in the figures may be implemented by hardware, software, or a combination of software and hardware.

[0105] The processor 110 may include one or more processing units. For example, the processor 110 may include an application processor (AP), a modem processor, a graphics processing unit (GPU), an image signal processor (ISP), a controller, a video codec, a digital signal processor (DSP), a baseband processor, and / or a neural-network processing unit (NPU). The different processing units may be separate components or may be integrated into one or more processors.

[0106] The controller may generate an operation control signal according to the instruction operation code and the time series signal to complete the control of instruction reading and instruction execution.

[0107] A memory may further be disposed within the processor 110 and configured to store instructions and data. In some embodiments, the memory within the processor 110 is a cache memory. The memory may store instructions or data that have just been used or that have been used periodically by the processor 110. When the processor 110 needs to use the instructions or data again, the processor can directly recall the instructions or data from the memory. This avoids repeated accesses and reduces the latency of the processor 110, thus improving system efficiency.

[0108] In some embodiments, the processor 110 may include one or more interfaces, which may include an inter-integrated circuit (I2C) interface, an inter-integrated circuit sound (I2S) interface, a pulse code modulation (PCM) interface, a universal asynchronous receiver / transmitter (UART) interface, a mobile industry processor interface (MIPI), a general-purpose input / output (GPIO) interface, a subscriber identity module (SIM) interface, and / or a universal serial bus (USB) interface.

[0109] The I2C interface is a bidirectional synchronous serial bus and includes a serial data line (SDA) and a serial clock line (SCL). The I2S interface may be configured to perform audio communications.

[0110] The PCM interface is also configured to perform audio communications and to sample, quantize, and encode analog signals.

[0111] The UART interface is a universal serial data bus that is configured to perform asynchronous communication. The bus may be a bidirectional communication bus. The UART interface converts data to be transmitted between serial and parallel communication.

[0112] The MIPI interface may be configured to connect the processor 110 to peripheral components such as a display screen 194 or a camera 193. MIPI interfaces include a camera serial interface (CSI), a display serial interface (DSI), and the like.

[0113] The GPIO interface may be configured by software. The GPIO interface may be configured as a control signal or a data signal. The GPIO interface may alternatively be configured as an I2C interface, an I2S interface, a UART interface, or a MIPI interface.

[0114] The USB interface 130 is an interface conforming to the USB standard specification, and may specifically be a Mini USB interface, a Micro USB interface, or a USB Type-C interface. The USB interface 130 may be configured to connect to a charger to charge the electronic device 100, or may be configured to transmit data between the electronic device 100 and a peripheral device, or may be configured to connect to a headset to play audio by using the headset.

[0115] It may be understood that the interface connection relationships between modules shown in this embodiment of the present invention are merely illustrative examples and do not constitute limitations on the structure of the electronic device 100. In some other embodiments of the present application, the electronic device 100 may alternatively use a different interface connection scheme than in the above-described embodiment, or may use a combination of multiple interface connection schemes.

[0116] The charging management module 140 is configured to receive a charging input from a charger, which may be a wireless charger or a wired charger.

[0117] The power management module 141 is configured to connect to the battery 142, the charging management module 140, and the processor 110. The power management module 141 receives input from the battery 142 and / or the charging management module 140 and provides power to the processor 110, the internal memory 121, the display screen 194, the camera 193, and the wireless communication module 160. The power management module 141 may be further configured to monitor parameters such as battery capacity, battery cycle count, and battery health (leakage or impedance). In some other embodiments, the power management module 141 may alternatively be located within the processor 110. In some other embodiments, the power management module 141 and the charging management module 140 may alternatively be located within the same component.

[0118] The wireless communication function of the electronic device 100 may be implemented by using antenna 1, antenna 2, a mobile communication module 150, a wireless communication module 160, a modem processor, and a baseband processor.

[0119] Antenna 1 and Antenna 2 are configured to transmit and receive electromagnetic signals. Each antenna in electronic device 100 may be configured to cover one or more communication frequency bands. Different antennas may be further multiplexed to improve antenna utilization. For example, Antenna 1 may be multiplexed as a diversity antenna for a wireless local area network. In some other embodiments, the antennas may be used in combination with a tuning switch.

[0120] The mobile communication module 150 can provide wireless communication solutions including 2G / 3G / 4G / 5G applied to the electronic device 100. The mobile communication module 150 may include at least one filter, switch, power amplifier, and low noise amplifier (LNA). The mobile communication module 150 can receive electromagnetic waves through the antenna 1, perform processing such as filtering or amplification on the received electromagnetic waves, and send the electromagnetic waves to a modem processor for demodulation. The mobile communication module 150 further amplifies the modulated signal in the modem processor and converts the signal into electromagnetic waves for emission through the antenna 1.

[0121] The modem processor may include a modulator and a demodulator. The modulator is configured to modulate a low-frequency baseband signal to be transmitted into a medium-frequency signal. The demodulator is configured to demodulate a received electromagnetic wave signal into a low-frequency baseband signal. The demodulator then transmits the low-frequency baseband signal obtained through demodulation to a baseband processor for processing. The low-frequency baseband signal is processed by the baseband processor and then transmitted to an application processor. The application processor outputs the audio signal using an audio device (not limited to a speaker or a telephone receiver) or displays an image or video using a display screen 194.

[0122] The wireless communication module 160 may be applied to the electronic device 100 to provide wireless communication solutions including wireless local area network (WLAN) (e.g., wireless fidelity (Wi-Fi) network), Bluetooth (BT), global navigation satellite system (GNSS), frequency modulation (FM), near field communication (NFC) technology, or infrared (IR) technology. The wireless communication module 160 may be one or more components integrating at least one communication processor module. The wireless communication module 160 receives electromagnetic waves through the antenna 2, performs frequency modulation and filtering processing on the electromagnetic wave signal, and sends the processed signal to the processor 110. The wireless communication module 160 further receives a signal to be transmitted from the processor 110, performs frequency modulation and amplification on the signal, and converts the signal into an electromagnetic wave for radiation through the antenna 2.

[0123] In some embodiments, antenna 1 of electronic device 100 is electrically connected to mobile communication module 150 and antenna 2 is electrically connected to wireless communication module 160, thereby enabling electronic device 100 to communicate with a network and another device by using wireless communication technologies. Wireless communication technologies include global system for mobile communications (GSM), general packet radio service (GPRS), and code division multiple access (CDMA).

[0124] The electronic device 100 can embody display functionality through a GPU, a display screen 194, and an application processor. The GPU is a microprocessor for image processing and is connected to the display screen 194 and the application processor. The GPU is configured to perform mathematical and geometric calculations and render images. The processor 110 can include one or more GPUs that execute program instructions that generate or modify display information.

[0125] The display screen 194 is configured to display images or video. In some embodiments, the electronic device 100 can include one or N display screens 194, where N is a positive integer greater than one.

[0126] The electronic device 100 may implement a photography function through an ISP, a camera 193, a video codec, a GPU, a display screen 194, and an application processor.

[0127] The ISP is configured to process the data fed back by the camera 193.

[0128] The camera 193 is configured to capture still images or video. In some embodiments, the electronic device 100 may include one or N cameras 193, where N is a positive integer greater than one.

[0129] The external memory interface 120 may be configured to connect to an external storage card, such as a micro SD card, to expand the storage capabilities of the electronic device 100. The external storage card communicates with the processor 110 through the external memory interface 120 to implement data storage functions. For example, files such as music and videos are stored on the external storage card.

[0130] The internal memory 121 may be configured to store computer executable program code. The executable program code includes instructions. The internal memory 121 may include a program storage area and a data storage area. The program storage area may store an operating system and application programs required by at least one function (e.g., audio playback function or image display function). The data storage area may store data created during use of the electronic device 100 (such as audio data and an address book). In addition, the internal memory 121 may include a high-speed random access memory or may include a non-volatile memory, such as at least one magnetic disk storage device, a flash memory device, or a universal flash storage (UFS). The processor 110 executes instructions stored in the internal memory 121 and / or instructions stored in a memory located within the processor to perform various functional applications and data processing of the electronic device 100.

[0131] The electronic device 100 may utilize an audio module 170 and an application processor to implement audio functions, such as music playback and recording functions.

[0132] The audio module 170 is configured to convert digital audio information to analog audio signals for output, and is also configured to convert analog audio input to digital audio signals. The audio module 170 may further be configured to encode and decode audio signals.

[0133] The buttons 190 include a power button, a volume button, etc. The buttons 190 may be mechanical or touch buttons. The electronic device 100 can receive button inputs and generate button signal inputs associated with user settings and function control of the electronic device 100.

[0134] The motor 191 may generate vibration prompts. The motor 191 may be configured to provide incoming vibration prompts and touch vibration feedback.

[0135] The indicator 192 may be an indicator light and may be configured to indicate charging status and power changes, or may be configured to indicate messages, missed calls, and notifications.

[0136] The SIM card interface 195 is configured to connect to a SIM card. The SIM card may be inserted into or removed from the SIM card interface 195 to effect contact with or separation from the electronic device 100. The electronic device 100 may support one or N SIM card interfaces, where N is a positive integer greater than one.

[0137] Based on this, the electronic device 100 may further include a circuit board, such as a printed circuit board (PCB). The processor 110 and the internal memory 121 may be disposed on the circuit board, and the processor 110 and the internal memory 121 are electrically connected to the circuit board.

[0138] The memory provided in this embodiment of the present application may be used as an internal memory 121 in the electronic device 100 or may be used as a memory in the processor 110 of the electronic device 100 .

[0139] The memory provided in this embodiment of the present application may be off-chip memory or on-chip memory (which may also be referred to as embedded memory).

[0140] In addition, the memory provided in this embodiment of the present application may be memory prepared based on a back end of line (BEOL) process.

[0141] 4, the memory 200 includes at least one layer of storage arrays 201 disposed on the substrate 101. FIG. 4 is a schematic diagram using an example in which the memory 200 includes two layers of storage arrays 201. When the memory 200 includes multiple layers of storage arrays 201, the storage arrays 201 may be stacked sequentially along the vertical direction, as shown in FIG.

[0142] Additionally, when memory 200 includes multiple layers of storage arrays 201, memory 200 may also be referred to as a three-dimensional integrated memory.

[0143] In addition, the number of layers of the storage array 201 may be stacked as needed. A larger number of layers of the stacked storage array 201 indicates a higher storage density of the memory 200.

[0144] When the memory 200 includes multiple layers of memory arrays 201, in some embodiments, referring to FIG. 4 , the memory 200 further includes a sixth dielectric layer 202 disposed between two adjacent layers of the memory array 201, and the two adjacent layers of the memory array 201 are separated by using the sixth dielectric layer 202.

[0145] The material of the sixth dielectric layer 202 may be one or more of insulating materials such as SiO2 (silicon dioxide), Al2O3 (aluminum oxide), HfO2 (hafnium dioxide), ZrO2 (zirconium oxide), TiO2 (titanium dioxide), Y2O3 (yttrium trioxide), and Si3N4 (silicon nitride).

[0146] The sixth dielectric layer 202 may be a single layer structure or a multi-layer stack structure, and the material of the single layer structure and the material of each layer in the multi-layer stack structure may be one or more of SiO2, Al2O3, HfO2, ZrO2, TiO2, Y2O3, and Si3N4.

[0147] 5 and 6a, each layer of the memory array 201 includes a plurality of memory cells 201A arranged in an array, write word lines WWL (write word line), write bit lines WBL (write bit line), read word lines RWL (read word line), and read bit lines RBL (read bit line).

[0148] 6a, 6b, 6c, 6d and 6e, the memory cell 201A includes a stacked first thin film transistor Tr0 and a second thin film transistor Tr1.

[0149] The first thin film transistor Tr0 includes a gate 106a, which includes a gate base 1061a located at the top and a gate body 1062a extending from the gate base 1061a to the bottom. The first thin film transistor Tr0 further includes a first electrode 109a, a second electrode 108a, a first dielectric layer 113a, a second dielectric layer 112a, and a semiconductor layer 102a. The first electrode 109a is located at the bottom, and the second electrode 108a is located between the first electrode 109a and the gate base 1061a. The first dielectric layer 113a is disposed between the second electrode 108a and the first electrode 109a, and the first dielectric layer 113a is configured to separate the first electrode 109a from the second electrode 108a. The semiconductor layer 102a is disposed along the sides of the gate body 1062a, and a second dielectric layer 112a separates the semiconductor layer 102a from the gate 106a. The first electrode 109a and the second electrode 108a are each electrically connected to the semiconductor layer 102a.

[0150] As shown in Figures 6a, 6b, 6c, and 6d, the second dielectric layer 112a covers the surface of the gate base 1061a and the surface of the gate body 1062a. Also, the second dielectric layer 112a surrounds the outside of the gate body 1062a on the first electrode 109a, the semiconductor layer 102a surrounds the outside of the second dielectric layer 112a, and the second electrode 108a is disposed on the outside of the semiconductor layer 102a and is electrically connected to the semiconductor layer 102a. The second electrode 108a is on the first electrode 109a and is separated by the first dielectric layer 113a, and the first electrode 109a is electrically connected to the semiconductor layer 102a.

[0151] The second thin film transistor Tr1 includes a gate 106b, which includes a gate base 1061b located at the top and a gate body 1062b extending from the gate base 1061b to the bottom. The second thin film transistor Tr1 further includes a first electrode 109b, a second electrode 108b, a first dielectric layer 113b, a second dielectric layer 112b, and a semiconductor layer 102b. The first electrode 109b is located at the bottom, and the second electrode 108b is located between the first electrode 109a and the gate base 1061a. The first dielectric layer 113b is disposed between the second electrode 108b and the first electrode 109b, and the first dielectric layer 113b is configured to separate the first electrode 109b from the second electrode 108b. The second dielectric layer 112b covers the surface of the gate base 1061b and the surface of the gate body 1062b. The semiconductor layer 102b is disposed along the side of the gate body 1062b, and the second dielectric layer 112b separates the semiconductor layer 102b from the gate 106b. The first electrode 109b and the second electrode 108b are each electrically connected to the semiconductor layer 102b.

[0152] As shown in Figures 6a, 6b, 6c and 6d, the second dielectric layer 112b surrounds the outside of the gate body 1062b on the first electrode 109b, the semiconductor layer 102b surrounds the outside of the second dielectric layer 112b, and the second electrode 108b is disposed outside the semiconductor layer 102b and electrically connected to the semiconductor layer 102b. The second electrode 108b is on the first electrode 109b and is separated by the first dielectric layer 113b, and the first electrode 109b is electrically connected to the semiconductor layer 102b.

[0153] The gate 106b (gate, G) of the second thin film transistor Tr1 is electrically connected to the write word line WWL, and the second electrode 108b is electrically connected to the write bit line WBL. The first electrode 109a and the second electrode 108a of the first thin film transistor Tr0 are electrically connected to the read word line RWL and the read bit line RBL, respectively. The first electrode 109b of the second thin film transistor Tr1 is adjacent to the gate 106a of the first thin film transistor Tr0, and the first electrode 109b of the second thin film transistor Tr1 is electrically connected to the gate 106a of the first thin film transistor Tr0.

[0154] Figure 6b is a schematic cross-sectional view along a first direction X in Figure 6a, Figure 6c is a schematic cross-sectional view along a second direction Y in Figure 6a, Figure 6d is a schematic cross-sectional view along direction AA in Figure 6b or Figure 6c, and Figure 6e is another schematic cross-sectional view along direction AA in Figure 6b or Figure 6c.

[0155] It can be understood that the memory 200 provided in this embodiment of the present application is a gain cell structure memory based on a 2T0C structure.

[0156] In some embodiments, the first electrode 109b of the second thin film transistor Tr1 is in direct contact with the gate 106a of the first thin film transistor Tr0. In some other embodiments, referring to Figures 6a, 6b and 6c, both the first electrode 109b of the second thin film transistor Tr1 and the gate 106a of the first thin film transistor Tr0 are in contact with the connecting electrode 111, and the first electrode 109b of the second thin film transistor Tr1 is electrically connected to the gate 106a of the first thin film transistor Tr0 by using the connecting electrode 111.

[0157] The second thin film transistor Tr1 is a write transistor, and the first thin film transistor Tr0 is a read transistor.

[0158] The second thin film transistor Tr1 and the first thin film transistor Tr0 may have the same structure or different structures. It should be understood that in some embodiments, the projection of the second thin film transistor Tr1 onto the substrate overlaps with the projection of the first thin film transistor Tr0 onto the substrate.

[0159] The write word line WWL may be fabricated synchronously with the gate 106b of the second thin film transistor Tr1, and the write bit line WBL may be fabricated synchronously with the second electrode 108b of the second thin film transistor Tr1.

[0160] The second electrode 108a of the first thin film transistor Tr0 may be electrically connected to the read word line RWL, and the first electrode 109a may be electrically connected to the read bit line RBL. In this case, the second electrode 108a of the first thin film transistor Tr0 and the read word line RWL may be manufactured synchronously, and the first electrode 109a of the first thin film transistor Tr0 and the read bit line RBL may be manufactured synchronously. Alternatively, the second electrode 108a of the first thin film transistor Tr0 may be electrically connected to the read bit line RBL, and the first electrode 109a of the first thin film transistor Tr0 may be electrically connected to the read word line RWL. In this case, the second electrode 108a of the first thin film transistor Tr0 and the read bit line RBL may be manufactured synchronously, and the first electrode 109a of the first thin film transistor Tr0 and the read word line RWL may be manufactured synchronously.

[0161] In this embodiment of the present application, for the first thin film transistor Tr0, the second electrode 108a may be the source (S) 103 and the first electrode 109a may be the drain (D) 104; or the second electrode 108a may be the drain 104 and the first electrode 109a may be the source 103. For the second thin film transistor Tr1, the second electrode 108b may be the source 103 and the first electrode 109b may be the drain 104; or the second electrode 108b may be the drain 104 and the first electrode 109b may be the source 103.

[0162] In addition, both the first thin film transistor Tr0 and the second thin film transistor Tr1 may be N-type transistors or P-type transistors. Of course, one of the first thin film transistor Tr0 and the second thin film transistor Tr1 may be an N-type transistor and the other may be a P-type transistor.

[0163] In some embodiments, the multiple first thin film transistors Tr0 included in each layer of the memory array 201 may be fabricated synchronously, and / or the multiple second thin film transistors Tr1 included in each layer of the memory array 201 may be fabricated synchronously.

[0164] Referring to FIG. 5, the following describes the write operation process and the read operation process of the memory 200 by using one memory cell 201A as an example.

[0165] Write operation process: In the write operation process, the voltages on the read word line RWL and the read bit line RBL are 0, and the first thin film transistor Tr0 does not operate. The write word line WWL provides a first switch signal, and the first switch signal controls the second thin film transistor Tr1 to be turned on. When the first logic information is written, and the first logic information is, for example, "0", the write bit line WBL provides a first level signal, and the first level signal is written to the node N by using the second thin film transistor Tr1, and the first level signal can be controlled to turn on the first thin film transistor Tr0. When the second logic information is written, and the second logic information is, for example, "1", the write bit line WBL provides a second level signal, and the second level signal is written to the node N by using the second thin film transistor Tr1. Here, the second level signal can be controlled to turn off the first thin film transistor Tr0.

[0166] It should be understood that after the write operation is completed, the voltages on the read word line RWL and the read bit line RBL are 0, and the first thin film transistor Tr0 does not operate. The write word line WWL provides a second switch signal, which controls the second thin film transistor Tr1 to be turned off. In this case, the potential stored by the node N is not affected by the external environment.

[0167] Read operation process: the write word line WWL provides a second switch signal, the second switch signal controls the second thin film transistor Tr1 to be turned off, the read word line RWL provides a third level signal, and the logic information stored in the memory cell 201A is determined based on the current on the read bit line RBL. When the node N stores a first level signal, the first level signal can control the first thin film transistor Tr0 to be turned on, so that when the read word line RWL provides a third level signal, the read word line RWL charges the read bit line RBL by using the first thin film transistor Tr0, and the voltage of the read bit line RBL rises. In this way, when it is detected that the current on the read bit line RBL is relatively large, the logic information "0" stored in the memory cell 201A can be read out. When the node N stores a second level signal, the second level signal can control the first thin film transistor Tr0 to be turned off, so that when the read word line RWL provides a third level signal, the read word line RWL does not use the first thin film transistor Tr0 to charge the read bit line RBL, and the read bit line RBL maintains a voltage of 0V. In this way, when it is detected that the current on the read bit line RBL is relatively small, the logical information "1" stored in the memory cell 201A can be read out.

[0168] For the plurality of second thin film transistors Tr1, in some embodiments, referring to Figures 5, 6a and 6b, the gates 106b of the second thin film transistors Tr1 in the plurality of memory cells 201A arranged sequentially in each layer of the memory array 201 along the first direction X are electrically connected to the same write word line WWL. Referring to Figures 5, 6a and 6c, the second electrodes 108b of the second thin film transistors Tr1 in the plurality of memory cells 201A arranged sequentially in each layer of the memory array 201A along the second direction Y are electrically connected to the same write bit line WBL. Here, the first direction X intersects with the second direction Y.

[0169] In some examples, the first direction X and the second direction Y are orthogonal. For ease of description, the following uses an example in which the first direction X is the row direction and the second direction Y is the column direction.

[0170] In each layer of the storage array 201, the gates 106b of the second thin film transistors Tr1 in the plurality of storage cells 201A arranged sequentially along the first direction X are electrically connected to the same write word line WWL, and the second electrodes 108b of the second thin film transistors Tr1 in the plurality of storage cells 201A arranged sequentially along the second direction Y are electrically connected to the same write bit line WBL. Thus, in a write operation process, a first switch signal may be provided row by row to the plurality of write word lines WWL, thereby turning on the plurality of rows of the second thin film transistors Tr1 row by row. When the first switch signal is provided to the write word line WWL of the current row, logical information is simultaneously written into the plurality of storage cells 201A electrically connected to the write word line WWL of the current row by using the plurality of write bit lines WBL. Thus, logical information is written into the storage cells 201A row by row, thereby realizing rapid writing of the plurality of storage cells 201A in the storage array 201.

[0171] For example, the multiple first thin film transistors Tr0 can be connected in the following four ways.

[0172] When the first electrode 109a of the first thin film transistor Tr0 is electrically connected to the read bit line RBL and the second electrode 108a is electrically connected to the read word line RWL, the following first or second aspect may be used.

[0173] First embodiment: referring to Figures 5, 6a and 6b, the second electrodes 108a of the first thin film transistors Tr0 in the plurality of memory cells 201A arranged sequentially in each layer of the memory array 201 along the first direction X are electrically connected to the same read word line RWL; referring to Figures 5, 6a and 6c, the first electrodes 109a of the first thin film transistors Tr in the plurality of memory cells 201A arranged sequentially in each layer of the memory array 201 along the second direction Y are electrically connected to the same read bit line RBL. Here, the first direction X crosses the second direction Y.

[0174] In each layer of the storage array 201, the second electrodes 108a of the first thin film transistors Tr0 in the plurality of storage cells 201A arranged sequentially along the first direction X are electrically connected to the same read word line RWL, and the first electrodes 109a of the first thin film transistors Tr0 in the plurality of storage cells 201A arranged sequentially along the second direction Y are electrically connected to the same read bit line RBL. Thus, in the read operation process, a third level signal may be provided to the plurality of read word lines RWL row by row. When the third level signal is provided to the read word line RWL of the current row, the current on each read bit line RBL is detected. In this way, the logical information stored in the plurality of storage cells 201A electrically connected to the read word line RWL of the current row can be read simultaneously. Thereby, the logical information stored in the storage cells 201A can be read row by row, thereby implementing a rapid read of the plurality of storage cells 201A in the storage array 201.

[0175] Second aspect: the second electrodes 108a of the first thin film transistors Tr0 of the memory cells 201A arranged in each layer of the memory array 201 sequentially along the second direction Y are electrically connected to the same read word line RWL, and the first electrodes 109a of the first thin film transistors Tr0 of the memory cells 201A arranged in each layer of the memory array 201 sequentially along the first direction X are electrically connected to the same read bit line RBL. Here, the first direction X intersects with the second direction Y.

[0176] When the first electrode 109a of the first thin film transistor Tr0 is electrically connected to the read word line RWL and the second electrode 108a is electrically connected to the read bit line RBL, the following third or fourth aspect may be used.

[0177] Third aspect: the second electrodes 108a of the first thin film transistors Tr0 in the plurality of memory cells 201A arranged sequentially in each layer of the memory array 201 along the first direction X are electrically connected to the same read bit line RWL; the first electrodes 109a of the first thin film transistors Tr0 in the plurality of memory cells 201A arranged sequentially in each layer of the memory array 201 along the second direction Y are electrically connected to the same read word line RWL. Here, the first direction X crosses the second direction Y.

[0178] Fourth aspect: the second electrodes 108a of the first thin film transistors Tr0 in the plurality of memory cells 201A arranged sequentially in each layer of the memory array 201 along the second direction Y are electrically connected to the same read bit line RWL; the first electrodes 109a of the first thin film transistors Tr0 in the plurality of memory cells 201A arranged sequentially in each layer of the memory array 201 along the first direction X are electrically connected to the same read word line RWL. Here, the first direction X intersects with the second direction Y.

[0179] It should be noted that the second, third and fourth aspects have the same technical effects as the first aspect. For details, please refer to the above description of the technical effects of the first aspect. The details will not be described again here.

[0180] Based on the above description, for each layer of the storage array 201, the amount of storage cells 201A along the first direction X and / or the second direction Y may be increased to implement a larger storage array.

[0181] 7, in some embodiments, memory 200 further includes an integrated circuit 203, and storage array 201 is disposed on integrated circuit 203. In this case, memory 200 is an on-chip memory. In this case, the substrate within memory 200 is integrated circuit 203.

[0182] The substrate of the integrated circuit 203 may be a silicon substrate, ie, the integrated circuit 203 may be an integrated circuit on a silicon substrate.

[0183] Additionally, integrated circuit 203 may be control circuitry for storage array 201 or other functional circuitry.

[0184] It should be noted that because the process temperature for fabricating thin film transistors is relatively low, the storage array 201 can be integrated into the back-end line of the integrated circuit 203. In addition, stacking of multiple layers of the storage array 201 may be implemented on the integrated circuit 203 to implement 3D system integration.

[0185] In some examples, storage cells 201A in storage array 201 may be electrically connected to integrated circuits 203. For example, storage cells 201A in storage array 201 may be connected to lower integrated circuits 203 by using interconnect lines.

[0186] The embodiment of the present application further provides a thin film transistor 10. This thin film transistor may be used as the above-mentioned first thin film transistor Tr0, or may be used as the above-mentioned second thin film transistor Tr1.

[0187] The structure of the thin film transistor 10 will now be described in detail.

[0188] 8a, 8b, and 8c, the thin film transistor 10 includes a gate 106, a first electrode 109, a second electrode 108, a first dielectric layer 113, a second dielectric layer 112, and a semiconductor layer 102.

[0189] The gate 106 includes a gate base 1061 located at the top and a gate body 1062 extending from the gate base 1061 to the bottom. The first electrode 109 is located at the bottom. The second electrode 108 is located between the first electrode 109 and the gate base 1061. The first dielectric layer 113 is disposed between the second electrode 108 and the first electrode 109, and the first dielectric layer 113 is configured to separate the first electrode 109 from the second electrode 108. The second dielectric layer 112 covers the surface of the gate base 1061 and the surface of the gate body 1062. The semiconductor layer 102 is disposed along the side of the gate body 1062, and the second dielectric layer 112 separates the semiconductor layer 102 from the gate 106. The first electrode 109 and the second electrode 108 are each electrically connected to the semiconductor layer 102.

[0190] FIG. 8b is a schematic cross-sectional view taken along the direction BB in FIG. 8a, and FIG. 8c is another schematic cross-sectional view taken along the direction BB in FIG. 8a.

[0191] 8a and 8b, the second dielectric layer 112 surrounds the outside of the gate body 1062 on the first electrode 109, the semiconductor layer 102 surrounds the outside of the second dielectric layer 112, and the second electrode 108 is disposed outside the semiconductor layer 102 and electrically connected to the semiconductor layer 102. The second electrode 108 is on the first electrode 109 and is separated by the first dielectric layer 113, and the first electrode 109 is electrically connected to the semiconductor layer 102.

[0192] The gate body 1062 has a surface in contact with the gate base 1061, a surface remote from the gate base 1061, and a side surface. The surface in contact with the gate base 1061 and the surface remote from the gate base 1061 are disposed opposite to each other.

[0193] In some embodiments, the gate body 1062 and the gate base 1061 are integrally formed. In some other embodiments, the gate body 1062 and the gate base 1061 are manufactured separately.

[0194] In some examples, the gate body 1062 is disposed perpendicular to the gate base 1061.

[0195] The first electrode 109 forms an ohmic contact with the semiconductor layer 102, and the second electrode 108 forms an ohmic contact with the semiconductor layer 102. The first electrode 109 being electrically connected to the semiconductor layer 102 may mean that the first electrode 109 is in direct contact with the semiconductor layer 102, or that the first electrode 109 is not in direct contact with the semiconductor layer 102 but is electrically connected to the semiconductor layer 102 using another medium. Similarly, the second electrode 108 being electrically connected to the semiconductor layer 102 may mean that the second electrode 108 is in direct contact with the semiconductor layer 102, or that the second electrode 108 is not in direct contact with the semiconductor layer 102 but is electrically connected to the semiconductor layer 102 using another medium.

[0196] In addition, the first electrode 109 of the thin film transistor 10 may be the drain and the second electrode 108 may be the source; or the first electrode 109 of the thin film transistor 10 may be the source and the second electrode 108 may be the drain.

[0197] Moreover, the thin film transistor 10 may be an N-type transistor or a P-type transistor.

[0198] In addition, the second dielectric layer 112 covers the surface of the gate base 1061 and the surface of the gate body 1062, so that, as shown in FIG. 8a, the second dielectric layer 112 includes a first dielectric portion 1121 and a second dielectric portion 1122, where the first dielectric portion 1121 covers the surface of the gate base 1061 and the second dielectric portion 1122 covers the surface of the gate body 1062.

[0199] Based on this, in some embodiments, the first dielectric portion 1121 and the second dielectric portion 1122 are manufactured synchronously. In some other embodiments, the first dielectric portion 1121 and the second dielectric portion 1122 may be manufactured separately.

[0200] If the distance between the first electrode 109 and the second electrode 108 is too short, there is a risk that the first electrode 109 and the second electrode 108 may be directly conductive with each other during manufacturing of the first electrode 109 and the second electrode 108. To avoid direct conduction between the first electrode 109 and the second electrode 108, in some embodiments, the second electrode 108 is disposed close to the gate base 1061.

[0201] It should be understood that the materials of the gate 106, the first electrode 109, and the second electrode 108 are all conductive materials, for example, metallic materials. Specifically, the materials of the gate 106, the first electrode 109, and the second electrode 108 may be one or more of conductive materials such as TiN (titanium nitride), Ti (titanium), Au (gold), W (tungsten), Mo (molybdenum), In-Ti-O (ITO, indium tin oxide), Al (aluminum), Cu (copper), Ru (ruthenium), Ag (silver), etc.

[0202] For the materials of the first dielectric layer 113 and the second dielectric layer 112, please refer to the materials of the sixth dielectric layer 202. Details will not be described again here. In addition, the first dielectric layer 113 and the second dielectric layer 112 may each be a single-layer structure or a multi-layer laminate structure.

[0203] The material of the semiconductor layer 102 may be one or more of semiconductor materials such as Si (silicon), poly-Si (p-Si, polysilicon), amorphous-Si (a-Si, amorphous silicon), In-Ga-Zn-O (IGZO, indium gallium zinc oxide) polycompound, ZnO (zinc oxide), ITO, TiO2 (titanium dioxide), and MoS2 (molybdenum disulfide).

[0204] An embodiment of the present invention provides a thin film transistor 10. The gate 106 of the thin film transistor 10 includes a gate base 1061 located at the top and a gate body 1062 extending from the gate base 1061 to the bottom. The semiconductor layer 102 is disposed along the side of the gate body 1062, the first electrode 109 is located at the bottom, and the second electrode 108 is located between the first electrode 109 and the gate base 1061, and the first electrode 109 and the second electrode 108 are each electrically connected to the semiconductor layer 102. In the prior art, the semiconductor layer 102 is disposed along a plane parallel to the gate 106 (the gate 106 in the prior art is equivalent to the gate base 1061 in this embodiment of the present application), and the second electrode 108 and the first electrode 109 are disposed in the same layer, so that the size of the thin film transistor 10 provided in this embodiment of the present application is relatively small in the plane parallel to the gate base 1061. Therefore, in this embodiment of the present application, the size of the thin film transistor 10 is reduced and the area utilization rate is improved. In addition, since the second electrode 108 and the first electrode 109 of the thin film transistor 10 in this embodiment of the present application are located in different layers, it is possible to avoid short circuit occurring during routing of the signal line electrically connected to the second electrode 108 and the signal line electrically connected to the first electrode 109, thereby reducing the process difficulty.

[0205] When the structure of the first thin film transistor Tr0 and the second thin film transistor Tr1 in the memory 200 is the above-mentioned thin film transistor 10, the size of the first thin film transistor Tr0 and the second thin film transistor Tr1 in the memory 200 can be reduced, and the area utilization rate can be improved.

[0206] Regarding the structure of the gate 106, the following three implementations can be used as examples.

[0207] First implementation: As shown in Figures 8a, 9, 10, and 11, the boundary of the projection of the gate body 1062 onto the gate base 1061 is located within the boundary of the gate base 1061, i.e., the gate body 1062 is located in the middle region of the gate base 1061.

[0208] Second implementation: As shown in Figures 12a and 12c, the boundary of the projection of the gate body 1062 onto the gate base 1061 partially overlaps with the boundary of the gate base 1061, i.e., the gate body 1062 is located in the edge region of the gate base 1061.

[0209] Third implementation: As shown in FIG. 12b, the gate body 1062 is a hollow structure, and the outer boundary of the projection of the gate body 1062 on the gate base 11061 overlaps with the boundary of the gate base 1061.

[0210] It should be understood that because the gate body 1062 is a hollow structure, the projection of the gate body 1062 onto the gate base 1061 includes two boundaries: an outer boundary and an inner boundary. The boundary closer to the center of the gate base 1061 is referred to as the inner boundary, and the boundary away from the center of the gate base 10161 is referred to as the outer boundary.

[0211] In addition, since the gate body 1062 is a hollow structure and the outer boundary of the projection of the gate body 1062 on the gate base 1061 overlaps with the boundary of the gate base 11061, at least a portion of the area of ​​the second dielectric layer 112 is located within the hollow structure, at least a portion of the area of ​​the semiconductor layer 102 is located within the hollow structure, the second electrode 108 is located within the hollow structure, and at least a portion of the area of ​​the first dielectric layer 113 is located within the hollow structure.

[0212] When the gate body 1062 is a hollow structure, the gate 106 regulates and controls the current in the semiconductor layer 102 from outside the semiconductor layer 102 .

[0213] For the structure of the semiconductor layer 102, the following four implementations can be used as examples.

[0214] First implementation: As shown in FIG. 8a, the semiconductor layer 102 is disposed only along the sides of the gate body 1062.

[0215] As shown in FIG. 8 a , the semiconductor layer 102 surrounds only the sides of the gate body 1062 and is disposed on the first electrode 109 .

[0216] The second electrode 108 and the first electrode 109 are in electrical connection or edge contact with the semiconductor layer 102 .

[0217] Second implementation: As shown in Fig. 12c, the semiconductor layer 102 is disposed along the side of the gate body 1062, and the semiconductor layer 102 further includes an extension portion that extends along the surface of the gate base 1061. The second dielectric layer 112 separates the semiconductor layer 102 from the gate 106. Also, as shown in Fig. 12c, the semiconductor layer 102 is disposed on the side of the first dielectric layer 113 and the side of the second electrode 108, and covers the top surface of the second electrode 108.

[0218] In some examples, the semiconductor layer 102 is further disposed on a side of the first electrode 109, as shown in FIG. 12c.

[0219] Third implementation: As shown in FIG. 9, the semiconductor layer 102 is disposed along the side of the gate body 1062, and the semiconductor layer 102 extends from the side of the gate body 1062 to the side of the gate body 1062 away from the gate base 1061, i.e., between the gate body 1062 and the first electrode 109. That is, the semiconductor layer 102 further includes an extension portion that is located between the gate body 1062 and the first electrode 109. Also, as shown in FIG. 9, the semiconductor layer 102 covers the side and bottom surfaces of the second dielectric layer 112.

[0220] In some examples, the semiconductor layer 102 is disposed on a first electrode 109, as shown in FIG.

[0221] Fourth implementation: As shown in FIG. 10, FIG. 11, FIG. 12a and FIG. 12b, the semiconductor layer 102 is disposed along the side of the gate body 1062, and the semiconductor layer 102 further includes an extension portion extending along the surface of the gate base 1061 and an extension portion located between the gate body 1062 and the first electrode 109. In this case, the semiconductor layer 102 is "Z" shaped. In other words, as shown in FIG. 10, FIG. 12a and FIG. 12b, the semiconductor layer 102 covers the side, bottom and top surfaces of the second dielectric layer 112. Alternatively, as shown in FIG. 11, the semiconductor layer 102 covers the side and bottom surfaces of the second dielectric layer 112, and further covers the bottom surface of the second electrode 108.

[0222] In some examples, as shown in Figures 10, 11, 12a, and 12b, the semiconductor layer 102 is disposed on a first electrode 109.

[0223] 8b, the semiconductor layer 102 is disposed around the entire side of the gate body 1062. In this case, the semiconductor layer 102 may surround the entire side of the gate body 1062, or the semiconductor layer 102 may surround only a portion of the side of the gate body 1062.

[0224] Since the semiconductor layer 102 is disposed over the entire side surface of the gate body 1062, the area of ​​the semiconductor layer 102 can be increased, and carrier mobility can be improved.

[0225] Regarding the second electrode 108, in some embodiments, the second electrode 108 is disposed on the side of the semiconductor layer 102 away from the second dielectric layer 112, as shown in Figures 8a, 9, 10, 12a, and 12b.

[0226] It should be understood that when the semiconductor layer 102 further includes an extension portion extending along the surface of the gate base 1061, when the second electrode 108 is disposed on the side of the semiconductor layer 102 away from the second dielectric layer 112, as shown in Figures 10, 12a, and 12b, the second electrode 108 does not contact the second dielectric layer 112, and the second electrode 108 and the second dielectric layer 112 are separated by the semiconductor layer 102. When the semiconductor layer 102 is disposed along the side of the gate body 1062 and the semiconductor layer 102 does not include an extension portion extending along the surface of the gate base 1061, when the second electrode 108 is disposed on the side of the semiconductor layer 102 away from the second dielectric layer 112, as shown in Figures 8a and 9, the second electrode 108 contacts the second dielectric layer 112.

[0227] 11, the second electrode 108 may be disposed on a side of the semiconductor layer 102 closer to the second dielectric layer 112. In this case, the second electrode 108 is located between the second dielectric layer 112 and the semiconductor layer 102.

[0228] Additionally, the second electrode 108 may be disposed around the entire side of the gate body 1062, or the second electrode 108 may be disposed around but not around the entire side of the gate body 1062.

[0229] Regarding the first electrode 109, the first electrode 109 is located at the bottom, i.e., the first electrode 109 is disposed on the side of the second electrode 108 that is remote from the gate base 1061. In some embodiments, as shown in Figures 8a, 9, 10, 11, 12a, and 12b, the first electrode 109 is disposed on the side of the gate body 1062 that is remote from the gate base 1061. In this case, the semiconductor layer 102 is disposed on the first electrode 109. In some other embodiments, as shown in Figure 12c, the first electrode 109 is disposed on the side of the gate body 1062. In this case, the semiconductor layer 102 also extends along the side of the first electrode 109.

[0230] In some embodiments, as shown in FIG. 13, the thin film transistor 10 further includes a fourth dielectric layer 114 disposed between the second electrode 108 and the semiconductor layer 102, and / or a fifth dielectric layer 115 disposed between the first electrode 109 and the semiconductor layer 102.

[0231] For the material of the fourth dielectric layer 114 and the material of the fifth dielectric layer 115, please refer to the material of the sixth dielectric layer 202. Details will not be described again here. In addition, the fourth dielectric layer 114 and the fifth dielectric layer 115 may be a single-layer structure or a multi-layer laminate structure.

[0232] It should be noted that the fourth dielectric layer 114 is disposed between the second electrode 108 and the semiconducting layer 102, which may or may not be in contact with the semiconducting layer 102. The fifth dielectric layer 115 is disposed between the first electrode 109 and the semiconducting layer 102, which may or may not be in contact with the semiconducting layer 102.

[0233] To ensure electrical continuity between the first electrode 109 and the second electrode 108 using the semiconductor layer 102 when a voltage is applied to the gate 106, in some embodiments, the thicknesses of both the fourth dielectric layer 114 and the fifth dielectric layer 115 are in the range of 0.1 nm to 2 nm.

[0234] For example, the thicknesses of the fourth dielectric layer 114 and the fifth dielectric layer 115 may be 0.1 nm, 0.5 nm, 1 nm, 1.5 nm and 2 nm.

[0235] Because the thickness of the fourth dielectric layer 114 and the fifth dielectric layer 115 is relatively small, ranging from 0.1 nm to 2 nm, even if the fourth dielectric layer 114 is disposed between the second electrode 108 and the semiconductor layer 102 and / or the fifth dielectric layer 115 is disposed between the first electrode 109 and the semiconductor layer 102, when a voltage is applied to the gate 106, the first electrode 109 and the second electrode 108 can still be conductive by using the semiconductor layer 102, and the performance of the thin film transistor 10 is not affected. In addition, the fourth dielectric layer 114 is disposed between the second electrode 108 and the semiconductor layer 102 so as to avoid the problem of diffusion of the second electrode 108 in the contact area with the semiconductor layer 102 and reduce the Fermi level pinning problem of the contact between the second electrode 108 and the semiconductor layer 102. The fifth dielectric layer 115 is disposed between the first electrode 109 and the semiconductor layer 102 so as to avoid diffusion problems of the first electrode 109 in the contact area with the semiconductor layer 102 and to reduce Fermi level pinning problems of the contact between the first electrode 109 and the semiconductor layer 102.

[0236] In some embodiments, the material of the second dielectric layer 112 is a ferroelectric material. In this case, as shown in FIG. 14, the thin film transistor 10 further includes a third dielectric layer 116 disposed between the semiconductor layer 102 and the second dielectric layer 112.

[0237] For the material of the third dielectric layer 116, please refer to the material of the sixth dielectric layer 202. Details will not be described again here. In addition, the third dielectric layer 116 may be a single-layer structure or a multi-layer laminate structure.

[0238] When the material of the second dielectric layer 112 is a ferroelectric material, it can be understood that the gate 106, the second dielectric layer 112, and the third dielectric layer 116 form a composite gate structure. By using the composite gate structure, the thin film transistor 10 can achieve the performance of a negative capacitance transistor, and the gate control ability of the thin film transistor 10 can be improved by using the negative capacitance. When the thin film transistor 10 is used in the memory 200, the performance of the memory 200 can be improved.

[0239] It should be noted that in this embodiment of the present application, the materials of the first dielectric layer 113, the second dielectric layer 112, the third dielectric layer 116, the fourth dielectric layer 114, and the fifth dielectric layer 115 may be the same or different.

[0240] Based on this, when the material of the second dielectric layer 112 is a ferroelectric material and the thin film transistor 10 includes a third dielectric layer 116, as shown in FIG. 15, the thin film transistor 10 further includes a first conductive layer 117 disposed between the second dielectric layer 112 and the third dielectric layer 116.

[0241] For the material of the first conductive layer 117, please refer to the materials of the gate 106, the first electrode 109, and the second electrode 108. The details will not be described again here.

[0242] The composite gate structure including the gate 106, the second dielectric layer 112, the first conductive layer 117, and the third dielectric layer 116 can enable the thin film transistor 10 to achieve the performance of a negative capacitance transistor, and the gate control capability of the thin film transistor 10 can be improved by using the negative capacitance. When the thin film transistor 10 is used in the memory 200, the performance of the memory 200 can be improved.

[0243] In some embodiments, as shown in FIG. 16 , the thin film transistor 10 further includes a modulating gate electrode 118 disposed between the first electrode 109 and the second electrode 108, the modulating gate electrode 118 being surrounded by a first dielectric layer 113.

[0244] For the material of the modulation gate electrode 118, please refer to the materials of the gate 106, the first electrode 109, and the second electrode 108. The details will not be described again here.

[0245] It should be noted that the modulating gate electrode 118 is surrounded by the first dielectric layer 113 such that the modulating gate electrode 118 is spaced apart from the first electrode 109, the second electrode 108, and the semiconductor layer 102. That is, the modulating gate electrode 118 is electrically insulated from the first electrode 109, the second electrode 108, and the semiconductor layer 102 by using the first dielectric layer 113.

[0246] In this embodiment of the present application, the thin film transistor 10 includes the modulating gate electrode 118 , so that the threshold voltage of the thin film transistor 10 can be adjusted by using the modulating gate electrode 118 .

[0247] When the thin film transistor 10 is used as the first thin film transistor Tr0 and the second thin film transistor Tr1 of the memory 200, as shown in Figures 17a, 17b and 17c, in the memory 200, the first thin film transistor Tr0 further includes a first modulation gate electrode 118a disposed between the first electrode 109a and the second electrode 108a, the first modulation gate electrode 118a is disposed on the side of the semiconductor layer 102a away from the gate body 1062a, and the first modulation gate electrode 118a is surrounded by a first dielectric layer 113a, so that the first modulation gate electrode 118a is spaced apart from the first electrode 109a, the second electrode 108a and the semiconductor layer 102a; the first modulation gate electrodes 118a of the first thin film transistor Tr0 are electrically connected together; and / or the second thin film transistor Tr1 further includes a second modulation gate electrode 118b arranged between the first electrode 109b and the second electrode 108b, where the second modulation gate electrode 118b is arranged on a side of the semiconductor layer 102b away from the gate body 1062b, and the second modulation gate electrode 118b is surrounded by the first dielectric layer 113b, whereby the second modulation gate electrode 118b is spaced apart from the first electrode 109b, the second electrode 108b and the semiconductor layer 102b; the second modulation gate electrodes 118b of multiple second thin film transistors Tr1 located in the same layer are electrically connected together.

[0248] 17b and 17c are schematic cross-sectional views taken along the direction CC in FIG. 17a.

[0249] The first modulation gate electrodes 118a of the multiple first thin film transistors Tr located in the same layer may be electrically connected to each other. That is, all of the first modulation gate electrodes 118a of the multiple first thin film transistors Tr0 located in the same layer may be electrically connected together, or some of the first modulation gate electrodes 118a of the multiple first thin film transistors Tr0 located in the same layer may be electrically connected together. Similarly, the second modulation gate electrodes 118b of the multiple second thin film transistors Tr1 located in the same layer may be electrically connected together. That is, the second modulation gate electrodes 118b of the multiple second thin film transistors Tr1 located in the same layer may be electrically connected together, or some of the second modulation gate electrodes 118b of the multiple second thin film transistors Tr1 located in the same layer may be electrically connected together.

[0250] For example, as shown in Fig. 17b, the first modulation gate electrodes 118a of four first thin film transistors Tr0 located in the same layer are electrically connected together. In this way, the joint modulation of four memory cells 201A can be implemented.

[0251] It should be noted that in practical applications, the number of storage cells 201A that are jointly modulated can be selected as needed.

[0252] For the material of the first modulating gate electrode 118a and the material of the second modulating gate electrode 118b, please refer to the materials of the gate 106, the first electrode 109, and the second electrode 108. The details will not be described again here.

[0253] Since the first thin film transistor Tr0 includes a first modulation gate electrode 118a, the threshold voltage of the first thin film transistor Tr0 can be adjusted by using the first modulation gate electrode 118a. Since the second thin film transistor Tr1 includes a second modulation gate electrode 118b, the threshold voltage of the second thin film transistor Tr1 can be adjusted by using the second modulation gate electrode 118b. Based on this, the memory performance of the memory 200 can be adjusted more flexibly. For example, for the first thin film transistor Tr0, a relatively low potential can be set for the first modulation gate electrode 118a, thereby reducing the leakage current of the first electrode 109a and the second electrode 108a of the first thin film transistor Tr0, thereby realizing a longer storage and retention time. In addition, a relatively high potential can be set for the second modulation gate electrode 118b of the second thin film transistor Tr1, thereby increasing the overall current of the second thin film transistor Tr1, thereby improving the data read speed.

[0254] An embodiment of the present application further provides a manufacturing method for a thin film transistor 10, which can be used to manufacture the aforementioned thin film transistor 10. Referring to Figure 18, the manufacturing method for the thin film transistor 10 includes:

[0255] S10. Form a first electrode 109, a first dielectric layer 113, a second electrode 108, and a semiconductor layer 102 on a substrate. The first electrode 109, the first dielectric layer 113, and the second electrode 108 are sequentially stacked, the first dielectric layer 113 separates the first electrode 109 from the second electrode 108, the semiconductor layer 102 is formed on the side of the first dielectric layer 113, and both the first electrode 109 and the second electrode 108 are electrically connected to the semiconductor layer 102.

[0256] It should be noted that the order of forming the first electrode 109, the first dielectric layer 113, the second electrode 108, and the semiconductor layer 102 is not limited.

[0257] Both the first electrode 109 and the second electrode 108 may be in direct contact with the semiconductor layer 102, or the first electrode 109 and the second electrode 108 may each be in contact with the semiconductor layer 102 through a separate dielectric layer.

[0258] Please refer to the above embodiments for the materials of the first electrode 109, the first dielectric layer 113, the second electrode 108 and the semiconductor layer 102. The details will not be described again here.

[0259] In addition, the first dielectric layer 113 has a surface close to the second electrode 108, a surface close to the first electrode 109, and a side surface. The surface close to the second electrode 108 and the surface close to the first electrode 109 are disposed opposite to each other.

[0260] Based on this, the first electrode 109 may be formed as a drain and the second electrode 108 may be formed as a source; or the first electrode 109 may be formed as a source and the second electrode 1081 may be formed as a drain.

[0261] S11. Sequentially form a second dielectric layer 112 and a gate 106, where the gate 106 includes a gate base 1061 located at the top and a gate body 1062 extending from the gate base 1061 to the bottom, and the second dielectric layer 112 separates the gate 106 from the semiconductor layer 102, the first electrode 109, and the second electrode 108.

[0262] For the material of the second dielectric layer 112, please refer to the above embodiments, and the details will not be described again here.

[0263] In addition, for the material of the gate 106, please refer to the above embodiment, and the details will not be described again here.

[0264] The gate base 1061 and the gate body 1062 may be formed simultaneously, or the gate base 1061 and the gate body 1062 may be formed separately.

[0265] Based on the foregoing description, in this embodiment of the present application, when the thin film transistor 10 is fabricated, steps S10 and S11 may be performed sequentially, or steps S11 and S10 may be performed sequentially.

[0266] An embodiment of the present invention provides a method for manufacturing a thin film transistor 10. The method for manufacturing the thin film transistor 10 provided in this embodiment of the present application has the same technical effect as the above-mentioned thin film transistor 10, so please refer to the above description. The details will not be described again here.

[0267] The following uses an example to describe a specific implementation of the manufacturing method for the thin film transistor 10. EXAMPLES

[0268] EMBODIMENT 1 For example, the fabrication of the thin film transistor 10 shown in FIG. 8a specifically includes the following steps.

[0269] S100. As shown in FIG. 19, a first conductive thin film 1090, a first dielectric thin film 1130 and a second conductive thin film 1080 are sequentially formed on a substrate 101.

[0270] The first conductive thin film 1090, the first dielectric thin film 1130 and the second conductive thin film 1080 may be formed sequentially using methods such as chemical vapor deposition, physical vapor deposition, sputtering, electroplating, and the like.

[0271] S101. As shown in Figure 19, the first conductive thin film 1090, the first dielectric thin film 1130 and the second conductive thin film 1080 are patterned to form a first electrode 109, a first dielectric layer 113 and a second electrode 108, which are stacked sequentially. Here, the first electrode 109, the first dielectric layer 113 and the second electrode 108 form a groove structure.

[0272] The first conductive thin film 1090, the first dielectric thin film 1130 and the second conductive thin film 1080 can be patterned using dry or wet etching.

[0273] Additionally, the first conductive thin film 1090, the first dielectric thin film 1130 and the second conductive thin film 1080 may be etched separately, or the first conductive thin film 1090, the first dielectric thin film 1130 and the second conductive thin film 1080 may be etched simultaneously.

[0274] S102. Form a semiconductor layer 102, as shown in Figure 19. Here, the semiconductor layer 102 is formed on the sidewall of the trench structure, i.e., the semiconductor layer 102 is formed on the side of the first dielectric layer 113 and the side of the second electrode 108, and both the first electrode 109 and the second electrode 108 are electrically connected to the semiconductor layer 102.

[0275] First, a semiconductor thin film may be formed by using an epitaxial growth method. Here, the semiconductor thin film is a whole layer, covering the exposed surfaces of the first electrode 109, the first dielectric layer 113, and the second electrode 108; then, the semiconductor thin film is etched. Also, in addition to the semiconductor thin film formed on the sidewall of the groove, the semiconductor thin film formed on other parts such as the bottom of the groove, the top surface of the second electrode 108, and the outside of the groove is etched, thereby forming the semiconductor layer 102.

[0276] Epitaxial growth methods include, for example, chemical vapor deposition, physical vapor deposition, sputtering, electroplating, and other processes.

[0277] S103. Form a second dielectric layer 112, as shown in Figure 19. Here, the second dielectric layer 112 covers the semiconductor layer 102, the second electrode 108, and the first electrode 109.

[0278] It should be noted that step S103 can be implemented in two ways. In the first way, the second dielectric layer 112 can be directly formed by using methods such as chemical vapor deposition, physical vapor deposition, sputtering, or electroplating. In this case, the second dielectric layer 112 is a whole layer and covers the exposed surfaces of the semiconductor layer 102, the second electrode 108, the first electrode 109, and the first dielectric layer 113. In the second way, the seventh dielectric thin film may be formed first by using chemical vapor deposition, physical vapor deposition, sputtering, or electroplating, where the seventh dielectric thin film covers the exposed surfaces of the semiconductor layer 102, the second electrode 108, the first electrode 109, and the first dielectric layer 113; then, the seventh dielectric thin film is etched. In addition to the portions formed on the side and bottom of the groove, the top surface of the second electrode 108, and the top surface of the semiconductor layer 102, the other seventh dielectric thin film is all etched, thereby forming the second dielectric layer 112. The first embodiment is not shown in the accompanying drawings.

[0279] S104. Form the gate 106, as shown in Fig. 19. Here, the gate 106 includes a gate base 1061 and a gate body 1062 extending from the gate base 1061, the gate body 1062 extending into the trench structure, i.e., the gate body 1062 extends along the side of the first dielectric layer 113 and the side of the second electrode 108, the gate base 1061 is formed on the side of the gate body 1062 away from the first electrode 109, and the second dielectric layer 112 separates the gate 106 from the semiconductor layer 102, the first electrode 109, and the second electrode 108.

[0280] The process of forming the gate 106 may specifically be to first form a conductive thin film, and then etch the conductive thin film to form the gate 106 . EXAMPLES

[0281] EMBODIMENT 2 For example, the manufacturing method of the thin film transistor 10 shown in FIG.

[0282] S110. As shown in FIG. 20, a first conductive thin film 1090, a first dielectric thin film 1130 and a second conductive thin film 1080 are sequentially formed on a substrate 101.

[0283] For the specific implementation process of step S110, please refer to the above step S100, and the details will not be described again here.

[0284] S111. As shown in FIG. 20, pattern the first conductive thin film 1090, the first dielectric thin film 1130 and the second conductive thin film 1080 to form a first electrode 109, a first dielectric layer 113 and a second electrode 108 which are stacked sequentially, and the first electrode 109, the first dielectric layer 113 and the second electrode 108 form a groove structure.

[0285] For the specific implementation process of step S111, please refer to the above step S101, and the details will not be described again here.

[0286] S112. As shown in Fig. 20, the semiconductor layer 102 is formed. Here, the semiconductor layer 102 is formed on the sidewall and bottom of the groove structure, i.e., the semiconductor layer 102 is formed on the side of the first dielectric layer 113 and the side of the second electrode 108, and the semiconductor layer 102 further extends from the side of the first dielectric layer 113 and the side of the second electrode 108 to the surface of the first electrode 109 closer to the second electrode 108, i.e., the top surface of the first electrode 109, and both the first electrode 109 and the second electrode 108 are electrically connected to the semiconductor layer 102.

[0287] First, a semiconductor thin film may be formed by using an epitaxial growth method. Here, the semiconductor thin film is a whole layer, covering the exposed surfaces of the first electrode 109, the first dielectric layer 113, and the second electrode 108; then, the semiconductor thin film is etched. In addition to the semiconductor thin film formed on the sidewall and bottom of the groove, the semiconductor thin film formed on other parts, such as the top surface of the second electrode 108 and the outside of the groove, is etched, thereby forming the semiconductor layer 102.

[0288] S113. As shown in Figure 20, a second dielectric layer 112 is formed, where the second dielectric layer 112 covers the semiconductor layer 102 and the second electrode 108.

[0289] For the specific implementation process of step S113, please refer to the above step S103, and the details will not be described again here.

[0290] S114. Form the gate 106, as shown in Figure 20. Here, the gate 106 includes a gate base 1061 and a gate body 1062 extending from the gate base 1061, the gate body 1062 extending into the trench structure, i.e., the gate body 1062 extends along the side of the first dielectric layer 113 and the side of the second electrode 108, the gate base 1061 is formed on the side of the gate body 1062 away from the first electrode 109, and the second dielectric layer 112 separates the gate 106 from the semiconductor layer 102, the first electrode 109, and the second electrode 108.

[0291] For the specific implementation process of step S114, please refer to the above step S104, and the details will not be described again here. EXAMPLES

[0292] EMBODIMENT 3 For example, the fabrication of the thin film transistor 10 shown in FIG.

[0293] S120. As shown in FIG. 21, a first conductive thin film 1090, a first dielectric thin film 1130 and a second conductive thin film 1080 are sequentially formed on a substrate 101.

[0294] For the specific implementation process of step S120, please refer to the above step S100, and the details will not be described again here.

[0295] S121. As shown in FIG. 21, pattern the first conductive thin film 1090, the first dielectric thin film 1130 and the second conductive thin film 1080 to form a first electrode 109, a first dielectric layer 113 and a second electrode 108 which are stacked sequentially, and the first electrode 109, the first dielectric layer 113 and the second electrode 108 form a groove structure.

[0296] For the specific implementation process of step S121, please refer to the above step S101, and the details will not be described again here.

[0297] S122. As shown in FIG. 21, a semiconductor layer 102 is formed, where the semiconductor layer 102 is formed on the sidewalls and bottom of the groove structure and the surface of the second electrode 108 away from the first electrode 109, i.e., the semiconductor layer 102 is formed on the side of the first dielectric layer 113 and the side of the second electrode 108, the semiconductor layer 102 further extends from the side of the first dielectric layer 113 and the side of the second electrode 108 to the surface of the second electrode 108 away from the first electrode 109 (i.e., the top surface of the second electrode 108) and the surface of the first electrode 109 close to the second electrode 108 (i.e., the top surface of the first electrode 109), and both the first electrode 109 and the second electrode 108 are electrically connected to the semiconductor layer 102.

[0298] First, a semiconductor thin film may be formed by using an epitaxial growth method. Here, the semiconductor thin film is an entire layer and covers the exposed surfaces of the first electrode 109, the first dielectric layer 113, and the second electrode 108; then, the semiconductor thin film is etched. In addition to the semiconductor thin film formed on the sidewalls and bottom of the groove and the top surface of the second electrode 108, the semiconductor thin film formed outside the groove is etched, thereby forming the semiconductor layer 102.

[0299] S123. As shown in FIG. 21, a second dielectric layer 112 is formed, and the second dielectric layer 112 covers the semiconductor layer 102.

[0300] For the specific implementation process of step S123, please refer to the above step S103, and the details will not be described again here.

[0301] S124. Form the gate 106, as shown in Fig. 21. Here, the gate 106 includes a gate base 1061 and a gate body 1062 extending from the gate base 1061, the gate body 1062 extending into the trench structure, i.e., the gate body 1062 extends along the side of the first dielectric layer 113 and the side of the second electrode 108, the gate base 1061 is formed on the side of the gate body 1062 away from the first electrode 109, and the second dielectric layer 112 separates the gate 106 from the semiconductor layer 102, the first electrode 109, and the second electrode 108.

[0302] For the specific implementation process of step S124, please refer to the above step S104, and the details will not be described again here.

[0303] It should be noted that the difference between the first, second and third embodiments lies in the structure of the semiconductor layer 102 that is formed. EXAMPLES

[0304] EMBODIMENT 4 For example, the manufacturing method of the thin film transistor 10 shown in FIG.

[0305] S130. As shown in FIG. 22, a first conductive thin film 1090, a first dielectric thin film 1130 and a second conductive thin film 1080 are sequentially formed on a substrate 101.

[0306] For the specific implementation process of step S130, please refer to the above step S100, and the details will not be described again here.

[0307] S131. As shown in FIG. 22, pattern the first conductive thin film 1090, the first dielectric thin film 1130 and the second conductive thin film 1080 to form a first electrode 109, a first dielectric layer 113 and a second electrode 108 which are sequentially stacked, where the first electrode 109, the first dielectric layer 113 and the second electrode 108 form a groove structure.

[0308] For the specific implementation process of step S131, please refer to the above step S101, and the details will not be described again here.

[0309] S132. As shown in Fig. 22, a fifth dielectric layer 115 is formed at the bottom of the groove structure, i.e., the fifth dielectric layer 115 is formed on the top surface of the first electrode 109, where the fifth dielectric layer 115 is in contact with the first electrode 109.

[0310] The process of forming the fifth dielectric layer 115 may specifically be: first forming a fifth dielectric thin film, and then etching the fifth dielectric thin film to form the fifth dielectric layer 115.

[0311] 22, a fourth dielectric layer 114 is formed on the side of the second electrode 108 away from the first electrode 109. That is, the fourth dielectric layer 114 is formed on the top surface of the second electrode 108. Here, the fourth dielectric layer 114 is in contact with the second electrode 108.

[0312] The process of forming the fourth dielectric layer 114 may specifically be to first form a sixth dielectric thin film, and then etch the sixth dielectric thin film to form the fourth dielectric layer 114.

[0313] It should be noted that step S132 and step S133 may be performed step by step. In this case, step S132 may be performed first and then step S133, or step S133 may be performed first and then step S132. Steps S132 and S133 may alternatively be performed synchronously. That is, the fourth dielectric layer 114 and the fifth dielectric layer 115 are formed simultaneously.

[0314] S134. As shown in Fig. 22, the semiconductor layer 102 is formed. Here, the semiconductor layer 102 is formed on the sidewalls and bottom of the groove structure and on the surface of the fourth dielectric layer 114 away from the second electrode 108, that is, the semiconductor layer 102 is formed on the side of the first dielectric layer 113, the side of the second electrode 108, and the side of the fourth dielectric layer 114, and the semiconductor layer 102 is formed on the side of the first dielectric layer 113, the side of the second electrode 108, and the side of the fourth dielectric layer 114 from the side of the first dielectric layer 113, the side of the second electrode 108, and the side of the fourth dielectric layer 114. The semiconductor layer 102 further extends to a surface of the fourth dielectric layer 114 away from the second electrode 108 (i.e., the top surface of the fourth dielectric layer 114) and a surface of the fifth dielectric layer 115 away from the first electrode 109 (i.e., the top surface of the fifth dielectric layer 115), the semiconductor layer 102 contacts both the fourth dielectric layer 114 and the fifth dielectric layer 115, and both the first electrode 109 and the second electrode 108 are electrically connected to the semiconductor layer 102.

[0315] First, a semiconductor thin film may be formed by using an epitaxial growth method, the semiconductor thin film is the whole layer, covering the exposed surfaces of the fourth dielectric layer 114, the fifth dielectric layer 115, the first electrode 109, the first dielectric layer 113, and the second electrode 108; then, the semiconductor thin film is etched. In addition to the semiconductor thin film formed on the sidewall and bottom of the groove and the top surface of the fourth dielectric layer 114, the semiconductor thin film formed outside the groove is etched to form the semiconductor layer 102.

[0316] S135. Form a second dielectric layer 112, as shown in Figure 22. Here, the second dielectric layer 112 covers the semiconductor layer 102.

[0317] For the specific implementation process of step S135, please refer to step S103 above, and the details will not be described again here.

[0318] S136. Form the gate 106, as shown in Fig. 22, where the gate 106 includes a gate base 1061 and a gate body 1062 extending from the gate base 1061, the gate body 1062 extending into the trench structure, i.e., the gate body 1062 extends along the side of the first dielectric layer 113, the side of the second electrode 108, and the side of the fourth dielectric layer 114, the gate base 1061 is formed on the side of the gate body 1062 away from the first electrode 109, and the second dielectric layer 112 separates the gate 106 from the semiconductor layer 102, the first electrode 109, and the second electrode 108.

[0319] For the specific implementation process of step S136, please refer to the above step S104, and the details will not be described again here.

[0320] In comparison with the third embodiment, the fourth embodiment adds steps S132 and S133.

[0321] In embodiment 4, both step S132 and step S133 are performed. In some embodiments, one of step S132 and step S133 may be alternatively performed.

[0322] In addition, in the fourth embodiment, the structure of the semiconductor layer 102 formed in step S134 is the same as the structure of the semiconductor layer 102 formed in the third embodiment. In some embodiments, the structure of the semiconductor layer 102 formed in step S134 may also be the same as the configuration of the semiconductor layer 102 formed in the first or second embodiment. EXAMPLES

[0323] EMBODIMENT 5 For example, the manufacturing method of the thin film transistor 10 shown in FIG.

[0324] S140. As shown in FIG. 23, a first conductive thin film 1090, a first dielectric thin film 1130 and a second conductive thin film 1080 are sequentially formed on a substrate 101.

[0325] For the specific implementation process of step S140, please refer to the above step S100, and the details will not be described again here.

[0326] S141. As shown in FIG. 23, pattern the first conductive thin film 1090, the first dielectric thin film 1130 and the second conductive thin film 1080 to form a first electrode 109, a first dielectric layer 113 and a second electrode 108 which are stacked sequentially, and the first electrode 109, the first dielectric layer 113 and the second electrode 108 form a groove structure.

[0327] For the specific implementation process of step S141, please refer to step S101 above, and the details will not be described again here.

[0328] S142. As shown in FIG. 23, a semiconductor layer 102 is formed, the semiconductor layer 102 is formed on the sidewalls and bottom of the trench structure, i.e., the semiconductor layer 102 is formed on the side of the first dielectric layer 113 and the side of the second electrode 108, the semiconductor layer 102 further extends from the side of the first dielectric layer 113 and the side of the second electrode 108 to the surface of the first electrode 109 closer to the second electrode 108, i.e., the top surface of the first electrode 109, and both the first electrode 109 and the second electrode 108 are electrically connected to the semiconductor layer 102.

[0329] For the specific implementation process of step S142, please refer to the above step S112, and the details will not be described again here.

[0330] S143. Form a third dielectric layer 116, as shown in Figure 23. Here, the third dielectric layer 116 is formed on the sidewalls and bottom of the trench structure.

[0331] It should be noted that step S143 can be implemented in two ways. In the first way, the third dielectric layer 116 can be directly formed by using methods such as chemical vapor deposition, physical vapor deposition, sputtering, or electroplating. In this case, the third dielectric layer 116 is a whole layer and covers the exposed surfaces of the semiconductor layer 102, the second electrode 108, the first electrode 109, and the first dielectric layer 113. In the second way, the eighth dielectric thin film may be formed first by using chemical vapor deposition, physical vapor deposition, sputtering, or electroplating. The eighth dielectric thin film covers the exposed surfaces of the semiconductor layer 102, the second electrode 108, the first electrode 109, and the first dielectric layer 113. Then, the eighth dielectric thin film is etched. In addition to the part formed on the side and bottom of the groove, the other eighth dielectric thin film is all etched to form the third dielectric layer 116.

[0332] S144. Form a second dielectric layer 112, as shown in Fig. 23. Here, the second dielectric layer 112 covers the third dielectric layer 116, the semiconductor layer 102 and the second electrode 108, and the material of the second dielectric layer 112 is a ferroelectric material.

[0333] For the specific implementation process of step S144, please refer to the above step S103, and the details will not be described again here.

[0334] S145. Form the gate 106, as shown in Fig. 23, where the gate 106 includes a gate base 1061 and a gate body 1062 extending from the gate base 1061, the gate body 1062 extending into the trench structure, i.e., the gate body 1062 extends along the side of the first dielectric layer 113 and the side of the second electrode 108, the gate base 1061 is formed on the side of the gate body 1062 away from the first electrode 109, and the second dielectric layer 112 separates the gate 106 from the semiconductor layer 102, the first electrode 109, and the second electrode 108.

[0335] For the specific implementation process of step S145, please refer to the above step S104, and the details will not be described again here.

[0336] In the fifth embodiment, step S143 is added as compared with the second embodiment.

[0337] In addition, in the fifth embodiment, the structure of the semiconductor layer 102 formed in step S142 is the same as the structure of the semiconductor layer 102 formed in the second embodiment. In some embodiments, the structure of the semiconductor layer 102 formed in step S142 is also the same as the configuration of the semiconductor layer 102 formed in the first embodiment or the third embodiment. EXAMPLES

[0338] EMBODIMENT 6 For example, the manufacturing method of the thin film transistor 10 shown in FIG.

[0339] S150. As shown in FIG. 24, a first conductive thin film 1090, a first dielectric thin film 1130 and a second conductive thin film 1080 are sequentially formed on a substrate 101.

[0340] For the specific implementation process of step S150, please refer to the above step S100, and the details will not be described again here.

[0341] S151. As shown in Fig. 24, the first conductive thin film 1090, the first dielectric thin film 1130 and the second conductive thin film 1080 are patterned to form a first electrode 109, a first dielectric layer 113 and a second electrode 108 which are stacked sequentially. Here, the first electrode 109, the first dielectric layer 113 and the second electrode 108 form a groove structure.

[0342] For the specific implementation process of step S151, please refer to step S101 above, and the details will not be described again here.

[0343] S152. As shown in Fig. 24, a semiconductor layer 102 is formed. Here, the semiconductor layer 102 is formed on the sidewall and bottom of the groove structure, i.e., the semiconductor layer 102 is formed on the side of the first dielectric layer 113 and the side of the second electrode 108, and the semiconductor layer 102 further extends from the side of the first dielectric layer 113 and the side of the second electrode 108 to the surface of the first electrode 109 close to the second electrode 108, i.e., the top surface of the first electrode 1109, and both the first electrode 109 and the second electrode 108 are electrically connected to the semiconductor layer 102.

[0344] For the specific implementation process of step S152, please refer to the above step S112, and the details will not be described again here.

[0345] S153. As shown in FIG. 24, form a third dielectric layer 116, which is formed on the sidewalls and bottom of the trench structure.

[0346] For the specific implementation process of step S153, please refer to the above step S143, and the details will not be described again here.

[0347] S154. As shown in FIG. 24, form a first conductive layer 117, which is formed on the sidewall and bottom of the trench structure.

[0348] A fourth conductive thin film may be formed first, where the fourth conductive thin film covers the exposed surfaces of the third dielectric layer 116, the semiconductor layer 102, the second electrode 108, the first dielectric layer 113, and the first electrode 109; then the fourth conductive thin film is etched. In addition to the portion formed on the side and bottom of the groove, another fourth conductive thin film is etched to form the first conductive layer 117.

[0349] S155. Form a second dielectric layer 112, as shown in Fig. 24, where the second dielectric layer 112 covers the first conductive layer 117, the second dielectric layer 116, the semiconductor layer 102 and the second electrode 108, and the material of the second dielectric layer 112 is a ferroelectric material.

[0350] For the specific implementation process of step S155, please refer to step S103 above, and the details will not be described again here.

[0351] S156. Form the gate 106, as shown in Fig. 24, where the gate 106 includes a gate base 1061 and a gate body 1062 extending from the gate base 1061, the gate body 1062 extending into the trench structure, i.e., the gate body 1062 extends along the side of the first dielectric layer 113 and the side of the second electrode 108, the gate base 1061 is formed on the side of the gate body 1062 away from the first electrode 109, and the second dielectric layer 112 separates the gate 106 from the semiconductor layer 102, the first electrode 109, and the second electrode 108.

[0352] For the specific implementation process of step S156, please refer to the above step S104, and the details will not be described again here.

[0353] In the sixth embodiment, step S154 is added as compared with the fifth embodiment. EXAMPLES

[0354] EMBODIMENT 7 For example, the fabrication of the thin film transistor 10 shown in FIG.

[0355] S160. As shown in FIG. 25, a first conductive thin film 1090, a first dielectric thin film 1130 and a second conductive thin film 1080 are sequentially formed on a substrate 101.

[0356] For the specific implementation process of step S160, please refer to the above step S100, and the details will not be described again here.

[0357] S161. As shown in Fig. 25, the first conductive thin film 1090, the first dielectric thin film 1130 and the second conductive thin film 1080 are patterned to form a first electrode 109, a first dielectric layer 113 and a second electrode 108 that are sequentially stacked, where the boundaries of the projections of the first dielectric layer 113 and the second electrode 108 on the first electrode 109 are located within the boundaries of the first electrode 109, i.e., the first dielectric layer 113 and the second electrode 108 are located in the central region of the first electrode 109.

[0358] For the specific implementation process of step S161, please refer to the above step S101, and the details will not be described again here.

[0359] 25, a semiconductor layer 102 is formed. Here, the semiconductor layer 102 covers the exposed surfaces of the second electrode 108 and the first dielectric layer 113 and the top surface of the first electrode 109, that is, the semiconductor layer 102 covers the top surface and side surfaces of the second electrode 108, the side surfaces of the first dielectric layer 113, and the top surface of the first electrode 109.

[0360] First, a semiconductor thin film may be formed by using an epitaxial growth method, where the semiconductor thin film is an entire layer and covers the exposed surfaces of the first electrode 109, the first dielectric layer 113, and the second electrode 108, and then the semiconductor thin film is etched. In addition to the semiconductor thin film formed on the top and side surfaces of the second electrode 108, the side surfaces of the first dielectric layer 113, and the top surface of the first electrode 109, the semiconductor thin film formed on other parts is etched, thereby forming the semiconductor layer 102.

[0361] S163. Form a second dielectric layer 112, as shown in Figure 25. Here, the second dielectric layer 112 covers the semiconductor layer 102.

[0362] For the specific implementation process of step S163, please refer to the above step S103, and the details will not be described again here.

[0363] S164. Form the gate 106, as shown in Fig. 25. Here, the gate 106 includes a gate base 1061 and a gate body 1062 extending from the gate base 1061, the gate body 1062 being disposed around the entire side of the first dielectric layer 113 and the second electrode 108, i.e., the gate body 1062 is a hollow structure, the gate base 1061 is formed on the side of the gate body 1062 away from the first electrode 109, and the second dielectric layer 112 separates the gate 106 from the semiconductor layer 102, the first electrode 109, and the second electrode 108.

[0364] For the specific implementation process of step S164, please refer to the above step S104, and the details will not be described again here. EXAMPLES

[0365] EMBODIMENT 8 For example, the fabrication of the thin film transistor shown in FIG. 12a specifically includes the following steps.

[0366] S170. As shown in FIG. 26, a first conductive thin film 1090, a first dielectric thin film 1130 and a second conductive thin film 1080 are sequentially formed on a substrate 101.

[0367] For the specific implementation process of step S170, please refer to the above step S100, and the details will not be described again here.

[0368] S171. As shown in Fig. 26, the first conductive thin film 1090, the first dielectric thin film 1130 and the second conductive thin film 1080 are patterned to form a first electrode 109, a first dielectric layer 113 and a second electrode 108 that are sequentially stacked. Here, the boundaries of the projections of the first dielectric layer 113 and the second electrode 108 on the first electrode 109 partially overlap with the boundaries of the first electrode 109, i.e., the first dielectric layer 113 and the second electrode 108 are located at the edge regions of the first electrode 109.

[0369] For the specific implementation process of step S171, please refer to the above step S101, and the details will not be described again here.

[0370] S172. As shown in Fig. 26, a semiconductor layer 102 is formed. Here, the semiconductor layer 102 is formed on the side surface of the second electrode 108 and the side surface of the first dielectric layer 113, and the semiconductor layer 102 further extends from the side surface of the second electrode 108 and the side surface of the first dielectric layer 113 to the top surface of the second electrode 108 and the top surface of the first electrode 109.

[0371] First, a semiconductor thin film may be formed by using an epitaxial growth method. The semiconductor thin film is an entire layer, covering the exposed surfaces of the first electrode 109, the first dielectric layer 113, and the second electrode 108. Then, the semiconductor thin film is etched. In addition to the semiconductor thin film formed on the side of the second electrode 108 and the side of the first dielectric layer 113, the top surface of the second electrode 108, and the top surface of the first electrode 109, the semiconductor thin film formed on other parts is etched, thereby forming the semiconductor layer 102.

[0372] S173. Form a second dielectric layer 112, as shown in Figure 26. Here, the second dielectric layer 112 covers the semiconductor layer 102.

[0373] It should be noted that step S173 can be implemented in two ways. In the first way, the second dielectric layer 112 can be directly formed by using a method such as chemical vapor deposition, physical vapor deposition, sputtering, or electroplating. In this case, the second dielectric layer 112 is a whole layer and covers the exposed surfaces of the semiconductor layer 102, the second electrode 108, the first electrode 109, and the first dielectric layer 113. In the second way, the seventh dielectric thin film is first formed by using chemical vapor deposition, physical vapor deposition, sputtering, or electroplating. The seventh dielectric thin film covers the exposed surfaces of the semiconductor layer 102, the second electrode 108, the first electrode 109, and the first dielectric layer 113. Then, the seventh dielectric thin film is etched. In addition to the seventh dielectric thin film formed on the surface of the semiconductor layer 102 away from the first electrode 109, the seventh dielectric thin film formed elsewhere is etched to form the second dielectric layer 112. The first embodiment is not shown in the accompanying drawings.

[0374] S174. Form the gate 106, as shown in Figure 26, where the gate 106 includes a gate base 1061 and a gate body 1062 extending from the gate base 1061, the gate body 1062 extending along a side of the first dielectric layer 113 and a side of the second electrode 108, the gate base 1061 is formed on a side of the gate body 1062 away from the first electrode 109, and the second dielectric layer 112 separates the gate 106 from the semiconductor layer 102, the first electrode 109, and the second electrode 108.

[0375] For the specific implementation process of step S174, please refer to the above step S104, and the details will not be described again here. EXAMPLES

[0376] EMBODIMENT 9 For example, the fabrication of the thin film transistor shown in FIG.

[0377] S180. As shown in FIG. 27, a first conductive thin film 1090, a first dielectric thin film 1130 and a second conductive thin film 1080 are sequentially formed on a substrate 101.

[0378] For the specific implementation process of step S180, please refer to the above step S100, and the details will not be described again here.

[0379] S181. As shown in FIG. 27, pattern the first conductive thin film 1090, the first dielectric thin film 1130 and the second conductive thin film 1080 to form a first electrode 109, a first dielectric layer 113 and a second electrode 108 that are sequentially stacked, such that boundaries of the projections of the first dielectric layer 113 and the second electrode 108 on the first electrode 109 overlap with boundaries of the first electrode 109.

[0380] For the specific implementation process of step S181, please refer to the above step S101, and the details will not be described again here.

[0381] S182. As shown in FIG. 27, form a semiconductor layer 102. The semiconductor layer 102 is formed on the side of the first electrode 109, the side of the first dielectric layer 113, and the side of the second electrode 108, and the semiconductor layer 102 further extends from the side of the first electrode 109, the side of the first dielectric layer 113, and the side of the second electrode 108 to the surface of the side of the second electrode 108 away from the first electrode 109, that is, the top surface of the second electrode 108. First, a semiconductor thin film may be formed by using an epitaxial growth method, and the semiconductor thin film is the entire layer and covers the exposed surfaces of the first electrode 109, the first dielectric layer 113, and the second electrode 108; then, the semiconductor thin film is etched. In addition to the semiconductor thin film formed on the left side surface of the first electrode 109, the left side surface of the first dielectric layer 113, the left side surface of the second electrode 108, and the top surface of the second electrode 108, the semiconductor thin film formed in other portions is etched, thereby forming the semiconductor layer 102.

[0382] S183. Form a second dielectric layer 112, as shown in Figure 27. Here, the second dielectric layer 112 covers the semiconductor layer 102.

[0383] It should be noted that step S183 can be implemented in two ways. In the first way, the second dielectric layer 112 can be directly formed by using a method such as chemical vapor deposition, physical vapor deposition, sputtering, or electroplating. In this case, the second dielectric layer 112 is a whole layer and covers the exposed surfaces of the semiconductor layer 102, the second electrode 108, the first electrode 109, and the first dielectric layer 113. In the second way, the seventh dielectric thin film may be formed first by using chemical vapor deposition, physical vapor deposition, sputtering, or electroplating. The seventh dielectric thin film covers the exposed surfaces of the semiconductor layer 102, the second electrode 108, the first electrode 109, and the first dielectric layer 113. Then, the seventh dielectric thin film is etched. The seventh dielectric thin film formed on the side and top surfaces of the semiconductor layer 102, as well as the seventh dielectric thin film formed elsewhere, is etched, thereby forming the second dielectric layer 112. The first embodiment is not shown in the accompanying drawings.

[0384] S184. Form the gate 106, as shown in Figure 27, where the gate 106 includes a gate base 1061 and a gate body 1062 extending from the gate base 1061, the gate body 1062 extending along a side of the first dielectric layer 113 and a side of the second electrode 108, the gate base 1061 is formed on a side of the gate body 1062 away from the first electrode 109, and the second dielectric layer 112 separates the gate 106 from the semiconductor layer 102, the first electrode 109, and the second electrode 108.

[0385] For the specific implementation process of step S184, please refer to the above step S104, and the details will not be described again here.

[0386] It should be noted that the difference between embodiment 7, embodiment 8 and embodiment 9 and the other embodiments described above is that the structures of the first electrode 109, the first dielectric layer 113 and the second electrode 108 formed to be stacked are different. EXAMPLES

[0387] EMBODIMENT 10 For example, the manufacturing method of the thin film transistor 10 shown in FIG.

[0388] S190. As shown in FIG. 28, form a first conductive thin film 1090 and a third dielectric thin film 1131 sequentially stacked on a substrate 101.

[0389] For the specific implementation process of step S190, please refer to the above step S100, and the details will not be described again here.

[0390] S191. As shown in FIG. 28, a modulation gate electrode 118 is formed on the third dielectric thin film 1131.

[0391] A specific process of forming the modulating gate electrode 118 may be to first form a fifth conductive thin film, and then pattern the fifth conductive thin film to form the modulating gate electrode 118.

[0392] 28, form a fourth dielectric thin film 1132 on the modulation gate electrode 118. Here, the fourth dielectric thin film 1132 covers the modulation gate electrode 118.

[0393] The fourth dielectric thin film 1132 can be formed using a method such as chemical vapor deposition, physical vapor deposition, sputtering, or electroplating.

[0394] S193: As shown in FIG. 28, the fourth dielectric thin film 1132 is ground.

[0395] Grinding may be performed on the fourth dielectric thin film 1132 using a chemical mechanical polishing technique.

[0396] It should be noted that step S193 is an optional step, for example, in some embodiments, step S193 may be omitted.

[0397] S194. Form a second conductive thin film 1080 on the fourth dielectric thin film 1132, as shown in FIG.

[0398] The second conductive thin film 1080 can be formed using methods such as chemical vapor deposition, physical vapor deposition, sputtering, electroplating, and the like.

[0399] 28, pattern the second conductive thin film 1080 to form the second electrode 108, pattern the fourth dielectric thin film 1132 and the third dielectric thin film 1131 to form the first dielectric layer 113, and pattern the first conductive thin film 1090 to form the first electrode 109. Here, the second electrode 108, the first dielectric layer 113 and the first electrode 109 form a groove structure, and the first dielectric layer 113 surrounds the modulating gate electrode 118, so that the modulating gate electrode 118 is spaced apart from the second electrode 108 and the first electrode 109.

[0400] For the specific implementation process of step S195, please refer to step S101 above, and the details will not be described again here.

[0401] S196. Form the semiconductor layer 102 as shown in Figure 28. Here, the semiconductor layer 102 is formed on the sidewall and bottom of the groove structure and the surface of the second electrode 108 away from the first electrode 109, i.e., the semiconductor layer 102 is formed on the side of the first dielectric layer 113 and the side of the second electrode 108, the semiconductor layer 102 further extends from the side of the first dielectric layer 113 and the side of the second electrode 108 to the surface of the second electrode 108 away from the first electrode 109 (i.e., the top surface of the second electrode 108) and the surface of the first electrode 109 close to the second electrode 108 (i.e., the top surface of the first electrode 109), and both the first electrode 109 and the second electrode 108 are electrically connected to the semiconductor layer 102.

[0402] For the specific implementation process of step S196, please refer to the above step S122, and the details will not be described again here.

[0403] S197. Form a second dielectric layer 112, as shown in Figure 28. Here, the second dielectric layer 112 covers the semiconductor layer 102.

[0404] For the specific implementation process of step S197, please refer to the above step S103, and the details will not be described again here.

[0405] S198. Form the gate 106, as shown in Fig. 28, where the gate 106 includes a gate base 1061 and a gate body 1062 extending from the gate base 1061, the gate body 1062 extending into the trench structure, i.e., the gate body 1062 extends along a side of the first dielectric layer 113 and a side of the second electrode 108, the gate base 1061 is formed on a side of the gate body 1062 away from the first electrode 109, and the second dielectric layer 112 separates the gate 106 from the semiconductor layer 102, the first electrode 109, and the second electrode 108.

[0406] For the specific implementation process of step S198, please refer to the above step S104, and the details will not be described again here.

[0407] It should be noted that the difference between the tenth embodiment and the other embodiments described above is mainly that step S191 is added in the tenth embodiment. EXAMPLES

[0408] EMBODIMENT 11 For example, the fabrication of the thin film transistor 10 shown in FIG.

[0409] S200. As shown in FIG. 29, a first conductive thin film 1090 and a first dielectric thin film 1130 are sequentially stacked on a substrate 101.

[0410] For the specific implementation process of step S200, please refer to the above step S100, and the details will not be described again here.

[0411] S201. As shown in Figure 29, pattern the first conductive thin film 1090 and the first dielectric thin film 1130 to form a first electrode 109 and a first dielectric layer 113 that are stacked sequentially, where the first dielectric layer 113 and the first electrode 109 form a groove structure.

[0412] For the specific implementation process of step S201, please refer to the above step S101, and the details will not be described again here.

[0413] S202. As shown in Fig. 29, a semiconductor layer 102 is formed. Here, the semiconductor layer 102 is formed on the sidewall and bottom of the groove structure and the surface of the first dielectric layer 113 away from the first electrode 109, i.e., the semiconductor layer 102 is formed on the side of the first dielectric layer 113, the semiconductor layer 102 further extends from the side of the first dielectric layer 113 to the surface of the first electrode 109 closer to the first dielectric layer 113 (i.e., the top surface of the first electrode 109) and the surface of the first dielectric layer 113 away from the first electrode 109 (i.e., the top surface of the first dielectric layer 113), and the first electrode 109 is electrically connected to the semiconductor layer 102.

[0414] First, a semiconductor thin film may be formed by using an epitaxial growth method, where the semiconductor thin film is a whole layer and covers the exposed surfaces of the first electrode 109 and the first dielectric layer 113, and then the semiconductor thin film is etched. In addition to the semiconductor thin film formed on the sidewalls and bottom of the groove and the top surface of the first dielectric layer 113, the semiconductor thin film formed outside the groove is etched to form the semiconductor layer 102.

[0415] 29, a second electrode 108 is formed. Here, the second electrode 108 is located on a side of the first dielectric layer 113 away from the first electrode 109. That is, the second electrode 108 is located on the top surface of the first dielectric layer 113.

[0416] The process of forming the second electrode 108 may specifically be to first form a second conductive thin film, and then etch the second conductive thin film to form the second electrode 108.

[0417] 29, form a second dielectric layer 112. Here, the second dielectric layer 112 covers the semiconductor layer 102 and the second electrode 108.

[0418] It should be noted that step S204 can be implemented in two ways. In the first way, the second dielectric layer 112 can be directly formed by using a method such as chemical vapor deposition, physical vapor deposition, sputtering, or electroplating. In this case, the second dielectric layer 112 is a whole layer and covers the exposed surfaces of the semiconductor layer 102, the second electrode 108, the first electrode 109, and the first dielectric layer 113. In the second way, the seventh dielectric thin film may be formed first by using chemical vapor deposition, physical vapor deposition, sputtering, or electroplating. The seventh dielectric thin film covers the exposed surfaces of the semiconductor layer 102, the second electrode 108, the first electrode 109, and the first dielectric layer 113. Then, the seventh dielectric thin film is etched. In addition to the portions formed on the sides and bottom of the groove and the top and sides of the second electrode 108, the other seventh dielectric thin film is all etched, thereby forming the second dielectric layer 112. The first embodiment is not shown in the accompanying drawings.

[0419] S205. As shown in FIG. 29, form the gate 106, the gate 106 including a gate base 1061 and a gate body 1062 extending from the gate base 1061, the gate body 1062 extending into the trench structure, i.e., the gate body 1062 extends along a side of the first dielectric layer 113 and a side of the second electrode 108, the gate base 1061 is formed on a side of the gate body 1062 away from the first electrode 109, and the second dielectric layer 112 separates the gate 106 from the semiconductor layer 102, the first electrode 109, and the second electrode 108.

[0420] For the specific implementation process of step S205, please refer to the above step S104, and the details will not be described again here.

[0421] The main difference between the eleventh embodiment and the other embodiments described above is that the sequence for forming the semiconductor layer 102 and the second electrode 108 in the eleventh embodiment is different from that in the other embodiments described above.

[0422] It should be understood that the thin film transistor 10 provided in the embodiment of the present application may be manufactured by using the above-mentioned manufacturing method of the thin film transistor 10, or may be manufactured by using another manufacturing method, which is not limited here.

[0423] An embodiment of the present application further provides a memory manufacturing method, which includes forming at least one layer of a storage array 201 on a substrate 101 .

[0424] For example, as shown in FIG. 30, fabricating any layer of the storage array 201 shown in FIG. 4 specifically includes the following steps.

[0425] S300. A plurality of first signal lines are formed on a substrate 101 in parallel.

[0426] S301. On the plurality of first signal lines, a plurality of first thin film transistors Tr0 distributed in an array and a plurality of second signal lines arranged in parallel are formed, a first electrode 109a of the first thin film transistor Tr0 is electrically connected to the first signal line, a second electrode 108a of the first thin film transistor Tr0 is electrically connected to the second signal line, the first signal line is one of the read bit line RBL or the read word line RWL, and the second signal line is the other of the read bit line RBL and the read word line RWL. The first thin film transistor Tr0 may be manufactured by using the manufacturing method of the thin film transistor 10 provided in any of the above-mentioned embodiments. Here, it can be understood that the plurality of first thin film transistors Tr0 distributed in an array may be formed synchronously.

[0427] The first signal line may be a read bit line RBL, and the second signal line may be a read word line RWL. In this case, the first electrode 109a of the first thin film transistor Tr0 is electrically connected to the read bit line RBL, and the second electrode 108a is electrically connected to the read word line RWL. Alternatively, the first signal line may be a read word line RWL, and the second signal line is a read bit line RBL. In this case, the first electrode 109a of the first thin film transistor Tr0 is electrically connected to the read word line RWL, and the second electrode 108a is electrically connected to the read bit line RBL.

[0428] It may be understood that in some embodiments, the first electrode 109a may be formed synchronously with a first signal line, and the second electrode 108a may be formed synchronously with a second signal line.

[0429] S302: A plurality of connection electrodes 111 distributed in an array are formed. Here, the gate 106a of one of the first thin film transistors Tr0 is electrically connected to one of the connection electrodes 111.

[0430] It should be noted that step S302 is an optional step, for example, in some embodiments, step S302 may be omitted.

[0431] First, the sixth conductive thin film may be formed, and then the sixth conductive thin film is etched to form a plurality of connecting electrodes 111.

[0432] S303. On the first thin film transistor Tr0, a plurality of second thin film transistors Tr1 distributed in an array and a plurality of write bit lines WBL arranged in parallel are formed. Here, the second electrode 108b of the second thin film transistor Tr1 is electrically connected to the write bit line WBL. One second thin film transistor Tr1 corresponds to one first thin film transistor Tr0, and the first electrode 109b of the second thin film transistor Tr1 is electrically connected to the gate 106a of the corresponding first thin film transistor Tr0. The second thin film transistor Tr1 can be manufactured by using the manufacturing method of the thin film transistor 10 provided in any of the above-mentioned embodiments. Here, it is understood that the plurality of second thin film transistors Tr1 distributed in an array may be formed synchronously.

[0433] It should be noted that when the manufacturing method of any layer of the memory array 201 includes step S302, the first electrode 109b of the second thin film transistor Tr1 is electrically connected to the gate 106a of the corresponding first thin film transistor Tr0 by using the connecting electrode 111.

[0434] In some embodiments, the second electrode 108b of the second thin film transistor Tr1 may be formed synchronously with the write bit line WBL.

[0435] S304: A plurality of write word lines WWL arranged in parallel are formed on the second thin film transistor Tr1, where the gates 106b of the second thin film transistors Tr1 are electrically connected to the write word lines WWL.

[0436] In some embodiments, the write word line WWL may be formed synchronously with the gate 106b of the second thin film transistor Tr1.

[0437] Based on the above description, if memory 200 includes multiple layers of memory arrays 201 disposed on substrate 101, when memory 200 is manufactured, steps S300 to S304 may be repeated to form multiple layers of memory arrays 201.

[0438] Moreover, after the first layer of the storage array 201 is manufactured, the sixth dielectric layer 202 may be formed first before the second layer of the storage array 201 is formed. In this case, the sixth dielectric layer 202 is used as a substrate for the second layer of the storage array 201. Similarly, the sixth dielectric layer 202 may also be formed first before the third layer of the storage array 201, the fourth layer of the storage array 201, etc. are manufactured. The above description is merely a specific implementation of the present application and is not intended to limit the protection scope of the present application. Any variation or replacement that is easily conceived by a person skilled in the art within the technical scope disclosed in this application shall fall within the protection scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.

Claims

1. 1. A thin film transistor comprising: a gate including a gate base located at an upper portion and a gate body extending from the gate base to a bottom portion; a first electrode located at the bottom; a second electrode located between the first electrode and the gate base; a first dielectric layer disposed between the second electrode and the first electrode, the first dielectric layer configured to separate the second electrode from the first electrode; a semiconductor layer disposed along a side of the gate body; a second dielectric layer separating the semiconductor layer from the gate; the first electrode and the second electrode are each electrically connected to the semiconductor layer; the second electrode is disposed between the semiconductor layer and the second dielectric layer; Thin film transistor.

2. The thin film transistor of claim 1 , wherein the second electrode is disposed proximate to the gate base.

3. The thin film transistor of claim 1 , wherein the semiconductor layer further includes an extension portion extending along a surface of the gate base.

4. The thin film transistor of claim 1 , wherein the semiconductor layer further comprises an extension portion located between the gate body and the first electrode.

5. The thin film transistor of claim 1 , wherein the semiconductor layer completely surrounds a side surface of the gate body.

6. 6. A thin film transistor according to claim 1, wherein the second electrode is disposed on a side of the semiconductor layer remote from the second dielectric layer.

7. A thin film transistor comprising: a gate including a gate base located at an upper portion and a gate body extending from the gate base to a bottom portion; a first electrode located at the bottom; a second electrode located between the first electrode and the gate base; a first dielectric layer disposed between the second electrode and the first electrode, the first dielectric layer configured to separate the second electrode from the first electrode; a semiconductor layer disposed along a side of the gate body; a second dielectric layer separating the semiconductor layer from the gate; the first electrode and the second electrode are each electrically connected to the semiconductor layer; the thin film transistor further includes a fourth dielectric layer disposed between the second electrode and the semiconductor layer, and / or a fifth dielectric layer disposed between the first electrode and the semiconductor layer. Thin film transistor.

8. A thin film transistor comprising: a gate including a gate base located at an upper portion and a gate body extending from the gate base to a bottom portion; a first electrode located at the bottom; a second electrode located between the first electrode and the gate base; a first dielectric layer disposed between the second electrode and the first electrode, the first dielectric layer configured to separate the second electrode from the first electrode; a semiconductor layer disposed along a side of the gate body; a second dielectric layer separating the semiconductor layer from the gate; the first electrode and the second electrode are each electrically connected to the semiconductor layer; The thin film transistor further includes a modulating gate electrode disposed between the first electrode and the second electrode, the modulating gate electrode being surrounded by the first dielectric layer. Thin film transistor.

9. the first electrode is a drain and the second electrode is a source; or The first electrode is a source and the second electrode is a drain. A thin film transistor according to any one of claims 1 to 8.

10. A memory including at least one layer of a storage array disposed on a substrate, each layer of the storage array including a plurality of storage cells, a write word line, a write bit line, a read word line and a read bit line distributed in an array; the storage cells including a second thin film transistor and a first thin film transistor stacked together; a first electrode and a second electrode of the first thin film transistor electrically connected to the read word line and the read bit line, respectively; a gate of the second thin film transistor electrically connected to the write word line and the second electrode electrically connected to the write bit line; The first thin film transistor and the second thin film transistor are thin film transistors according to any one of claims 1 to 9; a first electrode of the second thin film transistor adjacent to a gate of the first thin film transistor, and the first electrode of the second thin film transistor electrically connected to the gate of the first thin film transistor; Memory.

11. The memory cell further includes a connection electrode disposed between the first thin film transistor and the second thin film transistor; the gate of the first thin film transistor is electrically connected to the first electrode of the second thin film transistor by using the connecting electrode; The memory of claim 10.

12. Gates of second thin film transistors in a plurality of memory cells sequentially arranged in each layer of the memory array along the first direction are electrically connected to the same write word line; second electrodes of second thin film transistors in a plurality of memory cells sequentially arranged in each layer of the memory array along the second direction are electrically connected to the same write bit line; The first direction and the second direction are perpendicular to each other.

12. A memory according to claim 10 or 11.

13. second electrodes of first thin film transistors in the plurality of memory cells sequentially arranged in each layer of the memory array along the first direction are electrically connected to a same read bit line, and first electrodes of first thin film transistors in the plurality of memory cells sequentially arranged in each layer of the memory array along the second direction are electrically connected to a same read word line; second electrodes of first thin film transistors in the plurality of memory cells sequentially arranged in each layer of the memory array along the first direction are electrically connected to a same read word line, and first electrodes of first thin film transistors in the plurality of memory cells sequentially arranged in each layer of the memory array along the second direction are electrically connected to a same read bit line; Second electrodes of first thin film transistors in the plurality of memory cells arranged sequentially in each layer of the memory array along the second direction are electrically connected to a same read bit line, and first electrodes of first thin film transistors in the plurality of memory cells arranged sequentially in each layer of the memory array along the first direction are electrically connected to a same read word line; or Second electrodes of first thin film transistors in the plurality of memory cells sequentially arranged in each layer of the memory array along the second direction are electrically connected to a same read word line, and first electrodes of first thin film transistors in the plurality of memory cells sequentially arranged in each layer of the memory array along the first direction are electrically connected to a same read bit line; The first direction and the second direction are perpendicular to each other. The memory of claim 12.

14. the first thin film transistor further includes a first modulation gate electrode disposed between the first electrode and the second electrode, the first modulation gate electrode being surrounded by a first dielectric layer of the first thin film transistor, and the first modulation gate electrodes of multiple first thin film transistors located in the same layer are electrically connected together; and / or The second thin film transistor further includes a second modulation gate electrode disposed between the first electrode and the second electrode, the second modulation gate electrode being surrounded by a first dielectric layer of the second thin film transistor, and the second modulation gate electrodes of the multiple second thin film transistors located in the same layer are electrically connected together; A memory according to any one of claims 10 to 13.

15. 15. An electronic device comprising a circuit board and a memory electrically connected to said circuit board, said memory being a memory according to any one of claims 10 to 14.

16. 1. A method for manufacturing a thin film transistor, comprising: forming a first electrode, a first dielectric layer, a second electrode, and a semiconductor layer on a substrate, the first electrode, the first dielectric layer, and the second electrode being stacked in order, the first dielectric layer separating the first electrode from the second electrode, the semiconductor layer being formed on a side of the first dielectric layer, and both the first electrode and the second electrode being electrically connected to the semiconductor layer; sequentially forming a second dielectric layer and a gate, the gate including a gate base located at an upper portion and a gate body extending from the gate base to a bottom portion, the second dielectric layer isolating the gate from the semiconductor layer, the first electrode, and the second electrode; Forming a first electrode, a first dielectric layer, a second electrode, and a semiconductor layer on a substrate includes: forming a first conductive thin film and a third dielectric thin film sequentially stacked on the substrate; forming a modulating gate electrode on the third dielectric film; forming a fourth dielectric film surrounding the modulating gate electrode; forming a second conductive thin film on the fourth dielectric thin film; patterning the first conductive thin film to form the first electrode, patterning the fourth dielectric thin film and the third dielectric thin film to form the first dielectric layer, and patterning the second conductive thin film to form the second electrode; forming the semiconductor layer on a side surface of the first dielectric layer and a side surface of the second electrode; Manufacturing method.

17. the first electrode is formed as a drain and the second electrode is formed as a source; or The first electrode is formed as a source and the second electrode is formed as a drain. The method of claim 16.

18. A method for manufacturing a thin film transistor, comprising: forming a first electrode, a first dielectric layer, a second electrode, and a semiconductor layer on a substrate, the first electrode, the first dielectric layer, and the second electrode being stacked in order, the first dielectric layer separating the first electrode from the second electrode, the semiconductor layer being formed on a side of the first dielectric layer, and both the first electrode and the second electrode being electrically connected to the semiconductor layer; sequentially forming a second dielectric layer and a gate, the gate including a gate base located at an upper portion and a gate body extending from the gate base to a bottom portion, the second dielectric layer isolating the gate from the semiconductor layer, the first electrode, and the second electrode; After the first electrode is formed and before the semiconductor layer is formed, the method includes: forming a fifth dielectric layer, the fifth dielectric layer contacting the first electrode and the semiconductor layer, respectively; Manufacturing method.

19. A method for manufacturing a thin film transistor, comprising: forming a first electrode, a first dielectric layer, a second electrode, and a semiconductor layer on a substrate, the first electrode, the first dielectric layer, and the second electrode being stacked in order, the first dielectric layer separating the first electrode from the second electrode, the semiconductor layer being formed on a side of the first dielectric layer, and both the first electrode and the second electrode being electrically connected to the semiconductor layer; sequentially forming a second dielectric layer and a gate, the gate including a gate base located at an upper portion and a gate body extending from the gate base to a bottom portion, the second dielectric layer isolating the gate from the semiconductor layer, the first electrode, and the second electrode; After the second electrode is formed and before the semiconductor layer is formed; or after the semiconductor layer is formed and before the second electrode is formed, the method may include: forming a fourth dielectric layer, the fourth dielectric layer contacting the second electrode and the semiconductor layer, respectively; Manufacturing method.

20. 1. A memory manufacturing method comprising forming at least one layer of a memory array on a substrate, the method comprising: forming a plurality of first signal lines arranged in parallel on the substrate; forming a plurality of first thin film transistors distributed in an array and a plurality of second signal lines arranged in parallel on the plurality of first signal lines, the first thin film transistors being manufactured by using the manufacturing method according to any one of claims 16 to 19, a first electrode of the first thin film transistor being electrically connected to the first signal line, and a second electrode of the first thin film transistor being electrically connected to the second signal line; the first signal line being one of a read bit line and a read word line, and the second signal line being the other of the read bit line and the read word line; forming a plurality of second thin film transistors distributed in an array and a plurality of write bit lines arranged in parallel on the first thin film transistor, the second electrodes of the second thin film transistors being electrically connected to the write bit lines, the second thin film transistors being manufactured by the manufacturing method according to any one of claims 16 to 19, one second thin film transistor corresponding to one first thin film transistor, and a first electrode of the second thin film transistor being electrically connected to a gate of the corresponding first thin film transistor; forming a plurality of parallel-arranged write word lines on the second thin film transistors, the gates of the second thin film transistors being electrically connected to the write word lines; Memory manufacturing method.

21. After forming a plurality of first thin film transistors distributed in an array and a plurality of second signal lines arranged in parallel on the plurality of first signal lines, and before forming a plurality of second thin film transistors distributed in an array and a plurality of write bit lines arranged in parallel on the first thin film transistors, a manufacturing method of any layer of a memory array includes: The method further includes forming a plurality of connecting electrodes distributed in an array, and the gate of the first thin film transistor is electrically connected to the first electrode of the corresponding second thin film transistor by using the connecting electrode; 21. The memory manufacturing method of claim 20.

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