CIRCUIT DEVICE, ELECTRONIC DEVICE, AND IMAGE PROCESSING METHOD

Abstract

To provide a circuit arrangement that can execute right-wrong determination of image processing by using CRC even for image processing for changing the details of an image.SOLUTION: A circuit arrangement 100 includes an image processing circuit 10, a CRC arithmetic circuit 20, and a determination circuit 30. The image processing circuit 10 receives input of processing target image data TGIN obtained by adding known image data KIP to effective image data IMIN and performs image processing on the processing target image data TGIN. The image processing circuit 10 outputs processed effective image data that is the effective image data IMIN on which the image processing is executed and processed known image data that is the known image data KIP on which the image processing is executed. The CRC arithmetic circuit 20 determines a CRC value CC from the processed known image data TGQ. The determination circuit 30 compares the CRC value CC and a CRC expectation value CE of the processed known image data with each other to determine whether the image processing is right or wrong.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to a circuit device, an electronic device, an image processing method, and the like. [Background technology]

[0002] There is a known technology for checking communication errors using CRC during data transmission and reception. CRC is an abbreviation for Cyclic Redundancy Check. In this technology, a device receiving data compares a CRC expected value with a CRC value calculated from the received data to check whether an error has occurred in the received data with respect to the transmitted data. Such a technology is disclosed in, for example, Patent Document 1. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2002-164869 A Summary of the Invention [Problem to be solved by the invention]

[0004] Assume that the data transmitted and received is image data, and the device receiving the data is an image processing device. In this case, the device transmitting the data transmits the CRC expected value of the transmitted image data together with the transmitted image data. The image processing device receiving the data can determine whether the received image data is correct relative to the transmitted image data by comparing the CRC expected value with the CRC value calculated from the received image data. This type of correctness determination is based on the premise that the device does not change the image data before and after communication, and can be used only when this premise is met. However, some image processing modules in the image processing device change image data, and there is a problem in that correctness determination using CRC cannot be used for data output by such image processing modules. [Means for solving the problem]

[0005] One aspect of the present disclosure relates to a circuit device that includes an image processing circuit that receives input of target image data in which known image data has been added to valid image data, and performs image processing on the target image data to output processed valid image data, which is the valid image data after the image processing, and processed known image data, which is the known image data after the image processing; a CRC calculation circuit that calculates a CRC value from the processed known image data; and a judgment circuit that judges the accuracy of the image processing by comparing the CRC value with an expected CRC value of the processed known image data.

[0006] Furthermore, another aspect of the present disclosure includes a receiving circuit that receives valid image data, a known image adding circuit that adds known image data to the valid image data and outputs image data to be processed, 1st to nth image processing circuits (n is an integer of 2 or more), 1st to nth CRC calculation circuits, 1st to nth judgment circuits, a known image removal circuit, and a transmitting circuit, wherein a first image processing circuit of the 1st to nth image processing circuits performs a first image processing on the image data to be processed, thereby outputting first processed image data including first processed valid image data which is the valid image data to which the first image processing has been performed, and first processed known image data which is the known image data to which the first image processing has been performed, and an ith image processing circuit (i is an integer of 2 or more and n or less) of the 1st to nth image processing circuits performs the ith image processing on the i-1th processed image data, thereby The circuit device outputs i-th processed image data including i-th processed valid image data which is the i-1th processed valid image data subjected to the i-th image processing, and i-th processed known image data which is the i-1th processed known image data subjected to the i-th image processing, a k-th CRC calculation circuit (k is an integer greater than or equal to 1 and less than or equal to n) of the first to n-th CRC calculation circuits calculates a k-th CRC value from the k-th processed known image data, a k-th judgment circuit of the first to n-th judgment circuits judges the correctness of the k-th image processing by comparing a k-th CRC expected value of the k-th processed known image data with the k-th CRC value, the known image removal circuit extracts the k-th processed valid image data by removing the k-th processed known image data from the k-th processed image data, and the transmission circuit relates to a circuit device that transmits the k-th processed valid image data extracted by the known image removal circuit.

[0007] Yet another aspect of the present disclosure relates to an electronic device including any of the circuit devices described above.

[0008] Furthermore, still another aspect of the present disclosure relates to an image processing method that performs image processing on image data to be processed in which known image data has been added to valid image data, outputs post-processed valid image data, which is the valid image data after the image processing, and post-processed known image data, which is the known image data after the image processing, calculates a CRC value from the post-processed known image data, and compares the CRC value with an expected CRC value of the post-processed known image data, thereby determining the accuracy of the image processing. [Brief description of the drawings]

[0009] [Figure 1] 1 shows an example of the configuration of a circuit device. [Diagram 2] 4A and 4B are diagrams for explaining image data to be processed. [Diagram 3] 13 shows a modified example of the arrangement of effective image data and known image data. [Figure 4] 1 shows a first detailed configuration example of a circuit device. [Diagram 5] 1 is a flowchart of an image processing method. [Figure 6] 13 shows an example of a modified configuration of a circuit device. [Figure 7] 4 shows a second detailed configuration example of a circuit device. [Figure 8] 1 illustrates an example of a configuration of a processing device that executes a software tool. [Figure 9] 1 is a first configuration example of an electronic device. [Figure 10] 2 shows a second configuration example of an electronic device. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0010] A preferred embodiment of the present disclosure will be described in detail below. Note that the embodiment described below does not unduly limit the contents described in the claims, and all of the configurations described in the embodiment are not necessarily essential configurations.

[0011] 1.Circuit device 1 shows an example of the configuration of a circuit device 100. The circuit device 100 includes an image processing circuit 10, a CRC calculation circuit 20, a determination circuit 30, and a register 40.

[0012] In the case where multiple image processes are sequentially performed on image data output by a processing device or the like and then the image data is displayed on a display device, the multiple image processes sequentially performed are referred to as an image processing pipeline. The circuit device 100 is one of one or multiple circuit devices that constitute such an image processing pipeline. The circuit device 100 is, for example, an integrated circuit device in which multiple circuit elements are integrated on a semiconductor substrate.

[0013] Image data to be processed TGIN is input to the image processing circuit 10. FIG. 2 is a diagram for explaining the image data to be processed TGIN. The image data to be processed TGIN is image data in which known image data KIP is added to valid image data IMIN. The valid image data IMIN is image data that is displayed on the display device after being processed by the image processing pipeline. The known image data KIP is image data that is prepared in advance for performing a correct / incorrect judgment by CRC in this embodiment, and is not displayed on the display device.

[0014] The total number of pixels in one frame of the processing target image data TGIN is VH×VV, and the number of pixels in the effective image data IMIN is AH×AV. In this case, the area of ​​AH×AV is the effective image area ADR, and the area within the area of ​​VH×VV but other than the effective image area ADR is the non-display area VDR corresponding to the blanking period. The known image data KIP is added to the non-display area VDR, and is shown with hatching in FIG. 2. Note that, although the known image data KIP is added to the entire non-display area VDR in FIG. 2, the known image data KIP may be added to only a part of the non-display area VDR.

[0015] VH is the total number of horizontal pixels, which means the total number of pixels in the horizontal scanning direction including blanking periods. The total number of horizontal pixels is also called the Virtual Horizontal Resolution. AH is the number of horizontal active pixels, which is also called the Actual Horizontal Resolution. VV is the total number of vertical lines, which means the total number of lines in one frame including blanking periods. The total number of vertical lines is also called the Virtual Vertical Resolution. AV is the number of vertical active lines, which is also called the Actual Vertical Resolution. Note that blanking periods and other periods and the number of pixels can be treated as equivalent by considering one pulse of the pixel clock as one pixel.

[0016] In FIG. 1, the image processing circuit 10 performs image processing on the processing target image data TGIN to change the image contents, and outputs the resultant processed image data TGQ. Since both the valid image data IMIN and the known image data KIP are image processed, the processed image data TGQ is image data in which the processed known image data KIP, which is the image-processed known image data, is added to the processed valid image data IMIN, which is the image-processed valid image data. The image processing that changes the image contents is image processing that changes the pixel data constituting the image data, and does not include processing that does not change the pixel data itself, such as changing the format of the image data. The image processing that changes the image contents is, for example, gamma correction processing, FRC processing, OSD processing, scaling processing, white balance processing, image synthesis processing, or a combination of any two or more of these processes. FRC is an abbreviation for Frame Rate Control. OSD is an abbreviation for On-Screen Display.

[0017] The CRC calculation circuit 20 calculates the CRC value CC from the processed known image data in the processed image data TGQ. For example, the CRC calculation circuit 20 obtains the CRC value CC from the entire processed known image data present in the non-display area VDR. Alternatively, the CRC calculation circuit 20 may obtain the CRC value CC from the processed known image data in a part of the non-display area VDR. In this case, the CRC calculation circuit 20 may obtain multiple CRC values ​​CC from the processed known image data in multiple areas in one frame. For example, the CRC calculation circuit 20 may obtain the CRC value CC for each line from the processed known image data of each line.

[0018] The register 40 stores in advance a CRC expected value CE, which is an expected value of the CRC value CC. It is possible to simulate in advance what kind of image data the known image data after processing will become from the processing parameters of the image processing circuit 10, and it is also possible to calculate in advance the CRC expected value CE obtained from the known image data after processing. The CRC expected value CE thus prepared is written in advance to the register 40 from, for example, an external processing device.

[0019] The judgment circuit 30 judges whether the image processing in the image processing circuit 10 is correct by comparing the CRC value CC with the CRC expected value CE. That is, if the CRC value CC and the CRC expected value CE match, the judgment circuit 30 judges that the image processing has ended normally and that normal post-processing valid image data has been obtained. If the CRC value CC and the CRC expected value CE do not match, the judgment circuit 30 judges that an abnormality has occurred in the image processing and that normal post-processing valid image data has not been obtained. As an abnormality in the image processing, for example, a data abnormality due to a short circuit or noise is assumed. The judgment circuit 30 outputs the judgment result as a judgment signal DTQ.

[0020] The arrangement of the effective image data IMIN and the known image data KIP in the VH×VV region is not limited to that shown in FIG. 2. FIG. 3 shows an example of a modified example. In FIG. 3, the effective image region is divided into three regions ADR1, ADR2, and ADR3 in the horizontal scanning direction, and the number of pixels is AH1×AV, AH2×AV, and AH3×AV, respectively. AH1+AH2+AH3=AH, and for example, AH1=AH2=AH3, but AH1, AH2, and AH3 may be different from each other. The regions ADR1, ADR2, and ADR3 correspond to the effective image data IMIN1, IMIN2, and IMIN3 obtained by dividing the effective image data of one frame into three. The area between the region ADR1 and the region ADR2, and the area between the region ADR2 and the region ADR3 are part of the non-display region VDR. When the known image data is removed after the image processing pipeline, the effective image data divided into three is concatenated.

[0021] By using the arrangement as shown in Fig. 3, temporary processing abnormalities due to noise or the like can be easily detected. On the other hand, for non-temporary processing abnormalities due to short circuits or the like, either of the arrangements in Fig. 2 or Fig. 3 may be used. The arrangements in Fig. 2 or Fig. 3 are set in advance, for example, according to the expected processing abnormality or the processing abnormality to be detected. Based on the setting information, the CRC calculation circuit 20 can determine the non-display area VDR in which the processed known image data is placed out of the VH × VV area of ​​the processed image data TGQ, and calculate the CRC value CC from the processed known image data of the non-display area VDR.

[0022] In the above embodiment, the circuit device 100 includes an image processing circuit 10, a CRC calculation circuit 20, and a judgment circuit 30. The image processing circuit 10 receives the processing target image data TGIN in which known image data KIP is added to the valid image data IMIN, and performs image processing on the processing target image data TGIN. The image processing circuit 10 outputs processed valid image data, which is the valid image data IMIN on which image processing has been performed, and processed known image data, which is the known image data KIP on which image processing has been performed. The CRC calculation circuit 20 obtains a CRC value CC from the processed known image data. The judgment circuit 30 judges whether the image processing is correct or not by comparing the CRC value CC with a CRC expectation value CE of the processed known image data.

[0023] According to this embodiment, even if the image processing changes the content of the image, the correctness of the image processing can be judged using CRC. Various image processing is performed in the image processing pipeline, and CRC judgment can be applied to any image processing circuit. This makes it possible to detect which image processing circuit in the image processing pipeline has an abnormality. In addition, since the error detection method can be unified to CRC judgment throughout the image processing pipeline, it is no longer necessary to develop a dedicated error detection method for each image processing, and the development of the error detection method is simplified.

[0024] Although only one image processing circuit 10 is shown in FIG. 1, another image processing circuit may be provided in the previous stage. In that case, the processed image data output by the previous image processing circuit is input to the image processing circuit 10 as the image data to be processed. That is, the known image data input to the image processing circuit 10 may be the known image data after image processing by the previous image processing circuit. The contents of the image processing in the previous stage and the contents of the image processing performed by the image processing circuit 10 can be known by the respective image processing parameters. For this reason, it is possible to calculate the processed known image data output by the image processing circuit 10 in advance using a software tool or the like described later, and it is possible to obtain the CRC expected value in advance from the processed known image data.

[0025] In this embodiment, the image area corresponding to the processing target image data TGIN includes an effective image area ADR corresponding to the effective image data IMIN, and a non-display area VDR in which the effective image data IMIN is not displayed. The known image data KIP is added to the non-display area VDR.

[0026] Since the effective image data IMIN changes depending on the display image, the CRC expected value of the effective image data after processing cannot be known in advance. According to this embodiment, the known image data KIP is added to the non-display area VDR, so that the known image data KIP that is unrelated to the display image can be used for CRC judgment. In other words, it is possible to obtain the CRC expected value of the known image data after processing in advance.

[0027] The image area corresponding to the image data TGIN to be processed is an image area corresponding to one frame of image data TGIN to be processed, and is the area of ​​VH×VV in FIG. 2 or FIG. 3. The non-display area VDR is an area corresponding to the blanking period as described above, and can also be said to be an area other than the effective image area ADR in the image area corresponding to the image data TGIN to be processed. The image area means an area in an xy plane when the pixel position in the horizontal scanning direction is x and the pixel position in the vertical scanning direction is y. The pixel positions x and y are managed by a pixel clock, a horizontal synchronization signal, and a vertical synchronization signal. That is, a frame is managed based on a vertical synchronization signal, the number of lines, i.e., pixel position y, is managed based on the horizontal synchronization signal in the frame, and the pixel position x is managed based on the number of pulses of the pixel clock in each horizontal scanning period.

[0028] In this embodiment, the non-display area VDR is an area corresponding to a blanking period.

[0029] Since the blanking period is a period in which no valid image data exists, even if known image data KIP is added to the non-display area VDR corresponding to the blanking period, the known image data KIP is not displayed on the display device. By using such a non-display area VDR, CRC judgment using the known image data KIP is possible.

[0030] The region corresponding to the blanking period is a region other than the effective image region ADR, for example, a region corresponding to the front porch period and the back porch period as shown in Fig. 2. However, the region corresponding to the blanking period is not limited to Fig. 2, and may include regions between the effective image regions ADR1 to ADR3, etc., in addition to the regions corresponding to the front porch period and the back porch period as shown in Fig. 3.

[0031] Furthermore, in this embodiment, the effective image area may be divided into first to m-th effective image areas ADR1 to ADRm, where m is an integer equal to or greater than 2. The non-display area may include areas between the first to m-th effective image areas ADR1 to ADRm. Note that an example where m=3 is shown in FIG. 3.

[0032] According to this embodiment, known image data KIP is also added to the areas between the first to m-th effective image areas ADR1 to ADRm, and the CRC calculation circuit 20 can calculate the CRC value CC from the known image data KIP. As a result, the known image data KIP is more dispersed and arranged than in the example of Fig. 2, making it easier to detect temporary errors due to noise, etc.

[0033] In this embodiment, the circuit device 100 also includes a register 40. The register 40 stores a CRC expected value CE in advance.

[0034] According to this embodiment, the register 40 can store a CRC expected value CE that is calculated in advance by a software tool or the like (described later). Then, the determination circuit 30 can perform CRC determination using the CRC expected value CE that is stored in the register 40 in advance.

[0035] 2. First detailed configuration example Fig. 4 is a first detailed configuration example of the circuit device 100. The circuit device 100 includes a processing circuit 110, a receiving circuit 120, a transmitting circuit 130, and an interface circuit 140. Below, parts that differ from Fig. 1 will be described, and descriptions of parts that are similar to Fig. 1 will be omitted as appropriate.

[0036] The processing circuit 110 includes an image processing circuit 10, a CRC calculation circuit 20, a judgment circuit 30, a register 40, a known image adding circuit 50, and a known image removing circuit 60. The processing circuit 110 is a logic circuit. For example, each circuit included in the processing circuit 110 may be configured by an individual logic circuit. Alternatively, the processing circuit 110 may be a processor such as a DSP, and a program or instruction set describing the function of each circuit may be stored in a memory (not shown), and the function of each circuit may be realized by the processor executing the program or instruction set. DSP is an abbreviation for Digital Signal Processor.

[0037] The receiving circuit 120 receives valid image data IMIN from a processing device external to the circuit device 100. The receiving circuit 120 may be a receiving circuit of various communication interfaces, examples of which include LVDS, DVI, display port, GMSL, and GVIF. LVDS stands for Low voltage differential signaling, DVI stands for Digital Visual Interface, GMSL stands for Gigabit Multimedia Serial Link, and GVIF stands for Gigabit Video InterFace.

[0038] The known image adding circuit 50 generates image data to be processed TGIN by adding known image data KIP to the valid image data IMIN. The known image data KIP is written in advance in a memory (not shown) from an external processing device or the like via the receiving circuit 120 or the interface circuit 140, and the known image adding circuit 50 adds the known image data KIP stored in the memory to the non-display area VDR. Note that the known image adding circuit 50 may be omitted. In that case, the external processing device transmits the image data to be processed TGIN to which the known image data KIP has been added to the circuit device 100, and the receiving circuit 120 outputs the received image data to be processed TGIN to the image processing circuit 10.

[0039] The known image removal circuit 60 extracts the processed effective image data by removing the processed known image data from the non-display area VDR of the processed image data TGQ. The known image removal circuit 60 outputs the extracted processed effective image data IMQ.

[0040] The transmitting circuit 130 transmits the processed valid image data IMQ to a device downstream of the circuit device 100. The transmitting circuit 130 may be a transmitting circuit of various communication interfaces, examples of which include a transmitting circuit of LVDS, DVI, DisplayPort, GMSL, or GVIF.

[0041] The interface circuit 140 performs communication between the host device of the circuit device 100 and the circuit device 100. The host device may be the same as or different from the processing device that transmits the valid image data IMIN to the circuit device 100. The interface circuit 140 receives a CRC expected value CE from the host device and writes the CRC expected value CE to the register 40. The interface circuit 140 also outputs a determination signal DTQ determined by the determination circuit 30 using the CRC expected value CE written to the register 40 to the host device. The interface circuit 140 may be an interface circuit for various communication interfaces, and an example is an interface circuit such as I2C or SPI. I2C is an abbreviation for Inter Integrated Circuit, and SPI is an abbreviation for Serial Peripheral Interface.

[0042] 5 is a flowchart of an image processing method executed by the circuit device 100. The image processing method includes steps S1 to S6.

[0043] In step S1, the known image adding circuit 50 generates image data TGIN to be processed by adding known image data KIP to the valid image data IMIN. In step S2, the image processing circuit 10 performs image processing on the image data TGIN to be processed, and outputs the result as processed image data TGQ. In step S3, the CRC calculation circuit 20 calculates a CRC value CC from the processed known image data of the image data TGIN to be processed. In step S4, the judgment circuit 30 obtains a CRC expected value CE from the register 40. In step S5, the judgment circuit 30 compares the CRC value CC with the CRC expected value CE to judge whether the image processing is correct. In step S6, the known image removing circuit 60 removes the processed known image data from the processed image data TGQ to extract the processed valid image data. Note that, when the circuit device 100 includes a plurality of image processing circuits as shown in FIG. 7 described later, steps S2 to S5 in FIG. 5 are repeated for the number of the image processing circuits.

[0044] In the above-described embodiment, the circuit device 100 includes a known image adding circuit 50. The known image adding circuit 50 adds known image data KIP to effective image data IMIN, and outputs processing target image data TGIN.

[0045] According to this embodiment, the known image adding circuit 50 adds known image data KIP unrelated to the display image to the valid image data IMIN corresponding to the display image, thereby making it possible to perform CRC check using the known image data KIP.

[0046] In this embodiment, the circuit device 100 also includes a known image removal circuit 60. The known image removal circuit 60 removes the processed known image data from the processed image data TGQ output by the image processing circuit 10, thereby extracting the processed effective image data.

[0047] According to this embodiment, known image data that is not displayed on the display device is removed after the image processing pipeline, so that only valid image data to be displayed on the display device can be transmitted to a device downstream of the circuit device 100.

[0048] 3. Example of modified configuration Fig. 6 shows a modified configuration example of the circuit device 100. In this modified configuration example, the circuit device 100 includes a CRC extraction circuit 70 instead of the register 40 in Fig. 1. This modified configuration example is applicable to either the first detailed configuration example in Fig. 4 or the second detailed configuration example in Fig. 7 described later.

[0049] In Fig. 6, the CRC expected value CE is added together with known image data KIP to the non-display area VDR of the image data to be processed TGIN. When the circuit device 100 includes a known image adding circuit 50 as in Fig. 4, the known image adding circuit 50 adds the known image data KIP and the CRC expected value CE to the valid image data IMIN. When an external processing device transmits the image data to be processed TGIN to the circuit device 100, the external processing device generates the image data to be processed TGIN by adding the known image data KIP and the CRC expected value CE to the valid image data IMIN.

[0050] The CRC extraction circuit 70 extracts the CRC expected value CE from the non-display area VDR of the processing target image data TGIN, and outputs the CRC expected value CE to the determination circuit 30.

[0051] When another image processing circuit is provided in the stage preceding the image processing circuit 10, the CRC extraction circuit 70 may extract the CRC expected value CE from the processing target image data input to the image processing circuit 10, or may extract the CRC expected value CE from processing target image data including the first known image data before any image processing is performed. In the former case, data that will be the correct CRC expected value CE at the time of input to the image processing circuit 10 is added to the non-display area VDR, taking into account the image processing in the previous stage. In the latter case, the CRC expected value CE is added to the non-display area VDR in the processing target image data including the first known image data before any image processing is performed.

[0052] In the above embodiment, the CRC expected value CE is added to the non-display area VDR together with the known image data KIP.

[0053] According to this embodiment, there is no need to store the CRC expected value CE in advance in the register 40 in Fig. 1, and the CRC extraction circuit 70 can obtain the CRC expected value CE from the processing target image data TGIN. For example, an external processing device may add the CRC expected value to the processing target image data together with the known image data and transmit the added data to the circuit device 100. In this case, the known image adding circuit 50 of the circuit device 100 is omitted.

[0054] 4. Second detailed configuration example Fig. 7 is a second detailed configuration example of the circuit device 100. The circuit device 100 includes a processing circuit 110, a receiving circuit 120, a transmitting circuit 130, and an interface circuit 140. Below, parts different from Fig. 1 or Fig. 4 will be described, and descriptions of parts similar to Fig. 1 or Fig. 4 will be omitted as appropriate.

[0055] The processing circuit 110 includes a first image processing circuit 11, a second image processing circuit 12, a third image processing circuit 13, a first CRC calculation circuit 21, a second CRC calculation circuit 22, a third CRC calculation circuit 23, a first judgment circuit 31, a second judgment circuit 32, a third judgment circuit 33, a register 40, a known image adding circuit 50, and a known image removing circuit 60. The processing circuit 110 may include first to n-th image processing circuits, first to n-th CRC calculation circuits, and first to n-th judgment circuits. n is an integer equal to or greater than 2. FIG. 7 shows an example where n=3.

[0056] The register 40 stores a first CRC expected value CE1, a second CRC expected value CE2, and a third CRC expected value CE3.

[0057] The first image processing circuit 11 performs a first image processing on the processing target image data TGIN and outputs the result as first processed image data TGQ1. The first image processing is an image processing that changes the content of the image. The first processed image data TGQ1 includes first processed effective image data, which is the result of the first image processing being performed on the effective image data IMIN, and first processed known image data, which is the result of the first image processing being performed on the known image data KIP.

[0058] The first CRC calculation circuit 21 calculates a first CRC value CC1 from the first processed known image data. The first judgment circuit 31 compares the first CRC value CC1 with a first CRC expected value CE1 to judge whether the first image processing is correct or not, and outputs the judgment result as a first judgment signal DTQ1.

[0059] The second image processing circuit 12 performs the second image processing on the first processed image data TGQ1 and outputs the result as the second processed image data TGQ2. The second image processing is an image processing that changes the content of the image. The second image processing may be, for example, an image processing of a different type from the first image processing, or may be an image processing of the same type as the first image processing but with different image processing parameters. The second processed image data TGQ2 includes the second processed effective image data, which is a result of the first processed effective image data being subjected to the second image processing, and the second processed known image data, which is a result of the first processed known image data being subjected to the second image processing. Thus, in the second detailed configuration example, the first processed known image data output by the first image processing circuit 11 in the preceding stage is used as known image data in the second image processing circuit 12 in the following stage. The second image processing circuit 12 outputs the second processed known image data by performing the second image processing on the known image data.

[0060] The second CRC calculation circuit 22 calculates a second CRC value CC2 from the second processed known image data. The second judgment circuit 32 compares the second CRC value CC2 with a second CRC expected value CE2 to judge whether the second image processing is correct or not, and outputs the judgment result as a second judgment signal DTQ2.

[0061] The third image processing circuit 13 performs the third image processing on the second processed image data TGQ2 and outputs the result as the third processed image data TGQ3. The third image processing is an image processing that changes the content of the image. The third image processing may be, for example, an image processing of a different type from the first image processing or the second image processing, or may be an image processing of the same type as the first image processing or the second image processing but with different image processing parameters. The third processed image data TGQ3 includes the third processed effective image data, which is a result of the third image processing being performed on the second processed effective image data, and the third processed known image data, which is a result of the third image processing being performed on the second processed known image data. Thus, in the second detailed configuration example, the second processed known image data output by the second image processing circuit 12 in the previous stage is used as known image data in the next third image processing circuit 13. The third image processing circuit 13 outputs the third processed known image data by performing the third image processing on the known image data.

[0062] The third CRC calculation circuit 23 calculates a third CRC value CC3 from the known image data after the third processing. The third judgment circuit 33 judges whether the third image processing is correct by comparing the third CRC value CC3 with a third CRC expected value CE3, and outputs the judgment result as a third judgment signal DTQ3.

[0063] The interface circuit 140 transmits the first determination signal DTQ1, the second determination signal DTQ2, and the third determination signal DTQ3 to the host device.

[0064] In the above embodiment, the circuit device 100 includes a receiving circuit 120, a known image adding circuit 50, the first to nth image processing circuits, the first to nth CRC calculation circuits, the first to nth decision circuits, the known image removing circuit 60, and a transmitting circuit 130. The receiving circuit 120 receives valid image data IMIN. The known image adding circuit 50 adds known image data KIP to the valid image data IMIN and outputs the processing target image data TGIN. The first image processing circuit 11 outputs the first processed image data TGQ1 by performing the first image processing on the processing target image data TGIN. The first processed image data TGQ1 includes the first processed valid image data that is the valid image data IMIN that has been subjected to the first image processing, and the first processed known image data that is the known image data KIP that has been subjected to the first image processing. i is an integer that is 2 or more and n or less. The i-th image processing circuit outputs the i-th processed image data TGQi by performing the i-1th processed image data TGQi-1. The i-th processed image data TGQi includes the i-th processed valid image data, which is the i-1-th processed valid image data that has been subjected to the i-th image processing, and the i-th processed known image data, which is the i-1-th processed known image data that has been subjected to the i-th image processing. k is an integer between 1 and n. The k-th CRC calculation circuit obtains the k-th CRC value CCk from the k-th processed known image data. The k-th decision circuit compares the k-th CRC expected value CEk of the k-th processed known image data with the k-th CRC value CCk to decide whether the k-th image processing is correct. The known image removal circuit 60 extracts the n-th processed valid image data by removing the n-th processed known image data from the n-th processed image data TGQn. The transmission circuit 130 transmits the n-th processed valid image data IMQ extracted by the known image removal circuit 60.

[0065] According to this embodiment, the first to n-th image processing circuits are included in an image processing pipeline, and error detection by CRC judgment is performed for each image processing circuit on the image processing pipeline. This makes it possible to detect which image processing circuit in the image processing pipeline has an abnormality. In addition, since the error detection method can be unified to CRC judgment throughout the image processing pipeline, it is not necessary to develop a dedicated error detection method for each image processing, and the development of the error detection method is simplified.

[0066] 5. Software Tools 8 shows an example of the configuration of a processing device 300 that executes a software tool for generating a CRC expected value. The processing device 300 includes a processor 310 and a storage device 320. The processing device 300 is, for example, an information processing device such as a personal computer, or a portable information processing terminal such as a tablet terminal.

[0067] The storage device 320 is, for example, a semiconductor memory, a hard disk drive, or an optical disk drive. The storage device 320 stores known image data KIP, an area parameter ARP, first to n-th image processing parameters PAR1 to PARn, and a software tool program STL. The area parameter ARP indicates the position of the non-display area VDR in which the known image data KIP is placed. The first to n-th image processing parameters PAR1 to PARn are setting parameters for setting the operations or contents of the first to n-th image processing. The software tool program STL is a program in which the process of generating a CRC expected value is described.

[0068] The processor 310 is a CPU, a microcomputer, a DSP, or the like. CPU stands for Central Processing Unit, and DSP stands for Digital Signal Processor. The processor 310 executes the software tool program STL read from the storage device 320 to obtain the first to n-th CRC expected values ​​CE1 to CEn from the known image data KIP. For example, the software tool program STL describes the processing contents in the first to n-th image processing circuits and the first to n-th CRC calculation circuits. The processor 310 executes the software tool program STL to execute the same processing as the first to n-th image processing circuits, obtain the known image data after the first to n-th processing, and execute the same processing as the first to n-th CRC calculation circuits to calculate the first to n-th CRC values. The processor 310 outputs the first to n-th CRC values ​​as the first to n-th CRC expected values ​​CE1 to CEn.

[0069] 6.Electronic equipment 9 shows a first configuration example of an electronic device 500 to which the circuit device 100 is applied. The electronic device 500 includes a processing device 510 and an electro-optical device 520.

[0070] The electro-optical device 520 is a liquid crystal display, an EL display, or the like. EL is an abbreviation for Electro Luminescence. The electronic device 500 may be any of various devices equipped with such a display, and examples thereof include a display provided on an in-vehicle cluster panel, an information processing device such as a personal computer, or a portable information processing terminal such as a tablet terminal.

[0071] The electro-optical device 520 includes a display controller 521, a driver 522, and an electro-optical panel 523. The processing device 510 is a CPU, a microcomputer, a DSP, or the like, and transmits image data of a display image to the display controller 521. The display controller 521 performs image processing on the image data, and outputs a display control signal together with the resulting image data to the driver 522. The display control signal is, for example, a vertical synchronization signal, a horizontal synchronization signal, and a pixel clock signal. The driver 522 drives the electro-optical panel 523 based on the received image data and display control signal.

[0072] The circuit device 100 of this embodiment can be applied to, for example, the display controller 521 in FIG.

[0073] 10 shows a second configuration example of an electronic device 500 to which the circuit device 100 is applied. The electronic device 500 includes a processing device 510 and a HUD 530. HUD is an abbreviation for Head Up Display.

[0074] The HUD 530 includes a HUD controller 531 and a projection device 532. The processing device 510 transmits image data of a display image to the HUD controller 531. The HUD controller 531 performs image processing on the image data, and outputs a display control signal to the projection device 532 together with the resulting image data. The projection device 532 includes, for example, a driver, a liquid crystal display panel, a light source, and an optical device. The driver displays an image on the liquid crystal display panel based on the image data and the display control signal received from the HUD controller 531. The light source emits projection light to the liquid crystal display panel, and the projection light transmitted through the liquid crystal display panel is incident on the optical device. The optical device projects the projection light transmitted through the liquid crystal display panel onto a screen. The screen is, for example, the windshield of a moving object, but a dedicated screen may be provided. The moving object is an automobile, an airplane, a ship, or the like.

[0075] The circuit device 100 of this embodiment can be applied to, for example, the HUD controller 531 in FIG.

[0076] The circuit device of the present embodiment described above includes an image processing circuit, a CRC calculation circuit, and a judgment circuit. The image processing circuit receives processing target image data in which known image data has been added to valid image data, and performs image processing on the processing target image data to output processed valid image data, which is valid image data that has been subjected to image processing, and processed known image data, which is known image data that has been subjected to image processing. The CRC calculation circuit finds a CRC value from the processed known image data. The judgment circuit compares the CRC value with a CRC expected value of the processed known image data to judge whether the image processing is correct or not.

[0077] According to this embodiment, even if the image processing changes the content of the image, the correctness of the image processing can be judged using CRC. Various image processing is performed in the image processing pipeline, and CRC judgment can be applied to any image processing circuit. This makes it possible to detect which image processing circuit in the image processing pipeline has an abnormality. In addition, since the error detection method can be unified to CRC judgment throughout the image processing pipeline, it is no longer necessary to develop a dedicated error detection method for each image processing, and the development of the error detection method is simplified.

[0078] In the present embodiment, the image area corresponding to the image data to be processed may include an effective image area corresponding to the effective image data and a non-display area in which the effective image data is not displayed. The known image data may be added to the non-display area.

[0079] According to this embodiment, by adding known image data to the non-display area, it is possible to use known image data that is unrelated to the displayed image for CRC judgment. In other words, it is possible to obtain the CRC expected value of the processed known image data in advance.

[0080] In this embodiment, the non-display area may be an area corresponding to a blanking period.

[0081] Since a blanking period is a period in which no valid image data exists, even if known image data is added to a non-display area corresponding to a blanking period, the known image data will not be displayed on the display device. By using such a non-display area, CRC check using known image data is possible.

[0082] Furthermore, in this embodiment, the effective image area may be divided into first to mth effective image areas, where m is an integer equal to or greater than 2. The non-display area may include an area between the first to mth effective image areas.

[0083] According to this embodiment, known image data is also added to the areas between the first to mth effective image areas, and the CRC calculation circuit can calculate a CRC value from the known image data. This allows the known image data to be more dispersed than when the effective image area is not divided, making it easier to detect temporary errors due to noise, etc.

[0084] The circuit device of this embodiment may also include a register that stores a CRC expected value in advance.

[0085] According to this embodiment, the register can store a CRC expected value that is calculated in advance by a software tool or the like (described later).Then, the determination circuit can execute CRC determination using the CRC expected value that is stored in the register in advance.

[0086] Also, in this embodiment, the CRC expected value may be added to the non-display area together with the known image data.

[0087] According to this embodiment, it is not necessary to store the CRC expected value in a register beforehand, and it is possible to obtain the CRC expected value from the image data to be processed.

[0088] The circuit device of this embodiment may also include a known image adding circuit, which may add known image data to the valid image data and output the image data to be processed.

[0089] According to this embodiment, the known image adding circuit adds known image data unrelated to the display image to the valid image data corresponding to the display image, thereby making it possible to perform CRC check using the known image data.

[0090] The circuit device of the present embodiment may also include a known image removal circuit. The known image removal circuit may extract the processed effective image data by removing the processed known image data from the processed image data output by the image processing circuit.

[0091] According to this embodiment, known image data that is not displayed on the display device is removed after the image processing pipeline, so that only valid image data to be displayed on the display device can be transmitted to a device downstream of the circuit device.

[0092] The circuit device of the present embodiment may include a first image processing circuit, which is the image processing circuit, and a second image processing circuit. The first image processing circuit may receive image data to be processed and perform a first image processing, which is image processing, on the image data to be processed, to output first processed image data including first processed effective image data, which is processed effective image data, and first processed known image data, which is processed known image data. The second image processing circuit may perform a second image processing on the first processed image data, to output second processed image data including second processed effective image data, which is the first processed effective image data subjected to the second image processing, and second processed known image data, which is the first processed known image data subjected to the second image processing.

[0093] The circuit device of this embodiment may include a first CRC calculation circuit, which is the CRC calculation circuit, a first judgment circuit, which is the judgment circuit, a second CRC calculation circuit, and a second judgment circuit. The first CRC calculation circuit may calculate a first CRC value, which is the CRC value. The first judgment circuit may judge whether the first image processing is correct by comparing the first CRC value with a first CRC expected value, which is the CRC expected value. The second CRC calculation circuit may obtain a second CRC value from the second processed known image data. The second judgment circuit may judge whether the second image processing is correct by comparing the second CRC value with a second CRC expected value of the second processed known image data.

[0094] The circuit device of this embodiment may include a receiving circuit that receives valid image data, a known image adding circuit, first to nth image processing circuits, first to nth CRC calculation circuits, first to nth judgment circuits, a known image removing circuit, and a transmitting circuit, where n is an integer equal to or greater than 2. The known image adding circuit may add known image data to the valid image data and output the processing target image data. A first image processing circuit of the first to nth image processing circuits may perform a first image processing on the processing target image data, and output first processed image data including first processed valid image data which is valid image data that has been subjected to the first image processing, and first processed known image data which is known image data that has been subjected to the first image processing. The ith image processing circuit of the first to nth image processing circuits may perform the ith image processing on the i-1th processed image data, thereby outputting the ith processed image data including the ith processed valid image data which is the i-1th processed valid image data subjected to the ith image processing, and the ith processed known image data which is the i-1th processed known image data subjected to the ith image processing. i is an integer of 2 or more and n or less. The kth CRC calculation circuit of the first to nth CRC calculation circuits may obtain the kth CRC value from the kth processed known image data. k is an integer of 1 or more and n or less. The kth judgment circuit of the first to nth judgment circuits may judge the correctness of the kth image processing by comparing the kth CRC expected value of the kth processed known image data with the kth CRC value. The known image removal circuit may extract the nth processed valid image data by removing the nth processed known image data from the nth processed image data. The transmission circuit may transmit the nth processed valid image data extracted by the known image removal circuit.

[0095] According to these embodiments, a plurality of image processing circuits are included in the image processing pipeline, and error detection by CRC judgment is performed for each image processing circuit on the image processing pipeline. This makes it possible to detect which image processing circuit in the image processing pipeline has an abnormality. In addition, since the error detection method can be unified to CRC judgment throughout the image processing pipeline, it is no longer necessary to develop a dedicated error detection method for each image processing, and the development of the error detection method is simplified.

[0096] Moreover, an electronic device according to the present embodiment includes any of the circuit devices described above.

[0097] In addition, the image processing method of this embodiment performs image processing on processing target image data in which known image data has been added to valid image data, and outputs processed valid image data, which is valid image data that has been subjected to image processing, and processed known image data, which is known image data that has been subjected to image processing. The image processing method finds a CRC value from the processed known image data. The image processing method judges whether the image processing is correct by comparing the CRC value with an expected CRC value of the processed known image data.

[0098] Although the present embodiment has been described in detail as above, it will be easily understood by those skilled in the art that many modifications are possible that do not substantially deviate from the novel matters and effects of the present disclosure. Therefore, all such modifications are intended to be included in the scope of the present disclosure. For example, a term described at least once in the specification or drawings together with a different term having a broader meaning or synonymy can be replaced with that different term anywhere in the specification or drawings. All combinations of the present embodiment and modifications are also included in the scope of the present disclosure. Furthermore, the configuration or operation of a circuit device or electronic device, or the processing procedure of an image processing method, are not limited to those described in the present embodiment, and various modifications are possible. [Explanation of symbols]

[0099] 10...image processing circuit, 11...first image processing circuit, 12...second image processing circuit, 13...third image processing circuit, 20...CRC calculation circuit, 21...first CRC calculation circuit, 22...second CRC calculation circuit, 23...third CRC calculation circuit, 30...judgment circuit, 31...first judgment circuit, 32...second judgment circuit, 33...third judgment circuit, 40...register, 50...known image addition circuit, 60...known image removal circuit, 70...CRC extraction circuit, 100...circuit device, 110...processing circuit, 120...receiving circuit, 130...transmitting circuit, 140...interface circuit, 300...processing device, 310...processor, 320...storage device, 500...electronic device, 510...processing device, 520...electro-optical device, 521...display controller, 522...driver, 52 3...electro-optical panel, 530...HUD, 531...HUD controller, 532...projection device, ADR...effective image area, CC...CRC value, CC1...first CRC value, CC2...second CRC value, CC3...third CRC value, CE...expected CRC value, CE1...first expected CRC value, CE2...second expected CRC value, CE3...third expected CRC value, DTQ...determination signal, DTQ1...first determination signal, DTQ2...second determination signal, DTQ3...third determination signal, IMIN...effective image data, IMQ...processed effective image data, KIP...known image data, TGIN...image data to be processed, TGQ...processed image data, TGQ1...first processed image data, TGQ2...second processed image data, TGQ3...third processed image data, VDR...non-display area

Claims

1. an image processing circuit which receives as input image data to be processed in which known image data has been added to effective image data, and performs image processing on the image data to be processed, thereby outputting processed effective image data, which is the effective image data that has been subjected to the image processing, and processed known image data, which is the known image data that has been subjected to the image processing; a CRC calculation circuit for determining a CRC value from the processed known image data; a determination circuit that determines whether the image processing is correct by comparing the CRC value calculated by the CRC calculation circuit with a CRC expected value, which is the CRC value of the processed known image data when the image processing is normal; A circuit device comprising:

2. 2. The circuit device according to claim 1, the image area corresponding to the processing target image data includes an effective image area corresponding to the effective image data and a non-display area in which the effective image data is not displayed, A circuit device, characterized in that the known image data is added to the non-display area.

3. 3. The circuit device according to claim 2, The non-display area is an area corresponding to a blanking period.

4. 3. The circuit device according to claim 2, The effective image area is divided into first to m-th effective image areas (m is an integer of 2 or more), The circuit device is characterized in that the non-display area includes an area between the first to mth effective image areas.

5. 5. The circuit arrangement according to claim 1, A circuit device comprising: a register for storing the CRC expected value in advance.

6. A circuit arrangement according to any one of claims 2 to 4, A CRC extraction circuit is included, The image data to be processed, to which the CRC expected value has been added together with the known image data in the non-display area, is input to the image processing circuit; The CRC extraction circuit includes: a circuit device for extracting the CRC expected value from the image data to be processed before the image processing is performed, and outputting the extracted CRC expected value to the determination circuit.

7. 7. A circuit arrangement according to claim 1, a known image adding circuit for adding the known image data to the effective image data and outputting the processing target image data;

8. A circuit arrangement according to any one of claims 1 to 7, A circuit device comprising: a known image removal circuit that removes the processed known image data from the processed image data output by the image processing circuit, thereby extracting the processed effective image data.

9. A circuit arrangement according to any one of claims 1 to 8, A first image processing circuit which is the image processing circuit; A second image processing circuit; Including, The first image processing circuit is the processing target image data is input, and a first image processing, which is the image processing, is performed on the processing target image data, thereby outputting first processed image data including first processed effective image data, which is the processed effective image data, and first processed known image data, which is the processed known image data; The second image processing circuit is A circuit device characterized in that, by performing a second image processing on the first processed image data, second processed image data including second processed effective image data which is the first processed effective image data subjected to the second image processing, and second processed known image data which is the first processed known image data subjected to the second image processing is output.

10. 10. The circuit arrangement according to claim 9, the CRC calculation circuit, a first CRC calculation circuit that calculates a first CRC value that is the CRC value; a first determination circuit that determines whether the first image processing is correct by comparing the first CRC value with a first CRC expected value that is the CRC expected value; a second CRC calculation circuit for calculating a second CRC value from the second processed known image data; a second determination circuit that determines whether the second image processing is correct by comparing the second CRC value calculated by the second CRC calculation circuit with a second CRC expected value that is the second CRC value of the known image data after the second processing when the second image processing is normal; A circuit device comprising:

11. a receiving circuit for receiving valid image data; a known image adding circuit for adding known image data to the valid image data and outputting image data to be processed; first to n-th image processing circuits (n is an integer of 2 or more); first to n-th CRC calculation circuits; First to nth decision circuits; a known image removal circuit; A transmission circuit; Including, The first image processing circuit of the first to nth image processing circuits is performing a first image processing on the processing target image data, and outputting first processed image data including first processed effective image data, which is the effective image data that has been subjected to the first image processing, and first processed known image data, which is the known image data that has been subjected to the first image processing; The ith image processing circuit (i is an integer between 2 and n) of the first to nth image processing circuits includes: performing an ith image processing on the (i-1)th processed image data, outputting ith processed image data including ith processed effective image data which is the (i-1)th processed effective image data which has been subjected to the ith image processing, and ith processed known image data which is the (i-1)th processed known image data which has been subjected to the ith image processing; The kth CRC calculation circuit (k is an integer between 1 and n) of the first to nth CRC calculation circuits is A k-th CRC value is obtained from the k-th processed known image data; The k-th judgment circuit of the first to n-th judgment circuits is determining whether the kth image processing is correct or not by comparing a kth CRC expected value, which is the kth CRC value of the kth processed known image data when the first to kth image processing are normal, with the kth CRC value calculated by the kth CRC calculation circuit; The known image removal circuit includes: extracting the n-th processed effective image data by removing the n-th processed known image data from the n-th processed image data; The transmission circuit includes: A circuit device comprising: a known image removal circuit that transmits the nth processed effective image data extracted by the known image removal circuit.

12. The circuit device described in any one of claims 1 to 11, characterized in that it is a head-up display controller that controls a head-up display.

13. 12. An electronic device comprising the circuit device according to claim 1.

14. performing image processing on the processing target image data in which known image data has been added to valid image data, thereby outputting processed valid image data, which is the valid image data that has been subjected to the image processing, and processed known image data, which is the known image data that has been subjected to the image processing; A CRC value is obtained from the processed known image data; An image processing method characterized in that the correctness of the image processing is determined by comparing the obtained CRC value with a CRC expected value, which is the CRC value of the processed known image data when the image processing is normal.

Images