Processing system using shared memory, and processing method using shared memory

Abstract

To provide a processing system and a processing method which execute requests / responses of processing between a plurality of nodes via a shared memory without dropping any requests / responses, under environment in which busy control by hardware is not performed.SOLUTION: In a processing system 10 using a shared memory, a common RAM3 has data request flags 1, 2 in which a CPU1 in a data request side writes "55H", and data response flags 1, 2 in which a CPU2 in a response side writes "EEH". The CPU1 writes the data in an order of the data request flag 1→2 (S13, S14), and the CPU2 reads the data in the order of the data request flag 2→1 (S15, S16). Moreover, the CPU2 writes the data in the order of the data response flag 1→2 (S20, S21), and the CPU1 reads the data in the order of the data response flag 2→1 (S22, S23).SELECTED DRAWING: Figure 3

Description

[Technical field]

[0001] The present invention relates to a technology for executing requests and responses for processing between multiple nodes (devices, equipment, etc.) via a shared memory. [Background technology]

[0002] Patent Document 1 discloses a technique that enables memory access without deadlock by using one shared memory in each CPU of a plurality of nodes.

[0003] For example, in "FL-net" as shown in FIG. 1, a common RAM 3 accessible from CPUs 1 and 2 of each node is used as a shared memory.

[0004] In other words, the common RAM 3 is regarded as a memory block that can be commonly recognized and accessed by the CPUs of all nodes (devices, equipment) connected to, for example, the "FL-net," i.e., a global shared memory space. At this time, the common RAM 3 is used for requests and responses for processing such as data transfers in response to data requests between the CPUs 1 and 2. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] Patent Publication No. 06-110848 Summary of the Invention [Problem to be solved by the invention]

[0006] (1) The aforementioned common RAM 3 has busy control in hardware (a mechanism that allows read and write even if access from CPUs 1 and 2 overlaps), but without this, problems with data transfer, etc. may occur.

[0007] That is, when CPU accesses to the same memory address overlap (simultaneous access), for example, CPU1 cannot write data, and CPU2 cannot read the data that should have been written.

[0008] (2) Details will be explained with reference to Figure 2. Here, the procedure for data transfer in response to a data request from CPU 1 to CPU 2 is shown. Note that common RAM 3 is assumed to have been cleared to "0" during initialization processing.

[0009] S01, S02: When processing starts, the CPU 1 clears the data response flag "address: 00000001H" in the common RAM (bus width: 8 bits) 3 before requesting data from the CPU 2. Specifically, it writes "00H" to the data response flag (S01).

[0010] Thereafter, the CPU1 writes "55H (data request)" to the data request flag "address: 00000000H" and notifies the CPU2 that it has requested data (S02).

[0011] S03, S04: CPU 2 waits for polling of the data request flag (S03), and when it reads the "55H" written in S02, it sets the transfer data to "addresses: 00000100H-000001FFH" in common RAM 3 (S04).

[0012] S05, S06: The CPU 2 writes "00H" to the data request flag to clear it (S05). After that, it writes "EEH (data response)" to the data response flag to notify the CPU 1 that the transfer data has been set (S06).

[0013] S07, S08: The CPU 1 waits for polling of the data response flag (S07), and if "EEH" written in S06 is present, it recognizes that the transfer data has been set in the common RAM 3 (S07). After that, the CPU 1 takes in the transfer data and ends the process (S08).

[0014] (3) However, if the timing at which CPU1 writes "55H" to the data request flag in S02 and the timing at which CPU2 reads by polling in S03 overlap, CPU1 may not be able to write "55H" to the data request flag, which may result in a failure to transfer the data.

[0015] Furthermore, if the timing at which CPU2 writes "EEH" to the data response flag in S06 overlaps with the timing at which CPU1 reads by polling in S07, CPU2 may not be able to write "EEH" to the data response flag, and the data transfer may not be completed.

[0016] The present invention has been made to solve such conventional problems, and its problem to be solved is to execute processing requests and responses between multiple nodes without any dropouts via shared memory in an environment where hardware busy control is not performed. [Means for solving the problem]

[0017] (1) One aspect of the present invention is a system for executing processing requests and responses between multiple nodes via a shared memory, The shared memory includes a plurality of request flags to which the requester of the process writes the request; a plurality of response flags in which a responding side of the process writes the response; having When the responding side reads the request of any of the request flags, it sets the request contents in the shared memory, The request side is characterized in that, when it reads the response of any one of the response flags, it obtains the request contents from the shared memory.

[0018] (2) Another aspect of the present invention is a method for executing a request and response of a process between multiple nodes via a shared memory, comprising the steps of: a requester of the process writing the request in a plurality of requests; a responding side of the transaction writing the response to a plurality of response flags; a step in which the responding side sets the request contents in the shared memory if the responding side reads the request of any of the request flags; the request side acquiring the request content from the shared memory if the request side reads the response of any of the response flags; The present invention is characterized in that it has the following features. Effect of the Invention

[0019] According to the present invention, in an environment where busy control is not performed by hardware, it becomes possible to execute processing requests and responses between multiple nodes without any dropouts via shared memory. [Brief description of the drawings]

[0020] [Figure 1] A configuration diagram of a processing method using a common RAM between the CPUs of each node. [Diagram 2] FIG. 1 is a flow chart showing the procedure for data transfer between CPUs using a conventional common RAM. [Diagram 3] FIG. 4 is a process diagram showing a procedure for data transfer between CPUs using a shared memory according to an embodiment of the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0021] A processing system 10 using a shared memory according to an embodiment of the present invention will be described with reference to Fig. 3. Here, the same reference numerals as in Figs. 1 and 2 are used.

[0022] In the system 10, a common RAM 3 accessible from the CPUs 1 and 2 of each node is provided as a shared memory space. However, a measure for when busy control is not performed by hardware, that is, busy control by software, is provided.

[0023] That is, the common RAM 3 has a pair of data request flags 1 and 2 for writing requests for processing between the CPUs 1 and 2, such as data requests, and a pair of data response flags 1 and 2 for writing responses to the data requests.

[0024] Data request flag 1 is located at address "00000000H" in common RAM 3, while data request flag 2 is located at the same address "00000001H."

[0025] The data response flag 1 is located at address "00000002H" in the common RAM 3, while the data response flag 2 is located at the same address "00000003H".

[0026] <Processing Procedure> The busy control by the software will now be described. As an example, the procedure for data transfer from CPU1 to CPU2 in response to a data request will be described.

[0027] At this time, CPU1 is the data transfer requesting side, CPU2 is the data transfer responding side, and common RAM (bus width: 8 bits) 3 is cleared to "0" by initialization processing, as in Fig. 2. Note that the following steps S11 to S24 are executed by CPU1 and CPU2 accessing common RAM 3.

[0028] S11, S12: When processing starts, CPU1 clears data response flags 1 and 2 before requesting data from CPU2. Here, to clear data response flag 1 to "0", "00H" is written there (S11). Also, to clear data response flag 2 to "0", "00H" is written there as well (S12).

[0029] S13, S14: CPU1 writes "55H (data request)" to data request flags 1 and 2 in that order. That is, CPU1 first writes "55H" to data request flag 1, notifying CPU2 that it has requested data (S13). Next, CPU1 writes "55H" to data request flag 2, notifying CPU2 that it has requested data (S14).

[0030] S15, S16: The CPU 2 reads the data request flags 1 and 2 in the reverse order of the writes in S13 and S14. That is, the CPU 2 first reads the data request flag 2 (S15), and then reads the data request flag 1 (S16).

[0031] At this time, if either the read data request flag 1 or 2 is "55H", proceed to S17. On the other hand, if the read data request flag 1 or 2 is not "55H", that is, if "00H" is written in the data request flag 1 or 2, polling is repeated by repeating S15 and S16.

[0032] S17: The CPU 2 sets the transfer data in response to the data request of "55H" read in S15 / S16 to "addresses: 00000100H to 000001FFH" in the common RAM 3.

[0033] S18, S19: The CPU 2 writes "00H" to the data request flag 1 in order to clear it to "0" (S18). Also, the CPU 2 writes "00H" to the data request flag 2 in order to clear it to "0" (S19).

[0034] S20, 21: To send a data response to the common CPU1, CPU2 writes "EEH (data response)" to data response flags 1 and 2 in that order. That is, CPU2 first writes "EEH" to data response flag 1, notifying CPU1 that a data response has been sent (S20). Next, CPU2 also writes "EEH" to data response flag 2, notifying CPU1 that a data response has been sent (S21).

[0035] S22, S23: The CPU 1 reads the data response flags 1 and 2 in the reverse order of the writes in S20 and S21. That is, the CPU 1 first reads the data response flag 2 (S22), and then reads the data response flag 1 (S23).

[0036] At this time, if either the read data response flag 1 or 2 has "EEH", proceed to S24. On the other hand, if the read data response flag 1 or 2 does not have "EEH", that is, if "00H" has been written to the data response flag 1 or 2, polling is repeated by repeating S22 and S23.

[0037] S24: The CPU 1 imports and acquires the delivery data, and ends the process.

[0038] <Action and effect> The busy control by software in FIG. 3 has the following advantages.

[0039] (1) As described above, CPU1 writes "55H (data request)" to the data request flags 1 and 2 (S13, S14). Meanwhile, CPU2 reads the data request flags in the reverse order of S13 and S14, that is, in the order of 2 and 1 (S15, S16).

[0040] As a result, a timing lag occurs in the write / read of "55H" for at least one of data request flags 1 and 2, which ensures that "55H" is written and can be read by CPU 2. Therefore, the data request is transmitted reliably from CPU 1 to CPU 2, and in this respect failure in data transfer can be avoided.

[0041] (2) Moreover, CPU2 writes "EEH" to the data response flags 1 and 2 (S20, S21). Meanwhile, CPU1 reads the data response flags in the reverse order of S20, S21, that is, in the order of 2 and 1 (S22, S23).

[0042] As a result, a timing lag occurs in the write / read of "EEH" for at least one of the data response flags 1 and 2, which ensures that "EEH" is written and can be read by CPU 1. Therefore, data transfer from CPU 2 to CPU 1 can be completed reliably, and data transfer failures can be avoided in this respect as well.

[0043] (3) Because CPU1 and CPU2 can read "55H" and "EEH" more reliably than before, data transfer failures can be avoided even in environments where hardware busy control is not performed, and data can be transferred between CPU1 and CPU2 via common RAM3 without any errors.

[0044] The present invention is not limited to the above embodiment, and may be modified within the scope of the claims. For example, the processing between the CPUs 1 and 2 via the common RAM 3 may be not only data transfer but also requests for other processing.

[0045] Also, the data request flags 1 and 2 are not limited to the order of S13 to S16 as long as the write and read order is reversed. For example, the data request flags 2 and 1 may be written in this order in S13 and S14, and the data request flags 1 and 2 may be read in this order in S15 and S16.

[0046] Similarly, the data response flags 1 and 2 may be written and read in the reverse order, and are not limited to the order of S20 to S23. For example, the data response flags 2 and 1 may be written in the order of S20 and S21, and the data response flags 1 and 2 may be read in the order of S22 and S23. [Explanation of symbols]

[0047] 1,2…CPU 3...Common RAM (shared memory) 10... Processing system using shared memory 10

Claims

1. A system for executing processing requests and responses between multiple nodes via a shared memory, The shared memory includes a plurality of request flags in which a requester of the process writes the existence of the request; a plurality of response flags in which the responding side of the process writes the presence of the response; having If the responding side reads the existence of the request in any of the request flags, it sets the contents of the response in the shared memory, If the requester reads the presence of the response in any of the response flags, the requester obtains the contents of the response from the shared memory; a write order of the request flags on the request side; A read order of the request flags on the response side; and is the opposite, A write order of the response flags on the response side; and A read order of the response flag group on the request side; and is the opposite 23. A processing system using a shared memory comprising:

2. The request side writes in the order of the request flags, The responding side reads the request flags in the reverse order of the writing of the requesting side.

2. The processing system using a shared memory according to claim 1.

3. The responding side writes according to the order of the response flags, The requester reads the response flags in the reverse order of the writes of the response flags.

2. The processing system using a shared memory according to claim 1.

4. The request side notifies the responder side each time it writes to each of the request flags, while The responding side sets the request contents in the shared memory every time it writes to each of the response flags, and notifies the requesting side of the request contents.

4. A processing system using the shared memory according to claim 1.

5. A method for executing a request and response for processing between multiple nodes via a shared memory, comprising: a requester of said process writing the existence of said request to a plurality of request flags; a responder of the process writing the existence of the response to a plurality of response flags; if the responding side reads the existence of the request in any of the request flags, it sets the contents of the response in the shared memory; if the requester reads the presence of the response in any of the response flags, obtaining the contents of the response from the shared memory; having a write order of the request flags on the request side; A read order of the request flags on the response side; and is the opposite, A write order of the response flags on the response side; and A read order of the response flag group on the request side; and is the opposite 23. A processing method using a shared memory, comprising:

Images