Liquid crystal display device and manufacturing method thereof

Abstract

To provide a liquid crystal display device and its manufacturing method capable of improving reliability.SOLUTION: A liquid crystal display device 1 includes: a shift register part 161 for successively fetching s-bit-width video signals for the row number of multiple pixels 12; a one-line latch part 162 for simultaneously outputting multiple video signals fetched by the shift register part 161; a comparator part 163 for converting multiple video signals outputted from the one-line latch part 162 into multiple analog voltages each; and an analog switch part 17 for switching whether multiple analog voltages are supplied to multiple data lines each. The one-line latch part 162 is disposed near the comparator part 163 such that a length of a signal line through which the bit signal of the least significant bit is propagated becomes shorter than at least a signal line through which the bit signal of the most significant bit is propagated from among multiple bit signals for composing video signals.SELECTED DRAWING: Figure 9

Description

[Technical field]

[0001] The present invention relates to a liquid crystal display device and a manufacturing method thereof, which is suitable for improving, for example, reliability. The present invention also relates to a liquid crystal display device and a manufacturing method thereof. [Background technology]

[0002] The realization and spread of ultra-fast fifth-generation communication technology "5G" is underway. Therefore, in the field of optical communications, a ring-shaped optical network that can handle the rapidly increasing amount of information is required. Optical communication systems such as optical fiber networks and optical wavelength division multiplexing communication systems have been proposed.

[0003] In these optical communication systems, optical signals are transmitted without being converted to electrical signals or relayed. Reconfigurable Optical Add / Drop (ROADM) The ROAD Calc And Drop Multiplexer (ROAD Calc And Drop Multiplexer) equipment is used. As an optical switching device in the M equipment, WSS (Wavelength Select The WSS device uses an optical switching element and The liquid crystal on silicon (LCOS) technology uses the phase modulation function of liquid crystal. Silicon (hereinafter referred to as liquid crystal display device) is used.

[0004] The technology relating to the liquid crystal display device is disclosed in, for example, Patent Document 1. The liquid crystal display device includes a plurality of pixels arranged in a matrix and a plurality of columns of the pixels. A shift register that sequentially receives the video signal for each of the columns of pixels. The input and output register circuits are connected to the input and output terminals of the video signal input terminals. and a latch circuit for inputting a plurality of video signals output from the latch circuit into a plurality of analog inputs. Multiple comparators convert multiple analog voltages into multiple data lines. and an analog switch section for switching whether or not the signal is supplied to the [Prior art documents] [Patent documents]

[0005] [Patent Document 1] JP 2009-223289 A Summary of the Invention [Problem to be solved by the invention]

[0006] In the liquid crystal display device disclosed in Patent Document 1, a plurality of pixels constituting a video signal having a plurality of bit widths are Specific details regarding the wiring of the signal lines through which each of the bit signals propagates are disclosed. Therefore, the least significant bit signal, which changes frequently, is not transmitted through the signal line. In this case, current leakage from the signal line to the inter-layer film or wiring resistance due to manufacturing defects may occur. Resistance may increase in certain areas, leading to progressive failures caused by long-term continuous use. As a result, the reliability of the liquid crystal display device disclosed in Patent Document 1 is reduced. There was a problem with this.

[0007] The present invention has been made in consideration of the above points, and provides a liquid crystal display device capable of improving reliability. The present invention aims to provide a device and a method for manufacturing the same. [Means for solving the problem]

[0008] The liquid crystal display device according to one aspect of the present embodiment includes a plurality of pixels and a plurality of columns of the pixels. A plurality of corresponding data lines and a video signal with a bit width of s (s is an integer of 2 or more) are input to the front. a shift register section for sequentially acquiring the number of pixels corresponding to the number of columns of the plurality of pixels; a latch section for simultaneously outputting the plurality of video signals captured by the latch section; a plurality of comparators for converting the plurality of received video signals into a plurality of analog voltages, and switching whether or not to supply the plurality of analog voltages to the plurality of data lines, respectively. and an analog switch section for shifting the video signal having a bit width of s. The first to s-th bit signals constituting the signal are sequentially taken in for the number of columns of the plurality of pixels, respectively. The latch unit includes a first to an sth shift register circuit. The first to s-th bit signals are input by each of the input circuits, and the number of the first to s-th bit signals corresponds to the number of columns of the plurality of pixels. The first to s-th latch circuits each output a corresponding one of the first to s-th latch circuits. The first bit signals, which are the least significant bit signals, are output simultaneously from among the paths. The first latch circuit configured as above latches at least the most significant bit signal The sth latch circuit is configured to simultaneously output the sth bit signal. The first to s latch circuits are arranged in the vicinity of the comparators. The multiple comparators are directly connected by wiring.

[0009] A method for manufacturing a liquid crystal display device according to one aspect of the present embodiment includes: A plurality of data lines are provided corresponding to each column of the pixels, and a pixel having a bit width of s (s is an integer of 2 or more). a shift register section for sequentially receiving image signals corresponding to the number of columns of the plurality of pixels; a latch section for simultaneously outputting the plurality of video signals captured by the latch section; A plurality of converters for converting the plurality of video signals output from the respective converters into a plurality of analog voltages. a comparator, and whether or not the plurality of analog voltages are supplied to the plurality of data lines, and an analog switch unit for switching between a front end of an s-bit width. The first to s-th bit signals constituting the video signal are sequentially inputted for each of the columns of the plurality of pixels. The latch unit includes first to sth shift register circuits for capturing the first to sth shifts. The first to sth signals corresponding to the number of columns of the plurality of pixels captured by each of the light register circuits are A liquid crystal display device having first to s-th latch circuits each outputting a bit signal simultaneously. A manufacturing method comprising the steps of: the first latch circuit configured to simultaneously output a plurality of the first bit signals; , at least the s-bit signals which are the most significant bit signals are simultaneously outputted. The sth latch circuit is arranged closer to the plurality of comparators than the sth latch circuit configured to The first to s latch circuits and the plurality of comparators are directly connected by wiring. . Effect of the Invention

[0010] According to the present embodiment, a liquid crystal display device capable of improving reliability and a manufacturing method thereof are provided. can be provided. [Brief description of the drawings]

[0011] [Figure 1] FIG. 1 is a diagram showing an example of the configuration of a liquid crystal display device according to a concept prior to the present embodiment; [Diagram 2]2 is a diagram showing in more detail a horizontal driver 56 and an analog switch section 17 provided in the liquid crystal display device shown in FIG. [Diagram 3] 2 is a diagram showing a specific example of the configuration of a pixel provided in the liquid crystal display device shown in FIG. [Figure 4] 4 is a timing chart illustrating a method of driving a pixel in the liquid crystal display device shown in FIG. [Diagram 5] 4 is a diagram for explaining voltage levels from black to white of a positive polarity video signal and a negative polarity video signal written to a pixel. FIG. [Figure 6] 4 is a timing chart showing the operation of the liquid crystal display device shown in FIG. 1 in an image display mode. [Figure 7] 4 is a timing chart for explaining signal changes in each of a plurality of bit signals that constitute a video signal. [Figure 8] 1 is a schematic cross-sectional view for explaining current leakage and high resistance occurring in a signal line; [Figure 9] FIG. 1 is a diagram showing an example of a configuration of a liquid crystal display device according to a first embodiment. [Figure 10] 10 is a diagram showing in more detail a horizontal driver 16 and an analog switch section 17 provided in the liquid crystal display device shown in FIG. [Figure 11] 11A and 11B are diagrams showing the waveform of the least significant bit signal and the comparator output waveform. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0012] <Preliminary review by the inventor> Before describing the liquid crystal display device according to the first embodiment, the present inventors The content will be explained. (Configuration of liquid crystal display device 50 at concept stage) FIG. 1 is a diagram showing an example of the configuration of an active matrix type liquid crystal display device 50 at the concept stage. As shown in FIG. 1, the liquid crystal display device 50 includes an image display unit 11 and a timing generator 13. a polarity switching control circuit 14, a vertical shift register & level shifter 15, and a horizontal driver driver 56, an analog switch unit 17, and AND circuits ADA1 to ADAn, ADB1 to A The horizontal driver 56, together with the analog switch section 17, drives the data lines. The shift register circuit 561, the 1-line latch circuit 562, and the The comparator unit 563 and the gradation counter 564 are shown in FIG. Also shown is a ramp signal generator 2 connected to a liquid crystal display device 50 .

[0013] FIG. 2 shows a horizontal driver 56 and an analog switch section 17 provided in the liquid crystal display device 50. The comparator unit 563 is a diagram showing the above in more detail. 12. Analog switch The circuit 17 includes m sets of switch elements SW1+, SW1− to SWm+ corresponding to the pixels 12 in the mth column. ,SWm- is equipped.

[0014] The pixel arrangement area of ​​the image display unit 11 has n rows (n is 2 or more) extending in the horizontal direction (X-axis direction). (an integer) row scanning lines G1 to Gn and n-row read switch selection lines TG1 to TGn, A set of m columns of data lines D1+, D1− to Dm+, Dm− extending in the vertical direction (Y-axis direction), In addition, gate control signal lines S+, S- and the gate control signal line B are wired.

[0015] The image display unit 11 has a plurality of pixels 12 arranged regularly. 12 includes n row scanning lines G1 to Gn extending in the horizontal direction (X direction) and a vertical scanning line m sets of data lines D1+, D1- to Dm+, Dm- extending in the direction They are arranged in a two-dimensional matrix at the intersections.

[0016] The row scanning lines Gj (j is an arbitrary integer from 1 to n) and the read switch selection lines TGj are , is commonly connected to each of the m pixels 12 arranged in the j-th row. Lines Di+ and Di- (i is an arbitrary integer from 1 to m) are arranged in the i-th column of n pixels 12. The gate control signal lines S+, S-, and the gate The control signal lines B are connected in common to all the pixels 12. The signal lines S+, S- and the gate control signal line B may be provided individually for each row. stomach.

[0017] The polarity switching control circuit 14 receives the timing signal generated by the timing generator 13. Based on the signal, a gate control signal for positive polarity (hereinafter, gate A gate control signal for negative polarity is output to the gate control signal line S-. (hereinafter referred to as gate control signal S-) and further outputs a gate control signal to the gate control signal line B. The gate control signal B is outputted.

[0018] The vertical shift register & level shifter 15 shifts the scanning pulses for n rows from the 1st row to the nth row. The AND circuits ADA1 to AD An are each a vertical shift register based on a mode switching signal MD supplied from the outside. The n-row scanning pulses outputted from the level shifter 15 one row at a time are inputted to the row scanning lines G1 to Gn. Based on the mode switching signal MD supplied from the vertical shift register & level shifter 15, The scan pulses for n rows are sequentially output one row at a time from the read switch selection lines TG1 to TGn. This controls whether or not to output to

[0019] For example, in the case of an operation in which a video signal is written to the pixel 12 (image writing operation), In this case, the AND circuits ADA1 to ADA n is the nth row sequentially output from the vertical shift register & level shifter 15. The row scanning pulses are output to the row scanning lines G1 to Gn. are n rows that are sequentially output one row at a time from the vertical shift register & level shifter 15. The scan pulse is not output to the read switch selection lines TG1 to TGn. The read switch selection lines TG1 to TGn are all fixed to the L level.

[0020] On the other hand, the operation of reading out the video signal written in the pixel 12 (image reading operation In this case, the mode switching signal MD of L level is supplied from the outside. In this case, the AND circuit ADB1 to ADBn are each one row from the vertical shift register & level shifter 15. The scanning pulses for n rows are sequentially output to the read switch selection lines TG1 to TGn. On the other hand, the AND circuits ADA1 to ADAn are vertical shift registers & level shifters. The n-row scanning pulses outputted from the cover 15 one row at a time are outputted to the row scanning lines G1 to Gn. Therefore, all of the row scanning lines G1 to Gn are fixed to the L level. (Specific configuration example of pixel 12) FIG. 3 is a diagram showing a specific example of the configuration of the pixel 12. Here, the pixel 12 is arranged in n rows and m columns. The pixel 12 located in the j-th row and the i-th column will be described.

[0021] As shown in FIG. 3, the pixel 12 includes an N-channel MOS transistor (hereinafter, simply referred to as a transistor). Tr1, Tr2, Tr5, Tr6, and Tr9 are P-channel MOS transistors. The transistors Tr3, Tr4, Tr7, and Tr8 are also included.

[0022] The transistor Tr1 and the storage capacitor Cs1 are connected to a positive data line Di+. The sample and hold circuit samples and holds the video signal. In the transistor Tr1, the source is connected to one data line Di+ of the data line pair, The drain is connected to the gate of the transistor Tr3, and the gate is connected to the row scanning line Gj. The storage capacitor Cs1 is provided between the gate of the transistor Tr3 and the ground voltage terminal Vss. It is being done.

[0023] The transistor Tr2 and the storage capacitor Cs2 are connected to a negative data line Di- The sample and hold circuit samples and holds the video signal. In the transistor Tr2, the source is connected to the other data line Di- of the data line pair, The drain is connected to the gate of the transistor Tr4, and the gate is connected to the row scanning line Gj. The storage capacitor Cs2 is provided between the gate of the transistor Tr3 and the ground voltage terminal Vss. The storage capacitors Cs1 and Cs2 are provided independently of each other and are positive. The positive and negative video signals are held in parallel.

[0024] The transistors Tr3 and Tr7 form a source-fault circuit that outputs the voltage held in the holding capacitor Cs1. It constitutes a follower buffer (impedance conversion buffer). In the follower transistor Tr3, the drain is connected to the ground voltage line Vss and the source The transistor used as a bias-controllable constant current load is connected to node Na. The source of the transistor Tr7 is connected to the power supply voltage line Vdd, and the drain is connected to the node Na and its gate is connected to a gate control signal line B.

[0025] The transistors Tr4 and Tr8 form a source-fault circuit that outputs the voltage held in the holding capacitor Cs2. Specifically, the source follower transistor Tr4 , its drain is connected to the ground voltage line Vss, and its source is connected to a node Nb. In the transistor Tr8 used as a bias-controllable constant current load, the source is It is connected to the voltage line Vdd, its drain is connected to node Nb, and its gate is connected to the gate control signal It is connected to Line B.

[0026] The transistors Tr5 and Tr6 form a polarity changeover switch. In the transistor Tr5, the source is connected to the node Na, and the drain is connected to the pixel driving electrode PE and the gate is connected to one gate control signal line S+ of the gate control signal line pair. In the transistor Tr6, the source is connected to the node Nb, and the drain is connected to the pixel drive electrode PE, and its gate is connected to the other gate control signal line S- of the gate control signal line pair. is.

[0027] The liquid crystal display element LC is made up of a pixel drive electrode (reflective electrode) PE having light reflection characteristics and a pixel drive A common electrode CE having optical transparency is disposed opposite to the electrode and is filled in the space between them. The common electrode CE is connected to a common voltage Vcom. The transistor Tr9 is provided between the pixel driving electrode PE and the data line Di+. The read switch selection lines TGj are used to switch on and off the data.

[0028] The data line pair Di+, Di- is connected to the analog switch unit 17. Video signals of different polarities are supplied. Here, the vertical shift register and level shifter When a scanning pulse output from the power supply 15 is supplied to the row scanning line Gj, the transistors Tr1 and T r2 is turned on at the same time. As a result, the storage capacitors Cs1 and Cs2 are charged with positive polarity. The voltage of the negative polarity video signal is stored and held.

[0029] The input resistance of each source follower buffer on the positive and negative sides is almost infinite. Therefore, the charges stored in the storage capacitors Cs1 and Cs2 leak out. The image signal is held without being changed until one vertical scanning period has elapsed and a new image signal is written.

[0030] The transistors Tr5 and Tr6 that make up the polarity changeover switch (selection section) are gate-controlled. By switching on and off complementarily according to the control signals S+ and S-, the positive source The output voltage of the source follower buffer (the voltage of the positive video signal) and the negative source follower buffer The output voltage of the negative polarity video signal and the output voltage of the negative polarity video signal are alternately selected to be applied to the pixel driving electrode PE. As a result, the pixel driving electrodes PE are supplied with a voltage of a video signal whose polarity is periodically inverted. In this way, the liquid crystal display device has a polarity inversion function in the pixel itself. In order to achieve this, the polarity of the voltage of the video signal supplied to the pixel drive electrode PE is quickly changed in each pixel. By switching, AC driving at high frequencies is possible, regardless of the vertical scanning frequency. . (Description of AC driving method for pixel 12) FIG. 4 is a timing chart for explaining a method of AC driving the pixel 12 in the liquid crystal display device 50. In this chart, the pixel 12 in the jth row and the ith column of the nth row x mth column is A method for AC driving the pixel 12 will now be described.

[0031] In FIG. 4, VST represents a vertical sync signal that is the reference for vertical scanning of a video signal. B is a transistor used as a constant current load for two types of source follower buffers. The gate control signals supplied to the gates of Tr7 and Tr8 are shown in the figure. is supplied to the gate of the positive-side transistor Tr5 provided in the polarity changeover switch. S- represents the gate control signal for the negative polarity of the polarity changeover switch. VPE represents the gate control signal supplied to the gate of transistor Tr6. Vcom represents the voltage applied to the common electrode CE. VLC represents the AC voltage applied to the liquid crystal LCM.

[0032] FIG. 5 shows the relationship between the positive and negative video signals written to the pixel 12. 5 is a diagram for explaining voltage levels from black to white of a positive polarity video signal. represents the black level when the voltage level is minimum and the white level when the voltage level is maximum. In contrast, a negative video signal represents a white level when its voltage level is at its minimum, The maximum voltage level represents the black level. However, the positive polarity video signal is The minimum voltage level represents the white level and the maximum voltage level represents the black level. Also, the negative polarity video signal represents a black level when the voltage level is minimum, and The dashed line in the figure indicates the positive polarity image. 13 shows the inversion center of the video signal and the negative polarity video signal.

[0033] In the pixel 12, the transistor Tr9 is turned on when the read switch selection line TGj is at the L level. On the other hand, the transistors Tr1 and Tr2 are fixed to the row When a scanning pulse is supplied to the scanning line Gj, the storage capacitor C The voltages of positive and negative video signals are stored and held in s1 and Cs2, respectively.

[0034] As shown in FIG. 4, during the period when the gate control signal S+ indicates the H level, the positive-side transistor At this time, by setting the gate control signal B to the L level, the transistor Since start Tr7 is turned on, the source follower buffer on the positive side becomes active. As a result, the pixel driving electrode PE is charged to the voltage level of the positive polarity video signal. By setting the port control signal B to the L level, the transistor Tr8 is turned on, and the negative The source follower buffer on the positive side is also active. Since the pixel transistor Tr6 is off, the pixel driving electrode PE is at the voltage level of the negative video signal. When the pixel driving electrode PE is fully charged, the gate control Signal B is switched from L level to H level, and gate control signal S+ is switched from H level to This switches the pixel driving electrode PE to a floating state. Therefore, a positive drive voltage is maintained in the liquid crystal capacitance.

[0035] On the other hand, during the period when the gate control signal S- indicates the H level, the negative-side transistor Tr6 is on. At this time, by setting the gate control signal B to the L level, the negative-side transistor Tr8 turns on, and the negative side source follower buffer becomes active. As a result, the pixel driving electrode PE is charged to the voltage level of the negative video signal. By setting the control signal B to the L level, the transistor Tr7 turns on, The source follower buffer is also active. However, the positive-side transistor T Because r5 is off, the pixel drive electrode PE is charged to the voltage level of the positive polarity video signal. When the pixel driving electrode PE is fully charged, the gate control signal B The gate control signal S- is switched from H level to L level. This causes the pixel driving electrode PE to be in a floating state, A negative drive voltage is maintained in the crystal capacitance.

[0036] The above-mentioned operations on the positive and negative sides are alternately repeated to form a pixel driving electrode The PE is a driving voltage that is alternating with the voltage of each of the positive and negative video signals. VPE will be applied.

[0037] The charges stored in the storage capacitors Cs1 and Cs2 are directly transferred to the pixel driving electrode PE. Instead, the signal is transferred through a source follower buffer, so that the pixel driving electrode PE Even if the voltage of the positive and negative polarity video signals is repeatedly charged and discharged, the charge is neutralized. Therefore, it is possible to realize pixel driving without attenuation of the voltage level.

[0038] As shown in FIG. 4, the voltage level of the applied voltage VPE to the pixel driving electrode PE is switched. Instead, the voltage level of the applied voltage Vcom to the common electrode CE is synchronized with the applied voltage VPE. The voltage Vcom applied to the common electrode CE is switched to the opposite level. A voltage approximately equal to the inversion reference voltage of the voltage VPE applied to the electrode PE is used as the inversion reference voltage.

[0039] Here, the substantial AC voltage VLC applied to the liquid crystal LCM is the voltage applied to the pixel driving electrode PE. Since this is the difference voltage between the applied voltage VPE and the applied voltage Vcom to the common electrode CE, the liquid crystal LC An AC voltage VLC that does not include a DC component is applied to M. The voltage Vcom applied to the electrode CE is switched in phase with the voltage VPE applied to the pixel drive electrode PE. This makes it possible to reduce the amplitude of the voltage to be applied to the pixel driving electrode PE. This makes it possible to reduce the breakdown voltage and power consumption of the transistors that form the circuit portion of the pixel.

[0040] In addition, if the current flowing steadily through the source follower buffer per pixel is a minute 1μA, Even if the current is small, the current that steadily flows through all the pixels of a liquid crystal display cannot be ignored. For example, a full HD 2 million pixel liquid crystal display may In such a case, the current consumption may reach 2 A. Therefore, in the pixel 12, a constant current load is used. The transistors Tr7 and Tr8 used as loads are not always on, but are connected to the positive poles. And only for a limited period during which the negative side transistors Tr5 and Tr6 are on. Therefore, when one of the source follower buffers is operating, The operation of the other source follower buffer can be stopped, preventing an increase in current consumption. It can be suppressed.

[0041] The AC driving frequency of the liquid crystal display element LC is independent of the vertical scanning frequency, and the pixel inversion control is performed By adjusting the period, it can be freely adjusted. For example, the vertical scanning frequency is generally The number of vertical scanning lines in full HD is u, which is 60 Hz used in television video signals. The number of lines is 1125. Also, the polarity switching in each pixel is performed for about 15 line periods. In other words, the number of lines per polarity switching period for each pixel is The number of lines is 30. In this case, the AC driving frequency of the liquid crystal is 60Hz x 1125 In other words, the liquid crystal display device 50 has an AC driving frequency of 15 Hz. This allows the wave number to be dramatically increased. This solves the problem of low AC driving frequencies for liquid crystal. This has significantly improved the reliability, stability and display quality of images displayed on the LCD screen, which had been a problem. It is possible.

[0042] Next, the operation of the liquid crystal display device 50 in each operation mode will be described. (Operation of the liquid crystal display device 50 in the image display mode) First, the operation of the liquid crystal display device 50 in the image display mode will be described with reference to FIG. FIG. 6 is a timing chart showing the operation of the liquid crystal display device 50 in the image display mode.

[0043] As shown in FIG. 6, when a horizontal sync signal HST pulse signal is supplied, the shift register The circuit 561 outputs an s-bit (s is an integer of 2 or more)-bit video signal in synchronization with the clock signal HCK. The 1-line latch circuit 562 sequentially captures signals for m columns. The m rows of video signals captured in the memory are temporarily The signals are output simultaneously at the specified timing.

[0044] The grayscale counter 564 counts the number of rising edges of the clock signal CNT_CK. The gray scale counter 11 outputs a gray scale signal Cout having a gray scale level according to the count value of the gray scale counter 11. 564 is the minimum level at the start of one horizontal scanning period (at the rising edge of the horizontal sync signal HST). The grayscale signal Cout of the counter is output, and the grayscale level of the grayscale signal Cout increases with the increase in the count value. At the end of one horizontal scanning period (just before the next rising edge of the horizontal sync signal HST), The gradation counter 564 outputs the maximum level gradation signal Cout. The value is, for example, when the reset signal CNT_R becomes active in response to the rising edge of the horizontal sync signal HST. It is initialized to "0" when it becomes active.

[0045] The comparator section 563 includes m columns of comparators 563_1 to 563_m. The grayscale signal output from the grayscale counter 564 is synchronized with the clock signal CMP_CK. Cout is m-row video signals (line data) output simultaneously from the 1-line latch circuit 562. At the timing that coincides with each of the coincidence signals P1 to Pm, the coincidence signals P1 to Pm are made active (for example, the L level Bell).

[0046] The analog switch section 17 includes m pairs of switch elements SW1+, SW1- to SWm Among the positive polarity switch elements SW1+ to SWm+, the positive polarity switch elements SW1+ to SWm+ are It is provided between the lines D1+ to Dm+ and the common wiring Dcom+. The switch elements SW1- to SWm- are connected to the data lines D1- to Dm- and the common wiring D com- and m sets of switch elements SW1+, SW1- to SWm+ , SWm- are match signals P1 to Pm from the comparators 563_1 to 563_m, respectively. Switch it on and off with m.

[0047] The common wiring Dcom+ is connected to the positive polarity lamp output from the lamp signal generator 2. The reference lamp voltage Ref_R+ is supplied to the common wiring Dcom-. is the reference ramp voltage Re, which is a negative ramp signal output from the ramp signal generator 2. f_R- is supplied.

[0048] The reference ramp voltage Ref_R+ is the video level from the start to the end of each horizontal scan period. The reference ramp voltage Ref_R- is a sweep signal that changes from the black level to the white level. A scanning technique in which the image level changes from the white level to the black level from the start to the end of a horizontal scanning period. Therefore, the reference ramp voltage Ref_R+ relative to the common voltage Vcom, The reference ramp voltage Ref_R- and the common voltage Vcom have an inverse relationship with each other. do.

[0049] The switch elements SW1+, SW1- to SWm+, SWm- are switched on at the start of a horizontal scanning period. When the start signal SW_Start becomes active (for example, H level), Then, the switch elements SW1+, SW1- to SWm+, SWm- are turned on. , the match signals P1 to Pm output from the comparators 563_1 to 563_m are active. (for example, L level) to switch from ON to OFF. At the end of the start signal SW_Start becomes inactive (e.g., L level). .

[0050] In the example of FIG. 6, a pixel row to which a video signal of gradation level k is written is provided Switching on and off the switch elements SWq+ and SWq- (q is an integer from 1 to m) The waveform representing the timing of the above-mentioned step is shown as the waveform SPk. The switch elements SWq+ and SWq- turn on at the rising edge of the start signal SW_Start. After that, the match signal Pq becomes active, switching it from on to off. The switching elements SWq+ and SWq- are switched from on to off at the timing of the reference run. The amplifier samples the reference voltages Ref_R+ and Ref_R- (voltages P and Q in FIG. 6). These sampled voltages P and Q are supplied to the data lines Dq+ and Dq-. Then, analog voltages P and Q, which are the results of DA conversion of the video signal of gradation level k, are The signal is supplied to data lines Dq+ and Dq-.

[0051] In the image display mode, a mode switching signal MD of H level is supplied from the outside. Therefore, n rows of pixels are sequentially output one row at a time from the vertical shift register & level shifter 15. The scanning pulses are supplied to the row scanning lines G1 to Gn, respectively. The transistors Tr1 and Tr2 provided in each pixel 12 are turned on when a scanning pulse is supplied to the row scanning line Gj. As a result, the jth row pixel 12 is temporarily turned on by being supplied with The storage capacitors Cs1 and Cs2 store the voltages of the corresponding positive and negative video signals, respectively. On the other hand, the transistor Tr9 provided in each pixel 12 is maintained in the off state. The subsequent AC driving method for each pixel 12 is as already described.

[0052] As described above, the switch elements SW1+, SW1- to SWm+, SWm- are At the start of the period, they are all turned on at the same time, but each pixel 12 has a different gray level to display. In other words, the switch elements SW1+ and SW1- SWm+ and SWm- may be turned off at the same time or at different times. Also, the order in which they are turned off is not fixed.

[0053] In this way, the liquid crystal display device 50 converts the video signal into digital data using the ramp signal, By writing to pixel 12, the linearity of the image can be improved. (Operation of the liquid crystal display device 50 in pixel inspection mode) Next, the operation of the liquid crystal display device 50 in the pixel inspection mode will be described. In the inspection mode, the ramp signal generator 2 is replaced by an inspection device.

[0054] In the pixel inspection mode, first, m pixels 12 in the first row to m pixels 12 in the nth row are inspected. The video signal for inspection is written to each row in sequence. The operation is the same as in the pixel display mode. Then, writing is performed on the pixel 12 to be inspected. The captured video signal (pixel drive voltage VPE) is then read out.

[0055] In pixel readout operation, the mode switching signal MD supplied from the outside changes from H level to L level. Therefore, the vertical shift register & level shifter 15 outputs one row at a time. Of the n-row scanning pulses that are input, the j-th row scanning pulse to be inspected is As a result, the jth row pixel 12 to be inspected is provided with The transistor Tr9 is turned on when a scan pulse is supplied to the read switch selection line TGj. On the other hand, the transistors Tr1, Tr2 remains in the off state.

[0056] For example, in the pixel 12 located in the jth row and the ith column, the transistor Tr9 is turned on. As a result, the pixel driving electrode PE and the data line Di+ are brought into a conductive state, The voltage of PE is read out to the data line Di+. At this time, transistors Tr7 and Tr8 By making it active and turning on either transistor Tr5 or Tr6, the image The element driving electrode PE is made up of transistors Tr3 and Tr7 or transistors Tr4 and Tr8. The source follower buffer is driven by the The driving voltage VPE applied to the pixel driving electrode PE by the buffer is is read out.

[0057] The m pixels 12 in the jth row to be inspected are read out to the data lines D1+ to Dm+. The m pixel drive voltages VPE are outputted to the m sets of SWs provided in the analog switch unit 17. By sequentially turning on SW1+, SW1-, SWm+, and SWm-, the common wiring Dcom+ The test device (not shown) provided in place of the ramp signal generator 2 is a common Based on m pixel drive voltages VPE sequentially supplied via the wiring Dcom+, The presence or absence of failures (pixel defects and characteristic deterioration) in m pixels 12 is detected. , the process is performed row by row from the m pixels 12 in the first row to the m pixels 12 in the nth row. .

[0058] Here, in the pixel 12 to be inspected, a source follower buffer with low output impedance is Therefore, the voltage VPE of the driven pixel driving electrode PE is read out as it is. Therefore, defects or deterioration in the characteristics of the pixels 12 can be detected accurately and easily.

[0059] In the liquid crystal display device 50, several measures have been taken to improve the image display performance. This has been implemented.

[0060] First, of the 1st to sth bit signals constituting the s-bit video signal, The period of signal change of the first bit signal, which is the bit signal, is the shortest, and the period from the first bit signal to the first The period of the signal change gradually becomes longer toward the 0 bit signal, and the most significant bit signal The period of signal change of the 10th bit signal, which is the 10th bit signal, is the longest (see FIG. 7).

[0061] Therefore, the first bit signal line through which the first bit signal, which frequently changes, propagates is In comparison with the ground signal line, the signal line is arranged near the ground wiring, which is advantageous for high frequency operation. The first bit signal line, through which the first bit signal, which frequently changes, propagates, is different from the other bit signal lines. In comparison, in order to avoid the influence of noise from the analog switch section 17, They are arranged in an area away from the analog switch section 17. Even if the brightness is increased, stable operation is possible, and the sense of afterimage in the displayed image is eliminated.

[0062] However, in the liquid crystal display device 50, the first bit signal, which frequently changes, is propagated. The length of the first bit signal line (specifically, the length from the 1-line latch circuit 562 to the comparator unit 5 The length of the first bit signal line (up to 63) is longer than the other bit signal lines. Generally, the longer the signal line, the more likely it is that current leakage will occur from the signal line to the inter-layer film. At the same time, it is subject to the effects of dust due to manufacturing defects and dimensional fluctuations during pattern exposure. This makes it easier for the wiring resistance to increase in parts (see Figure 8). The higher the temperature, the more the deterioration caused by long-term continuous use will be affected by current leakage and high resistance. Therefore, the first bit signal, which changes frequently, is propagated. The first bit signal line, which is connected to the semiconductor memory device, is prone to progressive failure due to long-term continuous use. As a result, the liquid crystal display device 50 has a problem of reduced operational reliability. In addition, the effects of dust due to defects during manufacturing and dimensional fluctuations during pattern exposure may occur during the initial This also caused operational problems in the manufacturing process, resulting in a decrease in production yields. .

[0063] Therefore, the liquid crystal display according to the first embodiment is capable of improving reliability and manufacturing yield. A display device and method for manufacturing the same have been discovered. <Embodiment 1> 9 is a block diagram showing the liquid crystal display device 1 according to the first embodiment. 1 is equipped with a horizontal driver 16 instead of a horizontal driver 56 as compared with the liquid crystal display device 50. Other configurations of the liquid crystal display device 1 are similar to those of the liquid crystal display device 50. Therefore, the description thereof will be omitted.

[0064] The horizontal driver 16 includes a shift register section 161, a one-line latch section 162, and a comparator. The shift register section 161 includes a 1-line shift register section 163 and a gradation counter 164. The latch unit 162, the comparator unit 163, and the grayscale counter 164 are each a shift register. A register circuit 561, a 1-line latch circuit 562, a comparator section 563, and a gradation It corresponds to counter 564.

[0065] The shift register unit 161, like the shift register circuit 561, receives the clock signal HCK In synchronization with the 1 line, the video signal with a bit width of s (s is an integer of 2 or more) is sequentially captured for m lines. The in-latch unit 162 is similar to the one-line latch circuit 562 in that the shift register unit 161 The captured m-row s-bit image signal is temporarily activated when the trigger signal REG_S is activated. When the signal becomes active, the signals are all latched in and output.

[0066] The grayscale counter 164 counts the number of rising edges of the clock signal CNT_CK. The gray scale counter 11 outputs a gray scale signal Cout having a gray scale level according to the count value of the gray scale counter 11. 164 is the minimum level at the start of one horizontal scanning period (at the rising edge of the horizontal sync signal HST). The grayscale signal Cout of the counter is output, and the grayscale level of the grayscale signal Cout increases with the increase in the count value. At the end of one horizontal scanning period (just before the next rising edge of the horizontal sync signal HST), The gradation counter 164 outputs the maximum level gradation signal Cout. The value is, for example, when the reset signal CNT_R becomes active in response to the rising edge of the horizontal sync signal HST. It is initialized to "0" when it becomes active.

[0067] The comparator section 163 includes m columns of comparators 163_1 to 163_m. The grayscale signal output from the grayscale counter 164 is synchronized with the clock signal CMP_CK. Cout is m rows of video signals (line data) output simultaneously from the 1-line latch unit 162. ), the coincidence signals P1 to Pm are made active (for example, L level) at the timing coincident with each of the (ru).

[0068] Other configurations and operations of the horizontal driver 16 are similar to those of the horizontal driver 56. Therefore, the description thereof will be omitted. (Specific Configuration Example of Shift Register Unit 161 and Its Peripheral Circuits) FIG. 10 is a block diagram showing a specific example of the configuration of the shift register unit 161 and its peripheral circuits. In the example of FIG. 10, when the bit width of the video signal is 10 bits (s=10), In addition, in FIG. 10, a one-line latch unit 162, a comparator unit 163, , a grayscale counter 164, and an analog switch section 17 are also shown.

[0069] As shown in FIG. 10, the shift register section 161 has ten registers corresponding to the bit width of the video signal. The shift register circuits 161_1 to 161_10 are configured as follows. The latch unit 162 includes ten one-line latch circuits 162_ corresponding to the bit width of the video signal. It consists of 1~162_10.

[0070] The shift register circuit 161_1 shifts the first to tenth bits constituting a 10-bit video signal. The first bit signal, which is the least significant bit signal, is sequentially acquired for m columns of the bit signal. Similarly, the shift register circuits 161_2 to 161_10 are second to tenth shift register circuits 161_2 to 161_10, respectively. The bit signal is sequentially acquired for m columns.

[0071] The one-line latch circuit 162_1 latches the m columns of the shift register circuit 161_1. The first bit of the minute is sent to the trigger signal REG_S when it becomes temporarily active. Similarly, the 1-line latch circuits 162_2 to 162_10 output the signals at the same time. The second to tenth bits of m columns taken into the shift register circuits 161_2 to 161_10 are The trigger signals are output simultaneously when the trigger signal REG_S becomes temporarily active. To exert effort.

[0072] Here, among the first to tenth bit signals, the first bit signal is the least significant bit signal. The period of signal change is the shortest, and gradually changes from the 1st bit signal to the 10th bit signal. The period of signal change becomes longer, and the signal change of the 10th bit signal, which is the most significant bit signal, Therefore, if the signal lines are the same length, the first to tenth Among the first to tenth bit signal lines through which the bit signals propagate, The first bit signal line through which the first bit signal propagates has progressive defects caused by long-term continuous use. This can lead to malfunctions and manufacturing defects.

[0073] Therefore, in this embodiment, among the one-line latch circuits 162_1 to 162_10, The line latch circuit 162_1 is at least one line latch circuit lower than the line latch circuit 162_10. More preferably, the 1-line latch circuit 162 is disposed in the vicinity of the parameter unit 163. _1 is closer to the comparator unit 163 than the one-line latch circuits 162_2 to 162_10. It is placed nearby.

[0074] As a result, wiring is provided from the 1-line latch circuit 162_1 to the comparator unit 163. The length of the first bit signal line is determined by the length of each of the one-line latch circuits 162_2 to 162_10. The length of the second to tenth bit signal lines wired from the As a result, in the first bit signal line through which the first bit signal, which frequently changes, propagates, Current leakage from the signal line to the insulating interlayer film, or wiring resistance due to manufacturing defects, etc. Even if the load on the signal line is partially high, the load on the signal line is reduced by lowering the RC time constant. This reduces the risk of progressive breakdowns caused by long-term continuous use. The reliability of the LCD device 1 is improved, and the manufacturing yield is also improved.

[0075] Figure 11 shows the video signal of the least significant bit of m columns simultaneously output from one line latch section (line The waveform of the video signal in the i-th row of the data, and the video signal and the gradation signal Cout 13 shows the waveform of a coincidence signal Pi that is output from the comparator section at the coincidence timing.

[0076] The first row of Figure 11 shows the ideal waveform of the first bit signal, which is the least significant bit. As shown in FIG. 11, the ideal waveform of the first bit signal is a square wave.

[0077] The second row of FIG. 11 shows the waveform of the first bit signal in the liquid crystal display device 1. Specifically, the shift register circuit 161_1 and the 1-line latch circuit 162_1 are connected to the other shift registers 161_1 and 1-line latch circuits 162_1. The analog switch section 17 (i.e., 16 shows the waveform of the first bit signal when the first bit is placed near the modulator unit 163.

[0078] The third row of FIG. 11 shows the waveform of the first bit signal in the liquid crystal display device 50. Specifically, the shift register circuit 161_1 and the 1-line latch circuit 162_1 are The circuit equivalent to the above is more efficient than other shift register circuits and one-line latch circuits in analog switching. When the first bit is arranged away from the switch unit 17 (i.e., the comparator unit 563), 4 shows the waveform of a signal.

[0079] The second waveform in Figure 11 shows the time when the first bit signal is propagated, compared with the third waveform in Figure 11. Since the length of the signal line (hereinafter referred to as the first bit signal line) is short, the RC time constant is small. Therefore, the rounding of the first bit signal is small. On the other hand, the third waveform in Figure 11 is However, since the wiring length of the first bit signal line is long, the RC time constant becomes large, and the first bit signal The ball is getting bigger.

[0080] The fourth waveform in FIG. 11 is a match signal P corresponding to the first bit signal shown in the third waveform in FIG. That is, the fourth waveform in FIG. 11 shows the waveform of the first bit signal line when the wiring length is long. In this case, the first bit signal is rounded. Therefore, the rising and falling edges of the comparator output are both at the ideal first bit. The rising and falling edges of the clock signal are delayed.

[0081] The fifth waveform in FIG. 11 indicates the shift register circuit 161_1 and the one-line latch circuit 16 The circuits corresponding to each of 2_1 are different from the other shift register circuits and 1-line latch circuits. In addition, when the analog switch unit 17 (i.e., the comparator unit 563) is disposed away from the analog switch unit 17, In this case, if the first bit signal line becomes highly resistive due to current leakage or manufacturing defects, In this case, the wiring length of the first bit signal line is long, The RC time constant becomes larger, causing the first bit signal to become more rounded. In addition, the current leakage Due to the influence of high resistance of the wiring, the voltage level of the first bit signal is judged to be H level. It cannot rise above the threshold voltage. Therefore, as shown in the sixth row of Figure 11, The match signal Pi cannot rise to the H level and remains at the L level. As a result, the liquid crystal display device 50 cannot operate normally.

[0082] In contrast, in the liquid crystal display device 1 according to the present embodiment, the shift register circuit 161_ 1 and 1 line latch circuit 162_1 are other shift register circuits and 1 line latch circuits It is arranged closer to the analog switch section 17 (i.e., the comparator section 163) than the path. Since the length of the first bit signal line is short, the RC time constant is small, and the first bit signal Therefore, the liquid crystal display device 1 is resistant to small current leakage and high resistance of wiring. Even if any of the above occurs, the device can still operate normally.

[0083] In other words, the liquid crystal display device 1 according to the present embodiment is free from current leakage or manufacturing defects. Even if the wiring becomes highly resistive due to the influence of the current, the device can still function normally. As a result, reliability and manufacturing The manufacturing yield is improved.

[0084] In this manner, in the liquid crystal display device 1 according to the present embodiment, a plurality of video signals constituting a video signal The first bit signal is the bit signal that propagates the least significant bit that frequently changes among the bit signals. The length of the line is shorter than the lengths of the second to tenth bit signal lines through which the other bit signals propagate. This allows the first bit signal, which changes frequently, to propagate more smoothly. In the first bit signal line, current leakage from the signal line to the insulating interlayer film occurs, and Even if the wiring resistance becomes high in some places due to a malfunction, the length of the wiring is short. The load on the signal line is reduced by the decrease in the RC time constant due to the As a result, the reliability of the liquid crystal display device 1 is improved. In addition, the manufacturing yield is improved.

[0085] The liquid crystal display device 1 according to the present embodiment is, for example, a WSS mounted on an optical communication system. The liquid crystal display device 1 is used as an optical switching element of the WSS device. When used as a switching element, it operates at a higher frequency than when used for image display. Therefore, in order to shorten the first bit signal line, the one-line latch circuit 162_1 There is no problem if the MOSFET is placed away from the ground wiring (i.e., near the comparator section 163). In this case, a certain degree of afterimage is acceptable compared to when it is used for image display. Therefore, in order to shorten the first bit signal line, the 1-line latch circuit 162_1 is implemented as an analog switch. There is no problem even if it is placed near switch section 17 (that is, comparator section 163). [Explanation of symbols]

[0086] 1 LCD display device 2 Ramp signal generator 11 Image display section 12 pixels 13 Timing Generator 14 Polarity switching control circuit 15 Vertical shift register & level shifter 16 Horizontal Driver 17 Analog switch section 50 LCD display device 56 Horizontal driver 161 Shift register section 161_1~161_10 Shift register circuit 162 1 line latch section 163 Comparator section 163_1~163_m Comparator 164 Gradation Counter 561 Shift Register Circuit 562 1 line latch circuit 563 Comparator section 563_1~563_m Comparator 564 Gradation Counter ADA1~ADAn AND circuit ADB1~ADBn AND circuit B Gate control signal line CE Common electrode Cs1,Cs2 retention capacity D1+, D1-~Dm+, Dm- Data line Dcom+, Dcom- common wiring G1~Gn row scanning line LC Liquid crystal display element LCM LCD Na,Nb nodes PE Pixel driving electrode (reflective electrode) S+, S- Gate control signal lines SW1+, SW1- to SWm+, SWm- Switch elements TG1+~TGn+ Readout switch selection lines TG1-~TGn- Readout switch selection lines Tr1~Tr9 Transistors

Claims

1. A plurality of pixels; A plurality of data lines provided corresponding to each column of the plurality of pixels; a shift register unit for sequentially receiving a video signal having a bit width of s (s is an integer of 2 or more) by the number of columns of the plurality of pixels; a latch section which simultaneously outputs the plurality of video signals captured by the shift register section; a plurality of comparators for converting the plurality of video signals output from the latch unit into a plurality of analog voltages, respectively; an analog switch section for switching whether or not the plurality of analog voltages are supplied to the plurality of data lines; Equipped with The shift register unit includes: a first to an s-th shift register circuit for sequentially receiving first to s-th bit signals constituting the video signal having an s-bit width, the first to s-th bit signals being equal to the number of columns of the plurality of pixels; The latch portion is a first to an s-th latch circuit for simultaneously outputting first to s-th bit signals corresponding to the number of columns of the plurality of pixels captured by the first to s-th shift register circuits, respectively; Among the first to s latch circuits, the first latch circuit configured to simultaneously output the plurality of first bit signals which are bit signals of the least significant bit is disposed closer to the plurality of comparators than the s latch circuit configured to simultaneously output the plurality of s bit signals which are bit signals of the most significant bit, and the first to s latch circuits and the plurality of comparators are directly connected by wiring; the first to s shift register circuits and the first to s latch circuits are arranged adjacent to each other in correspondence with the first to s bit signals, and the first to s latch circuits for latching each bit signal are arranged between the first to s shift register circuits corresponding to each bit signal, respectively; LCD display device.

2. the first latch circuit is arranged such that a plurality of signal lines wired from the first latch circuit to each of the plurality of comparators are shorter than at least a plurality of signal lines wired from the s latch circuit to each of the plurality of comparators; The liquid crystal display device according to claim 1 .

3. the first latch circuit is disposed closer to the plurality of comparators than the second to s latch circuits are disposed; The liquid crystal display device according to claim 1 .

4. the first latch circuit is arranged such that a plurality of signal lines wired from the first latch circuit to each of the plurality of comparators are shorter than a plurality of signal lines wired from each of the second to s latch circuits to each of the plurality of comparators; The liquid crystal display device according to claim 3 .

5. The liquid crystal display device is an optical switching element used in an optical communication system.

5. The liquid crystal display device according to claim 1.

6. A plurality of pixels; A plurality of data lines provided corresponding to each column of the plurality of pixels; a shift register unit for sequentially receiving a video signal having a bit width of s (s is an integer of 2 or more) by the number of columns of the plurality of pixels; a latch section which simultaneously outputs the plurality of video signals captured by the shift register section; a plurality of comparators for converting the plurality of video signals output from the latch unit into a plurality of analog voltages, respectively; an analog switch section for switching whether or not the plurality of analog voltages are supplied to the plurality of data lines; Equipped with The shift register unit includes: a first to an s-th shift register circuit for sequentially receiving first to s-th bit signals constituting the video signal having an s-bit width, the first to s-th bit signals being equal to the number of columns of the plurality of pixels; The latch portion is a first to an s-th latch circuit for simultaneously outputting first to s-th bit signals corresponding to the number of columns of the plurality of pixels captured by the first to s-th shift register circuits, respectively; A method for manufacturing a liquid crystal display device, comprising the steps of: Among the first to s latch circuits, the first latch circuit configured to simultaneously output the plurality of first bit signals which are bit signals of the least significant bit is disposed closer to the plurality of comparators than the s latch circuit configured to simultaneously output the plurality of s bit signals which are bit signals of the most significant bit, and the first to s latch circuits and the plurality of comparators are directly connected by wiring; The first to s shift register circuits and the first to s latch circuits are arranged adjacent to each other in correspondence with the first to s bit signals, and the first to s latch circuits for latching each bit signal are arranged between the first to s shift register circuits corresponding to each bit signal, respectively. A method for manufacturing a liquid crystal display device.

7. In the step of disposing the first latch circuit, the first latch circuit is arranged such that a plurality of signal lines extending from the first latch circuit to each of the plurality of comparators are shorter than at least a plurality of signal lines extending from the s latch circuit to each of the plurality of comparators; The method for manufacturing a liquid crystal display device according to claim 6 .

8. The liquid crystal display device is an optical switching element used in an optical communication system. The method for manufacturing a liquid crystal display device according to claim 6 or 7.

Images